Comexpresspnp DG 09 .

COM Express Design Guide
Guidelines for designing COM Express carrier boards
Design Guide Revision .09 (Preli inar!"
Revision History
Revision Date (dd.mm.yy) Author
.09 06.04.07
Changes
COM Express Preliminary release PnP Initiative
Copyright COM Express PnP Initiative
COMExpressPnP !" 09
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re!a"e
&his 'o()ment provi'es in*ormation *or 'esigning a ()stom system (arrier +oar' *or COM Express mo')les. It in(l)'es re*eren(e s(hemati(s *or the external (ir()itry re,)ire' to implement the vario)s COM Express peripheral *)n(tions. It also explains ho- to exten' the s)pporte' +)ses an' ho- to a'' a''itional peripherals an' expansion slots to a COM Express +ase' system.
Dis"#aimer
&he in*ormation (ontaine' -ithin this 'esign g)i'e. in(l)'ing +)t not limite' to any pro')(t spe(i*i(ation. is s)+/e(t to (hange -itho)t noti(e. &he COM Express PnP Initiative provi'es no -arranty -ith regar' to this 'esign g)i'e or any other in*ormation (ontaine' herein an' here+y expressly 'is(laims any implie' -arranties o* mer(hanta+ility or *itness *or any parti()lar p)rpose -ith regar' to any o* the *oregoing. &he COM Express PnP Initiative ass)mes no lia+ility *or any 'amages in()rre' 'ire(tly or in'ire(tly *rom any te(hni(al or typographi(al errors or omissions (ontaine' herein. In no event shall the COM Express PnP Initiative +e lia+le *or any in(i'ental. (onse,)ential. spe(ial. or exemplary 'amages. -hether +ase' on tort. (ontra(t or other-ise. arising o)t o* or in (onne(tion -ith this 'esign g)i'e or any other in*ormation (ontaine' herein or the )se thereo*. &he typi(al appli(ation (ir()its 'es(ri+e' in this 'o()ment may not +e s)ita+le *or all appli(ations. In parti()lar. a''itional (omponents may nee' to +e a''e' to these (ir()its in or'er to meet spe(i*i( E0!. EMC or sa*ety isolation re,)irements. 0)(h reg)latory re,)irements an' the te(hni,)es *or meeting them vary +y in')stry an' are +eyon' the s(ope o* this 'o()ment.
$ntended Audien"e
&his 'esign g)i'e is inten'e' *or te(hni(ally ,)ali*ie' personnel. It is not inten'e' *or general a)'ien(es.
%ym&o#s
&he *ollo-ing sym+ols are )se' in this 'esign g)i'e1 'arning Warnings indicate conditions that, if not observed, can cause personal injury. Caution Cautions warn the user about how to prevent damage to hardware or loss of data. (ote Notes call attention to important information that should be observed.
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)ermino#ogy
)erm
PCI Express 3PCIe4 PCI Express 8ane
Des"ription
Peripheral Component Inter*a(e Express 5 next6generation high spee' 0eriali7e' I$O +)s One PCI Express 8ane is a set o* 4 signals that (ontains t-o 'i**erential lines *or &ransmitter an' t-o 'i**erential lines *or 9e(eiver. Clo(:ing in*ormation is em+e''e' into the 'ata stream. x% re*ers to one PCI Express 8ane o* +asi( +an'-i'th; x# to a (olle(tion o* t-o PCI Express 8anes; et(.. <lso re*erre' to as x%. x#. x4. x%6 lin:. < PCMCI< stan'ar' +)ilt on the latest =0> #.0 an' PCI Express +)ses. Catho'e 9ay &)+e !igital <nalog Converter !isplay !ata Channel is an I?C +)s inter*a(e +et-een a 'isplay an' a graphi(s a'apter. !igital @is)al Inter*a(e is a vi'eo inter*a(e stan'ar' 'evelope' +y the !igital !isplay Aor:ing "ro)p 3!!A"4. Ele(tri(al Bast &ransient Ele(tromagneti( Inter*eren(e Ele(trostati( !is(harge "iga+it Ethernet =niversal 0erial >)s 0erial <& <tta(hment1 serial6inter*a(e stan'ar' *or har' 'is:s 0erial !igital @i'eo O)t is a proprietary te(hnology intro')(e' +y IntelC to a'' a''itional vi'eo signaling inter*a(es to a system. <)'io CO!EC F97$Eigh !e*inition <)'io 8o- Pin6Co)nt Inter*a(e1 a lo- spee' inter*a(e )se' *or peripheral (ir()its s)(h as 0)per I$O (ontrollers. -hi(h typi(ally (om+ine lega(y6'evi(e s)pport into a single IC. 0ystem Management >)s 8o-6@oltage !i**erential 0ignaling Got (onne(te' Got availa+le &o +e 'etermine'
x%. x#. x4. x%6 ExpressCar' C9& !<C !!C !@I EB& EMI E0! ">E =0> 0<&< 0!@O <C D97 $ E!< 8PC 0M>)s 8@!0 G.C. G.<. &.>.!.
%"hemati"s (aming Conventions

)erm
%#@ @CC @CC2 H@ 0> @CC22 0> @CC%H @CC#H
Des"ription
%# volt inp)t po-er rail. H volt inp)t po-er rail. 2.2 volt inp)t po-er rail. H volt inp)t po-er rail ')ring stan'+y. 2.2 volt inp)t po-er rail ')ring stan'+y. %.H volt a)xiliary po-er rail. #.H volt a)xiliary po-er rail.
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Copyright (oti"e
Copyright #007. COM Express PnP Initiative. <ll rights reserve'. <ll text. pi(t)res an' graphi(s are prote(te' +y (opyrights. Go (opying is permitte' -itho)t -ritten permission *rom the COM Express PnP Initiative. &he COM Express PnP Initiative has ma'e every attempt to ens)re that the in*ormation in this 'o()ment is a(()rate yet the in*ormation (ontaine' -ithin is s)pplie' Ias6isJ.
)rademar*s
Intel an' Penti)m are registere' tra'emar:s o* Intel Corporation. <M! is a tra'emar: o* <'van(e' Mi(ro !evi(es. In(. Express(ar' is a registere' tra'emar: o* Personal Comp)ter Memory Car' International <sso(iation 3PCMCI<4. PCI Express is a registere' tra'emar: o* Peripheral Component Inter(onne(t 0pe(ial Interest "ro)p 3PCI60I"4. COM Express is a registere' tra'emar: o* PCI In')stial Comp)ter Man)*a(t)rers "ro)p 3PICM"4. I?C is a registere' tra'emar: o* Philips Corporation. Compa(tBlash is a registere' tra'emar: o* Compa(tBlash <sso(iation. Ain+on' is a registere' tra'emar: o* Ain+on' Ele(troni(s Corp. <@9 is a registere' tra'emar: o* <tmel Corporation. <MICO9EK is a registere' tra'emar: o* <meri(an Megatren's In(. Mi(roso*tC. Ain'o-sC. Ain'o-s G&C. Ain'o-s CE an' Ain'o-s LPC are registere' tra'emar:s o* Mi(roso*t Corporation. @xAor:s is a registere' tra'emar: o* Ain'9iver. <ll pro')(t names an' logos are property o* their o-ners.
E#e"trostati" %ensitive Devi"e

<ll ele(troni( parts 'es(ri+e' in this 'esign g)i'e are ele(trostati( sensitive 'evi(es an' are pa(:age' a((or'ingly. !o not open or han'le a (arrier +oar' or mo')le ex(ept at an ele(trostati(6*ree -or:station. <''itionally. 'o not ship or store ele(troni( 'evi(es near strong ele(trostati(. ele(tromagneti(. magneti(. or ra'ioa(tive *iel's )nless the 'evi(e is (ontaine' -ithin its original man)*a(t)rerFs pa(:aging.
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Con"ept o! COM Express)M

&he (on(ept o* Comp)ter On Mo')les or COMs are o** the shel* te(hnology in em+e''e' (omp)ter in')stries sin(e years. < Comp)ter On Mo')le integrates all the (ore (omponents an' stan'ar' I$O inter*a(es o* a (ommon PC onto an appli(ation spe(i*i( (arrier +oar'. &he :ey a'vantage o* the COM in the em+e''e' (omp)ter in')stries is. that all high integrate'. high spee' (omponents li:e CP=. (hipsets an' memory are (om+ine' on a small mo')le *orm *a(tor *or easy a'aptation into 'i**erent appli(ations a(ross m)ltiple mar:et segments. COM Express mo')les have stan'ar'i7e' *orm *a(tors an' have spe(i*ie' pino)ts on the t-o system (onne(tors that remain the same regar'less o* the ven'or. &he COM Express mo')le re*le(ts the *)n(tional re,)irements *or a -i'e range o* em+e''e' appli(ations. &hese *)n(tions in(l)'e. +)t are not limite' to PCI Express. PCI. "raphi(s. Eigh !e*inition <)'io. parallel <&<. serial <&<. "iga+it Ethernet an' =0> #.0 ports. &-o r)gge'i7e'. shiel'e' (onne(tors provi'e the (arrier +oar' inter*a(e an' (arry all the I$O signals to an' *rom the COM Express mo')le. Carrier +oar' 'esigners (an )tili7e as little or as many o* the I$O inter*a(es as 'eeme' ne(essary. &here*ore the (arrier +oar' (an provi'e all the inter*a(e (onne(tors re,)ire' to atta(h the system to the appli(ation spe(i*i( peripherals. &his versatility allo-s the 'esigner to (reate a 'ense an' optimi7e' pa(:age. -hi(h res)lts in a more relia+le pro')(t -hile simpli*ying system integration. Most importantly COM Express appli(ations are s(ala+le. -hi(h means on(e a pro')(t has +een (reate' there is the a+ility to 'iversi*y the pro')(t range thro)gh the )se o* 'i**erent per*orman(e (lass COM Express mo')les. 0imply )npl)g one mo')le an' repla(e it -ith another. no re'esign is ne(essary.
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Contents
% Bee'+a(:................................................................................................................................... %0 # COM Express 0pe(i*i(ation Overvie-.................................................................................... %% #.% #.# #.2 #.4 Mo')le Borm Ba(tors.............................................................................................................. Mo')le &ypes Overvie-.......................................................................................................... &ype # COM Express Mo')les............................................................................................ COM Express &ype # Mo')le.............................................................................................. %% %# %2 %4
2 COM Express Conne(tors..................................................................................................... %H 2.% Mo')le Conne(tors................................................................................................................. %H 2.# Carrier >oar' Conne(tors........................................................................................................ %H 2.#.% Carrier >oar' Conne(tor Pla(ement..................................................................................... %6 4 COM Express Conne(tor Pino)t............................................................................................ %7 4.% Conne(tor Pino)t 9o-s < an' >............................................................................................. %7 4.# Conne(tor Pino)t 9o-s C an' !............................................................................................. %9 H 0ignal !es(riptions.................................................................................................................... #% H.% PCI Express 3PCIe4.............................................................................................................. H.%.% PCI Express x%. x4. xK an' x%6 Conne(tors........................................................................ H.%.# PCI Express Implementation ")i'elines.............................................................................. H.%.#.% PCI Express 9e*eren(e Clo(:........................................................................................... H.%.#.# PCI Express 9eset............................................................................................................ H.%.#.2 PCI Express 8ane Con*ig)rations...................................................................................... H.%.#.4 PCI Express Po-er 9e,)irements.................................................................................... H.# =niversal 0erial >)s................................................................................................................ H.#.% =0> Conne(tors................................................................................................................... H.#.# =0> Implementation ")i'elines........................................................................................... H.#.#.% =0> Over6C)rrent Prote(tion............................................................................................ H.#.#.# EMI$E0! Prote(tion .......................................................................................................... H.#.#.2 9o)ting Consi'erations *or =0>........................................................................................ H.#.#.4 =0> 9e*eren(e 0(hemati(s.............................................................................................. H.2 ExpressCar' ....................................................................................................................... H.2.% ExpressCar' Conne(tor....................................................................................................... H.2.# ExpressCar' Implementation ")i'elines.............................................................................. H.2.#.% ExpressCar' 9e*eren(e 0(hemati(s................................................................................. H.2.#.# 9o)ting Consi'erations *or PCI Express an' =0>............................................................ H.4 PCI Express Mini Car'............................................................................................................ H.4.% PCIe Mini Car' 0o(:et ........................................................................................................ H.4.# PCIe Mini Car' Implementation ")i'elines.......................................................................... H.4.#.% PCIe Mini Car' 9e*eren(e 0(hemati(s............................................................................. H.4.#.# 9o)ting Consi'erations *or PCI Express an' =0>............................................................ H.H PCI Express "raphi(s 5 PE".................................................................................................. H.H.% PE" Implementation ")i'elines........................................................................................... H.H.%.% PE" Con*ig)ration............................................................................................................. H.H.%.# PE" 8ane 9eversal........................................................................................................... H.H.%.2 PE" Polarity Inversion....................................................................................................... H.H.%.4 PE" 9e*eren(e 0(hemati(s.............................................................................................. ## #2 #7 #7 #K #K #9 2% 2# 22 22 22 22 24 26 27 2K 2K 2K 29 40 4# 4# 4# 42 4H 4H 4H 46 46
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H.H.%.H 9o)ting Consi'erations *or PE"........................................................................................ H.H.# 0!@O Implementation ")i'elines........................................................................................ H.H.#.% 0!@O Port Con*ig)ration.................................................................................................. H.H.#.# 0)pporte' 0!@O !evi(es................................................................................................. H.H.#.2 0!@O to !@I &ransmitter 9e*eren(e Cir()itry................................................................... H.H.#.4 9o)ting Consi'erations *or 0!@O..................................................................................... H.H.#.H 9o)ting Consi'erations *or !@I......................................................................................... H.6 Peripheral Component Inter(onne(t >)s 5 PCI....................................................................... H.6.% PCI >)s 0lot Conne(tor........................................................................................................ H.6.# PCI Implementation ")i'elines............................................................................................ H.6.#.% PCI Interr)pt <ssignment.................................................................................................. H.6.#.# PCI 0lot 9EM$"G& <ssignment........................................................................................ H.6.#.2 PCI Clo(: 0ignal................................................................................................................ H.6.#.4 PCI 9o)ting ")i'elines..................................................................................................... H.7 8o(al <rea Get-or: 5 8<G...................................................................................................... H.7.% 8<G Implementation ")i'elines........................................................................................... H.7.%.% 8<G Magneti(s Mo')les.................................................................................................... H.7.%.# 8<G &ermination an' !e(o)pling...................................................................................... H.7.%.2 8<G Component Pla(ement.............................................................................................. H.7.%.4 8<G "ro)n' Plane 0eparation.......................................................................................... H.7.%.H 8<G 8in: <(tivity an' 0pee' 8E!...................................................................................... H.7.%.6 9o)ting Consi'erations *or 8<G........................................................................................ H.7.# 8<G 9e*eren(e 0(hemati(s................................................................................................. H.K I!E Inter*a(e........................................................................................................................... H.K.% 0tan'ar' I!E Conne(tor...................................................................................................... H.K.# I!E Implementation ")i'elines............................................................................................ H.K.#.% I!E 9e*eren(e 0(hemati(s............................................................................................... H.9 0erial <&< Inter*a(e 5 0<&<................................................................................................... H.9.% 0tan'ar' 0erial <&< Conne(tors.......................................................................................... H.9.%.% 9o)ting Consi'erations *or 0erial <&<.............................................................................. H.%0 8o- Pin Co)nt Inter*a(e 6 8PC ............................................................................................. H.%0.% 8PC Implementation ")i'elines......................................................................................... H.%0.%.% 8PC >)s Clo(: 0ignal..................................................................................................... H.%0.%.# 8PC 9eset 0ignal............................................................................................................ H.%0.%.2 9o)ting Consi'erations *or 8PC Clo(:............................................................................ H.%0.# <ppli(ation Example1 8PC 0)per I$O Controller.................................................................. H.%0.#.% >oot =p Con*ig)ration..................................................................................................... H.%0.#.# 8ega(y Inter*a(es............................................................................................................ H.%0.2 <ppli(ation Example1 External Birm-are E)+..................................................................... H.%% @"< @i'eo Inter*a(e.............................................................................................................. H.%%.% @"< Conne(tor.................................................................................................................. H.%%.# @"< Implementation ")i'elines......................................................................................... H.%%.#.% 9"> <nalog 0ignals ....................................................................................................... H.%%.#.# E0NGC an' @0NGC 0ignals .......................................................................................... H.%%.#.2 !!C Inter*a(e.................................................................................................................. H.%%.#.4 E0! Prote(tion $ EMI....................................................................................................... H.%%.2 @"< 9e*eren(e 0(hemati(s............................................................................................... H.%# 8@!0 Blat Panel Inter*a(e..................................................................................................... H.%#.% 8@!0 Implementation ")i'elines....................................................................................... H.%#.%.% Conne(tor an' Ca+le Consi'erations.............................................................................. H.%#.%.# !isplay &iming Con*ig)ration........................................................................................... H.%#.%.2 >a(:light Control............................................................................................................. H.%#.%.4 9o)ting Consi'erations *or 8@!0.................................................................................... H.%#.%.H 8@!0 9e*eren(e 0(hemati(s..........................................................................................
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46 47 47 47 4K 49 49 H0 H# H2 H2 H4 HH H6 H7 HK HK H9 H9 60 60 60 6% 6# 62 62 64 6H 66 66 67 6K 6K 6K 6K 69 70 70 7# 72 72 74 74 74 74 7H 7H 76 77 77 7K 7K 7K 79
H.%#.# Em+e''e' Panel Inter*a(e 0tan'ar' 6 EPI......................................................................... K0 H.%2 &@6O)t Inter*a(e.................................................................................................................... K# H.%2.% &@6O)t Conne(tor.............................................................................................................. K# H.%2.# &@6O)t Implementation ")i'elines..................................................................................... K2 H.%2.#.% 0ignal &ermination........................................................................................................... K2 H.%2.#.# @i'eo Bilter...................................................................................................................... K2 H.%2.#.2 E0! Prote(tion................................................................................................................ K2 H.%2.#.4 9o)ting ")i'elines *or &@6O)t........................................................................................ K2 H.%2.#.H &@6O)t 9e*eren(e 0(hemati(s........................................................................................ K2 H.%4 <)'io Co'e( Inter*a(e 3<CF97$E!<4...................................................................................... K4 H.%4.% <)'io Co'e( Implementation ")i'elines............................................................................ K4 H.%4.%.% <CF97 Co'e( 9e*eren(e 0(hemati(s............................................................................... K6 H.%4.%.# <CF97$E!< Pla(ement an' 9o)ting ")i'elines.............................................................. K7 H.%H I?C >)s Inter*a(es.................................................................................................................. KK H.%H.% 0ystem Management >)s................................................................................................... K9 H.%H.# "eneral P)rpose I?C >)s................................................................................................... 90 H.%H.#.% <ppli(ation Example1 I?C 0ystem Con*ig)ration EEP9OM.............................................. 90 H.%6 Inp)t Po-er........................................................................................................................... 9% H.%6.% 0ingle O%#@ Po-er 0)pply................................................................................................. 9% H.%6.# <&L Po-er 0)pply............................................................................................................. 9# H.%6.#.% <&L Po-er Conne(tor..................................................................................................... 9# H.%6.#.# <&L Po-er Cir()itry........................................................................................................ 92 H.%6.2 Po-er =p Control............................................................................................................... 94 H.%6.2.% Po-er =p Control +y Mo')le........................................................................................... 94 H.%6.2.# Po-er6=p Control +y 0)per I$O....................................................................................... 9H H.%6.4 Po-er Management........................................................................................................... 96 H.%6.H &hermal Management........................................................................................................ 9K H.%7 Mis(ellaneo)s 0ignals........................................................................................................... 99 H.%7.% Mo')le &ype !ete(tion..................................................................................................... %00 H.%7.%.% Mo')le &ype !ete(tion 9e*eren(e 0(hemati(s............................................................. %00 H.%7.# 0pea:er O)tp)t ............................................................................................................... %0% H.%7.#.% 0pea:er O)tp)t 9e*eren(e 0(hemati(s........................................................................ %0% H.%7.2 9&C >attery Implementation............................................................................................ %0# H.%7.2.% 9&C >attery 9e*eren(e Cir()itry................................................................................... %0# H.%7.2.# 9&C >attery 8i*etime..................................................................................................... %04 6 8ayo)t !esign Constraints...................................................................................................... %0H 6.% Mi(rostrip or 0tripline............................................................................................................. %0H 6.# Printe' Cir()it >oar' 0ta(:)p Example................................................................................. %0H 7 "eneral Consi'erations *or Eigh60pee' !i**erential Inter*a(es............................................... %07 7.% 7.# 7.2 7.4 7.H 7.6 7.7 PCI Express &ra(e 9o)ting ")i'elines................................................................................. =0> &ra(e 9o)ting ")i'elines.............................................................................................. PE" &ra(e 9o)ting ")i'elines.............................................................................................. 0!@O &ra(e 9o)ting ")i'elines........................................................................................... 8<G &ra(e 9o)ting ")i'elines.............................................................................................. 0erial <&< &ra(e 9o)ting ")i'elines.................................................................................... 8@!0 &ra(e 9o)ting ")i'elines............................................................................................ %09 %%0 %%% %%# %%2 %%4 %%H
K "eneral Consi'erations *or 0ingle En'e' Inter*a(es............................................................... %%6 K.% PCI &ra(e 9o)ting ")i'elines............................................................................................... %%7 K.# I!E &ra(e 9o)ting ")i'elines............................................................................................... %%K 9 In')stry 0pe(i*i(ations............................................................................................................. %%9
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,eed&a"*
&he COM Express PnP Initiative COM Express !esign ")i'e has +een (reate' to help -hen 'esigning COM Express (ompliant (arrier +oar's. It sho)l' +e )se' in (on/)n(tion -ith the COM Express 0pe(i*i(ation as -ell as any other relevant in*ormation -ith regar's to the implementation o* the inter*a(es mentione' -ithin this 'o()ment. &he g)i'elines set *orth in this 'o()ment have +een (are*)lly tho)ght o)t +y parti(ipating engineers an' are (onsi'ere' to +e the most important *a(tors -hen 'esigning a COM Express (arrier +oar'. &he COM Express PnP Initiative is (ommitte' to helping ()stomers -ho are 'esigning COM Express (ompliant (arrier +oar's +y sharing o)r expertise an' provi'ing the +est possi+le 'o()mentation. &here*ore. -e -el(ome any s)ggestions o)r val)e' s)pporters may have -ith regar's to alternate in*ormation that sho)l' +e in(l)'e' in this COM Express !esign ")i'e. <''itionally. -e en(o)rage any *ee'+a(: a+o)t the (ontents o* this 'o()ment -ith regar's to (larity an' )n'erstan'ing. I* yo) have any s)ggestions a+o)t a''itional (ontent. or any ,)estions a+o)t the existing (ontent. (onta(t the COM Express PnP Initiative via email at in*oP(omexpress6pnp.org.
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COM Express %pe"i!i"ation Overvie.

&he COM Express spe(i*i(ation -as 'evelope' +y the PCI In')strial Comp)ter Man)*a(t)ring "ro)p 3PICM"4 in (lose (olla+oration -ith many lea'ing (ompanies a(ross the em+e''e' in')stry in or'er to *in' an implementation sol)tion to han'le )p(oming ne- high spee' serial I$Os. pro(essors an' (hipsets. COM Express spe(i*ies t-o *orm *a(tors. as -ell as *ive 'i**erent types o* (onne(tor pino)ts. &he t-o *orm *a(tors are re*erre' to as >asi( an' Exten'e' 3Big)re #6%4. &he >asi( mo')le *ootprint is %#Hmm x 9Hmm an' *o()ses on spa(e6(onstraine'. lopo-er systems -hi(h typi(ally 'o not (ontain more than one hori7ontal mo)nte' 0O6!IMM. &he Exten'e' *ootprint is slightly larger at %HHmm x %%0mm an' s)pports )p to t-o *)ll si7e. verti(ally mo)nte' !IMM mo')les to a((ommo'ate larger memory (on*ig)rations *or high6per*orman(e CP=s. (hipsets an' m)ltipro(essor systems. &he pla(ement o* the shiel'e' ##06pin (onne(tors an' the mo)nting holes are i'enti(al +et-een these t-o *ootprints. ,igure -/+ Compa"t0 1asi" and Extended ,orm ,a"tor
-.+ Modu#e ,orm ,a"tors
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-.- Modu#e )ypes Overvie.

COM Express spe(i*ies *ive mo')le types -ith 'i**erent pino)ts an' (onne(tivity *eat)res 3&a+le #6%4. &he (ommon *eat)res are )tili7e' +y all *ive mo')le types an' (onstit)te the minim)m (on*ig)ration o* a COM Express mo')le. Common *eat)res )se' +y all mo')le types1

=p to K =0> #.0 ports =p to 4 0erial <&< =p to 6 PCI Express lanes 0)pport pins *or )p to # ExpressCar's !)al #46+it 8@!0 (hannels <nalog @"< &@ O)t <C F97 'igital a)'io inter*a(e "iga+it Ethernet 8PC inter*a(e K "PIO pins Modu#e type supported !eatures
Conne"tor Ro.s
<.> <.>.C.! <.>.C.! <.>.C.! <.>.C.!
)a&#e -/+
Modu#e )ype Conne"tors --2/pin

% # 2 4 H % # # # #
C$/Express 3anes
6 ## ## 2# 2#
C$ 1us
Go Nes Nes Go Go
$DE Channe#s
Go Nes Go Nes Go
3A( orts
% % 2 % 2
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-.4 )ype - COM Express Modu#es

<s mentione' a+ove. there are *ive 'i**erent pino)t types ()rrently 'e*ine' +y the COM Express 0pe(i*i(ation. &he pre*erre' (hoi(e o* the em+e''e' (omp)ter in')stry th)s *ar is the &ype # pino)t an' there*ore the lea'ing man)*a(t)rers have (hosen to pro')(e COM Express &ype # mo')les. &his pino)t o**ers the +est +alan(e +et-een ol'er te(hnology s)(h as PCI an' Parallel <&< -hile provi'ing the latest te(hnologies in(l)'ing PCI Express. 0erial <&< an' PCI Express graphi(s. &he in*ormation (ontaine' -ithin this 'esign g)i'e re*le(ts this ()rrent tren' to-ar's COM Express &ype # mo')les +)t is also appli(a+le to all COM Express mo')le types. 0ome o* the other COM Express mo')le types may re,)ire 'esign an' (onsi'eration g)i'elines that are not ()rrently mentione' in this 'o()ment. &his in*ormation -ill +e a''e' in *)t)re.
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-.5 COM Express )ype - Modu#e

,igure -/Modu#e )ype - supported !eatures
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COM Express Conne"tors

&he inter(onne(tion +et-een COM Express mo')les an' the (arrier +oar' )ses t-o ##0 pin 0.Hmm *ine pit(h +oar'6to6+oar' (onne(tors. Ea(h single ##0 pin (onne(tor is split into t-o (onne(tor ro-s. &his res)lts in a total o* 440 pins an' 4 (onne(tor ro-s. &hese (onne(tors sho)l' +e (apa+le o* 'riving )p to 6.#H"E7 8o- @oltage !i**erential 0ignals to mat(h the re,)irements *or PCI Express signaling.
4.+ Modu#e Conne"tors

&he single ##06pin 0.Hmm pit(h 4E mo')le (onne(tor is a re(epta(le +y virt)e o* the ven'orQs te(hni(al 'e*inition o* a re(epta(le. an' to some )sers it loo:s li:e a pl)g. < potential so)r(e *or this re(epta(le +oar'6to6+oar' (onne(tor is1 K6%2%K49066 <MP$&y(o E<9! &9<N <00N BE 0.H >&> COGGEC&O9 ##0PO0 9ECEP&<C8E 4E ,igure 4/+ -D dra.ing o! the re"epta"#e modu#e "onne"tor
4.- Carrier 1oard Conne"tors

&he single ##06pin 0.Hmm pit(h (arrier +oar' (onne(tors are HE$KE pl)g in (onne(tors -ith a +oar'6to6+oar' sta(: height o* H.0mm$K.0mm. < potential so)r(e *or this pl)g6in +oar'6to6+oar' (onne(tor is1 26%K#7#H266 <MP$&y(o E<9! &9<N <00N BE 0.H >&> COGGEC&O9 ##0PO0 P8=" HE AI&E "9O=G! P8<&E 3H.0mm sta(: height4 K6%2%K49%66 <MP$&y(o E<9! &9<N <00N BE 0.H >&> COGGEC&O9 ##0PO0 P8=" KE AI&E "9O=G! P8<&E 3K.0mm sta(: height4 ,igure 4/-D dra.ing o! the "arrier &oard "onne"tor
5.0mm board-to-board stack height
8.0mm board-to-board stack height
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4.-.+
Carrier 1oard Conne"tor #a"ement

Bor (arrier +oar' 'esigns it is essential that the 'istan(e an' the alignment o* the ')al (onne(tor shape on the PC> (omply to the 'imensions 'e*ine' +y the COM Express 0pe(i*i(ation. &he alignment +et-een the t-o single (onne(tors is g)arantee' +y the (onne(tors peg holes sho-n in *ollo-ing 'ra-ings. It is very important that the PC> 'rill toleran(es o* these peg holes are -ithin the re(ommen'e' ranges mentione' +elo-. Other-ise. the inter(onne(tion +et-een mo')le an' (arrier +oar' may (a)se *)n(tional pro+lems *or the system. Instea' o* t-o single (onne(tors. a ')al (onne(tor mo'el -ith a rein*or(ing +ar spa(er (an +e )se' to ens)re the alignment +et-een the t-o (onne(tors ')ring assem+ly. <ll 'imensions o* the *ollo-ing 'ra-ings are sho-n in millimeters. ,igure 4/4 %ing#e Conne"tor hysi"a# Dimension
,igure 4/5
Dua# Conne"tor ,ootprint and A#ignment
(ote The COM !press" #n# $nitiative strongly recommends to use the following location peg hole tolerances instead of those indicated in the footprint drawings from the COM !press" %pecification as shown above&

'.(mm )'.'*+,-'.'.+mm /.+mm )'.'*+,-'.'.+mm
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COM Express Conne"tor inout

)a&#e 5/+
in
<% <# <2 <4 <H <6 <7 <K <9 <%0 <%% <%# <%2 <%4 <%H <%6 <%7 <%K <%9 <#0 <#% <## <#2 <#4 <#H <#6 <#7 <#K <#9 <20 <2% <2# <22 <24 <2H
5.+ Conne"tor inout Ro.s A and 1

Modu#e )ype - Conne"tor inout Ro.s A and 1
in
>% ># >2 >4 >H >6 >7 >K >9 >%0 >%% >%# >%2 >%4 >%H >%6 >%7 >%K >%9 >#0 >#% >## >#2 >#4 >#H >#6 >#7 >#K >#9 >20 >2% >2# >22 >24 >2H
Ro. A
"G! 3BILE!4 ">E0 M!I26 ">E0 M!I2O ">E0 8IGS%00R ">E0 8IGS%000R ">E0 M!I#6 ">E0 M!I#O ">E0 8IGSR ">E0 M!I%6 ">E0 M!I%O "G! 3BILE!4 ">E0 M!I06 ">E0 M!I0O ">E0 C&9EB 0=0 02R 0<&<0 &LO 0<&<0 &L6 0=0 04R 0<&<0 9LO 0<&<0 9L6 "G! 3BILE!4 0<&<# &LO 0<&<# &L6 0=0 0HR 0<&<# 9LO 0<&<# 9L6 ><&8OAR <&< <C&R <C 0NGC <C 90&R "G! 3BILE!4 <C >I&C8S <C 0!O=& >IO0 !I0<>8ER &E9M&9IPR
Ro. 1
"G! 3BILE!4 ">E0 <C&R 8PC B9<MER 8PC <!0 8PC <!% 8PC <!# 8PC <!2 8PC !9M0R 8PC !9M%R 8PC C8S "G! 3BILE!4 PA9>&GR 0M> CS 0M> !<& 0M> <8E9&R 0<&<% &LO 0<&<% &L6 0=0 0&<&R 0<&<% 9LO 0<&<% 9L6 "G! 3BILE!4 0<&<2 &LO 0<&<2 &L6 PA9 OS 0<&<2 9LO 0<&<2 9L6 A!& <C 0!IG# <C 0!IG% <C 0!IG0 "G! 3BILE!4 0PS9 I#C CS I#C !<& &E9MR
in
<H6 <H7 <HK <H9 <60 <6% <6# <62 <64 <6H <66 <67 <6K <69 <70 <7% <7# <72 <74 <7H <76 <77 <7K <79 <K0 <K% <K# <K2 <K4 <KH <K6 <K7 <KK <K9 <90
Ro. A
PCIE &L46 "G! PCIE &L2O PCIE &L26 "G! 3BILE!4 PCIE &L#O PCIE &L#6 "PI% PCIE &L%O PCIE &L%6 "G! "PI# PCIE &L0O PCIE &L06 "G! 3BILE!4 8@!0 <0O 8@!0 <06 8@!0 <%O 8@!0 <%6 8@!0 <#O 8@!0 <#6 8@!0 @!! EG 8@!0 <2O 8@!0 <26 "G! 3BILE!4 8@!0 < CSO 8@!0 < CS6 8@!0 I#C CS 8@!0 I#C !<& "PI2 S>! 90&R S>! <#0"<&E PCIE0 CS 9EBO PCIE0 CS 9EB6 "G! 3BILE!4
in
>H6 >H7 >HK >H9 >60 >6% >6# >62 >64 >6H >66 >67 >6K >69 >70 >7% >7# >72 >74 >7H >76 >77 >7K >79 >K0 >K% >K# >K2 >K4 >KH >K6 >K7 >KK >K9 >90
Ro. 1
PCIE 9L46 "PO# PCIE 9L2O PCIE 9L26 "G! 3BILE!4 PCIE 9L#O PCIE 9L#6 "PO2 PCIE 9L%O PCIE 9L%6 A<SE0R A<SE%R PCIE 9L0O PCIE 9L06 "G! 3BILE!4 8@!0 >0O 8@!0 >06 8@!0 >%O 8@!0 >%6 8@!0 >#O 8@!0 >#6 8@!0 >2O 8@!0 >26 8@!0 >S8& EG "G! 3BILE!4 8@!0 > CSO 8@!0 > CS6 8@!0 >S8& C&98 @CC H@ 0>N @CC H@ 0>N @CC H@ 0>N @CC H@ 0>N 90@! @"< 9E! "G! 3BILE!4
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in
<26 <27 <2K <29 <40 <4% <4# <42 <44 <4H <46 <47 <4K <49 <H0 <H% <H# <H2 <H4 <HH
Ro. A
=0>66 =0>6O =0> 6 7 OCR =0>46 =0>4O "G! 3BILE!4 =0>#6 =0>#O =0> # 2 OCR =0>06 =0>0O @CC 9&C ELC!0 PE90&R ELC!0 CPPER 8PC 0E9I9M "G! 3BILE!4 PCIE &LHO PCIE &LH6 "PI0 PCIE &L4O
in
>26 >27 >2K >29 >40 >4% >4# >42 >44 >4H >46 >47 >4K >49 >H0 >H% >H# >H2 >H4 >HH
Ro. 1
=0>76 =0>7O =0> 4 H OCR =0>H6 =0>HO "G! 3BILE!4 =0>26 =0>2O =0> 0 % OCR =0>%6 =0>%O ELC!% PE90&R ELC!% CPPER 0N0 9E0E&R C> 9E0E&R "G! 3BILE!4 PCIE 9LHO PCIE 9LH6 "PO% PCIE 9L4O
in
<9% <9# <92 <94 <9H <96 <97 <9K <99
Ro. A
90@! 90@! "PO0 90@! 90@! "G! @CC %#@ @CC %#@ @CC %#@
in
>9% >9# >92 >94 >9H >96 >97 >9K >99
Ro. 1
@"< "9G @"< >8= @"< E0NGC @"< @0NGC @"< I#C CS @"< I#C !<& &@ !<C < &@ !<C > &@ !<C C
<%00 "G! 3BILE!4 <%0% @CC %#@ <%0# @CC %#@ <%02 @CC %#@ <%04 @CC %#@ <%0H @CC %#@ <%06 @CC %#@ <%07 @CC %#@ <%0K @CC %#@ <%09 @CC %#@ <%%0 "G! 3BILE!4
>%00 "G! 3BILE!4 >%0% @CC %#@ >%0# @CC %#@ >%02 @CC %#@ >%04 @CC %#@ >%0H @CC %#@ >%06 @CC %#@ >%07 @CC %#@ >%0K @CC %#@ >%09 @CC %#@ >%%0 "G! 3BILE!4
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5.- Conne"tor inout Ro.s C and D

)a&#e 5/in
C% C# C2 C4 CH C6 C7 CK C9 C%0 C%% C%# C%2 C%4 C%H C%6 C%7 C%K C%9 C#0 C#% C## C#2 C#4 C#H C#6 C#7 C#K C#9 C20 C2% C2# C22 C24 C2H C26 C27 C2K
Modu#e )ype - Conne"tor inout Ro.s C and D

in
!% !# !2 !4 !H !6 !7 !K !9 !%0 !%% !%# !%2 !%4 !%H !%6 !%7 !%K !%9 !#0 !#% !## !#2 !#4 !#H !#6 !#7 !#K !#9 !20 !2% !2# !22 !24 !2H !26 !27 !2K
Ro. C
"G! 3BILE!4 I!E !7 I!E !6 I!E !2 I!E !%H I!E !K I!E !9 I!E !# I!E !%2 I!E !% "G! 3BILE!4 I!E !%4 I!E IO9!N I!E IO9R PCI PMER PCI "G&#R PCI 9EM#R PCI "G&%R PCI 9EM%R PCI "G&0R "G! 3BILE!4 PCI 9EM0R PCI 9E0E&R PCI <!0 PCI <!# PCI <!4 PCI <!6 PCI <!K PCI <!%0 PCI <!%# "G! 3BILE!4 PCI <!%4 PCI C$>E%R PCI PE99R PCI 8OCSR PCI !E@0E8R PCI I9!NR PCI C$>E#R
Ro. D
"G! 3BILE!4 I!E !H I!E !%0 I!E !%% I!E !%# I!E !4 I!E !0 I!E 9EM I!E IOAR I!E <CSR "G! 3BILE!4 I!E I9M I!E <0 I!E <% I!E <# I!E C0%R I!E C02R I!E 9E0E&R PCI "G&2R PCI 9EM2R "G! 3BILE!4 PCI <!% PCI <!2 PCI <!H PCI <!7 PCI C$>E0R PCI <!9 PCI <!%% PCI <!%2 PCI <!%H "G! 3BILE!4 PCI P<9 PCI 0E99R PCI 0&OPR PCI &9!NR PCI B9<MER PCI <!%6 PCI <!%K
in
CH6 CH7 CHK CH9 C60 C6% C6# C62 C64 C6H C66 C67 C6K C69 C70 C7% C7# C72 C74 C7H C76 C77 C7K C79 CK0 CK% CK# CK2 CK4 CKH CK6 CK7 CKK CK9 C90 C9% C9# C92
Ro. C
PE" 9L%6 &NPE%R PE" 9L#O PE" 9L#6 "G! 3BILE!4 PE" 9L2O PE" 9L26 90@! 90@! PE" 9L4O PE" 9L46 B<G PAMO=& PE" 9LHO PE" 9LH6 "G! 3BILE!4 PE" 9L6O PE" 9L66 0!@O !<&< PE" 9L7O PE" 9L76 "G! B<G &<CEOIG PE" 9LKO PE" 9LK6 "G! 3BILE!4 PE" 9L9O PE" 9L96 90@! "G! PE" 9L%0O PE" 9L%06 "G! PE" 9L%%O PE" 9L%%6 "G! 3BILE!4 PE" 9L%#O PE" 9L%#6 "G!
in
!H6 !H7 !HK !H9 !60 !6% !6# !62 !64 !6H !66 !67 !6K !69 !70 !7% !7# !72 !74 !7H !76 !77 !7K !79 !K0 !K% !K# !K2 !K4 !KH !K6 !K7 !KK !K9 !90 !9% !9# !92
Ro. D
PE" &L%6 &NPE#R PE" &L#O PE" &L#6 "G! 3BILE!4 PE" &L2O PE" &L26 90@! 90@! PE" &L4O PE" &L46 "G! PE" &LHO PE" &LH6 "G! 3BILE!4 PE" &L6O PE" &L66 0@!O C8S PE" &L7O PE" &L76 "G! I!E C>8I!R PE" &LKO PE" &LK6 "G! 3BILE!4 PE" &L9O PE" &L96 90@! "G! PE" &L%0O PE" &L%06 "G! PE" &L%%O PE" &L%%6 "G! 3BILE!4 PE" &L%#O PE" &L%#6 "G!
%9$%%9
COMExpressPnP !" 09
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C29 C40 C4% C4# C42 C44 C4H C46 C47 C4K C49 CH0 CH% CH# CH2 CH4 CHH
Ro. C
PCI <!%7 PCI <!%9 "G! 3BILE!4 PCI <!#% PCI <!#2 PCI C$>E2R PCI <!#H PCI <!#7 PCI <!#9 PCI <!2% PCI I9M<R PCI I9M>R "G! 3BILE!4 PE" 9L0O PE" 9L06 &NPE0R PE" 9L%O
in
!29 !40 !4% !4# !42 !44 !4H !46 !47 !4K !49 !H0 !H% !H# !H2 !H4 !HH
Ro. D
PCI <!#0 PCI <!## "G! 3BILE!4 PCI <!#4 PCI <!#6 PCI <!#K PCI <!20 PCI I9MCR PCI I9M!R PCI C8S9=GR PCI M66EG PCI C8S "G! 3BILE!4 PE" &L0O PE" &L06 PE" 8<GE 9@R PE" &L%O
in
C94 C9H C96 C97 C9K C99 C%00 C%0% C%0# C%02 C%04 C%0H C%06 C%07 C%0K C%09 C%%0
Ro. C
PE" 9L%2O PE" 9L%26 "G! 90@! PE" 9L%4O PE" 9L%46 "G! 3BILE!4 PE" 9L%HO PE" 9L%H6 "G! @CC %#@ @CC %#@ @CC %#@ @CC %#@ @CC %#@ @CC %#@ "G! 3BILE!4
in
!94 !9H !96 !97 !9K !99
Ro. D
PE" &L%2O PE" &L%26 "G! PE" EG<>8ER PE" &L%4O PE" &L%46
!%00 "G! 3BILE!4 !%0% PE" &L%HO !%0# PE" &L%H6 !%02 "G! !%04 @CC %#@ !%0H @CC %#@ !%06 @CC %#@ !%07 @CC %#@ !%0K @CC %#@ !%09 @CC %#@ !%%0 "G! 3BILE!4
COMExpressPnP !" 09
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%igna# Des"riptions
&he *ollo-ing se(tion 'es(ri+es the signals *o)n' on COM Express &ype # (onne(tors. Most o* the signals liste' in the *ollo-ing se(tions also apply to other COM Express mo')le types. &he pino)t *or (onne(tor ro-s < an' > remains the same regar'less o* the mo')le type +)t the pino)t *or (onne(tor ro-s ! an' C are 'epen'ent on the mo')le type. 9e*er to the COM Express 0pe(i*i(ation *or in*ormation a+o)t the 'i**erent pino)ts o* the mo')le types other than &ype #. &he ta+le +elo- 'es(ri+es the terminology )se' in this se(tion *or the 0ignal !es(ription ta+les. &he IRJ sym+ol at the en' o* the signal name in'i(ates that the a(tive or asserte' state o(()rs -hen the signal is at a lo- voltage level. Ahen IRJ is not present. the signal is asserte' -hen at a high voltage level. )a&#e 6/+
)erm
I$O 2.2@ I$O H@ I 2.2@ I H@ I$O 2.2@0> O 2.2@ O H@ O! P !!C PCIE =0> ">E 0<&< 9EB P!0
%igna# )a&#es )ermino#ogy Des"riptions

Des"ription
>i6'ire(tional signal 2.2@ tolerant >i6'ire(tional signal H@ tolerant Inp)t 2.2@ tolerant Inp)t H@ tolerant >i6'ire(tional 2.2@ tolerant a(tive ')ring stan'+y an' r)nning state.3'aniel. is it ne(essary to a'' something here -hi(h expli(itly says Fstan'+y state <G! r)nning stateF or is it o+vio)s any-ayT4 O)tp)t 2.2@ signal level O)tp)t H@ signal level Open 'rain o)tp)t Po-er inp)t$o)tp)t !isplay !ata Channel In (omplian(e -ith PCI Express >ase 0pe(i*i(ation. 9evision %.0a In (omplian(e -ith the =niversal 0erial >)s 0pe(i*i(ation. 9evision #.0 In (omplian(e -ith IEEE K0#.2a+ %000>ase6& "iga+it Ethernet In (omplian(e -ith 0erial <&< spe(i*i(ation. 9evision %.0a 9e*eren(e voltage o)tp)t. May +e so)r(e' *rom a mo')le po-er plane. P)ll6'o-n strap. < mo')le o)tp)t pin that is either tie' to "G! or is not (onne(te'. =se' to signal mo')le (apa+ilities 3pin6o)t type4 to the Carrier >oar'.
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6.+ C$ Express ( C$e)

PCI Express provi'es a s(ala+le. high6spee'. serial I$O point6to6point +)s (onne(tion. < PCI Express lane (onsists o* ')al simplex (hannels. ea(h implemente' as a lo-6voltage 'i**erentially 'riven transmit pair an' re(eive pair. &hey are )se' *or sim)ltaneo)s transmission in ea(h 'ire(tion. &he +an'-i'th o* a PCI Express lin: (an +e s(ale' +y a''ing signal pairs to *orm m)ltiple lanes +et-een t-o 'evi(es. &he PCI Express spe(i*i(ation 'e*ines x%. x4. xK. x%6. an' x2# lin: -i'ths. Ea(h single lane has a ra'ata trans*er rate o* #.H"+ps P %.#H"E7. &he PCI Express inter*a(e o* the COM Express &ype # mo')le (onsists o* )p to 6 lanes. ea(h -ith a re(eive an' transmit 'i**erential signal pair 'esignate' *rom PCIE 9L0 3O an' 64 to PCIE 9LH 3O an' 64 an' (orrespon'ingly *rom PCIE &L0 3O an' 64 to PCIE &LH 3O an' 64. <((or'ing to the PCI Express spe(i*i(ation. these six lanes (an +e (on*ig)re' as several PCI Express x% lin:s or to a (om+ine' x4 lin: pl)s t-o x% lin:s. &hese (on*ig)ration possi+ilities are +ase' on the COM Express mo')leFs (hipset (apa+ilities. )a&#e 6/%igna#
PCIE 9L0O PCIE 9L06 PCIE &L0O PCIE &L06 PCIE 9L%O PCIE 9L%6 PCIE &L%O PCIE &L%6 PCIE 9L#O PCIE 9L#6 PCIE &L#O PCIE &L#6 PCIE 9L2O PCIE 9L26 PCIE &L2O PCIE &L26 PCIE 9L4O PCIE 9L46 PCIE &L4O PCIE &L46 PCIE 9LHO PCIE 9LH6 PCIE &LHO PCIE &LH6 PCIE C8S 9EBO PCIE C8S 9EB6 A<SE0R
C$ Express %igna# Des"riptions

in7
>6K >69 <6K <69 >64 >6H <64 <6H >6% >6# <6% <6# >HK >H9 <HK <H9 >HH >H6 <HH <H6 >H# >H2 <H# <H2 <KK <9K >66
Des"ription
PCIe (hannel 0. 9e(eive Inp)t 'i**erential pair. PCIe (hannel 0. &ransmit O)tp)t 'i**erential pair. PCIe (hannel %. 9e(eive Inp)t 'i**erential pair. PCIe (hannel %. &ransmit O)tp)t 'i**erential pair. PCIe (hannel #.. 9e(eive Inp)t 'i**erential pair. PCIe (hannel #. &ransmit O)tp)t 'i**erential pair. PCIe (hannel 2.. 9e(eive Inp)t 'i**erential pair. PCIe (hannel 2. &ransmit O)tp)t 'i**erential pair. PCIe (hannel 4. 9e(eive Inp)t 'i**erential pair. PCIe (hannel 4. &ransmit O)tp)t 'i**erential pair. PCIe (hannel H. 9e(eive Inp)t 'i**erential pair. PCIe (hannel H. &ransmit O)tp)t 'i**erential pair. PCIe 9e*eren(e Clo(: *or 8anes 0 to H. PCIe Aa:e Event1 0i'e+an' -a:e6)p signal.
$8O
I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE O PCIE I PCIE
Comment
<sserte' +y (omponents
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6.+.+
C$ Express x+0 x50 x9 and x+: Conne"tors

Big)re H6% ill)strates the pino)t 'e*inition *or the stan'ar' x%. x4. xK an' x%6 PCI Express (onne(tors. &he 'ashe' lines in the 'iagram 'epi(t -here ea(h 'i**erent (onne(tor type en's. ,igure 6/+ C$ Express Conne"tor inout Diagram
COMExpressPnP !" 09
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&he x%6 (onne(tor )s)ally is )se' to 'rive the PCI Express "raphi(s Port 3PE"4 (onsisting o* %6 PE" lanes. -hi(h are (onne(te' to the appropriate x%6 (onne(tor pins. Bor more in*ormation a+o)t the signal 'e*inition o* the PE" port. re*er to se(tion H.H FPCI Express "raphi(s 5 PE"F. &he signal *iel' in &a+le H62 'es(ri+es the pino)t *or the stan'ar' PCI Express x%. x4. xK an' x%6 (onne(tors. )a&#e 6/4
in
%> #> 2> 4> H> 6> 7> K> 9> %0> %%> %#> %2> %4> %H> %6> %7> %K> %9> #0> #%> ##> #2> #4> #H> #6> #7> #K> #9>
C$e x+0 x50 x9 and x+: Conne"tor %igna# Des"riptions

Des"ription
%#@ po-er %#@ po-er %#@ po-er "ro)n' 0M>)s Clo(: 0M>)s !ata "ro)n' 2.2@ po-er &90&R 6 >o)n'ary 0(an &est 9eset 2.2@ a)xiliary po-er 8in: 9ea(tivation 9eserve' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 0 "ro)n'
%igna#
O%#@ O%#@ O%#@ "G! 0MC8S0 0M!<&U "G! O2.2@ V&<"%0 O2.2@a)x0 A<SER 0 90@! "G! PE&p0 PE&n0 "G!
in
%< #< 2< 4< H< 6< 7< K< 9< %0< %%< Me"hani"a# ;ey %#< %2< %4< %H< %6< %7< %K< %9< #0< #%< ##< #2< #4< #H< #6< #7< #K< #9<
%igna#
P90G&%RU O%#@ O%#@ "G! V&<"#0 V&<"2U V&<"40 V&<"H0 O2.2@ O2.2@ PE90&R0 "G! 9EBC8SO0 9EBC8S60 "G! PE9p0 PE9n0 "G! 90@! "G! PE9p% PE9n% "G! "G! PE9p# PE9n# "G! "G! PE9p2
Des"ription
Eot6Pl)g presen(e 'ete(te' %#@ po-er %#@ po-er "ro)n' &CS 6 >o)n'ary 0(an &est Clo(: &!I 5 >o)n'ary 0(an &est !ata Inp)t &!O 6 >o)n'ary 0(an &est !ata O)tp)t &M0 6 >o)n'ary 0(an &est Mo'e 0ele(t 2.2@ po-er 2.2@ po-er 9eset "ro)n' 9e*eren(e Clo(: 'i**erential pair positive signal 9e*eren(e Clo(: 'i**erential pair negative signal "ro)n' 9e(eiver 'i**erential pair positive$negative signal . 8ane 0 "ro)n' 9eserve' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane % "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane # "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane 2
P90G&#R0 Eot6Pl)g presen(e 'ete(te' "G! PE&p% PE&n% "G! "G! PE&p# PE&n# "G! "G! PE&p2 PE&n2 "G! "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane % "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane # "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 2 "ro)n'
End o! x+ Conne"tor
COMExpressPnP !" 09
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in
20> 2%> 2#> 22> 24> 2H> 26> 27> 2K> 29> 40> 4%> 4#> 42> 44> 4H> 46> 47> 4K> 49> H0> H%> H#> H2> H4> HH> H6> H7> HK> H9> 60> 6%> 6#> 62> 64> 6H> 66> 67> 6K> 69>
%igna#
"G! "G! PE&p4 PE&n4 "G! "G! PE&pH PE&nH "G! "G! PE&p6 PE&n6 "G! "G! PE&p7 PE&n7 "G! "G! PE&pK PE&nK "G! "G! PE&p9 PE&n9 "G! "G! PE&p%0 PE&n%0 "G! "G! PE&p%% PE&n%% "G! "G! PE&p%# PE&n%# "G! "G!
Des"ription
"ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 4 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane H "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 6 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 7 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane K "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane 9 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane %0 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane %% "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane %# "ro)n' "ro)n'
in
20< 2%< 2#< 22< 24< 2H< 26< 27< 2K< 29< 40< 4%< 4#< 42< 44< 4H< 46< 47< 4K< 49< H0< H%< H#< H2< H4< HH< H6< H7< HK< H9< 60< 6%< 6#< 62< 64< 6H< 66< 67< 6K< 69<
%igna#
PE9n2 "G! 90@! 90@! "G! PE9p4 PE9n4 "G! "G! PE9pH PE9nH "G! "G! PE9p6 PE9n6 "G! "G! PE9p7 PE9n7 "G! 90@! "G! PE9pK PE9nK "G! "G! PE9p9 PE9n9 "G! "G! PE9p%0 PE9n%0 "G! "G! PE9p%% PE9n%% "G! "G! PE9p%# PE9n%#
Des"ription
"ro)n' 9eserve' 9eserve' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane 4 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane H "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane 6 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane 7 "ro)n' 9eserve' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane K "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane 9 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %0 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %% "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %#
P90G&#R0 Eot6Pl)g presen(e 'ete(te'
End o! x5 Conne"tor
End o! x9 Conne"tor
COMExpressPnP !" 09
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in
70> 7%> 7#> 72> 74> 7H> 76> 77> 7K> 79> K0> K%> K#>
%igna#
PE&p%2 PE&n%2 "G! "G! PE&p%4 PE&n%4 "G! "G! PE&p%H PE&n%H "G! 90@!
Des"ription
&ransmitter 'i**erential pair positive$negative signal. 8ane %2 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane %4 "ro)n' "ro)n' &ransmitter 'i**erential pair positive$negative signal. 8ane %H "ro)n' 9eserve'
in
70< 7%< 7#< 72< 74< 7H< 76< 77< 7K< 79< K0< K%< K#<
%igna#
"G! "G! PE9p%2 PE9n%2 "G! "G! PE9p%4 PE9n%4 "G! "G! PE9p%H PE9n%H "G!
Des"ription
"ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %2 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %4 "ro)n' "ro)n' 9e(eiver 'i**erential pair positive$negative signal. 8ane %H "ro)n'
End o! x+: Conne"tor
(ote 0 1u!iliary signals. The a!illary signals are provided on the #C$ !press connectors to assist with certain system level functionality or implementations. %ome of these signals are re2uired when implementing a #C$ connector on the carrier board. 3or more information about this subject refer to the 4#C$ !press Card lectromechanical %pecification, 5ev. /./ Chapter .4.
COMExpressPnP !" 09
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6.+.-
C$ Express $mp#ementation Guide#ines
6.+.-.+ C$ Express Re!eren"e C#o"*

PCI Express 'oes not spe(i*y the external (lo(: so)r(e *or PCI Express 'evi(es. It only provi'es a %00ME7 'i**erential 0erial 9e*eren(e Clo(: 309C4. -hi(h (an +e )se' +y the internal P88 o* the PCI Express 'evi(e to generate the re,)ire' %.#H"E7 (lo(:. &he (orrespon'ing 0erial 9e*eren(e Clo(: signals 4#C$6C7865 3)4 an' 4#C$6C7865 3-4 (an +e *o)n' on the COM Express mo')le (onne(tor ro- <. pins <KK an' <K9. In an appli(ation -here more than one PCI Express slot or 'evi(e is nee'e'. the 'i**erential 0erial 9e*eren(e Clo(: signal m)st +e repli(ate' +y )sing a 7ero6'elay +)**er. Big)re H6# sho-s an example implementing the IC09!>%06 PCI Express 7ero6 'elay +)**er *rom Integrate' Cir()it 0ystems 3IC04 3http1$$---.i't.(om4. &his 7ero6'elay +)**er provi'es six 0erial 9e*eren(e Clo(: o)tp)ts in(l)'ing (lo(: re,)est *)n(tionality. &his (ir()it is also )se' on the COM Express PnP InitiativeFs eval)ation (arrier +oar' 'esign. &he PCI Express ar(hite(t)re has spe(i*ie' the (lo(: signal to +e em+e''e' in the serial 'ata stream *or syn(hroni7ation o* the t-o 'evi(es. Bor (arrier +oar' 'esigns that implement PCI Express (onne(tors *or external a''6in (ar' 'evi(es. the 09C is re,)ire' on the (onne(tor inter*a(e. External a''6in (ar's may )tili7e this 09C 'i**erential signal pair to re')(e /itter *or maintaining maxim)m 'ata trans*er rate. Bor 'etaile' in*ormation a+o)t this s)+/e(t re*er to (hapter #.% o* the FPCI Express Car' Ele(trome(hani(al 0pe(i*i(ation 9evision %.%F. ,igure 6/C$ Express C#o"* 1u!!er Cir"uitry
COMExpressPnP !" 09
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6.+.-.- C$ Express Reset

&he PCI Inter*a(e o* the COM Express mo')le shares the reset signal 4#C$65 % T94 -ith the PCI Express inter*a(e. Bor +etter signal ,)ality it is re(ommen'e' to split this reset signal into a single PCI Express reset signal an' a single PCI +)s reset signal. &here*ore a +)**er (ir()itry li:e the one sho-n in Big)re H62 sho)l' +e )se'. ,igure 6/4 C$ Express Reset 1u!!er Cir"uitry
6.+.-.4 C$ Express 3ane Con!igurations

&he lane (on*ig)ration possi+ilities o* the PCI Express inter*a(e o* a COM Express mo')le is 'epen'ent o* the mo')leFs (hipset. I* an appli(ation re,)ires a x4 PCI Express lin:. it may +e ne(essary to implement a har'-are strap on the (arrier +oar' in or'er to tell the mo')leFs (hipset to s-it(h the PCI Express lanes 062 *rom x% to x4 mo'e. &he (on*ig)ration possi+ilities an' implementation re,)irements may 'i**er 'epen'ing on the mo')leFs (hipset. 9e*er to the COM Express mo')leFs )serFs g)i'e *or a''itional in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
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6.+.-.5 C$ Express o.er Re<uirements

&o )tili7e the *)ll *)n(tionality o* PCI Express 'evi(es on the COM Express (arrier +oar'. some a''itional s)pply voltages are ne(essary +esi'e the stan'ar' s)pply voltages o* the <&L po-er s)pply. Many PCI Express 'evi(es are (apa+le o* generating -a:e )p events ')ring stan'+y operation. *or example an external PCI Express Ethernet 'evi(e that s)pports FAa:e On 8<GF *)n(tionality. &here*ore. it is ne(essary to generate an a''itional 2.2@ stan'+y voltage on the (arrier +oar' to s)pply s)(h 'evi(es ')ring stan'+y operation. &he voltage reg)lator m)st +e 'esigne' to meet the po-er re,)irements o* the (onne(te' 'evi(es. (ote 5efer to the reference schematics of the COM !press" #n# $nitiative evaluation carrier board design for an e!ample of how to implement a :.:; standby voltage regulator. Ahen an external ExpressCar' or PCIe Mini Car' 'evi(e m)st +e implemente' on the (arrier +oar'. an a''itional %.H@ s)pply voltage is re,)ire' +y the appropriate (ar' so(:ets. &he voltage reg)lator m)st +e 'esigne' to meet the po-er re,)irements o* the (onne(te' 'evi(es. (ote 5efer to the reference schematics of the COM !press" #n# $nitiative evaluation carrier board design for an e!ample of how to implement a /.+; voltage regulator.
COMExpressPnP !" 09
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&he PCI Express spe(i*i(ation 'e*ines maxim)m po-er re,)irements *or the 'i**erent PCI Express (onne(tors an'$or 'evi(es. &he po-er s)pply *or the (arrier +oar' m)st +e 'esigne' to meet these maxim)m po-er re,)irements. &a+le H64 sho-s the maxim)m ()rrent (ons)mption 'e*ine' *or the 'i**erent types o* PCI Express (onne(tors. )a&#e 6/5
o.er Rai#
%#@ 2.2@ 2.2@ 0tan'+y 3optional4 %.H@
C$e Conne"tor o.er Re<uirements

C$e x+: Conne"tor H.H< P #000)B +)l: 2.0< P %000)B +)l: 27Hm< P %H0)B +)l: %.2H<
#7Hm< 7H0m<
C$e x+0 x5 or x9 Conne"tor #.%< P %000)B +)l: 2.0< P %000)B +)l: 27Hm< P %H0)B +)l:
ExpressCard Conne"tor
C$e Mini Card Conne"tor
%.0<
220m< H00m<
Implementing PCI Express (onne(tors on the (arrier +oar' re,)ires 'istin(tive 'e(o)pling o* the (onne(tor s)pply voltages to re')(e possi+le voltage 'rops an' to provi'e an <C ret)rn path in a manner (onsistent -ith high6spee' signaling te(hni,)es. !e(o)pling (apa(itors sho)l' +e pla(e' as (lose as possi+le to the po-er pins o* the (onne(tors. &a+le H6H sho-s the minim)m re,)irements *or po-er 'e(o)pling o* the 'i**erent po-er pin types o* ea(h PCI Express (onne(tor type. )a&#e 6/6
o.er in )ype
%#@ 2.2@ 2.2@ 0tan'+y 3optional4 %.H@
C$e o.er De"oup#ing Re<uirements

C$e x+: Conne"tor 4x ##)B. #x %00nB %x %00)B. #x %00nB %x ##)B. #x %00nB ExpressCard Conne"tor C$e Mini Card Conne"tor
C$e x+0 x5 or x9 Conne"tor %x ##WB. #x %00nB %x ##)B. #x %00nB %x ##)B. #x %00nB
COMExpressPnP !" 09
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6.- =niversa# %eria# 1us

&he =niversal 0erial >)s inter*a(e o* the COM Express mo')le is (ompliant to =0> %.% as -ell as =0> #.0 spe(i*i(ation. COM Express spe(i*ies a minim)m (on*ig)ration o* 4 =0> ports )p to a maxim)m o* K *or all mo')le types. &he (orrespon'ing signals )se' to inter(onne(t stan'ar' =0> (onne(tors (an +e *o)n' on the COM Express mo')leFs (onne(tor ro-s < an' >. )a&#e 6/:
%igna#
=0>0O =0>06 =0>%O =0>%6 =0>#O =0>#6 =0>2O =0>26 =0>4O =0>46 =0>HO =0>H6 =0>6O =0>66 =0>7O =0>76 =0> 0 % OCR
=%1 %igna# Des"riptions

in7
<46 <4H >46 >4H <42 <4# >42 >4# <40 <29 >40 >29 <27 <26 >27 >26 >44
Des"ription
=0> Port 0. 'ata O or !O =0> Port 0. 'ata 6 or !6 =0> Port %. 'ata O or !O =0> Port %. 'ata 6 or !6 =0> Port #. 'ata O or !O =0> Port #. 'ata 6 or !6 =0> Port 2. 'ata O or !O =0> Port 2. 'ata 6 or !6 =0> Port 4. 'ata O or !O =0> Port 4. 'ata 6 or !6 =0> Port H. 'ata O or !O =0> Port H. 'ata 6 or !6 =0> Port 6. 'ata O or !O =0> Port 6. 'ata 6 or !6 =0> Port 7. 'ata O or !O =0> Port 7. 'ata 6 or !6 =0> over6()rrent sense. =0> ports 0 an' %. < p)ll6)p *or this line shall +e present on the mo')le. <n open 'rain 'river *rom a =0> ()rrent monitor on the Carrier >oar' may 'rive this line lo-. !o not p)ll this line high on the Carrier >oar'. =0> over6()rrent sense. =0> ports # an' 2. < p)ll6)p *or this line shall +e present on the mo')le. <n open 'rain 'river *rom a =0> ()rrent monitor on the Carrier >oar' may 'rive this line lo-. !o not p)ll this line high on the Carrier >oar'. =0> over6()rrent sense. =0> ports 4 an' H. < p)ll6)p *or this line shall +e present on the mo')le. <n open 'rain 'river *rom a =0> ()rrent monitor on the Carrier >oar' may 'rive this line lo-. !o not p)ll this line high on the Carrier >oar'. =0> over6()rrent sense. =0> ports 6 an' 7. < p)ll6)p *or this line shall +e present on the mo')le. <n open 'rain 'river *rom a =0> ()rrent monitor on the Carrier >oar' may 'rive this line lo-. !o not p)ll this line high on the Carrier >oar'.
$8O
I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I$O =0> I 2.2@ CMO0
Comment
man'atory man'atory man'atory man'atory man'atory man'atory man'atory man'atory optional optional optional optional optional optional optional optional optional
=0> # 2 OCR
<44
I 2.2@ CMO0
optional
=0> 4 H OCR
>2K
I 2.2@ CMO0
optional
=0> 6 7 OCR
<2K
I 2.2@ CMO0
optional
COMExpressPnP !" 09
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6.-.+
=%1 Conne"tors
,igure 6/5 =%1 Conne"tor
+? @6A -? Data/ 4? Data@ 5? G(D
(!ront vie.)
Connector type& T,<, = ports, female, front view )a&#e 6/>

%igna#
@CC 6!<&< O!<&< "G! % # 2 4
=%1 Conne"tor inout

in Des"ription
OH@ Po-er 0)pply =niversal 0erial >)s !ata. negative 'i**erential signal.
$8O
P H@ I$O =0>
Comment
=niversal 0erial >)s !ata. positive 'i**erential I$O =0> signal. "ro)n' P
COMExpressPnP !" 09
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6.-.-
=%1 $mp#ementation Guide#ines
6.-.-.+ =%1 Over/Current rote"tion

&he =0> 0pe(i*i(ation 'es(ri+es po-er 'istri+)tion over the =0> port. -hi(h s)pplies po-er *or =0> 'evi(es that are 'ire(tly (onne(te' to the (arrier +oar'. &here*ore. the host m)st implement over6()rrent prote(tion on the ports *or sa*ety reasons. 0ho)l' the aggregate ()rrent 'ra-n +y the 'o-nstream ports ex(ee' a permitte' val)e. the over6()rrent prote(tion (ir()it removes po-er *rom all a**e(te' 'o-nstream ports. &he over6()rrent limiting me(hanism m)st +e resetta+le -itho)t )ser me(hani(al intervention. Bor more 'etaile' in*ormation a+o)t this s)+/e(t re*er to the F=niversal 0erial >)s 0pe(i*i(ations 9evision #.0F. -hi(h (an +e *o)n' on the -e+site http1$$---.)s+.org. Over6()rrent prote(tion *or =0> ports (an +e implemente' +y )sing po-er 'istri+)tion s-it(hes on the (arrier +oar' that monitor the =0> port po-er lines. Po-er 'istri+)tion s-it(hes )s)ally have a so*t6start (ir()itry that minimi7es inr)sh ()rrent in appli(ations -here highly (apa(itive loa's are employe'. &ransient *a)lts are internally *iltere'. <''itionally. they o**er a *a)lt stat)s o)tp)t that is asserte' ')ring over6()rrent an' thermal sh)t'o-n (on'itions. &hese o)tp)ts sho)l' +e (onne(te' to the (orrespon'ing COM Express mo')les =0> over6()rrent sense signals. 0imple resetta+le Poly0-it(h 'evi(es are (apa+le o* *)l*illing the re,)irements o* =0> over6()rrent prote(tion an' there*ore (an +e )se' as a repla(ement *or po-er 'istri+)tion s-it(hes.
6.-.-.- EM$8E%D rote"tion

&o improve the EMI +ehavior o* the =0> inter*a(e. a 'esign sho)l' in(l)'e (ommon mo'e (ho:es. -hi(h have to +e pla(e' as (lose as possi+le to the =0> (onne(tor signal pins. Common mo'e (ho:es (an provi'e re,)ire' noise atten)ation +)t they also 'istort the signal ,)ality o* *)ll6spee' an' high6spee' signaling. &here*ore. (ommon mo'e (ho:es sho)l' +e (hosen (are*)lly to meet the re,)irements o* the EMI noise *iltering -hile retaining the integrity o* the =0> signals on the (arrier +oar' 'esign. &o prote(t the =0> host inter*a(e o* the mo')le *rom over6voltage (a)se' +y ele(trostati( 'is(harge 3E0!4 an' ele(tri(al *ast transients 3EB&4. lo- (apa(itan(e steering 'io'es an' transient voltage s)ppression 'io'es have to +e implemente' on the (arrier +oar' 'esign. In the =0> re*eren(e s(hemati(s Big)re H6H. this is implemente' +y )sing F090H 9ailClampCF s)rge rate' 'io'e arrays *rom 0emte(h 3http1$$semte(h.(om4.
6.-.-.4 Routing Considerations !or =%1

0ee se(tion 7.# F=0> #.0 &ra(e 9o)ting ")i'elinesF an' the COM Express spe(i*i(ation *or more in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
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6.-.-.5 =%1 Re!eren"e %"hemati"s

&he po-er 'istri+)tion *or the *o)r =0> ports in the example +elo- is han'le' +y a FMIC#0#6F ')al (hannel po-er 'istri+)tion s-it(h *rom Mi(rel 3http1$$---.mi(rel.(om4. 0ome COM Express mo')les are (apa+le o* generating -a:e )p events over the =0> inter*a(e ')ring 02 or 0H system state. 0in(e these =0> ports are po-ere' +y the H@ main po-er rail. -a:e )p *)n(tionality (annot +e s)pporte'. ,igure 6/6 =%1 Re!eren"e Cir"uitry Main o.ered
COMExpressPnP !" 09
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&he po-er 'istri+)tion s-it(hes an' the E0! prote(tion sho-n in the *ollo-ing =0> (ir()itry are po-ere' +y the H@ stan'+y voltage o* the main po-er s)pply. Een(e the (ir()itry is po-ere' ')ring the 02 an' 0H system state. &his provi'es the a+ility *or the COM Express mo')le to generate system -a:e6)p events over the =0> inter*a(e. ,igure 6/: =%1 Re!eren"e Cir"uitry %tand&y o.ered
COMExpressPnP !" 09
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6.4 ExpressCard
ExpressCar' is a small. mo')lar a''6in (ar' 'esigne' to repla(e (ommon PCMCI< an' PC Car's. It ta:es a'vantage o* the s(ala+le. high6+an'-i'th serial PCI Express an' =0> #.0 inter*a(es to provi'e m)(h higher 'ata rates. COM Express mo')les o**er s)pport *or )p to t-o ExpressCar' slots. More in*ormation a+o)t the ExpressCar' 0tan'ar' (an +e *o)n' at http1$$---.express(ar'.org. In a''ition to the signals o* a PCI Express x% lin: an' a =0> #.0 lin:. the ExpressCar' inter*a(e re,)ires the *ollo-ing (ontrol signals provi'e' +y the COM Express mo')le. &he (orrespon'ing signals (an +e *o)n' on the mo')le (onne(tor ro-s < an' >. )a&#e 6/9
%igna#
ELC!0 CPPER ELC!% CPPER ELC!0 PE90&R ELC!% PE90&R 0M> !<& 0M> CS
ExpressCard %igna# Des"riptions

in
<49 >4K <4K >47 >%4 >%2
Des"ription
ExpressCar' (apa+le (ar' re,)est. slot %. ExpressCar' (apa+le (ar' re,)est. slot #. ExpressCar' reset. slot %. ExpressCar' reset. slot #. 0ystem Management >)s (lo(: signal. 0ystem Management >)s 'ata signal.
$8O
I 2.2@ CMO0 I 2.2@ CMO0 O 2.2@ CMO0 O 2.2@ CMO0 I$O 2.2@ O! CMO0 I$O 2.2@ O! CMO0
Comment
&he s(hemati(s example 'isplaye' in Big)re H67 also )tili7es the *ollo-ing signals that are not lo(ate' on the mo')le (onne(tor ro-s <6>.
%igna#
PCIE 90&R 6
in
Des"ription
PCI Express >)s 9eset.
$8O
I 2.2@ 0tan'+y CMO0 &his signal originates *rom the PCI Express reset +)**er sho-n in Big)re H62 FPCI Express 9eset >)**er Cir()itryF &his signal originates *rom the (lo(: +)**er sho-n in Big)re H6# FPCI Express Clo(: >)**er Cir()itryF
C8S9EMCExR
9e,)est *or PCI Express 9e*eren(e Clo(:. I 2.2@ 0ee se(tion H.%.#.% FPCI Express 9e*eren(e CMO0 Clo(:F *or 'etails.
COMExpressPnP !" 09
26$%%9
6.4.+
%igna#
"G! =0> !6 =0> !O CP=0>R 90@! 90@! 0M>C8S
ExpressCard Conne"tor
)a&#e 6/B
in
% # 2 4 H 6 7 K 9 %0 %% %# %2 %4 %H %6 %7 %K %9 #0 #% ## #2 #4 #H #6
ExpressCard Conne"tor inout

Des"ription
"ro)n' =0> 0erial !ata Inter*a(e 'i**erential pair. negative signal =0> 0erial !ata Inter*a(e 'i**erential pair. positive signal =0> Inter*a(e presen(e 'ete(te' 9eserve' 9eserve' 0ystem Management >)s Clo(: 0ystem Management >)s !ata 0e(on'ary voltage so)r(e. %.H@ 0e(on'ary voltage so)r(e. %.H@ I$O 2.2@ I$O 2.2@ P %.H@ P %.H@ optional signal optional signal
$8O
P I$O =0> I$O =0> I 2.2@
0M>!<&< O%.H@ O%.H@ A<SER O2.2@<=L PE90&R O2.2@ O2.2@ C8S9EMR CPPER 9EBC8S6 9EBC8SO "G! PE9n0 PE9p0 "G! PE&n0 PE&p0 "G!
9e,)est that the host inter*a(e ret)rn to *)ll operation I 2.2@ an' respon' to PCIe <)xiliary voltage so)r(e. 2.2@ PCI Express 9eset Primary voltage so)r(e. 2.2@ Primary voltage so)r(e. 2.2@ 9e,)est that 9EBC8S +e ena+le' PCI Express inter*a(e presen(e 'ete(t PCI Express re*eren(e (lo(: 'i**erential pair. negative signal P 2.2@ I 2.2@ P 2.2@ P 2.2@ I 2.2@ I 2.2@ I PCIe
PCI Express re*eren(e (lo(: 'i**erential pair. positive I PCIe signal "ro)n' PCI Express 9e(eiver 'i**erential pair positive signal "ro)n' PCI Express &ransmitter 'i**erential pair negative signal PCI Express &ransmitter 'i**erential pair positive signal "ro)n' P I$O PCIe P I$O PCIe I$O PCIe P PCI Express 9e(eiver 'i**erential pair negative signal I$O PCIe
(ote The #C$ !press 5eference Cloc> used for !pressCard slots must be buffered as shown in section +./.../ 4#C$ !press 5eference Cloc>4.
COMExpressPnP !" 09
27$%%9
6.4.-
ExpressCard $mp#ementation Guide#ines
6.4.-.+ ExpressCard Re!eren"e %"hemati"s

Big)re H67 sho-s an example o* ho- an ExpressCar' slot (an +e (onne(te' to a COM Express (arrier +oar'. &he po-er management *or the ExpressCar' slot is han'le' +y the po-er inter*a(e s-it(h F&P0##2%F *rom &exas Instr)ments 3http1$$---.ti.(om4. &he 4C785 ?94 signal originates *rom the (lo(: +)**er (ir()itry sho-n in se(tion H.%.#.% FPCI Express 9e*eren(e Clo(:F. &he same sol)tion has +een implemente' on the COM Express PnP InitiativeFs eval)ation (arrier +oar' 'esign. ,igure 6/> ExpressCard Re!eren"e Cir"uitry
6.4.-.- Routing Considerations !or C$ Express and =%1

0ee se(tion 7.% FPCI Express &ra(e 9o)ting ")i'elinesF. 7.# F=0> #.0 &ra(e 9o)ting ")i'elinesF an' the COM Express spe(i*i(ation *or more in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
2K$%%9
6.5 C$ Express Mini Card

&he PCI Express Mini Car' a''6in (ar' is a small si7e )ni,)e *orm *a(tor optimi7e' *or mo+ile (omp)ting plat*orms e,)ippe' -ith (omm)ni(ation appli(ations s)(h as Aireless 8<G. < small *ootprint (onne(tor (an +e implemente' on the (arrier +oar' provi'ing the a+ility to insert 'i**erent remova+le PCI Express Mini Car's. =sing this approa(h gives the *lexi+ility to mo)nt an )pgra'ea+le. stan'ar'i7e' PCI Express Mini Car' 'evi(e to the (arrier +oar' -itho)t a''itional expen'it)re o* a re'esign. In a''ition to a PCI Express x% lin: an' a =0> #.0 lin:. the PCI Express Mini Car' inter*a(e )tili7es the *ollo-ing (ontrol an' reset signals. -hi(h are provi'e' +y the COM Express mo')le (onne(tor ro-s < an' >. )a&#e 6/+2
%igna#
ELC!0 PE90&R ELC!% PE90&R 0M> !<& 0M> CS
C$e Mini Card Contro# %igna# Des"riptions

in
<4K >47 >%4 >%2
Des"ription
PCIe Mini Car' 9eset. 0lot % PCIe Mini Car' 9eset. 0lot # 0ystem Management >)s Clo(: 0ignal 0ystem Management >)s !ata 0ignal
$8O
O 2.2@ CMO0 O 2.2@ CMO0 I$O 2.2@ O! CMO0 I$O 2.2@ O! CMO0
Comment
&he re*eren(e (ir()it *or PCI Express Mini Car' a'aptation 'isplaye' in Big)re H69 )ses the *ollo-ing signals that are not lo(ate' on the mo')le (onne(tor ro-s <6>.
%igna#
PCIE 90&R 6
in
Des"ription
PCI Express >)s 9eset
$8O
I 2.2@ 0tan'+y CMO0 &his signal originates *rom the PCI Express reset +)**er sho-n in Big)re H62 FPCI Express 9eset >)**er Cir()itryF &his signal originates *rom the (lo(: +)**er sho-n in Big)re H6# FPCI Express Clo(: >)**er Cir()itryF.
C8S9EMCExR 6
9e,)est *or PCI Express 0erial 9e*eren(e I 2.2@ Clo(:. Bor more 'etails see se(tion H.%.#.% FPCI CMO0 Express 9e*eren(e Clo(:F *or 'etails.
COMExpressPnP !" 09
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6.5.+
C$e Mini Card %o"*et

,igure 6/9 C$ Express Mini Card and %o"*et
< potential so)r(e *or this PCI Express Mini Car' (arrier +oar' (onne(tor is1 <MP$&y(o E<9! &9<N <00N MIGI PCI ELP9E00 COGGEC&O9 H# PO0 <rti(le Go. %7%7K2%6% )a&#e 6/++
in
% 2 H 7 9 %% %2 %H %7 %9
C$e Mini Card Conne"tor inout

in %igna#
O2.2@ "G! O%.H@ =IM PA9 =IM !<&< =IM C8S =IM 9E0E& =IM @PP "G! A !I0<>8E
%igna#
A<SER 90@! 90@! C8S9EMR "G! 9EBC8S6 9EBC8SO "G! 90@! 90@!
Des"ription
9e,)est that the host inter*a(e ret)rn to # *)ll operation an' respon' to PCIe. 9eserve' 9eserve' 9e*eren(e (lo(: re,)est signal. "ro)n' 9e*eren(e Clo(: 'i**erential pair negative signal. 9e*eren(e Clo(: 'i**erential pair positive signal. "ro)n' 9eserve' *or *)t)re se(on' =ser I'entity Mo')les inter*a(e 3=IM CK4. 9eserve' *or *)t)re se(on' =ser I'entity Mo')le inter*a(e 3=IM C44. 4 6 K
Des"ription
Primary voltage so)r(e. 2.2@. "ro)n' 0e(on'ary voltage so)r(e. %.H@. Po-er so)r(e *or =ser I'entity Mo')les 3=IM4. !ata signal *or =IM. Clo(: signal *or =IM. 9eset signal *or =IM. @aria+le s)pply voltage *or =IM. "ro)n' =se' +y the system to 'isa+le ra'io operation on a''6in (ar's that implement ra'io *re,)en(y appli(ation. PCI Express 9eset <)xiliary voltage so)r(e. 2.2@. "ro)n' 0e(on'ary voltage so)r(e. %.H@. 0ystem Management >)s Clo(:.
%0 %# %4 %6 Me"hani"a# ;ey %K #0
#% #2 #H #7 #9
"G! PE9n0 PE9p0 "G! "G!
"ro)n' 9e(eiver 'i**erential pair negative signal. 8ane 0.
## #4
PE90&R 2.2@a)x "G! O%.H@ 0M> C8S
9e(eiver 'i**erential pair positive signal. #6 8ane 0. "ro)n' "ro)n' #K 20
COMExpressPnP !" 09
40$%%9
in
2% 22 2H 27 29 4% 42 4H 47 49 H%
%igna#
PE&n0 PE&p0 "G! 90@! 90@! 90@! 90@! 90@! 90@! 90@! 90@!
Des"ription
&ransmitter 'i**erential pair negative signal. 8ane 0. &ransmitter 'i**erential pair positive 0ignal. 8ane 0. "ro)n' 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane. 9eserve' *or *)t)re se(on' PCIe lane.
in
2# 24 26 2K 40 4# 44 46 4K H0 H#
%igna#
0M> !<&< "G! =0> !6 =0> !O "G! 8E! AA<GR 8E! A8<GR 8E! AP<GR O%.H@ "G! O2.2@
Des"ription
0ystem Management >)s !ata. "ro)n' =0> 0erial !ata Inter*a(e 'i**erential pair. negative signal. =0> 0erial !ata Inter*a(e 'i**erential pair. positive signal. "ro)n' 8E! stat)s in'i(ator signals provi'e' +y the system. 8E! stat)s in'i(ator signals provi'e' +y the system. 8E! stat)s in'i(ator signals provi'e' +y the system. 0e(on'ary voltage so)r(e. %.H@. "ro)n' Primary voltage so)r(e. 2.2@.
COMExpressPnP !" 09
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6.5.-
C$e Mini Card $mp#ementation Guide#ines
6.5.-.+ C$e Mini Card Re!eren"e %"hemati"s

Big)re H69 'isplays an example o* ho- a PCIe Mini Car' so(:et (an +e (onne(te' to a COM Express (arrier +oar'. &he same sol)tion has +een implemente' on the COM Express PnP InitiativeFs eval)ation (arrier +oar' 'esign. It )tili7es the =0> Port 7 an' either PCI Express lane # or lane H 'epen'ing on the (arrier +oar' (on*ig)ration. ,igure 6/B C$e Mini Card Re!eren"e Cir"uitry
6.5.-.- Routing Considerations !or C$ Express and =%1

0ee se(tion 7.% FPCI Express &ra(e 9o)ting ")i'elinesF. 7.# F=0> #.0 &ra(e 9o)ting ")i'elinesF an' the COM Express spe(i*i(ation *or more in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
4#$%%9
6.6 C$ Express Graphi"s C EG

&he PE" Port )tili7es PCI Express lanes %662# an' is s)ita+le to 'rive a x%6 lin: *or an external high6per*orman(e PCI Express "raphi(s (ar'. It s)pports a theoreti(al +an'-i'th o* )p to 4 ">$s. Ea(h lane o* the PE" Port (onsists o* a re(eive an' transmit 'i**erential signal pair 'esignate' *rom 4# @65A'4 3O an' 64 to 4# @65A/+4 3O an' 64 an' (orrespon'ingly *rom 4# @6TA'4 3O an' 64 to 4# @6TA/+4 3O an' 64. &he (orrespon'ing signals (an +e *o)n' on the mo')le (onne(tor ro-s C an' !. &he pins o* PE" Port are share' -ith the 0erial !igital @i'eo O)tp)t 30!@O4 *)n(tionality an' may +e alternatively )se' *or t-o thir' party 0!@O (ompliant 'evi(es (onne(te' to (hannels > an' C. It is also possi+le to (onne(t a stan'ar'i7e' <'van(e' !igital !isplay Car' #n' "eneration 3<!!#4 to the x%6 PE" Port (onne(tor. -hi(h o**ers the possi+ility to s)pport a -i'e variety o* 'isplay options li:e !@I. 8@!0. &@6O)t an' E!MI. <!!# (ar's are 'ete(te' a)tomati(ally +y the graphi(s (ontroller -hen they are (onne(te' to the PE" port. )a&#e 6/+%igna#
PE" 9L0O PE" 9L06 PE" &L0O PE" &L06 PE" 9L%O PE" 9L%6 PE" &L%O PE" &L%6 PE" 9L#O PE" 9L#6 PE" &L#O PE" &L#6 PE" 9L2O PE" 9L26 PE" &L2O PE" &L26 PE" 9L4O PE" 9L46 PE" &L4O PE" &L46 PE" 9LHO PE" 9LH6 PE" &LHO PE" &LH6 PE" 9L6O PE" 9L66 PE" &L6O PE" &L66 PE" 9L7O PE" 9L76 PE" &L7O
EG %igna# Des"riptions
in7
CH# CH2 !H# !H2 CHH CH6 !HH !H6 CHK CH9 !HK !H9 C6% C6# !6% !6# C6H C66 !6H !66 C6K C69 !6K !69 C7% C7# !7% !7# C74 C7H !74
Des"ription
PE" (hannel 0. 9e(eive Inp)t 'i**erential pair. PE" (hannel 0. &ransmit O)tp)t 'i**erential pair. PE" (hannel %. 9e(eive Inp)t 'i**erential pair. PE" (hannel %. &ransmit O)tp)t 'i**erential pair. PE" (hannel #. 9e(eive Inp)t 'i**erential pair. PE" (hannel #. &ransmit O)tp)t 'i**erential pair. PE" (hannel 2. 9e(eive Inp)t 'i**erential pair. PE" (hannel 2. &ransmit O)tp)t 'i**erential pair. PE" (hannel 4. 9e(eive Inp)t 'i**erential pair. PE" (hannel 4. &ransmit O)tp)t 'i**erential pair. PE" (hannel H. 9e(eive Inp)t 'i**erential pair. PE" (hannel H. &ransmit O)tp)t 'i**erential pair. PE" (hannel 6. 9e(eive Inp)t 'i**erential pair. PE" (hannel 6. &ransmit O)tp)t 'i**erential pair. PE" (hannel 7. 9e(eive Inp)t 'i**erential pair. PE" (hannel 7. &ransmit O)tp)t
$8O
I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE
Comment
0hare' -ith1 0!@O &@C8SIGO 0!@O &@C8SIG6 0hare' -ith1 0!@O> 9E!O 0!@O> 9E!6 0hare' -ith1 0!@O> IG&O 0!@O> IG&6 0hare' -ith1 0!@O> "9GO 0!@O> "9G6 0hare' -ith1 0!@O B8!0&<88O 0!@O B8!0&<886 0hare' -ith1 0!@O> >8=O 0!@O> >8=6
0hare' -ith1 0!@O> CSO 0!@O> CS6
0hare' -ith1 0!@OC 9E!O 0!@OC 9E!6 0hare' -ith1 0!@OC IG&O 0!@OC IG&6 0hare' -ith1 0!@OC "9GO 0!@OC "9G6
0hare' -ith1 0!@OC >8=O 0!@OC >8=6
0hare' -ith1 0!@OC CSO
COMExpressPnP !" 09
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%igna#
PE" &L76 PE" 9LKO PE" 9LK6 PE" &LKO PE" &LK6 PE" 9L9O PE" 9L96 PE" &L9O PE" &L96 PE" 9L%0O PE" 9L%06 PE" &L%0O PE" &L%06 PE" 9L%%O PE" 9L%%6 PE" &L%%O PE" &L%%6 PE" 9L%#O PE" 9L%#6 PE" &L%#O PE" &L%#6 PE" 9L%2O PE" 9L%26 PE" &L%2O PE" &L%26 PE" 9L%4O PE" 9L%46 PE" &L%4O PE" &L%46 PE" 9L%HO PE" 9L%H6 PE" &L%HO PE" &L%H6 0!@O I#C C8S 0!@O I#C !<&< PE" 8<GE 9@R
in7
!7H C7K C79 !7K !79 CK% CK# !K% !K# CKH CK6 !KH !K6 CKK CK9 !KK !K9 C9% C9# !9% !9# C94 C9H !94 !9H C9K C99 !9K !99 C%0% C%0# !%0% !%0# !72 C72 !H4
Des"ription
'i**erential pair. PE" (hannel K. 9e(eive Inp)t 'i**erential pair. PE" (hannel K. &ransmit O)tp)t 'i**erential pair. PE" (hannel 9. 9e(eive Inp)t 'i**erential pair. PE" (hannel 9. &ransmit O)tp)t 'i**erential pair. PE" (hannel %0. 9e(eive Inp)t 'i**erential pair. PE" (hannel %0. &ransmit O)tp)t 'i**erential pair. PE" (hannel %%. 9e(eive Inp)t 'i**erential pair. PE" (hannel %%. &ransmit O)tp)t 'i**erential pair. PE" (hannel %#. 9e(eive Inp)t 'i**erential pair. PE" (hannel %#. &ransmit O)tp)t 'i**erential pair. PE" (hannel %2. 9e(eive Inp)t 'i**erential pair. PE" (hannel %2 &ransmit O)tp)t 'i**erential pair. PE" (hannel H. 9e(eive Inp)t 'i**erential pair. PE" (hannel H. &ransmit O)tp)t 'i**erential pair. PE" (hannel H. 9e(eive Inp)t 'i**erential pair. PE" (hannel H. &ransmit O)tp)t 'i**erential pair. I?C +ase' (ontrol signal 3(lo(:4 *or 0!@O 'evi(e. I?C +ase' (ontrol signal 3'ata4 *or 0!@O 'evi(e PCI Express "raphi(s lane reversal inp)t strap. P)ll lo- on the (arrier +oar' to reverse lane or'er.
$8O
I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE I PCIE O PCIE O #.H@ CMO0 I$O #.H@ O! CMO0 I 2.2@ CMO0
Comment
0!@OC CS6
PE" EG<>8ER
!97
PE" ena+le *)n(tion. 0trap to I 2.2@ ena+le PCI Express x%6 external CMO0 graphi(s inter*a(e. P)ll lo- to 'isa+le internal graphi(s an' ena+le the x%6 inter*a(e.
COMExpressPnP !" 09
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6.6.+
EG $mp#ementation Guide#ines
6.6.+.+ EG Con!iguration
<s mentione' earlier. the PE" Port is (omprise' o* PCI Express lanes %662#. It (an either +e )se' as a stan'ar' PCI Express x%. x#. x4. xK or x%6 lin: *or (ommon PCI Express 'evi(es or as a x%6 lin: *or PCI Express "raphi(s. &he (on*ig)ration possi+ilities o* this PE" Port is 'epen'ent on the COM Express mo')leFs (apa+ilities. -hi(h are 'etaile' in the mo')leFs )serFs g)i'e. In or'er to 'etermine the ()rrent (on*ig)ration o* the PE" Port. the COM Express spe(i*i(ation 'e*ines a lo- a(tive signal F# @6 N1B7 94. -hi(h (an +e *o)n' on the mo')les (onne(tor ro- ! pin !97. &his pin -ill +e a)tomati(ally strappe' lo- -hen an external PE" 'evi(e is present so that the integrate' graphi(s *)n(tionality on the COM Express mo')le -ill +e 'isa+le' an' the PE" Port -ill +e ena+le'. I* the pins o* the PE" port is )se' *or 0!@O *)n(tionality to inter*a(e *or example an <!!# pl)g6in (ar'. the signal F# @6 N1B7 94 shall also +e strappe' lo-.
6.6.+.- EG 3ane Reversa#

!)ring the PC> layo)t o* a COM Express (arrier +oar'. it is ,)ite possi+le that the signals +et-een the mo')les (onne(tors an' the PCI Express 'evi(e on the (arrier +oar' have to +e (rosse'. &o help layo)t 'esigners over(ome this signal (rossing s(enario. PCI Express spe(i*ies 8ane 9eversal. 8ane 9eversal is the reverse mapping o* lanes *or x# or greater lin:s. Bor example. on a lin: -ith a -i'th o* x4. -hi(h s)pports 8ane 9eversal. the &L0. &L%. &L#. &L2 o* the transmitting 'evi(e have to +e (onne(te' to 9L2. 9L#. 9L%.9L0 o* the re(eiving 'evi(e. an' vi(e versa. 0ee Big)re H6%0. ,igure 6/+2 3ane Reversa# Mode
&o a(tivate the 8ane 9eversal mo'e *or the PE" Port the COM Express spe(i*i(ation
Copyright COM Express PnP Initiative COMExpressPnP !" 09 4H$%%9
'e*ines a lo- a(tive signal F# @671N 65;94. -hi(h (an +e *o)n' on the mo')les (onne(tor ro- ! pin !H4. &his pin shall +e strappe' lo- on the (arrier +oar' to invo:e 8ane 9eversal mo'e. (ote 8eep in mind that the %C;O lines that share the # @ #ort do not support 7ane 5eversal mode.
6.6.+.4 EG o#arity $nversion

Per 'e*inition. PCI Express s)pports polarity inversion +y ea(h re(eiver on a lin:. &he re(eiver a((omplishes this +y simply inverting the re(eive' 'ata on the 'i**erential pair i* it 'ete(ts a polarity inversion ')ring the initial training se,)en(e o* the lin:. In other -or's. a lane -ill still -or: (orre(tly i* a positive signal 4# @6TA)4 *rom a transmitter is (onne(te' to the negative signal 4# @65A-4 o* the re(eiver. @i(e versa. the negative signal *rom the transmitter 4# @6TA-4 m)st +e (onne(te' to the positive signal o* the re(eiver 4# @65A)4. &he polarity inversion *eat)re o* PCI Express solves the pro+lem o* (rossing a 4# @65A)4 an' 4# @6TA)4 signal pair -ithin a lin: ')ring layo)t an' ro)ting o* the PC>. Polarity inversion 'oes not imply 'ire(tion inversion. this means the 4# @6TA4 'i**erential pairs o* the mo')le m)st still +e (onne(te' to the 4# @65A4 'i**erential signal pairs o* the 'evi(e.
6.6.+.5 EG Re!eren"e %"hemati"s

&o implement the PE" port on the stan'ar' x%6 (onne(tor o* the (arrier +oar'. re*er to the pino)t an' the inter*a(e 'es(ription o* the PCIe x%6 (onne(tor in se(tion H.%.% FPCI Express x%. x4. xK an' x%6 Conne(torF.
6.6.+.6 Routing Considerations !or EG

Bor more in*ormation a+o)t this s)+/e(t see se(tion 7.2 FPE" &ra(e 9o)ting ")i'elinesF an' the FCOM Express 0pe(i*i(ationF.
COMExpressPnP !" 09
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6.6.-
%DAO $mp#ementation Guide#ines

0!@O -as 'evelope' +y the IntelC Corporation to inter*a(e thir' party 0!@O (ompliant 'isplay (ontroller 'evi(es that may have a variety o* o)tp)t *ormats. in(l)'ing !@I. 8@!0. E!MI an' &@6O)t. &he ele(tri(al inter*a(e is +ase' on the PCI Express inter*a(e. tho)gh the proto(ol an' timings are (ompletely )ni,)e. Ahereas PCI Express r)ns at a *ixe' *re,)en(y. the *re,)en(y o* the 0!@O inter*a(e is 'epen'ent )pon the a(tive 'isplay resol)tion an' timing. <s mentione' +e*ore. the pins *or 0!@O ports > an' C are share' -ith the PE" port. &he 0!@O inter*a(e o* the COM Express mo')le *eat)res its o-n 'e'i(ate' I?C +)s 3%C;O6$.C6C78 an' %C;O6$.C6C1TD. It is )se' to (ontrol the external 0!@O 'evi(es an' to rea' o)t the 'isplay timing 'ata *rom the (onne(te' 'isplay.
6.6.-.+ %DAO ort Con!iguration

&he 0!@O port an' 'evi(e (on*ig)ration is *ixe' -ithin the IntelC "raphi(s @i'eo >IO0 implementation o* the COM Express mo')le. COM Express PnP Initiative (ompliant mo')les ass)me an I?C +)s a''ress 70h *or 0!@O 'evi(es (onne(te' to port > an' an I?C +)s a''ress o* 7#h *or 0!@O 'evi(es (onne(te' to port C. &he *ollo-ing &a+le H6%2 lists the s)pporte' 0!@O port (on*ig)rations. )a&#e 6/+4 %DAO ort Con!iguration
%DAO ort 1
Devi"e )ype $DC Address $DC 1us DDC 1us 0ele(ta+le in >IO0 0et)p Program. 70h 0!@O I?C "PIO pins 0!@O I?C "PIO pins
%DAO ort C
0ele(ta+le in >IO0 0et)p Program. 7#h 0!@O I?C "PIO pins 0!@O I?C "PIO pins
6.6.-.- %upported %DAO Devi"es

!)e to the *a(t that 0!@O is an IntelC 'e*ine' inter*a(e. the n)m+er o* s)pporte' 0!@O 'evi(es is limite' to 'evi(es that are s)pporte' +y the IntelC "raphi(s @i'eo >IO0 an' "raphi(s !river so*t-are. )a&#e 6/+5
Devi"e
CE70#%< CE720K< CE7207C CE72%# CL#H90H 0i8%26#$%264 0i8 %290
$nte#E %DAO %upported Devi"e Des"riptions

)ype
0!&@ $ E!&@ 8@!0 !@I !@I !@I6! $ &@ $ C9& !@I E!MI
Aendor
Chrontel Chrontel Chrontel Chrontel Conexant 0ili(on Image 0ili(on Image
3in*
http1$$---.(hrontel.(om http1$$---.(hrontel.(om http1$$---.(hrontel.(om http1$$---.(hrontel.(om http1$$---.(onexant.(om http1$$---.sili(onimage.(om http1$$---.sili(onimage.(om
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6.6.-.4 %DAO to DA$ )ransmitter Re!eren"e Cir"uitry

Bor in*ormation a+o)t ho- to implement a stan'ar' <!!# Car' inter*a(e on the (arrier +oar' PE" Port (onne(tor re*er to &a+le H6%# FPE" 0ignal !es(riptionsF. &he *ollo-ing (ir()itry sho-s an example o* ho- to inter(onne(t a Chrontel CE7207C 0!@O !@I transmitter 'ire(tly to the 0!@O (hannel C o* the COM Express mo')le. Ahen implementing a 0!@O 'evi(e on the (arrier +oar'. the I?C +)s signals 4%C;O6$.C6C784 an' 4%C;O6$.C6C1T4 sho)l' have a H.6:X 3YHZ4 p)ll6)p resistor (onne(te' to the #.H@ s)pply voltage. &hese p)ll6)p resistors allo- the mo')leFs graphi(s (ontroller to 'etermine i* the pins. -hi(h are share' +et-een the PE" port an' the 0!@O (hannels > an' C. are )se' *or 0!@O *)n(tionality. &he (on*ig)ration EEP9OM *or the Chrontel 0!@O transmitter CE7207C is optional. ,igure 6/++ %DAO to DA$ )ransmitter Re!eren"e Cir"uitry
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,igure 6/+-
DA$ Conne"tor Re!eren"e Cir"uitry
6.6.-.5 Routing Considerations !or %DAO

Bor the 0!@O inter(onne(tion +et-een the COM Express mo')le an' a thir'6party 0!@O (ompliant 'evi(e re*er to se(tion 7.4 F0!@O &ra(e 9o)ting ")i'elinesF an' to the layo)t an' ro)ting (onsi'erations spe(i*ie' +y the 0!@O 'evi(e man)*a(t)rer.
6.6.-.6 Routing Considerations !or DA$

&he !igital @i'eo Inter*a(e 3!@I4 is +ase' on the 'i**erential signaling metho' &!M0. &o a(hieve the *)ll per*orman(e an' relia+ility o* !@I. the &!M0 'i**erential signals +et-een the 0!@O to !@I transmitter an' the !@I (onne(tor have to +e ro)te' in pairs -ith a 'i**erential impe'an(e o* %00X. &he length o* the 'i**erential signals m)st +e :ept as (lose to the same as possi+le. &he maxim)m length 'i**eren(e m)st not ex(ee' %00mils *or any o* the pairs relative to ea(h other. 0pa(ing +et-een the 'i**erential pair tra(es sho)l' +e more than #x the tra(e -i'th to re')(e tra(e6to6tra(e (o)plings. Bor example. having -i'er gaps +et-een 'i**erential pair !@I tra(es -ill minimi7e noise (o)pling. It is also strongly a'vise' that gro)n' not +e pla(e' a'/a(ent to the !@I tra(es on the same layer. &here sho)l' +e a minim)m 'istan(e o* 20mils. Bor more in*ormation re*er to the layo)t an' ro)ting (onsi'erations as spe(i*ie' +y the man)*a(t)rer o* the 0!@O to !@I transmitter.
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6.: eriphera# Component $nter"onne"t 1us C C$

COM Express spe(i*ies that all &ype # an' 2 mo')les o**er s)pport *or the stan'ar' 2# +it. 22ME7 PCI +)s inter*a(e (ompliant to the FPCI 8o(al >)s 0pe(i*i(ation 9evision #.2F. &he (orrespon'ing PCI +)s signals (an +e *o)n' on the mo')le (onne(tor ro-s C an' !. &he PCI +)s signals (an +e )se' to implement )p to *o)r PCI +)s slots or external PCI +)s master 'evi(es on the (arrier +oar'. I* the system re,)ires more than *o)r PCI +)s master 'evi(es a PCI to PCI +ri'ge may +e implemente' on the (arrier +oar'. )a&#e 6/+6
%igna#
PCI <!0 PCI <!% PCI <!# PCI <!2 PCI <!4 PCI <!H PCI <!6 PCI <!7 PCI <!K PCI <!9 PCI <!%0 PCI <!%% PCI <!%# PCI <!%2 PCI <!%4 PCI <!%H PCI <!%6 PCI <!%7 PCI <!%K PCI <!%9 PCI <!#0 PCI <!#% PCI <!## PCI <!#2 PCI <!#4 PCI <!#H PCI <!#6 PCI <!#7 PCI <!#K PCI <!#9 PCI <!20
C$ %igna# Des"riptions
in7 Des"ription
PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s m)ltiplexe' a''ress an' 'ata lines
$8O
I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@
Comment
C#4 !## C#H !#2 C#6 !#4 C#7 !#H C#K !#7 C#9 !#K C20 !#9 C2# !20 !27 C29 !2K C40 !29 C4# !40 C42 !4# C4H !42 C46 !44 C47 !4H
I!0E8 *or slot 0 I!0E8 *or slot % I!0E8 *or slot # I!0E8 *or slot 2
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%igna#
PCI <!2% PCI C$>E0R PCI C$>E%R PCI C$>E#R PCI C$>E2R PCI !E@0E8R PCI B9<MER PCI I9!NR PCI &9!NR PCI 0&OPR PCI P<9 PCI PE99R PCI 9EM0R PCI 9EM%R PCI 9EM#R PCI 9EM2R PCI "G&0R PCI "G&%R PCI "G&#R PCI "G&2R PCI 9E0E&R PCI 8OCSR PCI 0E99R PCI PMER
in7
C4K !#6 C22 C2K C44 C26 !26 C27 !2H !24 !2# C24 C## C%9 C%7 !#0 C#0 C%K C%6 !%9 C#2 C2H !22 C%H
Des"ription
PCI +)s m)ltiplexe' a''ress an' 'ata lines PCI +)s +yte ena+le line 0. a(tive loPCI +)s +yte ena+le line %. a(tive loPCI +)s +yte ena+le line #. a(tive loPCI +)s +yte ena+le line 2. a(tive loPCI +)s !evi(e 0ele(t. a(tive lo-. PCI +)s Brame (ontrol line. a(tive lo-. PCI +)s Initiator 9ea'y (ontrol line. a(tive lo-. PCI +)s &arget 9ea'y (ontrol line. a(tive lo-. PCI +)s 0&OP (ontrol line. a(tive lo-. PCI +)s parity Parity Error1 <n external PCI 'evi(e 'rives PE99R to lo-. -hen it re(eives 'ata that has a parity error. PCI +)s master re,)est inp)t line. a(tive lo-. PCI +)s master re,)est inp)t line. a(tive lo-. PCI +)s master re,)est inp)t line. a(tive lo-. PCI +)s master re,)est inp)t line. a(tive lo-. PCI +)s master grant o)tp)t line. a(tive lo-. PCI +)s master grant o)tp)t line. a(tive lo-. PCI +)s master grant o)tp)t line. a(tive lo-. PCI +)s master grant o)tp)t line. a(tive lo-. PCI 9eset o)tp)t. a(tive lo-. PCI 8o(: (ontrol line. a(tive lo-. 0ystem Error1 0E99R may +e p)lse' a(tive +y any PCI 'evi(e that 'ete(ts a system error (on'ition.
$8O
I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I 2.2@ I 2.2@ I 2.2@ I 2.2@ O 2.2@ O 2.2@ O 2.2@ O 2.2@ O 2.2@ I$O 2.2@ I$O 2.2@
Comment
<sserte' ')ring system reset.
I 2.2@0> PCI Po-er Management Event1 PCI peripherals 'rive PMER to lo- to -a:e )p the system *rom lo-6po-er states 0%50H.
PCI C8S9=GR PCI I9M<R PCI I9M>R PCI I9MCR PCI I9M!R PCI C8S PCI M66EG
!4K C49 CH0 !46 !47 !H0 !49
>i'ire(tional pin )se' to s)pport PCI (lo(: r)n proto(ol *or mo+ile systems. PCI interr)pt re,)est line <. PCI interr)pt re,)est line >. PCI interr)pt re,)est line C. PCI interr)pt re,)est line !. PCI 22ME7 (lo(: o)tp)t.
I$O 2.2@ I 2.2@ I 2.2@ I 2.2@ I 2.2@ O 2.2@
I 2.2@ Mo')le inp)t signal that in'i(ates -hether an (arrier +oar' PCI 'evi(e is (apa+le o* 66ME7 operation. It is p)lle' to gro)n' +y (arrier +oar' 'evi(e or +y slot (ar'. i* one o* the 'evi(es are GO& (apa+le o* 66ME7 operation.
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6.:.+
C$ 1us %#ot Conne"tor

,igure 6/+4 C$ 1us %#ot +
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6.:.-
C$ $mp#ementation Guide#ines
&he COM Express PCI inter*a(e is (ompliant to the FPCI 8o(al >)s 0pe(i*i(ation 9evision #.2F. It s)pports )p to *o)r +)s master (apa+le PCI +)s slots or external PCI 'evi(es 'esigne' on the COM Express (arrier +oar'. &he PCI inter*a(e is spe(i*ie' to +e OH@ tolerant. -ith O2.2@ signaling. <ll ne(essary PCI +)s p)ll6)p resistors are in(l)'e' on the COM Express mo')le. &he signal 4$C% 74 o* ea(h external PCI 'evi(e or PCI slot has to +e (onne(te' thro)gh a ##X resistor to a separate PCI a''ress line. Bor PCI +)s slots %64. COM Express spe(i*ies the PCI a''ress lines <![#0\ to <![#2\ 3see Big)re H6%44.
6.:.-.+ C$ $nterrupt Assignment

Most o* this PCI 'evi(es only )tili7e the interr)pt signal 4$NT194. &o 'istri+)te the interr)pt so)r(e o* the 'evi(es over the interr)pt signals 4$NTB94. 4$NTC94 an' 4$NTC94. an interr)pt (ross ro)ting has to +e implemente' on the COM Express (arrier +oar' 'esign. Big)re H6%4 an' &a+le H6%6 ill)strate the PCI +)s interr)pt ro)ting *or the PCI +)s slots %64. ,igure 6/+5 C$ 1us $nterrupt Routing
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)a&#e 6/+:
Devi"e %igna#
I!0E8 IG&<R IG&>R 3i* )se'4 IG&CR 3i* )se'4 IG&CR 3i* )se'4
C$ 1us $nterrupt Routing

%#ot 8 Devi"e +
PCI <![#0\ PCI I9M[<\R PCI I9M[>\R PCI I9M[C\R PCI I9M[!\R
%#ot 8 Devi"e PCI <![#%\ PCI I9M[>\R PCI I9M[C\R PCI I9M[!\R PCI I9M[<\R
%#ot 8 Devi"e 4
PCI <![##\ PCI I9M[C\R PCI I9M[!\R PCI I9M[<\R PCI I9M[>\R
%#ot 8 Devi"e 5
PCI <![#2\ PCI I9M[!\R PCI I9M[<\R PCI I9M[>\R PCI I9M[C\R
6.:.-.- C$ %#ot REF8G() Assignment

In a''ition to this. COM Express mo')les may provi'e )p to *o)r 'e'i(ate' 9EM$"G& pairs *or +)s6master (apa+le PCI 'evi(es or PCI +)s slots. &he 9EM$"G& 'istri+)tion *or ea(h o* the *o)r s)pporte' external 'evi(es. or slots. re,)ires (ross ro)ting on the COM Express (arrier +oar' 'esign. &a+le H6%7 sho-s the PCI 9EM$"G& (ross ro)ting *or the external PCI slots %64 spe(i*ie' +y COM Express. )a&#e 6/+>
%igna# on Devi"e
I!0E8 9EM0R 3i* )se'4 9EM%R 3i* )se'4 9EM#R 3i* )se'4 9EM2R 3i* )se'4 "G&0R 3i* )se'4 "G&%R 3i* )se'4 "G&#R 3i* )se'4 "G&2R 3i* )se'4
C$ REF8G() Routing
%#ot 8 Devi"e +
PCI <![#0\ PCI 9EM[0\R PCI 9EM[%\R PCI 9EM[#\R PCI 9EM[2\R PCI "G&[0\R PCI "G&[%\R PCI "G&[#\R PCI "G&[2\R
%#ot 8 Devi"e PCI <![#%\ PCI 9EM[%\R PCI 9EM[#\R PCI 9EM[2\R PCI 9EM[0\R PCI "G&[%\R PCI "G&[#\R PCI "G&[2\R PCI "G&[0\R
%#ot 8 Devi"e 4
PCI <![##\ PCI 9EM[#\R PCI 9EM[2\R PCI 9EM[0\R PCI 9EM[%\R PCI "G&[#\R PCI "G&[2\R PCI "G&[0\R PCI "G&[%\R
%#ot 8 Devi"e 5
PCI <![#2\ PCI 9EM[2\R PCI 9EM[0\R PCI 9EM[%\R PCI 9EM[#\R PCI "G&[2\R PCI "G&[0\R PCI "G&[%\R PCI "G&[#\R
(ote The #C$ 5 ? and @NT lines with the same inde! must be considered as a pair. $t is not permitted to combine 5 ? and @NT lines with a different inde!. 1 #C$ 5 ?,@NT pair can only be used once for a single #C$ bus-master device.
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6.:.-.4 C$ C#o"* %igna#

&he COM Express 0pe(i*i(ation only s)pports a single PCI (lo(: signal (alle' 4#C$6C784 to +e )se' on the (arrier +oar'. I* there are m)ltiple 'evi(es or slots implemente' on the (arrier +oar'. a 7ero 'elay (lo(: +)**er is re,)ire' to expan' the n)m+er o* PCI (lo(:s so that ea(h 'evi(e or ea(h +)s slot -ill +e provi'e' -ith a separate (lo(: signal. Big)re H6%H sho-s an example )sing the &exas Instr)ments FC!C@B#H0HF 7ero 'elay (lo(: +)**er provi'ing *o)r o)tp)t (lo(: signals -ith sprea' spe(tr)m (ompati+ility 3http1$$---.ti.(om4. ,igure 6/+6 C$ C#o"* 1u!!er Cir"uitry
(ote $n accordance to the 4#C$ 7ocal Bus %pecification 5evision ..:4, the #C$ cloc> signal re2uires a rise and fall time Eslew rateD within /;,ns and =;,ns. The slew rate must be met across the minimum pea>-to-pea> portion of the cloc> wave form, which is between '.FF; and /.G(; for :.:; cloc> signaling. These parameters are very critical for M; and must be observed during carrier board layout when implementing the #C$ Bus.
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6.:.-.5 C$ Routing Guide#ines

Parti()lar attention m)st +e pai' to the PCI (lo(: ro)ting. &he PCI 8o(al >)s spe(i*i(ation re,)ires a maxim)m propagation 'elay *or the (lo(: signals o* %0ns -ithin a propagation s:e- o* #ns P 22ME7 +et-een the several (lo(: signals. &he COM Express 0pe(i*i(ation allo-s %.6ns Y 0.%ns P 22ME7 propagation 'elay *or the PCI (lo(: signal +eginning *rom the mo')le pin to the 'estination pin o* the PCI 'evi(e. &he propagation 'elay is 'epen'ent on the tra(e geometries. PC> sta(:6)p an' the PC> 'iele(tri( (onstant. Cal()lating )sing a typi(al propagation 'elay val)e o* %K0ps$in(h *or an internal layer (lo(: tra(e o* the (arrier +oar'. a maxim)m tra(e length o* K.KK in(hes is allo-e'. &he (lo(: tra(e *rom the COM Express mo')le to a PCI +)s slot sho)l' +e #.H in(hes shorter +e(a)se PCI (ar's are spe(i*ie' to have #.H in(hes o* (lo(: tra(e length on the (ar' itsel*. PCI (lo(: signals sho)l' +e ro)te' as a single en'e' tra(e -ith a tra(e impe'an(e o* HHX. &o re')(e EMI. a single gro)n' re*eren(e' internal layer is re(ommen'e'. &he (lo(: tra(es sho)l' +e separate' as *ar as possi+le *rom other signal tra(es. 9e*er to se(tion K.% FPCI &ra(e 9o)ting ")i'elinesF an' the FPCI 8o(al >)s 0pe(i*i(ation 9evision #.2F to get more in*ormation a+o)t this s)+/e(t. (ote 1n appro!imate value for the signal propagation delay per trace length inch can be calculated by using the following formula&
Hr4 can be determined from the dielectric constant of the #CB that is used by the following appro!imatation. 1 typical value for the dielectric constant of an 35= #CB material is =.. I Hr I =.+.

for stripline routing& for microstrip routing&
Hr4 J Hr Hr4 J '.=*+ 0 Hr ) '.F* for ..' I Hr I F.'
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6.> 3o"a# Area (et.or* C 3A(

<ll COM Express mo')les provi'e at least one 8<G port -ith the minim)m (apa+ility o* %0$%00>ase&x Ethernet an' optional %0$%00$%000>ase& "iga+it Ethernet (ompliant to the IEEE K0#.2a+ spe(i*i(ation. &he 8<G inter*a(e o* the COM Express mo')le (onsists o* 4 pairs o* lo- voltage 'i**erential pair signals 'esignate' *rom 4@B '6MC$'4 3O an' 64 to 4@B '6MC$:4 3O an' 64 pl)s a''itional (ontrol signals *or lin: a(tivity in'i(ators. &hese signals (an +e )se' to (onne(t a %0$%00$%000>ase& 9V4H (onne(tor -ith integrate' or external isolation magneti(s to the (arrier +oar'. &he (orrespon'ing 8<G 'i**erential pair an' (ontrol signals (an +e *o)n' on the mo')les (onne(tor ro-s < an' >. )a&#e 6/+9
%igna#
">E0 M!I0O ">E0 M!I06 ">E0 M!I%O ">E0 M!I%6 ">E0 M!I#O ">E0 M!I#6 ">E0 M!I2O ">E0 M!I26 ">E0 C&9EB
3A( $nter!a"e %igna# Des"riptions

in7 Des"ription
<%2 <%# <%0 <9 <7 <6 <2 <# <%4 Me'ia !epen'ent Inter*a(e 3M!I4 'i**erential pair 0. &he M!I (an operate in %000. %00. an' %0M+it$se( mo'es. Me'ia !epen'ent Inter*a(e 3M!I4 'i**erential pair %. &he M!I (an operate in %000. %00. an' %0M+it$se( mo'es. Me'ia !epen'ent Inter*a(e 3M!I4 'i**erential pair #. &he M!I (an operate in %000. %00. an' %0M+it$se( mo'es. Me'ia !epen'ent Inter*a(e 3M!I4 'i**erential pair 2. &he M!I (an operate in %000. %00. an' %0M+it$se( mo'es.
$8O
I$O ">E
Comment
&his signal pair is )se' *or all mo'es. &his signal pair is )se' *or all mo'es. &his signal pair is only )se' *or %000M+it$se( "iga+it Ethernet mo'e. &his signal pair is only )se' *or %000M+it$se( "iga+it Ethernet mo'e.
I$O ">E
I$O ">E
I$O ">E
9e*eren(e voltage *or (arrier +oar' 9EB Ethernet (hannel 0 magneti(s (enter tap. &he re*eren(e voltage is 'etermine' +y the re,)irements o* the mo')leFs PEN an' may +e as lo- as 0@ an' as high as 2.2@. &he re*eren(e voltage o)tp)t sho)l' +e ()rrent limite' on the mo')le. In a (ase in -hi(h the re*eren(e is shorte' to gro)n'. the ()rrent m)st +e limite' to #H0m< or less. Ethernet (ontroller 0 lin: in'i(ator. a(tive lo-. Ethernet (ontroller 0 %00M+it$se( lin: in'i(ator. a(tive lo-. Ethernet (ontroller 0 %000M+it$se( lin: in'i(ator. a(tive lo-. Ethernet (ontroller 0 a(tivity in'i(ator. a(tive lo-. O 2.2@ O! CMO0 O 2.2@ O! CMO0 O 2.2@ O! CMO0 O 2.2@ O! CMO0
">E0 8IGSR ">E0 8IGS%00R
<K <4
">E0 8IGS%000R <H ">E0 <C&R >#
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6.>.+
3A( $mp#ementation Guide#ines

&he most (riti(al (omponent o* the 8<G inter*a(e is the isolation magneti(s (onne(te' 'ire(tly to the M!I 'i**erential pair signals o* the COM Express mo')le. It sho)l' +e (are*)lly ,)ali*ie' *or 9et)rn 8oss. Insertion 8oss. Open Cir()it In')(tan(e. Common Mo'e 9e/e(tion an' Crosstal: Isolation to pass the IEEE (on*orman(e tests an' EMI tests. Even i* a COM Express mo')le (omplies -ith the +asi( spe(i*i(ations set *orth *or IEEE (erti*i(ation. itFs still possi+le that the overall system (o)l' *ail IEEE testing +e(a)se o* a poor ,)ality or )ns)ita+le external isolation magneti(s mo')le an'$or improper PC> layo)t o* the (arrier +oar'.
6.>.+.+ 3A( Magneti"s Modu#es

%000>ase6& Ethernet magneti(s mo')les are similar to those 'esigne' solely *or %0$%00 >ase&x Ethernet. ex(ept that there are *o)r M!I 'i**erential signal pairs instea' o* t-o. %000>ase6& magneti(s mo')les have a (enter tap pin that is (onne(te' to the re*eren(e voltage o)tp)t 4@B '6CT5 34 o* the COM Express mo')le. -hi(h +iases the (ontrollerFs o)tp)t +)**ers. Magneti(s -ith *o)r (enter tap pins may have +etter (hara(teristi(s than those -ith one or t-o (enter tap pins. &he isolation magneti(s (an +e integrate' in a 9V4H /a(:. -hi(h also provi'es a(tivity an' spee' 8E! in'i(ators. B)rthermore. they (an +e 'esigne' as 'is(rete magneti(s mo')les. -hi(h -ill +e (onne(te' to a p)re 9V4H /a(:. &a+le H6%9 lists re(ommen'e' magneti(s mo')les an' 9V4H /a(:s *or )sage on a (arrier +oar' 'esign. )a&#e 6/+B
Manu!a"turers
P)lse Engineering P)lse Engineering >el B)se P)lse Box(onn
Re"ommended 3A( Magneti" Modu#es

art (um&er )e"hno#ogy
EH007 VS060026 %0$%00$%000>ase& %0$%00$%000>ase&
Comments
!is(rete magneti(s mo')le 9V4H /a(: -ith integrate' magneti(s an' a(tivity 8E!s !is(rete magneti(s mo')le 9V4H /a(: -ith integrate' magneti(s an' =0> /a(:s 9V4H /a(: -ith integrate' magneti(s an' =0> /a(:s
0HHK6H9995P2 %0$%00$%000>ase& VA0<%P0%96E %0$%00$%000>ase& =>%%%#26VH% %0$%00$%000>ase&
!)e to the COM Express spe(i*i(ation. the minim)m 8<G inter*a(e (apa+ility o* a COM Express mo')le is %0$%00>ase&x. In or'er to +e a+le to 'rive a %0$%00$%000>ase& magneti(s mo')le. -hen the COM Express mo')le is only e,)ippe' -ith a %0$%00>ase&x (ontroller. itFs ne(essary to 'is(onne(t the *irst t-o (enter tap pins o* the magneti(s mo')le *rom the (enter re*eren(e voltage o* the COM Express mo')le. &here*ore. a har'-are /)mper or a 0X resistor sho)l' +e pla(e' on the (arrier +oar' to open the (onne(tion +et-een the (enter re*eren(e voltage signal 4@B '6CT5 34 an' these (enter tap pins o* the magneti(s mo')le. !oing this also :eeps the (arrier +oar' s(ala+le *or COM Express mo')le )pgra'es. Bor a''itional in*ormation a+o)t this s)+/e(t re*er to the 8<G re*eren(e s(hemati(s in se(tion H.7.# F8<G 9e*eren(e 0(hemati(sF.
COMExpressPnP !" 09
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6.>.+.- 3A( )ermination and De"oup#ing

In some (ases the 8<G (ontroller o* the COM Express mo')le re,)ires a termination net-or: applie' to the M!I inter*a(e signals 'esigne' on the (arrier +oar'. Een(e. a termination net-or: (an +e implemente' on the (arrier +oar' *or optional mo)nting p)rposes. &his may not +e ne(essary -hen )sing (ertain COM Express mo')les. Aith the optional termination net-or:. all *o)r M!I 'i**erential pair signals are terminate' )sing 49.9 Y%Z resistors pla(e' near the magneti(s mo')le. One si'e o* the resistors (onne(ts respe(tively to the positive an' negative M!I signal tra(e. &he other si'e o* the t-o resistors *rom the M!I signal pair (onne(t together an' to gro)n' thro)gh a parallel pair o* %0nB an' %nB (apa(itors. &he (apa(itors shall +e pla(e' as (lose as possi+le to the 49.9 Y%Z resistors )sing a -i'e tra(e. &he pa's an' tra(es *or these (omponents sho)l' +e arrange' symmetri(al so that the length an' symmetry o* the 'i**erential pairs are not 'ist)r+e'. 9e*er to the optional termination net-or: sho-n in Big)re H6%7. &o terminate the pair6to6pair (ommon mo'e impe'an(e o* C<& (a+les. a F>o+ 0mith &erminationF m)st +e implemente' on the (a+le6si'e (enter6tap. &o a(hieve this. 7H resistors are )se' +et-een the (enter6tap pins an' an EB& %nB$2:@ (apa(itor atta(he' to the termination plane. !e(o)pling on the (enter6tap o* the magneti(s mo')le sho)l' +e a+le to han'le a -i'e +an'-i'th o* noise. %00nB (apa(itors -ith lo- E,)ivalent 0eries 9esistan(e 3E094 are re(ommen'e' to +e pla(e' as (lose as possi+le to the (ontroller6si'e (enter6tap pins o* the magneti(s mo')le. 9e*er to Big)re H6%7.
6.>.+.4 3A( Component #a"ement

Ahen )sing 9V4H (onne(tors -itho)t integrate' magneti(s. the 'is(rete magneti(s mo')le has to +e pla(e' as (lose as possi+le to the 9V4H (onne(tor. &he 'istan(e +et-een the magneti(s mo')le an' 9V4H (onne(tor m)st +e less than % in(h. &his 'istan(e re,)irement m)st +e o+serve' ')ring the (arrier +oar' layo)t -hen implementing 8<G. !)e to the insertion loss +)'get o* COM Express. the overall tra(e length o* the M!I signal pairs on the (arrier +oar' sho)l' +e less than H in(hes. 0ignal atten)ation (o)l' (a)se 'ata trans*er pro+lems *or tra(es longer than H in(hes.
COMExpressPnP !" 09
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6.>.+.5 3A( Ground #ane %eparation

Isolate' separation +et-een the analog gro)n' plane an' 'igital gro)n' plane is re(ommen'e'. I* this is not implemente' properly then +a' gro)n' plane partitioning (o)l' (a)se serio)s EMI emissions an' 'egra'e analog per*orman(e ')e to +o)n(ing noise. &he plane area )n'erneath the magneti( mo')le sho)l' +e le*t voi'. &he voi' area is to :eep trans*ormer in')(e' noise a-ay *rom the po-er an' system gro)n' planes. &he isolate' gro)n'. also (alle' (hassis gro)n'. (onne(ts 'ire(tly to the *)lly shiel'e' 9V4H (onne(tor. Bor +etter isolation it is also important to maintain a gap +et-een (hassis gro)n' an' system gro)n' that is -i'er than 60mils. Bor E0! prote(tion a 2:@ high voltage (apa+ility (apa(itor is re(ommen'e' to (onne(t to this (hassis gro)n' *or E0! prote(tion. <''itionally. a *errite +ea' (an +e pla(e' parallel to the (apa(itor. ,igure 6/+: 3A( Ground #ane %eparation
6.>.+.6 3A( 3in* A"tivity and %peed 3ED

&he COM Express mo')le has *o)r 2.2@ open 'rain o)tp)ts to 'ire(tly 'rive a(tivity. spee' in'i(ation an' lin: stat)s 8E!s. &he 2.2@ stan'+y voltage sho)l' +e )se' as 8E! s)pply voltage so that the lin: a(tivity (an +e vie-e' ')ring system stan'+y state. 0in(e 8E!s are li:ely to +e integrate' into a 9V4H (onne(tor -ith integrate' magneti(s mo')le. the 8E! tra(es nee' to +e ro)te' a-ay *rom potential so)r(es o* EMI noise. Consi'er a''ing a *iltering (apa(itor per 8E! *or extremely noisy sit)ations. &he s)ggeste' val)e *or this (apa(itor is 470pB.
6.>.+.: Routing Considerations !or 3A(

9e*er to se(tion 7.H F8<G &ra(e 9o)ting ")i'elinesF an' the COM Express 0pe(i*i(ation *or more in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
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6.>.-
3A( Re!eren"e %"hemati"s

,igure 6/+> 3A( Re!eren"e Cir"uitry .ith Dis"rete Magneti"s Modu#e
COMExpressPnP !" 09
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6.9 $DE $nter!a"e

&ype # an' 4 COM Express mo')les provi'e a single (hannel I!E inter*a(e s)pporting t-o stan'ar' I!E har' 'rives or <&<PI 'evi(es -ith a maxim)m trans*er rate o* <&<%00 3=ltra6!M<6%00 -ith %00M>$s trans*er rate4. &he (orrespon'ing signals (an +e *o)n' on the mo')le (onne(tor ro-s C an' !. )a&#e 6/-2
%igna#
I!E !0 I!E !% I!E !# I!E !2 I!E !4 I!E !H I!E !6 I!E !7 I!E !K I!E !9 I!E !%0 I!E !%% I!E !%# I!E !%2 I!E !%4 I!E !%H I!E <[01#\ I!E IOAR I!E IO9R I!E 9EM I!E <CSR I!E C0%R I!E C02R I!E IO9!N
ara##e# A)A %igna# Des"riptions

Des"ription
>i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. >i'ire(tional 'ata to $ *rom I!E 'evi(e. <''ress lines to I!E 'evi(e. I$O -rite line to I!E 'evi(e. I$O rea' line to I!E 'evi(e. I!E 'evi(e !M< re,)est. It is asserte' +y the I!E 'evi(e to re,)est a 'ata trans*er. I!E 'evi(e !M< a(:no-le'ge. I!E 'evi(e (hip sele(t *or %B0h to %BBh range. I!E 'evi(e (hip sele(t *or 2B0h to 2BBh range.
in
!7 C%0 CK C4 !6 !# C2 C# C6 C7 !2 !4 !H C9 C%# CH !%26!%H !9 C%4 !K !%0 !%6 !%7 C%2
$8O
I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ I$O 2.2@ O 2.2@ O 2.2@ O 2.2@ I 2.2@ O 2.2@ O 2.2@ O 2.2@
Comment
I!E 'evi(e I$O rea'y inp)t. P)lle' lo- +y the I!E 'evi(e to I 2.2@ exten' the (y(le. 9eset o)tp)t to I!E 'evi(e. a(tive lo-. Interr)pt re,)est *rom I!E 'evi(e. O 2.2@ I 2.2@
I!E 9E0E&R !%K I!E I9M I!E C>8I!R !%# !77
Inp)t *rom o**6mo')le har'-are in'i(ating the type o* I!E I 2.2@ (a+le +eing )se'. Eigh in'i(ates a 406pin (a+le )se' *or lega(y I!E mo'es. 8o- in'i(ates that an K06pin (a+le -ith interleave' gro)n's is )se'. 0)(h a (a+le is re,)ire' *or =ltra6!M< 66. %00 mo'es.
COMExpressPnP !" 09
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6.9.+
%tandard $DE Conne"tor

&o inter*a(e stan'ar' 2.H6in(h parallel <&< 'rives. a stan'ar' #.H4mm. t-o ro-. 406pin (onne(tor in (om+ination -ith a ri++on (on')(tor (a+le is )se'. Bor slo-er 'rive spee's )p to <&<22. a normal 406pin. %.0mm6pit(h (on')(tor (a+le is s)**i(ient. Eigher trans*er rates li:e <&<66 an' <&<%00 re,)ire K06pin (on')(tor (a+les. -here the extra 40 (on')(tors are tie' to gro)n' to isolate the a'/a(ent signals *or +etter signal integrity. &he signal 4$C 6CB7$C94 o* the COM Express (arrier +oar' in'i(ates -hi(h (on')(tor (a+le is )se'. It ties to gro)n' i* a K06pin (on')(tor (a+le is (onne(te'. &his allo-s the mo')leFs >IO0 to 'etermine the maxim)m trans*er rate that (an +e 'riven an' set )p the proper 'rive parameters *or the I!E (ontroller. ,igure 6/+9 %tandard $DE Conne"tor
Connector type& =' pin, . row ..+=mm grid female )a&#e 6/-+
in
% 2 H 7 9 %% %2 %H %7 %9
%tandard $DE Conne"tor inout

in
#% #2 #H #7 #9 2% 22 2H 27 29
%igna#
E!90&R I!E !7 I!E !6 I!E !H I!E !4 I!E !2 I!E !# I!E !% I!E !0 "G!
%igna#
I!E 9EM I!E IOAR I!E IO9R I!E IO9!N I!E <CSR I!E I9M I!E <% I!E <0 I!E C0%R <C&I@I&N # 4 6 K
in %igna#
"G! I!E !K I!E !9 I!E !%0 I!E !%% I!E !%# I!E !%2 I!E !%4 I!E !%H G.C.
in
## #4 #6 #K 20 2# 24 26 2K 40
%igna#
"G! "G! "G! C0E8 "G! G.C. I!E C>8I!R I!E <# I!E C02R "G!
%0 %# %4 %6 %K #0
6.9.-
$DE $mp#ementation Guide#ines

Compa(tBlash 3CB4 (ar's -ith !M< (apa+ility re,)ire that the t-o signals 4$C 65 ?4 an' 4$C 61C894 are ro)te' to the CB (ar' so(:et on the COM Express (arrier +oar'. I* this is not 'one then some !M< (apa+le CB (ar's may not -or: +e(a)se they are not 'esigne' *or non !M< mo'e. Bor more in*ormation a+o)t this s)+/e(t re*er to the 'atasheet o* the CB (ar' or (onta(t yo)r CB (ar' man)*a(t)rer. I* t-o CB (ar's are )se' in master$slave mo'e on the same I!E (hannel. the signal 4C% 794 o* the CB (ar' so(:et that 'rives the slave CB (ar' m)st +e tie' to gro)n'. In master mo'e the 4C% 794 signal m)st +e le*t open. Big)re H6#0 sho-s a (ir()itry implementing a CB (ar' so(:et that is !M< (apa+le.
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6.9.-.+ $DE Re!eren"e %"hemati"s

,igure 6/+B $DE 52 in Header Re!eren"e Cir"uitry
(ote When using a == pin $C header, pins =/ and =. must be connected to ;CC and pins =: and == must be connected to ground. 1ll other pins are e2uivalent to a =' pin $C header. 1dditionally, decoupling capacitors should be connected to the ;CC pins. ,igure 6/-2 $DE Compa"t,#ash %o"*et Re!eren"e Cir"uitry
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6.B %eria# A)A $nter!a"e C %A)A

0erial <&< is a serial inter*a(e *or (onne(ting storage 'evi(es 3mainly har' 'is:s4 an' -as 'e*ine' to repla(e the ol' parallel <&< inter*a(e. 0<&< )ses a point6to6point serial (onne(tion +et-een the system an' the storage 'evi(e. &he *irst generation o* stan'ar' 0<&< provi'es a maxim)m e**e(tive 'ata trans*er rate o* %H0M>$s per port. Aith the se(on' generation 0<&< II. an e**e(tive trans*er rate o* )p to 200M>$s per port is possi+le. 0erial <&< is (ompletely so*t-are transparent to the I!E inter*a(e -hile provi'ing a lo-er pin (o)nt an' higher per*orman(e. <ll COM Express mo')les provi'e )p to 4 0erial <&< (hannels. ea(h -ith a re(eive an' transmit 'i**erential signal pair 'esignate' *rom 4%1T1'65A4 3O an' 64 to 4%1T1:65A4 3O an' 64 an' (orrespon'ingly *rom 4%1T1'6TA4 3O an' 64 to 4%1T1:6TAF 3O an' 64. &he appropriate signals (an +e *o)n' on the COM Express mo')le (onne(tor ro-s < an' >. )a&#e 6/-%igna#
0<&<0 9LO 0<&<0 9L6 0<&<0 &LO 0<&<0 &L6 0<&<% 9LO 0<&<% 9L6 0<&<% &LO 0<&<% &L6 0<&<# 9LO 0<&<# 9L6 0<&<# &LO 0<&<# &L6 0<&<2 9LO 0<&<2 9L6 0<&<2 &LO 0<&<2 &L6 0<&< <C&R
%eria# A)A %igna# Des"riptions

Des"ription
0erial <&< (hannel 0 9e(eive inp)t 'i**erential pair. 0erial <&< (hannel 0 &ransmit o)tp)t 'i**erential pair. 0erial <&< (hannel % 9e(eive inp)t 'i**erential pair. 0erial <&< (hannel % &ransmit o)tp)t 'i**erential pair. 0erial <&< (hannel # 9e(eive inp)t 'i**erential pair. 0erial <&< (hannel # &ransmit o)tp)t 'i**erential pair. 0erial <&< (hannel 2 9e(eive inp)t 'i**erential pair. 0erial <&< (hannel 2 &ransmit o)tp)t 'i**erential pair. 0erial <&< a(tivity 8E!. Open (olle(tor o)tp)t pin 'riven ')ring 0<&< (omman' a(tivity.
in
<%9 <#0 <%6 <%7 >%9 >#0 >%6 >%7 <#H <#6 <## <#2 >#H >#6 >## >#2 <#K
$8O
I 0<&< O 0<&< I 0<&< O 0<&< I 0<&< O 0<&< I 0<&< O 0<&< O 2.2@ CMO0 OC
Comment
COMExpressPnP !" 09
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6.B.+
%tandard %eria# A)A Conne"tors

,igure 6/-+ %eria# A)A Conne"tor Diagram
)a&#e 6/-4
%eria# A)A Conne"tor inout

in %igna# Des"ription
H 6 9L6 9LO "G! 9e(eiver 'i**erential pair negative signal 9e(eiver 'i**erential pair positive signal "ro)n'
in %igna# Des"ription
% # 2 4 "G! &LO &L6 "G! "ro)n' &ransmitter 'i**erential pair positive signal "ro)n'
&ransmitter 'i**erential pair negative signal 7
)a&#e 6/-5
ins
%.#.2 4.H.6 7.K.9
%eria# A)A o.er Conne"tor inout

Des"ription
2.2@ po-er s)pply "ro)n' H@ po-er s)pply
%igna#
O2.2@ "G! OH@
ins
%0.%%.%# %2.%4.%H
%igna#
"G! O%#@
Des"ription
"ro)n' %#@ po-er s)pply
6.B.+.+ Routing Considerations !or %eria# A)A

0ee se(tion 7.6 F0erial <&< &ra(e 9o)ting ")i'elinesF an' the COM Express 0pe(i*i(ation *or more in*ormation a+o)t this s)+/e(t.
COMExpressPnP !" 09
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6.+2 3o. in Count $nter!a"e / 3 C

&he 8o- Pin Co)nt Inter*a(e -as 'e*ine' +y the Intel C Corporation to *a(ilitate the in')stries transition to-ar' lega(y *ree systems. It allo-s the integration o* lo-6+an'-i'th lega(y I$O (omponents -ithin the system. -hi(h are typi(ally provi'e' +y a 0)per I$O (ontroller. B)rthermore. it (an +e )se' to inter*a(e Birm-are E)+s. &r)ste' Plat*orm Mo')le 3&PM4 'evi(es an' Em+e''e' Controller sol)tions. !ata trans*er on the 8PC +)s is implemente' over a 4 +it seriali7e' 'ata inter*a(e. -hi(h )ses a 22ME7 8PC +)s (lo(:. Bor more in*ormation a+o)t 8PC +)s re*er to the FIntel C 8o- Pin Co)nt Inter*a(e 0pe(i*i(ation 9evision %.%F. 0in(e COM Express is 'esigne' to +e a lega(y *ree stan'ar' *or em+e''e' mo')les. it 'oes not s)pport lega(y *)n(tionality s)(h as P0$# :ey+oar'$mo)se. serial an' parallel ports. Instea' it provi'es an 8PC inter*a(e that (an +e )se' to a'' peripheral 'evi(es to the (arrier +oar' 'esign. &he re')(e' pin (o)nt o* the 8PC inter*a(e ma:es it easy to implement s)(h 'evi(es. <ll (orrespon'ing signals (an +e *o)n' on the mo')les (onne(tor ro-s < an' >. )a&#e 6/-6
%igna#
8PC 0E9I9M 8PC B9<MER 8PC 8PC 8PC 8PC <!0 <!% <!# <!2
3 C $nter!a"e %igna# Des"riptions

in Des"ription
8PC seriali7e' I9M. 8PC *rame in'i(ates start o* a ne- (y(le or termination o* a +ro:en (y(le. 8PC m)ltiplexe' (omman'. a''ress an' 'ata.
$8O
I$O 2.2@ CMO0 O 2.2@ CMO0 I$O 2.2@ CMO0
Comment
<H0 >2 >4 >H >6 >7 >K >9 >%0
8PC !9M0R 8PC !9M%R 8PC C8S
8PC en(o'e' !M<$>)s master re,)est. 8PC (lo(: o)tp)t 22ME7.
I 2.2@ CMO0 O 2.2@ CMO0
(ote $mplementing e!ternal 7#C devices on the COM !press" carrier board always re2uires customiKation of the COM !press" module4s B$O% in order to support basic initialiKation for the 7#C device. Otherwise the functionality of 7#C device will not be supported by a #lugL#lay or 1C#$ capable system.
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6.+2.+
3 C $mp#ementation Guide#ines
6.+2.+.+ 3 C 1us C#o"* %igna#

COM Express spe(i*ies a single 8PC re*eren(e (lo(: signal (alle' 47#C6C784 on the mo')les (onne(tor ro- > pin >%0. I* more than one 8PC (lo(: signal is re,)ire' on the (arrier +oar' to s)pply several 8PC 'evi(es. a 7ero 'elay +)**er m)st +e )se' to expan' the n)m+er o* 8PC (lo(: lines. Big)re H6## sho-s an example o* ho- to implement a Cypress FCN#20HF 7ero 'elay (lo(: +)**er -ith *o)r o)tp)t (lo(: signals 3http1$$---.(ypress.(om4. &his (ir()itry is also )se' on the COM Express PnP InitiativeFs eval)ation (arrier +oar' 'esign. ,igure 6/-3 C C#o"* 1u!!er Re!eren"e Cir"uitry
6.+2.+.- 3 C Reset %igna#

&he 8PC inter*a(e sho)l' )se the signal 4CB65 % T94 as reset inp)t. &his signal is iss)e' +y the COM Express mo')le as a res)lt o* a lo- 4%M%65 % T94, a lo4#W56O84 or a -at(h'og timeo)t event. I* there are m)ltiple 8PC 'evi(es implemente' on the (arrier +oar'. it is re(ommen'e' to split the signal 4CB65 % T94 so that ea(h 8PC 'evi(e -ill +e provi'e' -ith a separate reset signal. &here*ore a +)**er (ir()itry li:e the one sho-n in Big)re H6#2 sho)l' +e )se'. ,igure 6/-4 3 C Reset 1u!!er Re!eren"e Cir"uitry
6.+2.+.4 Routing Considerations !or 3 C C#o"*

&he 8PC (lo(: implementation sho)l' *ollo- the ro)ting g)i'elines *or the PCI (lo(: 'e*ine' in the COM Express spe(i*i(ation an' the FPCI 8o(al >)s 0pe(i*i(ation 9evision #.2F. In a''ition to this re*er to se(tion K.% FPCI &ra(e 9o)ting ")i'elinesF.
COMExpressPnP !" 09
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6.+2.-
App#i"ation Examp#e? 3 C %uper $8O Contro##er

0ome COM Express mo')les )tili7e a >IO0 that (ontains +)ilt6in s)pport *or an external Ain+on' AK26#7E" 8PC 0)per I$O (ontroller 3http1$$---.-in+on'6)sa.(om4 that (an +e implemente' on the (arrier +oar'. &he +ase a''ress *or this 0)per I$O sho)l' +e 0x#E to +e s)re that the lega(y 'evi(es (an +e initiali7e' +y the >IO0. &he implementation o* this 'evi(e on the COM Express (arrier +oar' -ill provi'e lega(y inter*a(es s)(h as P0$# :ey+oar'$mo)se. *loppy port. t-o serial ports 3COM% an' COM#4 an' one parallel port 38P&%4. &he other *)n(tions o* this 0)per I$O (ontroller are not s)pporte'. ,igure 6/-5 'in&ond '94:->HG 3 C %uper $8O Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.+2.-.+ 1oot =p Con!iguration

&he 'e*a)lt (on*ig)ration o* the Ain+on' AK26#7 8PC 0)per I$O (ontroller ')ring po-er6on (an +e implemente' +y har'-are strap options. &he har'-are strap pins are lo(ate' on the serial port inter*a(e o* the 0)per I$O (ontroller. &hey (an +e ena+le' +y pla(ing a 4.7:X p)ll6)p resistor +et-een OH@ s)pply voltage an' one o* the 'e'i(ate' har'-are strap pins. Big)re H6#H sho-s the +oot strap (on*ig)ration options *or the Ain+on' AK26#7E" 8PC 0)per I$O (ontroller. ,igure 6/-6 '94:->HG 3 C %uper $8O 1oot %trap Con!iguration
6.+2.-.- 3ega"y $nter!a"es

&he *ollo-ing *ig)res 'isplay re*eren(e (ir()itries *or the lega(y I$O inter*a(es s)(h as P0$# :ey+oar'$mo)se. 90#2# serial port. parallel port an' *loppy port (onne(te' to the Ain+on' AK26#7E" 0)per I$O (ontroller. &he P0$# (onne(tor has to +e po-ere' )p +y the OH@ stan'+y voltage to s)pport :ey+oar' an' mo)se -a:e )p *)n(tionality *rom lopo-er system states 30% an' 024. Bor E0! prote(tion. lo- (apa(itan(e steering 'io'es an' &@0 'io'es have to +e implemente' on the (arrier +oar' 'esign. &his (an +e a(hieve' +y )sing 090H 9ailClampC s)rge rate' 'io'e arrays *rom 0emte(h 3http1$$---.semte(h.(om4 or similar (omponents. ,igure 6/-: %8- ;ey&oard and Mouse Re!eren"e Cir"uitry
COMExpressPnP !" 09
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,igure 6/->
R%-4- %eria# ort Re!eren"e Cir"uitry
,igure 6/-9
ara##e# ort 3 )+ Re!eren"e Cir"uitry
,igure 6/-B
,#oppy ort Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.+2.4
App#i"ation Examp#e? Externa# ,irm.are Hu&
&he 8PC +)s inter*a(e on COM Express mo')les o**ers the possi+ility to +oot the mo')le )sing >IO0 (o'e programme' into an external *irm-are h)+ 3BAE4. &he external BAE (an +e implemente' on the (arrier +oar'. < har'-are /)mper m)st +e provi'e' on the (arrier +oar' to 'isa+le the mo')leFs on+oar' BAE an' to ena+le the external BAE. &he (orrespon'ing signal FB$O%6C$%1B7 94 (an +e *o)n' on the mo')leFs (onne(tor ro- < pin <24. Big)re H620 sho-s a re*eren(e (ir()itry *or an external 2#6pin P8CC BAE so(:et. ,igure 6/42 Externa# ,irm.are Hu& Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.++ AGA Aideo $nter!a"e

COM Express s)pports an analog @"< 9"> inter*a(e to 'rive stan'ar' @"< monitors -ith !isplay !ata Control s)pport 3!!C4 *or monitor (apa+ility i'enti*i(ation. &he (orrespon'ing signals (an +e *o)n' on the COM Express mo')le (onne(tor ro- >. )a&#e 6/-:
%igna#
@"< 9E! @"< "9G @"< >8= @"< E0NGC @"< @0NGC @"< I#C CS
AGA %igna# Des"riptions

Des"ription
9e' (omponent o* analog !<C monitor o)tp)t. 'esigne' to 'rive a 27.H] e,)ivalent loa'.
in
>K9 >9% >9# >92 >94 >9H
$8O
O <nalog
Comment
<nalog o)tp)t <nalog o)tp)t <nalog o)tp)t
"reen (omponent o* analog !<C monitor o)tp)t. O <nalog 'esigne' to 'rive a 27.H] e,)ivalent loa'. >l)e (omponent o* analog !<C monitor o)tp)t. 'esigne' to 'rive a 27.H] e,)ivalent loa'. Eori7ontal syn( o)tp)t to @"< monitor. @erti(al syn( o)tp)t to @"< monitor. !!C (lo(: line 3I?C port 'e'i(ate' to i'enti*y @"< monitor (apa+ilities4. !!C 'ata line. O <nalog O 2.2@ CMO0 O 2.2@ CMO0 I$O 2.2@ CMO0 I$O 2.2@ CMO0
@"< I#C !<& >96
6.++.+
AGA Conne"tor
,igure 6/4+ AGA Conne"tor D/%=1+6
)a&#e 6/->
in %igna#
% 2 H 7 9 %% %2 %H 9E! >8=E "G! "G!
AGA Conne"tor inout

Des"ription
<nalog !<C o)tp)t *or re' signal (omponent. <nalog !<C o)tp)t *or +l)e signal (omponent. !igital gro)n'. # 4 6 %0 %# %4
in
%igna#
"9EEG G.C. "G! "G! "G!
Des"ription
<nalog !<C o)tp)t *or green signal (omponent. Got (onne(te'. <nalog gro)n' *or re' (omponent. <nalog gro)n' *or +l)e (omponent. !igital gro)n'.
<nalog gro)n' *or green (omponent. K
!!C POAE9 H@ !!C s)pply voltage *or monitor EEP9OM. G.C. E0NGC !!C C8S Got (onne(te'. Eori7ontal syn( signal. !!C (lo(: line 3I?C port 'e'i(ate' to i'enti*y @"< monitor (apa+ilities4.
!!C !<& !!C 'ata line 3I?C port 'e'i(ate' to i'enti*y @"< monitor (apa+ilities4. @0NGC @erti(al syn( signal.
COMExpressPnP !" 09
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6.++.-
AGA $mp#ementation Guide#ines
6.++.-.+ RG1 Ana#og %igna#s

&he 9"> signal inter*a(e o* the COM Express mo')le (onsists o* three i'enti(al K6+it 'igital6to6analog (onverter 3!<C4 (hannels. One *or the re'. green. an' +l)e (omponent o* the monitor signal. Ea(h o* these (hannels sho)l' have a %H0 Y%Z p)ll6'o-n resistor (onne(te' *rom the !<C o)tp)t to the (arrier +oar' gro)n'. < se(on' %H0 Y%Z termination resistor exists on the COM Express mo')le itsel*. <n a''itional 7H termination resistor exists -ithin the monitor *or ea(h analog !<C o)tp)t signal. 0in(e the !<C r)ns at spee's )p to 2H0ME7. spe(ial attention sho)l' +e pai' to signal integrity an' EMI. &here sho)l' +e a PI6*ilter pla(e' on ea(h 9"> signal that is )se' to re')(e high6*re,)en(y noise an' EMI. &he PI6*ilter (onsists o* t-o %0pB (apa(itors -ith a %#0X P %00ME7 *errite +ea' +et-een them. It is re(ommen'e' to pla(e the PI6*ilters an' the terminating resistors as (lose as possi+le to the stan'ar' @"< (onne(tor.
6.++.-.- H%G(C and A%G(C %igna#s

&he hori7ontal an' verti(al syn( signals 4;@16<%MNC4 an' 4;@16;%MNC4 provi'e' +y the COM Express mo')le are 2.2@ tolerant o)tp)ts. 0in(e @"< monitors may 'rive the monitor syn( signals -ith H@ toleran(e. it is ne(essary to implement high impe'an(e )ni'ire(tional +)**ers. &hese +)**ers prevent potential ele(tri(al over6stress o* the mo')le an' avoi' that @"< monitors may attempt to 'rive the monitor syn( signals +a(: to the mo')le. Bor optimal E0! prote(tion. a''itional lo- (apa(itan(e (lamp 'io'es sho)l' +e implemente' on the monitor syn( signals. &hey sho)l' +e pla(e' +et-een the H@ po-er plane an' gro)n' an' as (lose as possi+le to the @"< (onne(tor.
6.++.-.4 DDC $nter!a"e

COM Express provi'es a 'e'i(ate' I?C +)s *or the @"< inter*a(e. It (orrespon's to the @E0< 'e*ine' !!C inter*a(e that is )se' to rea' o)t the C9& monitor spe(i*i( Exten'e' !isplay I'enti*i(ation !ata 3E!I!4. &he appropriate signals 4;@16$.C6C1T4 an' 4;@16$.C6C84 o* the COM Express mo')le are s)ppose' to +e 2.2@ tolerant. 0in(e the most @"< monitors 'rive the internal E!I! EEP9OM -ith a s)pply voltage o* H@. the !!C inter*a(e on the @"< (onne(tor m)st also +e so)r(e' -ith H@. &his (an +e a((omplishe' +y pla(ing a %00:] p)ll6)p resistors +et-een the H@ po-er plane an' ea(h !!C inter*a(e line. 8evel shi*ters *or the !!C inter*a(e signals are re,)ire' +et-een the COM Express mo')le signal si'e an' the signals on the stan'ar' @"< (onne(tor on the (arrier +oar'. <''itional 0(hott:y 'io'es m)st +e pla(e' +et-een H@ an' the p)ll6)p resistors o* the !!C signals to avoi' +a(:-ar' ()rrent lea:age ')ring stan'+y operation o* the mo')le.
COMExpressPnP !" 09
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6.++.-.5 E%D rote"tion 8 EM$

<ll @"< signals nee' E0! prote(tion an' EMI *ilters. &his (an +e provi'e' +y )sing a @"< port (ompanion (ir()it or similar prote(tive (omponents. &he COM Express PnP Initiative evaluation carrier board design utilizes the VGA port companion circuit 'CM2009' from CMD (http://www.calmicro.com). The (ompanion (ir()it implements E0! prote(tion *or the analog !<C o)tp)t. !!C an' 0NGC signals thro)gh the )se o* lo-6(apa(itan(e ()rrent steering 'io'es. <''itionally. it incorporates level shifting for the DDC signals and buffering for the SYNC signals. For more details refer to the 'CM2009' datasheet.
6.++.4
AGA Re!eren"e %"hemati"s

,igure 6/4AGA ort Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.+- 3AD% ,#at ane# $nter!a"e

COM Express 'e*ines a 8@!0 *lat panel inter*a(e that s)pports )p to #x#46+it 8@!0. It permits ')al pixel. t-o (hannel 'ata transmission +et-een the host an' *lat panel 'isplay. Ea(h 8@!0 (hannel (onsists o* *ive 8@!0 signal pairs transmitting a serial +it stream 'ire(tly to a 8@!0 *lat panel or to an external 8@!0 re(eiver. <''itional (ontrol signals. as -ell as a 'e'i(ate' I?C +)s inter*a(e. are spe(i*ie' to (ontrol *lat panel attri+)tes. &his 'e'i(ate' I?C +)s (an +e )se' to (onne(t an external I?C EEP9OM (ontaining the spe(i*i( timing 'ata o* the *lat panel. &he appli(a+le signals (an +e *o)n' on the COM Express mo')le (onne(tor ro-s < an' >. )a&#e 6/-9
%igna#
8@!0 <0O 8@!0 <06 8@!0 <%O 8@!0 <%6 8@!0 <#O 8@!0 <#6 8@!0 <2O 8@!0 <26 8@!0 < CSO 8@!0 < CS6 8@!0 >0O 8@!0 >06 8@!0 >%O 8@!0 >%6 8@!0 >#O 8@!0 >#6 8@!0 >2O 8@!0 >26 8@!0 > CSO 8@!0 > CS6 8@!0 @!! EG 8@!0 >S8& EG 8@!0 >S8& C&98 8@!0 I#C CS 8@!0 I#C !<&
3AD% %igna# Des"riptions

in
<7% <7# <72 <74 <7H <76 <7K <79 <K% <K# >7% >7# >72 >74 >7H >76 >77 >7K >K% >K# <77 >79 >K2 <K2 <K4
Des"ription
8@!0 (hannel < 'i**erential signal pair 0 8@!0 (hannel < 'i**erential signal pair % 8@!0 (hannel < 'i**erential signal pair # 8@!0 (hannel < 'i**erential signal pair 2 8@!0 (hannel < 'i**erential (lo(: pair 8@!0 (hannel > 'i**erential signal pair 0 8@!0 (hannel > 'i**erential signal pair % 8@!0 (hannel > 'i**erential signal pair # 8@!0 (hannel > 'i**erential signal pair 2 8@!0 (hannel > 'i**erential (lo(: pair 8@!0 *lat panel po-er ena+le. 8@!0 *lat panel +a(:light ena+le high a(tive signal 8@!0 *lat panel +a(:light +rightness (ontrol !!C I?C (lo(: signal )se' *or *lat panel 'ete(tion an' (ontrol. !!C I?C 'ata signal )se' *or *lat panel 'ete(tion an' (ontrol.
$8O
O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 8@!0 O 2.2@ CMO0 O 2.2@ CMO0 O 2.2@ CMO0 O 2.2@ CMO0 I$O 2.2@ O! CMO0
Comment
COMExpressPnP !" 09
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6.+-.+
3AD% $mp#ementation Guide#ines

Many (arrier +oar' 'esigns 'o not nee' the *)ll range o* 8@!0 per*orman(e o**ere' +y COM Express mo')les. It 'epen's on the *lat panel (on*ig)ration o* the COM Express mo')le. as -ell as the (arrier +oar' 'esign. as to ho- many 8@!0 signal pairs are s)pporte'. Ahile the ')al (hannel #46+it 8@!0 (on*ig)ration nee's all %0 8@!0 signal pairs. a single (hannel %K6+it 8@!0 (on*ig)ration only re,)ires 4 8@!0 signal pairs. In this (ase all )n)se' 8@!0 signal pairs sho)l' +e le*t open on the (arrier +oar'. I* the 8@!0 'isplay inter*a(e o* the COM Express mo')le is not implemente'. all signals asso(iate' -ith this inter*a(e sho)l' +e le*t open. &he COM Express PnP Initiative 'oesnFt 'e*ine the (onne(tor layo)t *or inter*a(ing 8@!0 on the COM Express (arrier +oar' 'esign. It is )p to the system 'esigner an' the system re,)irements as to -hi(h (onne(tors an' -hi(h pino)t -ill +e )se' *or the appli(ation. &he *ollo-ing re*eren(e (ir()itry in Big)re H622 sho)l' only +e (onsi'ere' as an example o* ho- to implement the 8@!0 inter*a(e on the (arrier +oar'.
6.+-.+.+ Conne"tor and Ca&#e Considerations

Ahen implementing 8@!0 signal pairs on a single6en'e' (arrier +oar' (onne(tor. the signals o* a pair sho)l' +e arrange' so that the positive an' negative signal are si'e +y si'e. &he tra(e lengths o* the 8@!0 signal pairs +et-een the COM Express mo')le an' the (onne(tor on the (arrier +oar' sho)l' +e the same as possi+le. <''itionally. one or more gro)n' tra(es$pins m)st +e pla(e' +et-een the 8@!0 pairs. >alan(e' (a+les 3t-iste' pair4 are )s)ally +etter than )n+alan(e' (a+les 3ri++on (a+le4 *or noise re')(tion an' signal ,)ality. >alan(e' (a+les ten' to generate less EMI ')e to *iel' (an(eling e**e(ts an' also ten' to pi(: )p ele(tromagneti( ra'iation as (ommon6mo'e noise. -hi(h is re/e(te' +y the re(eiver. &-iste' pair (a+les provi'e a lo-6(ost sol)tion -ith goo' +alan(e an' *lexi+ility. &hey are (apa+le o* me'i)m to long r)ns 'epen'ing )pon the appli(ation s:e- +)'get. < variety o* shiel'ing options are availa+le. 9i++on (a+les are a (ost e**e(tive an' easy sol)tion. Even tho)gh they are not -ell s)ite' *or high6spee' 'i**erential signaling they 'o -or: *ine *or very short r)ns. Most (a+les -ill -or: e**e(tively *or (a+le 'istan(es o* ^0.Hm. &he (a+les an' (onne(tors that are to +e )tili7e' sho)l' have a 'i**erential impe'an(e o* %00] Y%HZ. &hey sho)l' not intro')(e ma/or impe'an(e 'is(ontin)ities that (a)se signal re*le(tions. Bor more in*ormations a+o)t this s)+/e(t re*er to the F8@!0 O-ners Man)al Chapter 6F availa+le *rom Gational 0emi(on')(tor 3http1$$---.national.(om4.
COMExpressPnP !" 09
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6.+-.+.- Disp#ay )iming Con!iguration

=s)ally the timing parameters *or the *lat panel 'isplay are store' in an external EEP9OM that is implemente' on the COM Express (arrier +oar'. It is a((essi+le thro)gh the 'e'i(ate' 8@!0 I?C +)s via the signals 47;C%6$.C6C84 an' 47;C%6$.C6C1T4, -hi(h (an +e *o)n' on the mo')leFs (onne(tor ro- < pins <K2 an' <K4. !)ring PO0& the mo')leFs >IO0 rea's o)t the 'isplay timing 'ata *rom the EEP9OM an' (on*ig)res the mo')leFs graphi(s (ontroller *or proper *lat panel operation. In or'er to +e a+le to 'o this. the 'evi(e a''ress o* the 8@!0 I?C EEP9OM m)st +e strappe' to 0x<0. Bor more in*ormation a+o)t the (ontents o* the 'isplay timing 'ata re*er to se(tion H.%#.# FEm+e''e' Panel Inter*a(e 0tan'ar' 5 EPIF.
6.+-.+.4 1a"*#ight Contro#

&he *ollo-ing 8@!0 re*eren(e (ir()itry sho-s a +a(:light (ontrol sol)tion )sing the 'igital potentiometer M<LH424 *rom Maxim 3http1$$---.maxim.(om4. =s)ally (ommon +a(:light inverters are either voltage or resistor (ontrolle'. &here*ore 'igital potentiometers are a *lexi+le sol)tion to meet the re,)irements o* most inverters. I* a +a(:light inverter is resistan(e (ontrolle'. the 'igital potentiometer (an +e (onne(te' 'ire(tly to the +a(:light (ontrol inp)t o* the inverter. Other-ise the potentiometer (an +e )se' to implement a simple voltage 'ivi'er 'riving the +a(:light voltage (ontrol inp)t pin o* the inverter.
6.+-.+.5 Routing Considerations !or 3AD%

0ee se(tion 7.7 F8@!0 &ra(e 9o)ting ")i'elinesF an' the F8@!0 O-ners Man)al Chapter 2F *rom Gational 0emi(on')(tor 3http1$$---.national.(om4 *or more in*ormation a+o)t this s)+/e(t
COMExpressPnP !" 09
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6.+-.+.6 3AD% Re!eren"e %"hemati"s

,igure 6/44 3AD% ,#at ane# $nter!a"e Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.+-.-
Em&edded ane# $nter!a"e %tandard / E $

EPI 3Em+e''e' Panel Inter*a(e4 is an open stan'ar' that allo-s easy an' 'ire(t (ontrol o* all 'igital *lat panel 'isplays. One o* the +iggest a'vantages o* COMFs 3Comp)ter On Mo')les4 is the inter(hangea+ility o* mo')les +et-een 'i**erent s)ppliers. &he only -ea: point -as the 'ire(t (ontrol o* 'igital *lat panel 'isplays. !)e to the la(: o* a )ni*orm stan'ar' all man)*a(t)rers ha' to 'e*ine their o-n inter*a(e strategy. &his pro+lem is solve' -ith the )se o* EPI 3Em+e''e' Panel Inter*a(e4. EPI is +ase' on the @E0< stan'ar' E!I! 3Exten'e' !isplay I'enti*i(ation !ata4 9evision %.2 an' 'e*ines the so*t-are *ormat *or 'isplay properties an' the s(ala+le har'-are inter*a(e. &he E!I!%.2 'ata set is implemente' in all (ommer(ial monitors. -hi(h have a lo(al intelligen(e. &he pro+lem is that this lo(al intelligen(e is not availa+le *or em+e''e' appli(ations on the 'isplay si'e. In or'er *or an em+e''e' (omp)ter mo')le to have 'ire(t (ontrol o* a 'igital *lat panel 'isplay. some more in*ormation is re,)ire' -ithin the E!I! 'ata set. &his a''itional in*ormation in(l)'es the (olor mapping. ')al pixel per (lo(: (on*ig)ration an' inter*a(e te(hnology o* the em+e''e' *lat panel. &here*ore. EPI a''s the missing parameters to (omplete the set o* E!I! %.2 'ata +y )sing a %2 +yte 'ata area -ithin +lo(: 4 o* the E!I! %.2 !&! 3!etaile' &iming !es(riptor4. ,igure 6/45 1#o"* Diagram o! the Em&edded ane# $nter!a"e %o#ution
<n EPI 'ata set. )se' to 'es(ri+e the (ontrol o* a 'igital *lat panel 'isplay. (an +e easily (reate' )sing the in*ormation *o)n' in the 'isplay 'atasheet. &he EPI 'ata set 'es(ription is in'epen'ent *rom the vi'eo (ontroller an' is interprete' +y the >IO0 o* the COM Express mo')le in or'er to set the (orre(t 'isplay parameters ')ring graphi(s
Copyright COM Express PnP Initiative COMExpressPnP !" 09 K0$%%9
initiali7ation. &his means that the man)*a(t)rer o* the COM Express mo')le m)st g)arantee that the a''itional 'ata is interprete' +y the >IO0. &he res)lt is a man)*a(t)rer in'epen'ent Ipl)g6an'6'isplayJ sol)tion that ena+les *ree inter(hangea+ility o* 'isplays an' COM Express mo')les. &ypi(ally the EPI 'ata set is store' in an external EEP9OM (onne(te' to the 8@!0 I?C +)s inter*a(e. &his EEP9OM is lo(ate' either on the COM Express (arrier +oar' or on the *lat panel 'isplay itsel*. 0ome COM Express mo')les also o**er the possi+ility to omit the external EEP9OM an' to store more than one ()stomi7e' EPI 'ata set in the >IO0 *irm-are h)+. !epen'ing on the system *lat panel implementation. the ()stomer (an (hoose one o* these ()stomi7e' EPI 'ata sets. Bor more in*ormation a+o)t the EPI stan'ar' re*er to the EPI 0pe(i*i(ation at http1$$---.epi6stan'ar'.org. &his site also in(l)'es 'e*a)lt EPI 'ata sets *or most (ommon panel resol)tions *or 'o-nloa'.
COMExpressPnP !" 09
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6.+4 )A/Out $nter!a"e

&he &@6O)t 'isplay inter*a(e o* the COM Express Mo')le (onsists o* 2 in'ivi')al 'igital6to6analog (onverter 3!<C4 (hannels. -hi(h (an +e )se' in 'i**erent (om+inations to s)pport 06@i'eo 3N$C4. Composite @i'eo or Component @i'eo 3NP+Pr4. &he (orrespon'ing signals (an +e *o)n' on the COM Express mo')le (onne(tor ro- >. )a&#e 6/-B
%igna#
&@ !<C <
)A/Out %igna# Des"riptions

Des"ription
&@6!<C (hannel < o)tp)t s)pporting1 Composite video1 Composite CA1% Component video1 Chrominan(e 3P+4 %/Aideo1 not )se' &@6!<C (hannel > o)tp)t s)pporting1 Composite video1 not )se' Component video1 8)minan(e 3N4 %/Aideo1 8)minan(e 3N4 &@6!<C (hannel C o)tp)t s)pporting1 Composite video1 not )se' Component1 Chrominan(e 3Pr4 %/Aideo1 Chrominan(e 3C4
in
>97
$8O
O <nalog
Comment
<nalog o)tp)t
&@ !<C >
>9K
O <nalog
<nalog o)tp)t
&@ !<C C
>99
O <nalog
<nalog o)tp)t
It 'epen's on the COM Express mo')leFs so*t-are (on*ig)ration as to -hi(h o)tp)t mo'e is 'riven on the three &@ !<C (hannels. Only one o)tp)t mo'e (an +e )se' at any given time.
6.+4.+
)A/Out Conne"tor
,igure 6/46 )A/Out Aideo Conne"tor ("om&ined %/Aideo and Composite)
)a&#e 6/42
in %igna#
% 2 H 7
)A/Out Conne"tor inout

Des"ription in %igna# Des"ription
Chrominan(e 3C4 06@i'eo Chrominan(e <nalog 0ignal # 3C4 "G! 3C4 "G! Composite <nalog "ro)n' *or Chrominan(e 3C4 4 <nalog "ro)n' Composite @i'eo O)tp)t 6
8)minan(e 3N4 06@i'eo 8)minan(e <nalog 0ignal 3N4 "G! 3N4 "G! <nalog "ro)n' 8)minan(e 3N4 <nalog "ro)n'
COMExpressPnP !" 09
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6.+4.-
)A/Out $mp#ementation Guide#ines
6.+4.-.+ %igna# )ermination

Ea(h o* the &@6!<C (hannels sho)l' have a %H0 Y%Z p)ll6'o-n termination resistor (onne(te' *rom the &@6!<C o)tp)t o* the COM Express mo')le to the (arrier +oar' gro)n'. &his termination resistor sho)l' +e pla(e' as (lose as possi+le to the &@6O)t (onne(tor on the (arrier +oar'. < se(on' %H0 Y%Z termination resistor exists on the COM Express mo')le itsel*.
6.+4.-.- Aideo ,i#ter

&here sho)l' +e a PI6*ilter pla(e' on ea(h &@6!<C (hannel o)tp)t to re')(e high6*re,)en(y noise an' EMI. &he PI6*ilter (onsists o* t-o %0pB (apa(itors -ith a %#0 P 20Mh7 *errite +ea' +et-een them. It is re(ommen'e' to pla(e the PI6*ilters an' the termination resistors as (lose as possi+le to the &@6O)t (onne(tor on the (arrier +oar'. &he PI6*ilters sho)l' +e separate' *rom ea(h other +y at least H0mils or more in or'er to minimi7e (rosstal: +et-een the &@6!<C (hannels.
6.+4.-.4 E%D rote"tion

E0! (lamp 'io'es are re,)ire' *or ea(h &@6!<C (hannel. &hese lo- (apa(itan(e (lamp 'io'es sho)l' +e pla(e' as near as possi+le to the &@6O)t (onne(tor on the COM Express (arrier +oar' +et-een OH@ s)pply voltage an' gro)n'.
6.+4.-.5 Routing Guide#ines !or )A/Out

<t least 20mils o* spa(ing sho)l' +e )se' *or the ro)ting +et-een ea(h &@6!<C (hannel to prevent (rosstal: +et-een the &@6!<C signals. &he maxim)m tra(e length 'istan(e o* the &@6!<C signals +et-een the COM Express (onne(tor an' the %H0 Y%Z termination resistor sho)l' +e -ithin %# in(hes. &his 'istan(e sho)l' +e ro)te' -ith a H0 tra(e impe'an(e.
6.+4.-.6 )A/Out Re!eren"e %"hemati"s

,igure 6/4: )A/Out Re!eren"e Cir"uitry
COMExpressPnP !" 09
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6.+5 Audio Code" $nter!a"e (ACHB>8HDA)

<ll COM Express mo')le types s)pport <)'io Co'e( F97 3<CF974 an'$or Eigh !e*inition <)'io 3E!<4 !igital Inter*a(e 3<C6lin:4 spe(i*i(ally 'esigne' *or implementing a)'io an' mo'em I$O *)n(tionality. &he (orrespon'ing signals (an +e *o)n' on the COM Express mo')le (onne(tor ro-s < an' >. )a&#e 6/4+
%igna#
<C 90&R
Audio Code" %igna# Des"riptions

Des"ription
CO!EC 9eset.
in
<20
$8O
O 2.2@ 0tan'+y CMO0 O 2.2@ CMO0 O 2.2@ CMO0 O 2.2@ CMO0 I 2.2@ 0tan'+y CMO0
Comment
<C 0NGC <C >I&C8S <C 0!O=& <C 0!IG0 <C 0!IG% <C 0!IG#
<#9 <2# <22 >20 >#9 >#K
0erial 0ample 9ate 0yn(hroni7ation. %#.##K ME7 0erial >it Clo(: *or CO!EC. <)'io 0erial !ata O)tp)t 0tream. <)'io 0erial !ata Inp)t 0tream *rom CO!EC[01#\.
In*ormation a+o)t -hi(h a)'io inter*a(e is s)pporte' on the COM Express mo')le (an +e *o)n' in the (orrespon'ing COM Express mo')leFs )serFs g)i'e. On COM Express mo')les that s)pport the <CF97 !igital Inter*a(e only. it is not possi+le to )se E!< (o'e(s. &he Eigh !e*inition <)'io ar(hite(t)re is (ompletely 'i**erent than the <CF97 ar(hite(t)re an' there*ore is not +a(:-ar's (ompati+le. 0ome COM Express mo')les s)pport +oth the <CF97 an' E!< Inter*a(e. In these (ases the COM Express mo')leFs F>IO0 0et)p ProgramF o**ers a set)p entry to (hoose -hi(h inter*a(e sho)l' +e )tili7e'. Only a)'io (o'e(s that mat(h this setting -ill -or: properly. <CQ97 an' Eigh !e*inition <)'io (o'e(s (annot +e mixe' on the same lin: or +ehin' the same (ontroller.
6.+5.+
Audio Code" $mp#ementation Guide#ines

&he a)'io *)n(tion on COM Express is provi'e' thro)gh an <CF97 or E!< (o'e( on the (arrier +oar'. &he <CF97 or E!< (o'e( on a COM Express (arrier +oar' is )s)ally (onne(te' as primary (o'e( -ith the (o'e( I! 00 )sing the 'ata inp)t line 41C6%C$N.4. =p to t-o a''itional (o'e(s -ith I! 0% an' I! %0 (an +e (onne(te' to the COM Express mo')le +y )sing the other 'esignate' signals 41C6%C$N/4 an' 41C6%C$N'4. Conne(t the primary a)'io (o'e( to the serial 'ata inp)t signal 41C6%C$N.4 an' ens)re that the (orrespon'ing +it (lo(: inp)t signal 41C6B$TC784 is (onne(te' to the <CF97$E!< inter*a(e o* the COM Express mo')le. Clo(:ing over the signal 41C6B$TC784 is 'erive' *rom a #4.H76 ME7 (rystal or (rystal os(illator provi'e' +y the primary (o'e(. &his (lo(: also 'rives the se(on' an' the thir' a)'io (o'e( i* more than one (o'e( is )se' in the appli(ation. Bor (rystal or (rystal
COMExpressPnP !" 09
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os(illator re,)irements. re*er to the 'atasheet o* the primary (o'e(. Bollo-ing Big)re H627 ill)strates ho- to inter(onne(t <C97$E!< (o'e(s on a COM Express (arrier +oar' 'esign. ,igure 6/4> Mu#tip#e Audio Code" Con!iguration
<ll <CF97$E!< (o'e(s liste' +elo- in &a+le H62# are re(ommen'e' +y the COM Express PnP Initiative *or )se on COM Express (arrier +oar' 'esigns. )a&#e 6/4Manu!a"turers
9ealte( @I< &e(hnology @I< &e(hnology
Re"ommended Audio Code"s

art (um&er )e"hno#ogy
<8C#02 @&%6%6 @&%70K <C F97 <C F97 Eigh !e*inition <)'io
Comments
http1$$---.realte:.(om.thttp1$$---.via.(om.thttp1$$---.via.(om.t-
COMExpressPnP !" 09
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6.+5.+.+ ACHB> Code" Re!eren"e %"hemati"s

,igure 6/49 ACHB> Code" Cir"uitry
COMExpressPnP !" 09
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6.+5.+.- ACHB>8HDA #a"ement and Routing Guide#ines

&he implementation o* proper (omponent pla(ement an' ro)ting te(hni,)es -ill help to ens)re that the maxim)m per*orman(e availa+le *rom the (o'e( is a(hieve'. 9o)ting te(hni,)es that sho)l' +e o+serve' in(l)'e properly isolating the (o'e(. asso(iate' a)'io (ir()itry. analog po-er s)pplies an' analog gro)n' planes *rom the rest o* the (arrier +oar'. &his in(l)'es split planes an' the proper ro)ting o* signals not asso(iate' -ith the a)'io se(tion. &he *ollo-ing is a list o* +asi( re(ommen'ations1
&ra(es m)st +e ro)te' -ith a target impe'an(e o* HHX -ith an allo-e' toleran(e o* Y%HZ. "ro)n' ret)rn paths *or the analog signals m)st +e given spe(ial (onsi'eration. !igital signals ro)te' in the vi(inity o* the analog a)'io signals m)st not (ross the po-er plane split lines. 8o(ate the analog an' 'igital signals as *ar as possi+le *rom ea(h other. Partition the (arrier +oar' -ith all analog (omponents gro)pe' together in one area an' all 'igital (omponents in another. Seep 'igital signal tra(es. espe(ially the (lo(:. as *ar as possi+le *rom the analog inp)t an' voltage re*eren(e pins. Provi'e separate analog an' 'igital gro)n' planes -ith the 'igital (omponents over the 'igital gro)n' plane. an' the analog (omponents. in(l)'ing the analog po-er reg)lators. over the analog gro)n' plane. &he split +et-een planes m)st +e a minim)m o* 0.0H in(h -i'e. 9o)te analog po-er an' signal tra(es over the analog gro)n' plane. 9o)te 'igital po-er an' signal tra(es over the 'igital gro)n' plane. Position the +ypassing an' 'e(o)pling (apa(itors (lose to the IC pins -ith -i'e tra(es to re')(e impe'an(e. Pla(e the (rystal or os(illator as (lose as possi+le to the (o'e(. !o not (ompletely isolate the analog$a)'io gro)n' plane *rom the rest o* the (arrier +oar' gro)n' plane. Provi'e a single point 30.#H in(h to 0.H in(h -i'e4 -here the analog$isolate' gro)n' plane (onne(ts to the main gro)n' plane. &he split +et-een planes m)st +e a minim)m o* 0.0H in(h -i'e. <ny signals entering or leaving the analog area m)st (ross the gro)n' split in the area -here the analog gro)n' is atta(he' to the main (arrier +oar' gro)n'. &hat is. no signal sho)l' (ross the split$gap +et-een the gro)n' planes. -hi(h -o)l' (a)se a gro)n' loop there+y greatly in(reasing EMI emissions an' 'egra'ing the analog an' 'igital signal ,)ality.
COMExpressPnP !" 09
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6.+6 $DC 1us $nter!a"es

>e(a)se o* the simple t-o6-ire serial +)s proto(ol an' the high availa+ility o* 'evi(es. the I?C +)s is a *re,)ently )se' lo- spee' +)s inter*a(e *or (onne(ting em+e''e' 'evi(es s)(h as sensors. (onverters or 'ata storage. COM Express provi'es *ive 'i**erent I?C +)ses on the mo')leFs (onne(tors. Bo)r o* the *ive I?C +)ses ass)me 'e'i(ate' mo')le *)n(tionality s)(h as rea'ing o)t !!C 'isplay timing 'ata o* an external @"<. 0!@O or 8@!0 'isplayFs EEP9OM. Only the "eneral P)rpose I?C >)s -ith the signals 4$.C6C84 an' 4$.C6C1T4 is inten'e' *or (ommon )sage on the COM Express (arrier +oar'. &he *ollo-ing ta+le s)mmari7es the *ive availa+le I?C signal gro)ps an' their 'e*ine' p)rposes. )a&#e 6/44
%igna#
I#C CS I#C !<& 8@!0 I#C CS 8@!0 I#C !<& @"< I#C CS @"< I#C !<& 0!@O C8S 0!@O !<&< 0M> CS 0M> !<&
$DC %igna# Group Overvie.

in Des"ription $8O
I$O 2.2@ CMO0 I$O 2.2@ CMO0 I$O 2.2@ CMO0 I$O #.H@ CMO0
Comment
Max. 400 :E7. m)lti6master I?C +)s. I#C !<& is open 'rain 3O!4. Max. %00 :E7 I?C +)s. 8@!0 I#C !<& is open 'rain 3O!4. Max. %00 :E7 I?C +)s. @"< I#C !<& is open 'rain 3O!4. Max. %00 :E7 I?C +)s. 0!@O !<&< is open 'rain 3O!4.
>22 "eneral p)rpose I?C +)s *or (ommon >24 )sage on the (arrier +oar'. <K2 !e'i(ate' I?C +)s *or rea'ing o)t 8@!0 <K4 *lat panel (on*ig)ration 'ata an' *or +a(:light (ontrol. >9H !e'i(ate' I?C +)s *or rea'ing o)t monitor >96 (on*ig)ration 'ata. !72 !e'i(ate' I?C +)s *or 0!@O 'evi(e C72 (on*ig)ration an' *or rea'ing o)t monitor (on*ig)ration 'ata.
>%2 0ystem Management >)s 30M>)s4 is )se' I$O 2.2@ Max. %00 :E7 I?C +)s. >%4 +y the COM Express mo')le *or O! CMO0 memory (on*ig)ration an' (lo(: Note& 1n error on the %MBus can synthesi7er (on*ig)ration. It is also )se' prevent the module from functioning. +y the external PCI Express slots an' ExpressCar' slots. >%H &he 0M>)s alert signal )se' +y the 0M>)s slave to in*orm the 0M>)s master that a slave transa(tion is pen'ing. I 2.2@ CMO0 Optional signal )se' +y the 0M>)s slave.
0M> <8E9&R
(ote The ma!imum transfer rate on the $NC bus is determined by the $NC device with the lowest transfer rate.
COMExpressPnP !" 09
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6.+6.+
%ystem Management 1us

On the COM Express mo')le. the 0ystem Management >)s 30M>)s4 is po-ere' +y the stan'+y po-er rail in or'er to have (ontrol over the system ')ring the system states 0060H. &he 'evi(es on the (arrier +oar' )sing the 0M>)s are normally po-ere' +y the 2.2@ main po-er. &o avoi' ()rrent lea:age +et-een the main po-er o* the (arrier +oar' an' the stan'+y po-er o* the mo')le. the 0M>)s on the (arrier +oar' m)st +e separate' +y a +)s s-it(h *rom the 0M>)s o* the mo')le. Big)re H629 sho-s an appropriate +)s s-it(h (ir()itry *or separating the 0M>)s o* the (arrier +oar' *rom the 0M>)s o* the mo')le. Eo-ever. i* the (arrier +oar' also )ses stan'+y po-ere' 0M>)s 'evi(es that are 'esigne' to operate ')ring system states 0260H. then these 'evi(es m)st +e (onne(te' to the stan'+y po-ere' si'e o* the 0M>)s. i.e. +et-een the COM Express mo')le an' the +)s s-it(h. ,igure 6/4B %M1us %eparation Cir"uitry
COMExpressPnP !" 09
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6.+6.-
Genera# urpose $DC 1us

&he COM Express PnP Initiative strongly re(ommen's implementing a har'-are I?C >)s -ith +)s master (apa+ilities. (ote The COM !press" #n# $nitiative has yet to fully define the re2uirements for the above mentioned recommendation and will do so in the near future.
6.+6.-.+ App#i"ation Examp#e? $DC %ystem Con!iguration EE ROM

&he COM Express spe(i*i(ation re(ommen's implementing a serial I?C EEP9OM o* at least #:+it on the (arrier +oar' -here all the ne(essary system (on*ig)ration (an +e save'. Bor more in*ormation a+o)t the (ontent o* this system (on*ig)ration EEP9OM re*er to the COM Express 0pe(i*i(ation. &he *ollo-ing (ir()itry 3Big)re H6404 sho-s ho- to (onne(t an <tmel F<&#4C%6<F %6:+it EEP9OM to the "eneral P)rpose I?C +)s on the COM Express(arrier +oar' 3http1$$---.atmel.(om4. <((or'ing to the COM Express spe(i*i(ation the I?C a''ress lines <#. <% an' <0 o* the system (on*ig)ration EEP9OM m)st +e p)lle' high. !epen'ing on the EEP9OM si7e this lea's to the I?C a''resses 0x<E 3#:+it4. 0x<C 34:+it4. 0x<K 3K:+it4 or 0x<0 3%6:+it4. ,igure 6/52 %ystem Con!iguration EE ROM Cir"uitry
(ote The COM !press" configuration #5OM is an optional feature to support auto configuration of the COM !press" module4s interfaces. $f the configuration #5OM is not implemented on the COM !press" carrier board, or the COM !press" module4s B$O% does not support auto configuration, the module comes up with the default configuration.
COMExpressPnP !" 09
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6.+: $nput o.er

COM Express mo')les are 'esigne' to +e 'riven -ith a single O%#@ po-er rail. <''itionally. t-o optional po-er rails are spe(i*ie' +y COM Express to provi'e a H@ stan'+y voltage an' a 2@ 9eal &ime Clo(: 39&C4 +attery voltage on the (arrier +oar'. 9e*er to se(tion 4 FCOM Express Conne(tor Pino)tF to o+tain 'etaile' in*ormation a+o)t the (orrespon'ing pins assigne' *or the inp)t po-er rails 4;CC6/.;4. 4;CC6+;6%BM4. 4;CC65TC4 an' 4@NC4. I* stan'+y *)n(tionality is not re,)ire' on the (arrier +oar'. the H@ stan'+y po-er rail (an +e omitte'. &he (orrespon'ing signals 4;CC6+;6%BM4 (an +e *o)n' on the (onne(tor ro- > pins >K4. >KH. >K6 an' >K7. &he same applies to the 2@ 9&C +attery voltage. I* no 9&C$CMO0 +a(:)p *)n(tionality is re,)ire' +y the system then the 2@ 9&C +attery voltage (an +e omitte'. &he (orrespon'ing signal 4;CC65TC4 (an +e *o)n' on the (onne(tor ro- < pin <47. COM Express spe(i*ies the inp)t po-er (hara(teristi(s *or the po-er rails a((or'ing to &a+le H624. &he (arrier +oar' 'esigner sho)l' also (onsi'er the po-er re,)irements o* the COM Express mo')le that is to +e )se' as -ell as any other po-er (ons)ming (omponent that -ill +e implemente' on the (arrier +oar'. 9e*er to the (orrespon'ing COM Express mo')les )serFs g)i'e *or more in*ormation a+o)t this s)+/e(t. )a&#e 6/45
o.e Rai#
@CC %#@ @CC H@ 0>N @CC 9C
COM Express $nput o.er Chara"teristi"s

(omina# $nput
%#@ H@ 2@
$nput Range
%%.4@6%#.6@ 4.7H@6H.#H@ #.0@62.2@
Max $nput Ripp#e

Y%00 m@ YH0 m@ Y#0 m@
6.+:.+
%ing#e @+-A o.er %upp#y

<s mentione' earlier. COM Express mo')les are 'esigne' to +e 'riven -ith a single O%#@ <& po-er rail. It 'epen's on the appli(ation i* a''itional inp)t voltages are re,)ire' on the (arrier +oar' 'esign or not. 9e*er to the s(hemati(s o* the COM Express PnP Initiative eval)ation (arrier +oar' 'esign *or an example o* ho- to implement 2.2@ an' H@ inp)t voltage reg)lators on a COM Express (arrier +oar'. Caution When designing customiKed single )/.; power supplies it is strongly recommended that the power supply supports power off re2uests by the COM Express mo')le signale' via 0=0 02R or 0=0 0HR. >esi'es the +ene*it that the system (an +e s-it(he' o** +y so*t-are it also g)aranties that the system gets s-it(he' o** ')ring an overheating (on'ition o* the pro(essor th)s preventing 'amage to the system. <lternatively. the &E9M&9IPR signal 3see se(tion H.%6.H &hermal Management4 (o)l' +e )se' to 'ete(t an overheating (on'ition an' there)pon s-it(h o** po-er.
COMExpressPnP !" 09
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6.+:.-
A)I o.er %upp#y

<&L po-er s)pplies are -i'ely )se' *or (ons)mer PC mother+oar's an' they are also a (ost e**e(tive an' relia+le sol)tion *or em+e''e' 'esigns. <&L po-er s)pplies provi'e all the ne(essary po-er rails re,)ire' *or a (arrier +oar' 'esign. &a+le H62H 'es(ri+es all the signals provi'e' +y a #4 pin <&L po-er s)pply (onne(tor.
6.+:.-.+ A)I o.er Conne"tor

)a&#e 6/46
%igna#
2.2@ COM COM COM % 2 H 7
A)I Conne"tor (-5 pin0 re"epta"#e)

%igna#
2.2@ H@ H@ # 4 6
in Des"ription
O2.2@ "ro)n' "ro)n' "ro)n'
in Des"ription
O2.2@ OH@ OH@ 0tat)s signal generate' +y the <&L po-er s)pply to noti*y the COM Express mo')le that the !C operating voltages are -ithin the ranges re,)ire' *or proper operation. O%#@ O2.2@ 6%#@ <(tive lo- signal. -hi(h is (ontrolle' +y the COM Express mo')le to t)rn on or o** the <&L po-er s)pply. "ro)n' G.C. OH@ "ro)n'
PA9 OS K
H@0> %#@ 2.2@ COM
9 %% %2 %H
OH@ 0tan'+y @oltage O%#@ O2.2@ "ro)n'
%#@ 2.2@ 6%#@ P0 OGR
%0 %# %4 %6
COM COM OH@ OH@
%7 %9 #% #2
"ro)n' "ro)n' OH@ OH@
COM OH@ COM
%K ## #4
9eserve' #0
(ote Optionally, an 1TA #ower %upply with a .' pin main power connector can be used. The .' pin main power connector complies with older versions of the 1TA %pecification. 1TA %pecification ;ersion ... enhanced the main power connector from .' pin to .= pin in order to meet the re2uirements of #C$- !press. 3or more information about the 1TA %pecification and the 1TA/.; #ower %upply %pecification refer to the $ntelO 41TA/.; #ower %upply Cesign @uide4. These documents can be found at the following website http&,,www.formfactors.org.
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6.+:.-.- A)I o.er Cir"uitry

&he *ollo-ing *ig)re sho-s the <&L po-er (arrier +oar' (ir()itry )sing a #4 pin <&L main po-er (onne(tor. &he H@ an' 2.2@ po-er rail are provi'e' +y the <&L po-er s)pply on the 4;CC4 an' 4;CC:4 po-er rails. &o meet the 'eman's o* the systems po-er (ons)mption. t-o a''itional O%#@ po-er pins may +e implemente' )sing an a)xiliary 4 pin 3#x#4 O%#@$"G! po-er (onne(tor. ,igure 6/5+ A)I Main o.er Cir"uitry
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6.+:.4
o.er =p Contro#
&he po-er )p (ontrol is responsi+le *or s-it(hing the <&L po-er s)pply on or o** -hen a po-er6)p or a po-er6'o-n event o(()rs. < po-er event (an +e generate' +y pressing the po-er +)tton or +y another system event. -hi(h (an originate *rom or +e 'ete(te' +y the COM Express mo')leFs (hipset. &here are t-o -ays to implement the system po-er6)p (ontrol on a COM Express 'esign1 %. Gative system po-er6)p s)pport o* the mo')le. #. 0ystem po-er6)p s)pport o* a 0)per I$O (ontroller.
6.+:.4.+ o.er =p Contro# &y Modu#e

&he native system po-er6)p s)pport o* COM Express mo')les )tili7e the 4%P%6%:94 signal to (ontrol the 4#%6ON94 signal, -hi(h is )se' to s-it(h the <&L po-er s)pply on or o** . Ahen )sing the %P%6%:94 signal the COM Express mo')le is (apa+le o* s)pporting 0)spen' to 9<M 3024. Ahen the system goes to 0)spen' to 9<M 3024 or 0o*t O** 30H4. the 4%P%6%:94 signal is asserte' +y the (hipset o* the mo')le. &hro)gh the )se o* an inverter. the lo- a(tive 4#%6ON94 signal goes high an' s-it(hes o** the <&L po-er s)pply. @i(e versa. i* the system resi'es in a po-er6'o-n system state. any system -a:e6)p event invo:es the (hipset o* the mo')le to 'eassert the 4%P%6%:94 signal. &his res)lts in a system transition to B)ll On 3004. &he -ay 0)spen' to 9<M is implemente' on a COM Express mo')le may 'i**er 'epen'ing on the mo')le man)*a(t)rer. Bor this reason it is re(ommen'e' that a har'-are /)mper +e implemente' on the (arrier +oar' in or'er to provi'e the a+ility to (hoose i* the 4#%6ON94 signal sho)l' +e (ontrolle' either +y the 4%P%6%:94 signal or F%P%6%+94 signal. &he 4#%6ON49 signal *or the <&L po-er s)pply (an +e optionally lo(:e' to prevent po-er6)p i* an )ns)ita+le COM Express mo')le type is (onne(te' to the (arrier +oar'. &his is (ontrolle' +y a H@ tolerant tri6state +)**er. -hi(h is ena+le' +y the 4TM# 6#%ON6CT5794 signal o* the type 'ete(tion (ir()itry. Bor more in*ormation re*er to se(tion H.%7.% FMo')le &ype !ete(tionF. ,igure 6/5o.er =p Contro# Cir"uitry (hand#ed &y modu#e)
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6.+:.4.- o.er/=p Contro# &y %uper $8O

&he *ollo-ing 'es(ription o* the po-er6)p logi( is +ase' on the Ain+on' AK26#7EB 0)per I$O (ontroller. It is also appli(a+le to other 0)per I$O (ontrollers an' (an +e )se' as an example. Bor spe(i*i( in*ormation a+o)t the po-er6)p logi( an' the appropriate 0)per I$O (ontroller signals )se'. re*er to the (orrespon'ing (ontroller 'atasheet. &he Ain+on' AK26#7EB 0)per I$O is (apa+le o* 'ete(ting a po-er +)tton event )sing the F#%$N4 inp)t pin. Bor this reason the po-er +)tton signal 4#W5BTN6 AT94 is (onne(te' via an inverter to the high a(tive 4#%$N4 inp)t pin. I* a po-er +)tton event o(()rs. the po-er6)p logi( o* the 0)per I$O sets the o)tp)t pin 4#%OPT94 to lo- an' asserts the 4#W5BTN94 signal o* the mo')leFs (hipset. Passing the po-er +)tton signal thro)gh the 0)per I$O via P0IG$P0O=&R provi'es the option to )tili7e system -a:e6)p events generate' +y the 0)per I$O. B)rthermore. the Ain+on' AK26#7EB 0)per I$O provi'es a 4%7#6%A94 signal. -hi(h (an +e (onne(te' to the 0)spen' to 9<M 3024 system stat)s 4%P%6%:94 signal. I* the mo')le transitions to a po-er 'o-n system state s)(h as 0)spen' to 9<M 3024 or 0o*t O** 30H4. the mo')les (hipset asserts the 4%P%6%:94 signal to a'vise the 0)per I$O (ontroller to s-it(h o** the <&L po-er s)pply. &his -ay it is also possi+le to -a:e6)p the system -hen it is in a 0)spen' to 9<M or 0o*t O** state. I* the po-er management logi( o* the mo')les (hipset 'ete(ts a system -a:e6)p event it 'easserts the 4%P%6%:94 signal to a'vise the 0)per I$O to s-it(h on the <&L po-er s)pply. &he 4#%6ON49 signal *or the <&L po-er s)pply (an +e optionally lo(:e' to prevent po-er6)p i* an )ns)ita+le COM Express mo')le type is (onne(te' to the (arrier +oar'. &his is (ontrolle' +y a H@ tolerant tri6state +)**er. -hi(h is ena+le' +y the 4TM# 6#%ON6CT5794 signal o* the type 'ete(tion (ir()itry. Bor more in*ormation re*er to se(tion H.%7.% FMo')le &ype !ete(tionF. ,igure 6/54 o.er/=p Contro# Cir"uitry (hand#ed &y %uper $8O)
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6.+:.5
o.er Management
COM Express spe(i*ies a set o* signals to (ontrol the system po-er states s)(h as the po-er6on an' reset (on'itions. &his ena+les the system 'esigner to implement a *)lly <CPI (ompliant system s)pporting system states *rom 00 to 0H. &he minim)m har'-are re,)irements *or an <CPI (ompliant system is an <&L (on*orming po-er s)pply an' a po-er +)tton. &he *ollo-ing ta+le provi'es a short 'es(ription o* the <CPI 'e*ine' system states 00 to 0H in(l)'ing the (orrespon'ing po-er rail state. Bor more in*ormation a+o)t <CPI an' the several system po-er states re*er to the F<'van(e' Con*ig)ration an' Po-er Inter*a(e 0pe(i*i(ation 9evision 2.0F. )a&#e 6/4: %ystem %tates %2/%6 De!initions
Des"ription
!)ring 00 state. all (omponents are po-ere' an' the system is *)lly *)n(tional. In 0% sleeping state. no system (ontext is lost. har'-are maintains all system (ontext. !)ring 0% operation some system (omponents are set into lopo-er state. Got s)pporte'. In 02 state. the ()rrent system state an' (ontext is store' in main memory an' all )nne(essary system logi( is t)rne' o**. Only main memory an' logi( re,)ire' to -a:e6)p the system remain po-ere' +y the stan'+y voltages. <ll other po-er rails are s-it(he' o**.
%ystem %tate
00 B)ll On 0% Po-er6on 0tan'+y 3PO04 0# 02 0)spen' to 9<M 30&94
o.er Rai# %tate

B)ll po-er on all po-er rails. B)ll po-er on all po-er rails.
04U 0)spen' to !is: 30&!4 0H 0o*t O**
04 0leep (ontrol signal in'i(ating that the system resi'es in 04 state 30)spen' to !is:4. In 0H state the system is s-it(he' o**. 9estart is only 0tan'+y po-er rails may or may not possi+le -ith the po-er +)tton or +y a system -a:e6)p +e po-ere'. 'epen'ing on i* event s)(h as FAa:e On 8<GF or 9&C alarm. system -a:e6)p is s)pporte'.
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)a&#e 6/4>
%igna#
PA9>&GR
o.er Management %igna# Des"riptions

Des"ription
Po-er +)tton lo- a(tive signal )se' to -a:e )p the system *rom 0H state 3so*t o**4. &his signal is triggere' on the *alling e'ge. 9eset inp)t signal. &his signal may +e 'riven to lo+y external (ir()itry s)(h as a reset +)tton to hol' the system mo')le in har'-are reset.
in
>%#
$8O
I 2.2@ 0tan'+y CMO0 I 2.2@ 0tan'+y CMO0
Comment
0N0 9E0E&R >49
C> 9E0E&R
>H0
9eset o)tp)t signal *rom mo')le to (arrier +oar'. O 2.2@ &his signal may +e 'riven lo- +y the mo')le to reset 0tan'+y external (omponents lo(ate' on the (arrier +oar'. CMO0 Po-er OS stat)s signal generate' +y the <&L po-er I 2.2@ s)pply to noti*y the mo')le that the !C operating CMO0 voltages are -ithin the ranges re,)ire' *or proper operation. 0)spen' stat)s signal to in'i(ate that the system -ill O 2.2@ +e entering a lopo-er state soon. It (an +e )se' 0tan'+y +y other peripherals on the (arrier +oar' as an CMO0 in'i(ation that they sho)l' go into po-er6'o-n mo'e. 02 0leep (ontrol signal in'i(ating that the system resi'es in 02 state 30)spen' to 9<M4. 04 0leep (ontrol signal in'i(ating that the system resi'es in 04 state 30)spen' to !is:4. 0H 0leep Control signal in'i(ating that the system resi'es in 0H 0tate 30o*t O**4. PCI Express -a:e6)p event signal. O 2.2@ 0tan'+y CMO0 O 2.2@ 0tan'+y CMO0 O 2.2@ 0tan'+y CMO0 I 2.2@ 0tan'+y CMO0 I 2.2@ 0tan'+y CMO0 I 2.2@ 0tan'+y CMO0 =se' *or -a:e6)p +y P0$# :ey+oar' or mo)se. &his signal (an +e )se' to (ontrol the <&L po-er s)pply via the 4#%6ON94 signal.
PA9 OS
>#4
0=0 0&<&R
>%K
0=0 02R
<%H
0=0 04R
<%K
0=0 0HR
<#4
A<SE0R
>66
A<SE%R
>67
"eneral p)rpose -a:e6)p signal. May +e )se' to implement -a:e6)p +y 0)per I$O a(tivity. >attery lo- inp)t. &his signal may +e 'riven lo- +y external (ir()itry to signal that the system +attery is lo-. It also (an +e )se' to signal some other external po-er management event.
><&8OAR
<#7
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6.+:.6
)herma# Management
COM Express provi'es the 4T<5M94 an' 4T<5MT5$#94 signals. -hi(h are )se' *or system thermal management. In most ()rrent system plat*orms thermal management is (losely asso(iate' -ith system po-er management. Bor more 'etaile' in*ormation a+o)t the thermal management (apa+ilities o* the COM Express mo')le re*er to the mo')leFs )serFs g)i'eF. )a&#e 6/49 )herma# Management %igna# Des"riptions
in
>2H
%igna#
&E9MR
Des"ription
&hermal <larm a(tive lo- signal generate' +y the external har'-are to in'i(ate an over temperat)re sit)ation. &his signal (an +e )se' to initiate thermal throttling. &hermal &rip in'i(ates an overheating (on'ition o* the pro(essor. I* 4T<5MT5$#94 goes a(tive the system imme'iately transitions to the 0H 0tate 30o*t O**4.
$8O
I 2.2@ 0tan'+y CMO0 O 2.2@ 0tan'+y CMO0
Comment
&E9M&9IPR
<2H
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6.+> Mis"e##aneous %igna#s

)a&#e 6/4B
%igna#
&ype0R &ype%R &ype#R
Mis"e##aneous %igna# Des"riptions

in Des"ription $8O Comment
CH4 &he &ype pins in'i(ate the COM Express pino)t O H@ CH7 type o* the mo')le. &o in'i(ate the mo')leFs pino)t P!0 !H7 type. the pins are either not (onne(te' or strappe' to gro)n' on the mo')le. &he (arrier +oar' has to implement a''itional logi(. -hi(h prevents the system to s-it(h po-er on. i* a mo')le -ith an in(ompati+le pino)t type is 'ete(te'. >2# O)tp)t )se' to (ontrol an external BE& or a logi( gate to 'rive an external PC spea:er. O 2.2@ CMO0 9e*er to se(tion H.%0.2 F<ppli(ation Example1 External Birm-are E)+F.
0PS9
>IO0 !I0<>8ER <24 Inp)t to 'isa+le the mo')les >IO0 *lash memory I 2.2@ (hip. &his signal provi'es the a+ility to implement an CMO0 external >IO0 *lash memory (hip that (an +e lo(ate' on the (arrier +oar'. A!& S>! 90&R S>! <#0"<&E >#7 O)tp)t in'i(ating that a -at(h'og time6o)t event has o(()rre'. <K6 Inp)t signal o* the mo')le )se' +y an external :ey+oar' (ontroller to *or(e a system reset. <K7 Inp)t signal o* the mo')le )se' +y an external :ey+oar' (ontroller to (ontrol the CP= <#0 gate line. &he <#0 gate restri(ts the memory a((ess to the +ottom mega+yte o* the system. P)lle' high on the mo')le. O 2.2@ CMO0 I 2.2@ CMO0 I 2.2@ CMO0
"PO0 "PO% "PO# "PO2 "PI0 "PI% "PI# "PI2
<92 "eneral P)rpose O)tp)ts *or system spe(i*i( )sage. O 2.2@ >H4 CMO0 >H7 >62 <H4 "eneral P)rpose Inp)t *or system spe(i*i( )sage. <62 &he signals are p)lle' )p +y the mo')le. <67 <KH I 2.2@ CMO0
9e*er to the mo')leFs )sers g)i'e *or in*ormation a+o)t the *)n(tionality o* these signals. 9e*er to the mo')leFs )sers g)i'e *or in*ormation a+o)t the *)n(tionality o* these signals.
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6.+>.+
Modu#e )ype Dete"tion

&he COM Express 0pe(i*i(ation in(l)'es three signals to 'etermine the pino)t type o* the mo')le (onne(te' to the (arrier +oar'. I* an in(ompati+le mo')le pino)t type is 'ete(te'. an external logi( sho)l' prevent the (arrier +oar' *rom po-ering )p the -hole system +y (ontrolling the 4#%6ON94 signal o* the <&L po-er s)pply. &he pins 4TM# '94. 4TM# /94 an' 4TM# .94 are either le*t open 3GC4 or strappe' to gro)n' 3"G!4 +y the mo')le to en(o'e the pino)t type a((or'ing to the *ollo-ing ta+le. &he Mo')le &ype % 'oesnFt nee' any en(o'ing +e(a)se it is a s)+set o* all other mo')le types. Bor more in*ormation a+o)t this s)+/e(t re*er to the COM Express 0pe(i*i(ation. )a&#e 6/52 Modu#e inout )ype En"oding
in )G E27
L 3'onFt (are4 GC GC GC GC
Modu#e )ype
Mo')le &ype % Mo')le &ype # Mo')le &ype 2 Mo')le &ype 4 Mo')le &ype H
in )G E+7
L 3'onFt (are4 GC GC "G! "G!
in )G E-7
L 3'onFt (are4 GC "G! GC "G! Go I!E inter*a(e Go PCI inter*a(e Go I!E. no PCI inter*a(e
6.+>.+.+ Modu#e )ype Dete"tion Re!eren"e %"hemati"s

&he *ollo-ing re*eren(e s(hemati(s ill)strates a 'ete(tion (ir()itry *or &ype # mo')les. I* any mo')le type other than &ype # is (onne(te'. the 4#%6ON94 signal. -hi(h (ontrols the <&L po-er s)pply. is lo(:e' +y the signal 4TM# 6#%ON6CT5794 to prevent po-ering )p. In this (ase the re' 8E! in'i(ates a -rong mo')le type. &he type 'ete(tion pins o* the mo')le m)st +e p)lle' )p +y the H@ stan'+y voltage o* the po-er s)pply. ,igure 6/55 Modu#e )ype - Dete"tion Cir"uitry
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6.+>.-
%pea*er Output
&he COM Express mo')le provi'es a spea:er o)tp)t signal (alle' 4%#854, -hi(h is inten'e' to 'rive an external BE& or a logi( gate to (onne(t a PC spea:er. &he 4%#854 signal (an +e *o)n' on the mo')les pin >2#. &he 4%#854 signal is o*ten )se' as (on*ig)ration strap *or the mo')les (hipset. It sho)l' not +e (onne(te' to a p)ll6)p or p)ll6'o-n resistor. -hi(h (o)l' over-rite the internal (hipset (on*ig)ration an' res)lt in a mal*)n(tion o* the mo')le. &he *ollo-ing re*eren(e s(hemati(s ill)strates a (ir()itry *or an a(tive pie7oele(tri( spea:er FEN60HF *rom ENCOM 3http1$$---.hy(om'evi(e.(om.t-4.
6.+>.-.+ %pea*er Output Re!eren"e %"hemati"s

,igure 6/56 %pea*er Output Cir"uitry
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6.+>.4
R)C 1attery $mp#ementation

&he 9eal &ime Clo(: 39&C4 is responsi+le *or maintaining the time an' 'ate even -hen the COM Express mo')le is not (onne(te' to a main po-er s)pply. =s)ally a O2@ lithi)m +attery (ell is )se' to s)pply the internal 9&C o* the mo')le. &he COM Express 0pe(i*i(ation 'e*ines an extra po-er pin 4;CC65TC4, -hi(h (onne(ts the 9&C o* the mo')le to the external +attery. &he spe(i*ie' inp)t voltage range o* the +attery is 'e*ine' +et-een O#.0@ an' O2.0@. &he signal 4;CC65TC4 (an +e *o)n' on the mo')leFs (onne(tor ro- < pin <47.
6.+>.4.+ R)C 1attery Re!eren"e Cir"uitry

&o implement the 9&C >attery a((or'ing to the =n'er-riters 8a+oratories In(C 3=84 g)i'elines. +attery (ells m)st +e prote(te' against a reverse ()rrent going to the (ell. &his (an +e 'one +y either a series 0(hott:y 'io'e or a series resistor. &here are t-o implementation possi+ilities an' the *ollo-ing examples explain the a'vantages an' 'isa'vantages o* ea(h one. &he sa*est -ay. an' the one re(ommen'e' +y the COM Express PnP Initiative. is to implement a 9&C +attery (ir()itry )sing a 0(hott:y 'io'e as sho-n in Big)re H646. &his metho' o**ers prote(tion against a possi+le explosion ha7ar' as a res)lt o* reverse ()rrent *lo-ing to the +attery. Moreover. this implementation o**ers more *lexi+ility -hen (hoosing +attery type an' man)*a(t)rer. 8ithi)m +atteries are the most (ommon *orm o* +attery )se' in this s(enario. < +ig 'ra-+a(: o* this (ir()itry is that the +attery voltage monitoring res)lt 'isplaye' +y the COM Express mo')le -ill +e ina(()rate ')e to ()rrent lea:age on the mo')le si'e. Ahen the system is r)nning this ()rrent lea:age loa's (apa(itor C9% o* the +attery (ir()itry. &his lea's to a higher voltage on the signal pin 4;CC65TC4 an' there*ore pro')(es ina(()rate monitoring res)lts. ,igure 6/5: R)C 1attery Cir"uitry .ith %eria# %"hott*y Diode
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&he se(on' implementation possi+ility *or a 9&C +attery (ir()itry on the (arrier +oar' is the )se o* t-o serial resistors as sho-n in Big)re H647. &his type o* 9&C +attery (ir()itry -ill provi'e a(()rate +attery voltage monitoring on the mo')leFs 4;CC65TC4 signal pin. Only a *e- man)*a(t)rers o**er +atteries types that allo- a reverse ()rrent an' (an +e )se -ith this :in' o* +attery (ir()itry. One o* the t-o serial resistors m)st limit the reverse ()rrent to the val)e spe(i*ie' *or the +attery. 9e*er to the +attery spe(i*i(ation or (onta(t yo)r +attery man)*a(t)rer *or in*ormation a+o)t the maxim)m allo-e' reverse ()rrent o* the +attery yo) have (hosen. Caution Be aware, if a battery that does not permit a reverse current flow is implemented using the circuitry displayed on 3igure +-=* there is a strong possibility that the battery could e!plode and cause personal injury and,or damage to the system. ,igure 6/5> R)C 1attery Cir"uitry .ith %eria# Resistors
(ote The battery is part of your system design. Consult the appropriate system safety certification lab about the implications of choosing the 5TC Battery Circuitry method displayed in 3igure +-=*. The COM !press" #n# $nitiative cannot be held responsible for any damage when using the 5TC Battery Circuitry method displayed in 3igure +-=* with battery types that do not permit reverse current flow. The battery manufacturer 5enata clearly specifies reverse current flows for their batteries and therefore 5enata batteries are recommend by the COM !press" #n# $nitiative when using the 5TC Battery Circuitry method displayed in 3igure +-=*. The COM !press" #n# $nitiative also recommends that a warning label be placed on or near the carrier board battery soc>et to indicate the appropriate manufacturer and model of battery that must be used to avoid creating an e!plosion haKard. This applies regardless of which 5TC Battery Circuitry method has been implemented on the carrier board.
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6.+>.4.- R)C 1attery 3i!etime

&he 9&C +attery li*etime 'etermines the time interval +et-een system +attery repla(ement (y(les. C)rrent lea:age *rom the 9&C +attery (ir()itry on the (arrier +oar' is a serio)s iss)e an' m)st +e (onsi'ere' ')ring the system 'esign phase. &he ()rrent lea:age -ill in*l)en(e the 9&C +attery li*etime an' m)st +e *a(tore' in -hen a spe(i*i( li*e expe(tan(y o* the system +attery is +eing 'e*ine'. In or'er to a(()rately meas)re the val)e o* the 9&C ()rrent it sho)l' +e meas)re' -hen the (omplete system is 'is(onne(te' *rom <C po-er.
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3ayout Design Constraints

&his (hapter provi'es ro)ting g)i'elines *or layo)t an' 'esign o* a printe' (ir()it +oar' )sing high6spee' inter*a(es s)(h as PCI Express. PE". 0erial <&<. 8@!0. "iga+it Ethernet an' =0> #.0. &he signal integrity r)les *or high6spee' inter*a(es nee' to +e (onsi'ere'. In *a(t. it is highly re(ommen'e' that the +oar' 'esign +e sim)late' to 'etermine optim)m layo)t *or signal integrity an' ,)ality. Seep in min' that this 'o()ment (an only point to the most important iss)es that sho)l' +e (onsi'ere' -hen 'esigning an COM Express (arrier +oar'. &he 'esigner has to ta:e into a((o)nt the (orrespon'ing in*ormation 3spe(i*i(ation. 'esign g)i'elines. e(t.4 (ontaine' in the 'o()mentation *or ea(h inter*a(e that is to +e implemente' on their (arrier +oar'. (ote 3or more information about #CB design considerations we recommend you refer to the boo> Q#C$ !press lectrical $nterconnect CesignR available from $ntel Ehttp&,,www.intel.com,intelpress,D $%BN '-G*=:F=G-G-/.
:.+ Mi"rostrip or %trip#ine

Either e'ge6(o)ple' mi(rostrip. e'ge6(o)ple' stripline. or +roa'6si'e striplines are re(ommen'e' *or 'esigns -ith 'i**erential signals. !esigns -ith mi(rostrip lines o**er the a'vantage that a lo-er n)m+er o* layers (an +e )se'. <lso. -ith mi(rostrip lines it may +e possi+le to ro)te *rom a (onne(tor pa' to the 'evi(e pa' -itho)t any via. &his provi'es +etter signal ,)ality on the signal path that (onne(ts 'evi(es. < limitation o* mi(rostrip lines is that they (an only +e ro)te' on the t-o o)tsi'e layers o* the PC>. th)s ro)ting (hannel 'ensity is limite'. 0tripline may +e either e'ge6(o)ple' or +roa'6si'e (o)ple' lines. 0tripline 'esigns provi'e a''itional shiel'ing sin(e they are em+e''e' in the +oar' sta(: an' are typi(ally san'-i(he' +et-een gro)n' an' po-er planes. &his re')(es ra'iation an' (o)pling o* noise onto the lines. 0triplines have the 'isa'vantage that they re,)ire the )se o* vias to (onne(t to them.
:.- rinted Cir"uit 1oard %ta"*up Examp#e

It is re(ommen'e' to )se PC>Fs -ith at least a 4 layer sta(:)p -here the impe'an(e (ontrolle' layer % 3top layer4 is )se' *or 'i**erential signals an' layer 4 3+ottom layer4 *or other perio'i( signals 3CMO0$&&84. &he 'e'i(ate' po-er planes 3layer # 5 "G! an' layer 2 5 @CC4 are typi(ally re,)ire' *or high6spee' 'esigns. &he soli' gro)n' plane is ne(essary to esta+lish a (ontrolle' 3:no-n4 impe'an(e *or the transmission line inter(onne(ts. < narro- spa(ing +et-een po-er an' gro)n' planes -ill a''itionally (reate an ex(ellent high *re,)en(y +ypass (apa(itan(e. &he *ollo-ing example sho-s a *o)r layer PC> sta(:)p )sing mi(rostrip tra(e ro)ting. < goo' r)le to *ollo- *or mi(rostrip 'esigns is to :eep 0 ^ A an' 0 ^ E 3IEJ _ spa(e +et-een 'i**erential signal layers an' the re*eren(e plane4. &he +est pra(ti(e is to )se
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the (losest spa(ing. I0.J allo-e' +y yo)r PC> ven'or an' then a'/)st tra(e -i'ths. IA.J to (ontrol 'i**erential impe'an(e. ,igure :/+ 5 3ayer C1 Mi"rostrip Routing
' % '
3+/)op/%igna#
3plate' %$#o7 C)4
# mils
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`r a 4.%
4.4 mils %.4 mils
3-/ Re!eren"e8ACC8A%%
3)nplate' %o7 C)4
Core
34/ Re!eren"e8A%%
3)nplate' %o7 C)4
47 mils
%.4 mils
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`r a 4.%
4.4 mils # mils
35/1ottom/%igna#
3plate' %$#o7 C)4
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Bor stripline ro)ting. a PC> sta(:)p o* at least 6 layers is ne(essary. &he internal layers 382 an' 844 (an +e )se' *or ro)ting 'i**erential signals as stripline tra(es -hile the o)ter layers 38% an' 864 (an +e )se' *or mi(rostrip ro)ting. ,igure :/: 3ayer C1 %trip#ine and Mi"rostrip Routing
' % '
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3plate' %$#o7 C)4
# mils
3-/ Re!eren"e8ACC
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4.2 mils %.4 mils 6.H mils
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#2mils
6.H mils %.4 mils
&hin(ore
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`r a 4.%
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3)nplate' %o7 C)4
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3plate' %$#o7 C)4
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>
Genera# Considerations !or High/%peed Di!!erentia# $nter!a"es

&he *ollo-ing is a list o* s)ggestions *or 'esigning -ith high6spee' 'i**erential signals. &his sho)l' help implement these inter*a(es -hile provi'ing maxim)m COM Express (arrier +oar' per*orman(e.
=se (ontrolle' impe'an(e PC> tra(es that mat(h the spe(i*ie' 'i**erential impe'an(e. Seep the tra(e lengths o* the 'i**erential signal pairs as short as possi+le. &he 'i**erential signal pair tra(es sho)l' +e tra(e6length mat(he' an' the maxim)m tra(e6length mismat(h sho)l' not ex(ee' the spe(i*ie' val)es. Mat(h ea(h 'i**erential pair per segment. Maintain parallelism an' symmetry +et-een 'i**erential signals -ith the tra(e spa(ing nee'e' to a(hieve the spe(i*ie' 'i**erential impe'an(e. Maintain maxim)m possi+le separation +et-een the 'i**erential pairs an' any high6spee' (lo(:s$perio'i( signals 3CMO0$&&84 an' any (onne(tor leaving the PC> 3s)(h as. I$O (onne(tors. (ontrol an' signal hea'ers. or po-er (onne(tors4. 9o)te 'i**erential signals on the signal layer nearest to the gro)n' plane )sing a minim)m o* vias an' (orners. &his -ill re')(e signal re*le(tions an' impe'an(e (hanges. =se "G! stit(hing vias -hen (hanging layers. It is +est to p)t CMO0$&&8 an' 'i**erential signals on a 'i**erent layer3s4. -hi(h sho)l' +e isolate' +y the po-er an' gro)n' planes. <voi' tight +en's. Ahen it +e(omes ne(essary to t)rn 90b. )se t-o 4Hb t)rns or an ar( instea' o* ma:ing a single 90b t)rn. !o not ro)te tra(es )n'er (rystals. (rystal os(illators. (lo(: synthesi7ers. magneti( 'evi(es or ICs that )se. an'$or generate. (lo(:s. 0t)+s on 'i**erential signals sho)l' +e avoi'e' ')e to the *a(t that st)+s -ill (a)se signal re*le(tions an' a**e(t signal ,)ality. Seep the length o* high6spee' (lo(: an' perio'i( signal tra(es that r)n parallel to high6spee' signal lines at a minim)m to avoi' (rosstal:. >ase' on EMI testing experien(e. the minim)m s)ggeste' spa(ing to (lo(: signals is H0mil. =se a minim)m o* #0mil spa(ing +et-een the 'i**erential signal pairs an' other signal tra(es *or optimal signal ,)ality. &his helps to prevent (rosstal:. 9o)te all tra(es over (ontin)o)s planes 3@CC or "G!4 -ith no interr)ptions. <voi' (rossing over anti6et(h i* at all possi+le. Crossing over anti6et(h 3split planes4 in(reases in')(tan(e an' ra'iation levels +y *or(ing a greater loop area. 3ayout Considerations
,igure >/+
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In or'er to 'etermine the ne(essary tra(e -i'th. tra(e height an' spa(ing nee'e' to *)l*ill the re,)irements o* the inter*a(e spe(i*i(ation. itFs ne(essary to )se an impe'an(e (al()lator.
COMExpressPnP !" 09
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>.+ C$ Express )ra"e Routing Guide#ines

arameter
&rans*er 9ate $ PCIe 8ane Maxim)m signal line length 3(o)ple' tra(es4 Maxim)m signal length allo-an(e on the COM Express mo')le 0ignal length allo-an(e on the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een 9L an' &L pairs 3inter6pair4 3s4
)ra"e Routing
#.H "+its$se( &L an' 9L path1 #%.0 in(hes &L an' 9L path1 H.%H in(hes &L an' 9L path1 %H.KH in(hes P 0.#K'>$"E7$in(h to PCIe 'evi(e 9.00 in(hes P 0.#K'>$"E7$in(h to PCIe slot %00 Ohms O$6#0Z HH Ohms O$6%HZ H mils 3mi(rostrip ro)ting4 3U4 4 mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' Min. H0mils perio'i( signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een 9L an' &L pairs 3inter6pair4 8ength mat(hing +et-een re*eren(e (lo(: 'i**erential pairs 9EBC8SO an' 9EBC8S6 3intra6pair4 8ength mat(hing +et-een re*eren(e (lo(: pairs 3inter6pair4 9e*eren(e plain 0pa(ing *rom e'ge o* plane @ia =sage <C (o)pling (apa(itors Min. #0mils Max. Hmils Go stri(t ele(tri(al re,)irements. Seep 'i**eren(e -ithin a 2.0 in(h 'elta to minimi7e laten(y. Max. Hmils
Go ele(tri(al re,)irements. "G! re*eren(e' pre*erre' Min. 40mils Max. # vias per &L tra(e Max. 4 vias per 9L tra(e &he <C (o)pling (apa(itors *or the &L lines are in(orporate' on the COM Express mo')le. &he <C (o)pling (apa(itors *or 9L signal lines have to +e implemente' on the ()stomer COM Express (arrier +oar'. Capa(itor type1 L79. %00nB O$6%0Z. %6@. shape 040#.
(ote E0D $n order to determine the value for trace width, trace height and differential pair spacing that matches the differential impedance determined by your #CB, it4s necessary to use an ade2uate impedance calculator.
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>.- =%1 )ra"e Routing Guide#ines

arameter
&rans*er rate $ Port Maxim)m signal line length 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the COM Express (onne(tor4 0ignal length allo-an(e *or the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een pairs6to6pairs 3inter6pair4 3s4
)ra"e Routing
4K0 M+it$s Max. %7.0 in(hes 2.0 in(hes %4.0 in(hes 90 Ohms O$6%HZ 4H Ohms O$6%0Z Hmils 3mi(rostrip ro)ting4 3U4 6mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' perio'i( Min. H0mils signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 9e*eren(e plain 0pa(ing *rom e'ge o* plane @ia =sage Min. #0mils %H0mils "G! re*eren(e' pre*erre' Min. 40mils &ry to minimi7e n)m+er o* vias
(ote E0D $n order to determine the value for trace width, trace height and differential pair spacing that matches the differential impedance determined by your #CB, it4s necessary to use an impedance calculator.
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>.4 EG )ra"e Routing Guide#ines

arameter
&rans*er 9ate $ PCIe 8ane Maxim)m signal line length 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the (arrier +oar' (onne(tor4 0ignal length allo-an(e *or the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een 9L an' &L pairs 3inter6pair4 3s4
)ra"e Routing
#.H "+its$se( &L path1 6.H in(hes 9L path1 6.H in(hes &L path1 # in(hes 9L path1 # in(hes &L path1 4.H in(hes to PE" 'evi(e an' 2.H in(hes to PE" slot 9L path1 4.H in(hes to PE" 'evi(e an' 2.H in(hes to PE" slot %00 Ohms O$6#0Z HH Ohms O$6%HZ Hmils 3mi(rostrip ro)ting4 3U4 %#mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' Min. H0mils perio'i( signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een 9L an' &L pairs 3inter6pair4 8ength mat(hing +et-een re*eren(e (lo(: 'i**erential pairs 9EBC8SO an' 9EBC8S6 3intra6pair4 8ength mat(hing +et-een re*eren(e (lo(: pairs 3inter6pair4 0pa(ing *rom e'ge o* plane @ia )sage <C (o)pling (apa(itors Min. #0mils Max. Hmils Go stri(t ele(tri(al re,)irements. Seep 'i**eren(e -ithin a 2.0 in(h 'elta to minimi7e laten(y. Max. Hmils
Go ele(tri(al re,)irements. Min. 40mils Max. # vias per &L tra(e on the mo')les (onne(tor Max. 4 vias per 9L tra(e on the mo')les (onne(tor &he <C (o)pling (apa(itors *or the &L transmit signal lines are in(orporate' on the COM Express mo')le. &he <C (o)pling (apa(itors *or 9L re(eive signal lines have to +e implemente' on the ()stomer COM Express (arrier +oar'. Capa(itor type1 L79. %00nB O$6%0Z. %6@. shape 040#.
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>.5 %DAO )ra"e Routing Guide#ines

arameter
&rans*er 9ate $ 0!@O 8ane Maxim)m signal line length 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the (arrier +oar' (onne(tor4 0ignal length allo-an(e *or the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een pairs6to6pair
)ra"e Routing
=p to #.0 "+its$se( 7 in(hes # in(hes H in(hes to 0!@O 'evi(e %00 Ohms O$6#0Z HH Ohms O$6%HZ H mils 3mi(rostrip ro)ting4 3U4 7 mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' perio'i( Min. H0mils signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een 'i**erential pairs 3inter6pair4 8ength mat(hing +et-een 'i**erential signal pair an' 'i**erential (lo(: pair 0pa(ing *rom e'ge o* plane @ia =sage <C (o)pling (apa(itors Min. #0mils Max. Hmils Seep 'i**eren(e -ithin a #.0 in(h 'elta. Max. Hmils Min. 40mils Max. 4 vias per 'i**erential signal tra(e <C Co)pling (apa(itors on the signals 4%C;O6$NT)4 an' 4%C;O$NT-4 have to +e implemente' on the ()stomer COM Express (arrier +oar'. Capa(itor type1 L79. %00nB O$6%0Z. %6@. shape 040#.
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>.6 3A( )ra"e Routing Guide#ines

arameter
&rans*er 9ate Maxim)m signal line length 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the (arrier +oar' (onne(tor4 0ignal length allo-an(e *or the COM Express (arrier +oar' Maxim)m signal length +et-een isolation magneti(s mo')le an' 9V4H (onne(tor on the (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een 9L an' &L pairs 3inter6pair4 3s4
)ra"e Routing
%.0 "+its$se( K.0 in(hes spe(i*ie' +y COM Express 2.0 in(hes spe(i*ie' +y COM Express H.0 in(hes to the magneti(s mo')le %.0 in(h 9H Ohms O$6#0Z HH Ohms O$6%HZ Hmils 3mi(rostrip ro)ting4 3U4 7mils 3mi(rostrip ro)ting4 3U4 Min. H0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' perio'i( Min. 200mils signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een 9L an' &L pairs 3inter6pair4 0pa(ing +et-een 'igital gro)n' an' analog gro)n' plane 3+et-een the magneti(s mo')le an' 9V4H (onne(tor4 0pa(ing *rom e'ge o* plane @ia =sage Min. %00mils Max. Hmils Max. 20mils Min. 60mils Min. 40mils Max. o* # vias on &L path Max. o* # vias on 9L path
COMExpressPnP !" 09
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>.: %eria# A)A )ra"e Routing Guide#ines

arameter
&rans*er 9ate Maxim)m signal line length 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the COM Express (arrier +oar' (onne(tor4 0ignal length availa+le *or the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pairs 3intra6pair4 304 0pa(ing +et-een 9L an' &L pairs 3inter6pair4 3s4
)ra"e Routing
2.0 "+its$se( 7.0 in(hes on PC> 3COM Express mo')le an' (arrier +oar'. &he length o* the 0<&< (a+le is spe(i*ie' +et-een 0 an' 40 in(hes4 #.H in(hes 4.H in(hes %00 Ohms O$6#0Z HH Ohms O$6%HZ Hmils 3mi(rostrip ro)ting4 3U4 7mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' perio'i( Min. H0mils signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een 9L an' &L pairs 3inter6pair4 Min. #0mils Max. Hmils Go stri(t ele(tri(al re,)irements. Seep 'i**eren(e -ithin a 2.0 in(h 'elta to minimi7e laten(y. !o not serpentine to meet tra(e length g)i'elines *or the 9L an' &L path. Min. 40mils &ry to minimi7e n)m+er o* vias &he <C (o)pling (apa(itors *or the &L an' 9L lines are in(orporate' on the COM Express mo')le.
0pa(ing *rom e'ge o* plane @ia =sage <C Co)pling (apa(itors
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>.> 3AD% )ra"e Routing Guide#ines

arameter
&rans*er 9ate Maxim)m signal line length to the 8@!0 (onne(tor 3(o)ple' tra(es4 0ignal length )se' on COM Express mo')le 3in(l)'ing the COM Express (arrier +oar' (onne(tor4 0ignal length to the 8@!0 (onne(tor availa+le *or the COM Express (arrier +oar' !i**erential Impe'an(e 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een 'i**erential pair signals 3intra6pair4 304 0pa(ing +et-een pair to pairs 3inter6pair4 3s4
)ra"e Routing
H.2K "+its$se( K.7H in(hes #.0 in(hes 6.7H in(hes %00 Ohms O$6#0Z HH Ohms O$6%HZ 4mils 3mi(rostrip ro)ting4 3U4 7mils 3mi(rostrip ro)ting4 3U4 Min. #0mils
0pa(ing +et-een 'i**erential pairs an' high6spee' perio'i( Min. #0mils signals 0pa(ing +et-een 'i**erential pairs an' lo-6spee' non perio'i( signals 8ength mat(hing +et-een 'i**erential pairs 3intra6pair4 8ength mat(hing +et-een (lo(: an' 'ata pairs 3inter6pair4 8ength mat(hing +et-een 'ata pairs 3inter6pair4 0pa(ing *rom e'ge o* plane 9e*eren(e plain @ia =sage Min. #0mils O$6 #0mils O$6 #0mils O$6 40mils O$6 40mils "G! re*eren(e' pre*erre' Max. o* # vias per line
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Genera# Considerations !or %ing#e Ended $nter!a"es

&he *ollo-ing is a list o* s)ggestions *or 'esigning -ith signal en'e' signals. &his sho)l' help implement these inter*a(es -hile provi'ing maxim)m COM Express (arrier +oar' per*orman(e.
!o not ro)te tra(es )n'er (rystals. (rystal os(illators. (lo(: synthesi7ers. magneti( 'evi(es or ICs that )se. an'$or generate. (lo(:s. <voi' tight +en's. Ahen it +e(omes ne(essary to t)rn 90b. )se t-o 4Hb t)rns or an ar( instea' o* ma:ing a single 90b t)rn. 0t)+s on signals sho)l' +e avoi'e' ')e to the *a(t that st)+s -ill (a)se signal re*le(tions an' a**e(t signal ,)ality. Seep the length o* high6spee' (lo(: an' perio'i( signal tra(es that r)n parallel to high6spee' signal lines at a minim)m to avoi' (rosstal:. >ase' on EMI testing experien(e. the minim)m s)ggeste' spa(ing to (lo(: signals is H0mil. 9o)te all tra(es over (ontin)o)s planes -ith no interr)ptions 3gro)n' re*eren(e pre*erre'4. <voi' (rossing over anti6et(h i* at all possi+le. Crossing over anti6et(h 3split planes4 in(reases in')(tan(e an' ra'iation levels +y *or(ing a greater loop area. 9o)te 'igital po-er an' signal tra(es over the 'igital gro)n' plane. Position the +ypassing an' 'e(o)pling (apa(itors (lose to the IC pins -ith -i'e tra(es to re')(e impe'an(e.
COMExpressPnP !" 09
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9.+ C$ )ra"e Routing Guide#ines

arameter
&rans*er 9ate P 22ME7 0ignal length )se' on COM Express mo')le 3in(l)'ing the COM Express (arrier +oar' (onne(tor4 Maxim)m 'ata an' (ontrol signal length allo-an(e *or the COM Express (arrier +oar'. Maxim)m (lo(: signal length allo-an(e *or the COM Express (arrier +oar'. 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een signals 3inter6signal4 304 8ength mat(hing +et-een single en'e' signals 8ength mat(hing +et-een (lo(: signals 0pa(ing *rom e'ge o* plane 9e*eren(e plain @ia =sage !e(o)pling (apa(itors *or ea(h PCI slot.
)ra"e Routing
%2# M>$se( 2.0 in(hes %0 in(hes K.KK in(hes HH Ohms O$6%HZ Hmils 3mi(rostrip ro)ting4 3U4 7mils 3mi(rostrip ro)ting4 3U4 Max. #00mils Max. #00mils Min. 40mils "G! re*eren(e' pre*erre' &ry to minimi7e n)m+er o* vias Min. %x##WB. #x %00nB P @CC H@ Min. #x##WB. 4x %00nB P @CC 2.2@ Min. %x##WB. #x %00nB P O%#@ 3i* )se'4 Min. %x##WB. #x %00nB P 6%#@ 3i* )se'4 &he 'e(o)pling (apa(itors *or the po-er rails sho)l' +e pla(e' as (lose as possi+le to the slot po-er pins (onne(te' -ith -i'e tra(es.
(ote E0D $n order to determine the value for trace width and trace height it4s necessary to use an impedance calculator.
COMExpressPnP !" 09
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9.- $DE )ra"e Routing Guide#ines

arameter
Maxim)m &rans*er 9ate P <&<%00 0ignal length )se' on COM Express mo')le.
)ra"e Routing
%00 M>$se( 2.0 in(hes
Maxim)m length allo-an(e *or signals on the COM Express 7.0 in(hes (arrier +oar' P <&<%00. 0ingle6en'e' Impe'an(e &ra(e -i'th 3A4 0pa(ing +et-een signals 3inter6signal4 304 8ength mat(hing +et-een stro+e an' 'ata signals 8ength mat(hing +et-een 'ata signals 8ength mat(hing +et-een stro+e signals 4$C 6$O54 an' 4$C 6$OW4. 0pa(ing *rom e'ge o* plane 9e*eren(e plain @ia =sage HH Ohms O$6%HZ Hmils 3mi(rostrip ro)ting4 3U4 7mils 3mi(rostrip ro)ting4 3U4 Max. 4H0mils Max. #00mils Max. %00mils Min. 40mils "G! re*eren(e' pre*erre' &ry to minimi7e n)m+er o* vias
(ote E0D $n order to determine the value for trace width and trace height it4s necessary to use an impedance calculator.
COMExpressPnP !" 09
%%K$%%9
$ndustry %pe"i!i"ations
&he list +elo- provi'es lin:s to in')stry spe(i*i(ations that sho)l' +e )se' as re*eren(e material -hen 'esigning a COM Express (arrier +oar'.
%pe"i!i"ation
PICM" COM Express Mo')le >ase 0pe(i*i(ation
C
3in*
http1$$---.pi(mg.org$ http1$$---.p(isig.(om$spe(i*i(ations http1$$---.p(isig.(om$spe(i*i(ations http1$$---.)s+.org$home http1$$---.express(ar'.org$ http1$$---.serialata.org http1$$'eveloper.intel.(om$'esign$(hipsets$in')stry$lp(.htm http1$$---.intel.(om$'esign$(hipsets$a)'io$ http1$$---.intel.(om$stan'ar's$h'a)'io$ http1$$---.national.(om
PCI Express >ase 0pe(i*i(ation. 9evision #.0 PCI 8o(al >)s 0pe(i*i(ation. 9evision #.2 =niversal 0erial >)s 3=0>4 0pe(i*i(ation. 9evision #.0 ExpressCar' 0tan'ar' 9elease %.0 0erial <&< 0pe(i*i(ation. 9evision %.0a 8o- Pin Co)nt Inter*a(e 0pe(i*i(ation. 9evision %.0 38PC4 <)'io Co'e( D97 Component 0pe(i*i(ation. @ersion #.2 Eigh !e*inition <)'io 0pe(i*i(ation. 9ev. %.0 8@!0 O-nerFs Man)al
Exten'e' !isplay I'enti*i(ation !ata 0tan'ar' @ersion %.2 http1$$---.vesa.org 3E!I!4 Enhan(e' !isplay !ata Channel 0pe(i*i(ation @ersion %.% http1$$---.vesa.org 3!!C4 IEEE stan'ar' K0#.2a+ %000><0E & Ethernet http1$$---.ieee.org$portal$site <'van(e' Con*ig)ration an' Po-er Inter*a(e 0pe(i*i(ation http1$$---.a(pi.in*o$ 9ev. 2.0a
&he *ollo-ing re*eren(e material *rom Min'share >oo:s is re(ommen' *or )se +y the COM Express PnP Initiative. Bor more in*ormation an' a''itional +oo:s visit ---.min'share.(om.
)it#e
PCI Express 0ystem <r(hite(t)re PCI 0ystem <r(hite(t)re 34th E'ition4 =niversal 0erial >)s 0ystem <r(hite(t)re 0<&< 0torage &e(hnology Prote(te' Mo'e 0o*t-are <r(hite(t)re 3&he PC 0ystem <r(hite(t)re 0eries4 &he =na+ri'ge' Penti)m 4
Author
9avi >)'r):. !on <n'erson. &om 0hanley &om 0hanley. !on <n'erson !on <n'erson !on <n'erson &om 0hanley &om 0hanley
<''itional +oo:s (overing vario)s PC ar(hite(t)re s)+/e(ts. that sho)l' +e )se' as re*eren(e material. (an +e *o)n' at ---.intel.(om$intelpress.
COMExpressPnP !" 09
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COM Express Design Guide

Guidelines for designing COM Express carrier boards

Design Guide Revision .09 (Preli inar!"

COM Express Preliminary release PnP Initiative

Copyright COM Express PnP Initiative

Copyright COM Express PnP Initiative

%"hemati"s (aming Conventions

Copyright COM Express PnP Initiative

E#e"trostati" %ensitive Devi"e

Copyright COM Express PnP Initiative

Con"ept o! COM Express)M

Copyright COM Express PnP Initiative

Copyright COM Express PnP Initiative

Copyright COM Express PnP Initiative

COM Express %pe"i!i"ation Overvie.

-.+ Modu#e ,orm ,a"tors

Copyright COM Express PnP Initiative

-.- Modu#e )ypes Overvie.

Modu#e )ype Conne"tors --2/pin

Copyright COM Express PnP Initiative

-.4 )ype - COM Express Modu#es

Copyright COM Express PnP Initiative

-.5 COM Express )ype - Modu#e

Copyright COM Express PnP Initiative

COM Express Conne"tors

4.+ Modu#e Conne"tors

4.- Carrier 1oard Conne"tors

5.0mm board-to-board stack height

8.0mm board-to-board stack height

Copyright COM Express PnP Initiative

Carrier 1oard Conne"tor #a"ement

Dua# Conne"tor ,ootprint and A#ignment

'.(mm )'.'*+,-'.'.+mm /.+mm )'.'*+,-'.'.+mm

Copyright COM Express PnP Initiative

COM Express Conne"tor inout

5.+ Conne"tor inout Ro.s A and 1

Copyright COM Express PnP Initiative

Copyright COM Express PnP Initiative

5.- Conne"tor inout Ro.s C and D

Modu#e )ype - Conne"tor inout Ro.s C and D

Copyright COM Express PnP Initiative

Copyright COM Express PnP Initiative

%igna# )a&#es )ermino#ogy Des"riptions

Copyright COM Express PnP Initiative

6.+ C$ Express ( C$e)

C$ Express %igna# Des"riptions

Copyright COM Express PnP Initiative

C$ Express x+0 x50 x9 and x+: Conne"tors

Copyright COM Express PnP Initiative

C$e x+0 x50 x9 and x+: Conne"tor %igna# Des"riptions

Copyright COM Express PnP Initiative

P90G&#R0 Eot6Pl)g presen(e 'ete(te'

P90G&#R0 Eot6Pl)g presen(e 'ete(te'

Copyright COM Express PnP Initiative

P90G&#R0 Eot6Pl)g presen(e 'ete(te'

End o! x+: Conne"tor

Copyright COM Express PnP Initiative

C$ Express $mp#ementation Guide#ines

6.+.-.+ C$ Express Re!eren"e C#o"*

Copyright COM Express PnP Initiative

6.+.-.- C$ Express Reset

6.+.-.4 C$ Express 3ane Con!igurations

Copyright COM Express PnP Initiative

'.(mm )'.'+,-'.'.+mm /.+mm )'.'+,-'.'.+mm