1.

Simulation Results

Figure 2: Schematic of circuit used in simulation

In the simulation only one input and output capacitor is present as we assume the electrolytic capacitors are ideal and that their series inductance does not affect the output. Also the sense resistor is absent, as well as the frequency defining components which is compensated for in the sawtooth signal created by Vpulse. Here the capacitor C5 is now labeled C11.

Figure 3: Simulation with Cout = 17uF (all other values same as schematic) Ripple is around 0.9 volts when ideally it should be 0.1 to 0.2 volts. An initial spike voltage of 8volts is worrying. Current is sitting on 1 Amp and rippling up to 1.2 Amps which may trigger the overcurrent protection of the chip.

Figure 4: Simulation with Cout = 47UF Ripple is over 1 volt and current ripple has also increased. The initial voltage spike has lowered to around 7.5 volts. The current is definitely a problem and should ideally sit just below 1 Amp so as to not limit the PWM output.

Figure 4: Simulation with Cout =100uF and Cin = 2200uF (left) and Cin = 1000uF (right) Initial voltage peak is roughly the same. The difference with the introduction of the smaller Cin is a reduction in ripple and a higher frequency output.

Figure 5: Simulation with Cout =22uF and Cin = 640uF Ripple is reduced, 4.84 to 5.85 volts. This shows that smaller capacitors work just as good. But ripple is still 1 volt.

Figure 6: Simulation with Cout =22uF and Cin = 1000uF Ripple is unchanged, at 4.85 to 5.9 volts.

Figure 7: Simulation with Cout =22uF and Cin = 2200uF Ripple is unchanged, ranging from 4.85 to 5.8 volts.

Figure 8: Simulation with Cout =22uF and Cin = 640uF and R17 = 1k Ripple hugely increased compared to figure 5 when R17 was 51k.

Figure 9: Simulation with Cout =22uF and Cin = 640uF and R17 = 40k and C10 = 10nF

Figure 10: Simulation with Cout =22uF and Cin = 2200uF and R17 = 40k and C10 = 10nF

Figure 11: Simulation with Cout =22uF and Cin = 2200uF and R17 = 50k and C10 = 10nF

Figure 12: Simulation with Cout =47uF and Cin = 2200uF and R17 = 50k and C10 = 10nF Ripple from 4.9 volts to 5.5 volts, which is an improvement.

Figure 13: Simulation with Cout =47uF and Cin = 2000uF and R17 = 50k and C10 = 10nF Ripple from 4.9 volts to 5.45 volts, which is a further improvement.

Figure 14: Simulation with Cout =47uF and Cin = 2000uF and R17 = 47k and C10 = 10nF

Ripple from 4.9 volts to 5.42 volts, with a voltage spike of 6volts. This simulation is deemed the best result thus far and will be used as an acceptable base for real world component values.

Figure 15: Simulation with Cout =47uF and Cin = 2200uF and R17 = 1k and C10 = 20nF 0.3 ripple!!

Figure 16: Simulation with Cout =47uF and Cin = 2200uF and R17 = 1k and C10 = 20nF with gate drive resistors decreased to 220 and 100Ohm 0.2 ripple!!