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Xu Ly Anh Video Dung FPGA Tren DE2-CLBRobot-RobotGiaoDuc
Xu Ly Anh Video Dung FPGA Tren DE2-CLBRobot-RobotGiaoDuc
\ .
va
2
1 0
0 1
H
| |
=
|
\ .
Chu y la cac ky thuat tren thc s ch la mo phong va xap x ao ham bang ky thuat
nhan chap do anh so la tn hieu ri rac, do vay ao ham thc s khong ton tai.
Vi ky thuat Sobel va Prewitt, ta s dung cap mat na:
H
x
=
1 0 1
2 0 2
1 0 1
| |
|
|
|
\ .
H y =
1 2 1
0 0 0
1 2 1
| |
|
|
|
\ .
Gradient c xap x bi cong thc:
x x
G H I =
va
y y
G H I =
Thc te cho thay toan t Sobel va Prewitt tot hn toan t Robert do t nhay cam vi
nhieu hn. Viec lay ao ham mot tn hieu co xu hng lam tang nhieu trong tn hieu o.
o nhay cam nay co the giam bt bang thao tac lay trung bnh cuc bo trong mien phu bi
mat na.
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Chng 3: C che hien th hnh anh len monitor
Trang 30
CHNG 3: C CHE HIEN TH HNH ANH LEN MONITOR
3.1 NGUYEN TAC CHUNG
e hien th hnh anh ra man hnh c tch hp th can phai co mot bo VGA
Generator vi cac tn hieu va c che lam viec nh sau:
3.1.1 VGA COLOR SIGNALS
Co 3 tn hieu color la: red, green va blue gi tn hieu mau sac (color information)
en man hnh VGA. Moi mot tn hieu ieu khien mot sung ban ien t (electron gun)
e phong cac hat electron ve len mot mau c ban tai mot iem tren man hnh. Dai
cua tn hieu nam t t 0 V (tng ng vi mau toi hoan toan) va 0.7V (sang hoan toan)
ieu khien cng o cua moi thanh phan mau va 3 thanh phan mau ket hp vi nhau
tao len mau cua iem anh (dot) hay phan t anh (pixel) tre n man hnh.
Hnh 3.1 : VGA Connection
Tuy vao o rong A bit cua tn hieu mau ngo vao tn ma moi mau analog ngo ra
la mot trong 2
A
mc vi bo chuyen oi digital to analog A bit. 3 tn hieu analog ket
hp vi nhau tao nen phan t anh (pixel) vi 2
A
2
A
2
A
=
3
2
A
mau khac nhau.
3.1.2. VGA SIGNAL TIMING
Moi mot anh (hay frame) tren man hnh hien th la ket hp cua h dong, moi
dong co w pixel. Kch thc cua moi frame c bieu dien w x h d i cac dang tieu
bieu gom 640 x 480m 800 x 600, 1024 x 768 va 1280 x 1024.
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Chng 3: C che hien th hnh anh len monitor
Trang 31
Hnh 3.2 : CRT Display Timing Example
e ve mot frame, co nhng mach ien co trach nhiem di chuyen dong
electron t trai sang phai va t tren xuong di doc theo man hnh goi la deflection
circuit. Nhng mach nay yeu cau phai co 2 tn hieu ong bo e khi ong va dng
dong electron tai ung thi iem e cho mot dong cac iem anh c ve doc theo
man hnh va moi dong c ien theo c che t tren xuong di e tao len mot anh.
3.1.3 NGUYEN TAC HOAT O NG CUA VGA GENERATOR
He thong ben ngoai ghi gia tr pixel vao trong thanh ghi pixel (data register) .
No i dung cu a thanh ghi nay c dch sau moi xung clock e thay the pixel hien tai.
Cac bit nay c gi en bo DAC e chuyen sang dang tn hieu mau analog. Roi kiem
tra xem gia tr tren chan Blank e xuat ra cong VGA.
Hai mach tao xung ong bo (pulse generation circuit) c dung e tao cac xung
ong bo do c (VSYNC) va ngang (HSYNC). Bo hirizontal sync generator co au ra la
tn hieu gate mot chu k trung khp vi sn len cua xung ong bo ngang ( horizontal
sync pulse), tn hieu gate nay noi vi tn hieu clock-enable cua bo vertical sync
generator v the nen clock-enable ch cap nhat bo em thi gian sau moi dong pixel
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Chng 3: C che hien th hnh anh len monitor
Trang 32
(line of pixels). Tn hieu gate cua vertical sync generator c dung nh tn hieu bao
ket thuc mot frame, ong thi no cung reset va xoa toan bo noi dung cua pixel buffer
nen bo VGA generator luon khi ong t trang thai xoa sach hoan toan vi moi frame.
Bo tao tn hieu ong bo cung tao ra cac tn hieu horizontal va vertical
blanking. Khi dung phep toan OR logic ta c tn hieu blanking toan cuc.
3.2 BO VGA DAC ADV7123
Kit DE2 tch hp mot bo VGA DAC la ADV7123 vi cau truc:
Ho tr tn hieu mau 10 bit ngo vao, vi bo DAC 10 bit se cho ra
10
2 mc mau
Analog ngo ra, tuy nhien trong thiet ke d lieu mau ta cung cap cho ADV7181 ch la 8
bit nen tn hieu mau Analog ngo ra co
8
2 mc. 3 tn hieu analog ket hp lai vi nhau tao
nen phan t anh
24
2 (16 trieu ) mau.
Cac tn hieu ong bo la SYNC va BLANK: gia tr cua SYNC th khong anh hng
en qua trnh hien th, BLANK vi gia tr 0 th chot cac d lieu mau ngo vao.
Hnh 3.3: S o cau truc cua ADV7123
cac chan cua ngo ra c noi tng ng vi cac chan cua cong VGA tren KIT
DE2, v vay e s dung c bo VGA DAC nay ta phai tao ra mot khoi va cung cap cac
tn hieu BLANK, Red, Green, Blue cho ADV7123 va phai tao ra 2 tn hieu ong bo
VSYN va HSYNC noi trc tiep vao cong VGA mot cach ong thi.
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Chng 4: S lc he thong
Trang 33
PHAN II: THIET KE HE THONG
CHNG 4: S LC HE THONG
4.1. YEU CAU
Tm hieu ve cac giai thuat x ly anh.
ng dung giai thuat x ly anh video vao phan cng, cu the la mo ta phan cng
thc hien giai thuat bang ngon ng Verilog HDL.
ng dung FPGAs e kiem tra ket qua, ong thi so sanh vi ket qua vi hnh anh
video ban au.
4.2 NOI DUNG THC HIEN
Lay nguon tn hieu video t DVD ( VCD ) Player a vao kit DE2 cua Altera qua
cong TV-IN.
S dung phan mem Quartus II cua Altera e viet chng trnh bang ngon ng
Verilog HDL va giao tiep vi kit DE2.
Thiet ke khoi loc trung bnh va do bien cho anh ngo ra bang Verilog HDL.
Giao tiep vi ADV7181B, VGA, SDRAM tren kit DE2.
Hien th ket qua len Monitor va so sanh vi tn hieu goc
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Chng 4: S lc he thong
Trang 34
4.3 S O THIET KE VA NGUYEN LY HOAT ONG
4.3.1 S O THIET KE
Hnh 4.1: S o he thong
4.3.2 NGUYEN LY HOAT ONG
Khoi I2C_Video_Config: vi giao thc giao tie p I2C se at gia tr cho cac thanh
ghi cua bo ma hoa ADV7181 e cau hnh hoat ong cho chip ma hoa nay.
Khi Timer tr hon ban u: Sau chuoi khi ong, ADV7181B ri vao thi k
khong on nh, khoi se phat hien thi k khong o n nh nay roi tnh toan thi iem bat au
lam viec cua cac khoi khac.
Khoi Desize_Horizon: Lay ra chuoi lien tuc cac Pixel trong dong d lieu do
ADV7181B xuat ra ong thi nh lai kch thc frame anh t dang 720 x 480 sang chuan
VGA 640 x480.
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Chng 4: S lc he thong
Trang 35
SDRAM BUFFER: Nhan d lieu va tn hieu ieu khien ghi t khoi Desize Horizon
e ghi gia tr cac Pixel vao SDRAM, ong thi cung nhan tn hieu t VGA controller e
ieu khien viec xuat d lieu, a ch phu hp (xuat xen ke cac line thuoc Odd field va
Even field)
Khoi x ly anh YUV: X ly d lieu anh nhan c t SDRAM BUFFER roi xuat ra
d lieu anh cho khoi Convert YUV to RGB
Khoi ConvertYUVtoRGB: ADV7181B xuat ra anh video dang YUV, e co the
hien th len VGA th trc tien chuyen oi thanh dang RGB.
Khoi VGA_Controller: Nhan d lieu anh RGB t khoi ConvertYUVtoRGB e xuat
d lieu va tn hieu ong bo cho Video DAC 7123, ong thi cung phat ra cac tn hieu ieu
khien SDRAM_BUFFER e xuat d lieu t SDRAM.
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Chng 5: Khoi I2C_Video_Config
Trang 36
PHAN III: NOI DUNG THIET KE
CHNG 5: Khoi I2C_VIDEO_CONFIG
5.1 S O KHOI
Hnh 5.1: S o khoi I2C_Video_Config
Ten Mo ta
ICLK Xung Clock 50MHz t Kit DE2
RESET Tn hieu Reset he thong
I2C_SCLK Ngo ra cha xung Clock cung cap cho ADV7181B
I2C_DATA
Port 2 chieu e cau hnh gia tr cac thanh ghi cua
ADV7181B
Hnh 5.2: Dang song e truyen d lieu va cau truc ghi vi giao thc I2C
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Chng 5: Khoi I2C_Video_Config
Trang 37
5.2 LU O GIAI THUAT:
5.3 MO TA
Vai tro cua khoi ch la ghi gia tr vao cac thanh ghi cua ADV7181B nen co the chon
xung clock lam viec cua khoi la 20KHz nh vao bo chia tan t tan so 50MHz. a ch
Slaver cua ADV7181B la 40h nen ta s dung cach gan mI2C_DATA <= {8h40,
LUT_DATA}. Vi mI2C_DATA la chuoi d lieu can truyen tren Bus va LUT_DATA
cha a ch cua thanh ghi va gia tr can nap.
Khi reset, bat au cau hnh lai cho ADV7181B bang cach xoa gia tr cac bo em va
c. Sau o e nap gia tr cho cac thanh ghi ta s dung may trang thai sau:
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Chng 5: Khoi I2C_Video_Config
Trang 38
always@(posedge mI2C_CTRL_CLK or negedge iRST_N)
begin
if(!iRST_N) begin
LUT_INDEX <= 0;
mSetup_ST <= 0;
mI2C_GO <= 0; end
else
begin
if(LUT_INDEX < LUT_SIZE)
//LUT_SIZE laso lan nap gia tr cho cac thanh ghi can thiet vaLUT_INDEX
//la bien em e anh xa en a ch cua cac thanh ghi va gia tr can nap.
begin
case(mSetup_ST)
0: begin
// Nhap chuoi d lieu can truyen e at gia tr cho cac thanh ghi
mI2C_DATA <= {8'h40,LUT_DATA};
mI2C_GO <= 1;
mSetup_ST <= 1;
end
1: begin
if(mI2C_END)
// mI2C_END la c bao khi truyen het chuoi d lieu
Begin
//Co xac nhan ACK la a nap xong gia tr cho 1 thanh
ghi t ADV th nhay ti trang thai 2
if(!mI2C_ACK)
mSetup_ST <= 2;
//Khong co xac nhan th nhay ve trang thai 0
else
mSetup_ST <= 0;
mI2C_GO <= 0;
end
end
2: begin
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Chng 5: Khoi I2C_Video_Config
Trang 39
// Tang LUT_INDEX len 1 e nhay en thanh ghi mi roi quay ve
trang thai 0
LUT_INDEX <= LUT_INDEX+1;
mSetup_ST <= 0;
end
endcase
end
end
end
Ta ch can at gia tr cho mot so thanh ghi can thiet nen khong thc hien viec tang
dan a ch thanh ghi ma se anh xa t LUX_INDEX en LUX_DATA nh vao lenh case,
chang han nh khi LUX_INDEX =27 e nap gia tr 8h50 vao thanh ghi co a ch 8h00 ta
co cau truc:
case(LUX_INDEX):
27: LUT_DATA <= 16'h0050;
e ADV7181B co the phat hien chuan video NTSC th ta se nap cac gia tr cho cac
thanh ghi theo bang gia tr cai at phan mo ta ADV7181B . Tuy nhien khi truyen chuoi
nay tren bus ta can phai them cac bit ong bo: 1 bit cho trang thai IDE, 2 bit e thiet lap
c START, 3 bit e ch 3 ACK do ADV xac nhan, 3 bit e thiet lap c STOP va bao ket
thuc chuoi, v vay thc s chuoi dai 33 bit:
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ; END=0; SDO=1; SCLK=1;end
//Thiet lap c START
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//a ch SLAVER cua ADV7181B
6'd3 : SDO=SD[23];
6'd4 : SDO=SD[22];
6'd5 : SDO=SD[21];
6'd6 : SDO=SD[20];
6'd7 : SDO=SD[19];
6'd8 : SDO=SD[18];
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Chng 5: Khoi I2C_Video_Config
Trang 40
6'd9 : SDO=SD[17];
6'd10 : SDO=SD[16];
//Tha noi ng truyen e nhap ACK t ADV7181B qua Port 2 chieu I2C_DATA
6'd11 : SDO=1'bz;
//a ch thanh ghi can nap
6'd12 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[14];
6'd14 : SDO=SD[13];
6'd15 : SDO=SD[12];
6'd16 : SDO=SD[11];
6'd17 : SDO=SD[10];
6'd18 : SDO=SD[9];
6'd19 : SDO=SD[8];
// Tha noi ng truyen nhap e ACK t ADV7181B qua Port 2 chieu I2C_DATA
6'd20 : SDO=1'bz;
//Gia tr can ghi vao thanh ghi
6'd21 : begin SDO=SD[7]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[6];
6'd23 : SDO=SD[5];
6'd24 : SDO=SD[4];
6'd25 : SDO=SD[3];
6'd26 : SDO=SD[2];
6'd27 : SDO=SD[1];
6'd28 : SDO=SD[0];
// Tha noi ng truyen nhap ACK t ADV7181B qua Port 2 chieu I2C_DATA
6'd29 : SDO=1'bz;
//Thiet lap c STOP va bao ket thuc chuoi
6'd30 : begin SDO=1'b0; SCLK=1'b0; ACK3=I2C_SDAT; end
6'd31 : SCLK=1'b1;
6'd32 : begin SDO=1'b1; END=1; end
endcase
Trong o SD_COUNTER thc hien em t 0 -> 63, nh vay viec nap cho mot thanh
ghi ch thc hien trong 33 chu ky au con 30 chu ky sau th Bus trang thai IDE (SCLK =
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Chng 5: Khoi I2C_Video_Config
Trang 41
1 va SDO = 1) e ch chu ky ghi tiep theo. ong thi e am bao c yeu cau ve dang
song tren chan I2C_SCLK va xac nhan (ACK) a nap xong thanh ghi, ta thc hien:
wire I2C_SCLK = SCLK | ( ( (SD_COUNTER >= 4) & (SD_COUNTER <=30) )?
~CLOCK : 0 );
wire ACK=ACK1 | ACK2 |ACK3;
// khi xet xac nhan a nap xong thanh ghi ta s dung gia tr bu cua ACK(tch c mc thap),
ch xac nhan khi co u 3 xac nhan ACK1, ACK2, ACK3
Va dang song thu c tren chan I2C_SCLK nh sau (END t 0 len 1 ch ra rang a
nap xong gia tr cho mot thanh ghi):
Hnh 5.3: Dang song mo phong tren chan I2C_SCLK
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Chng 6: Khoi Timer tr hoan ban au
Trang 42
CHNG 6: KHOI TIMER TR HOAN BAN AU
6.1 S O KHOI
Hnh 6.1: S o cua khoi Timer tr hoan ban au
Ten Mo ta
ICLK Xung clock 50Mhz t kit DE2
VS Tn hieu VS ( Vertical Sync ) t ADV7181B
HS Tn hieu HS (Horizontal Sync) t ADV7181B
TD_Stable Bao hieu ADV7181b a hoat ong on nh
RST0, RST1, RST3
Ngo ra cho phep cac khoi khac bat au lam viec
6.2 MO TA
Vi cau hnh a cai at phan trc, khi a hoat ong on nh, dang song do
ADV7181B phat ra nh sau:
V vay e phat hien xem chip ma hoa nay a hoat ong on nh hay cha khoi
TD_DETEC tien hanh kiem tra ieu kien: VS mc cao trong 9 chu ky lien tiep cua HS
roi chuyen xuong mc thap, neu thoa man th a TD_Stable len mc cao. Khi tn hieu
TD_Stable len mc cao, khoi RESET_DELAY bat au em len theo xung nhip cua ICLK
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Chng 6: Khoi Timer tr hoan ban au
Trang 43
(50MHz) e tnh thi iem xuat ra mc 1 tren cac chan RST0, RST1, RST2. Cac tn hieu
nay dung e khi ong cac khoi khac theo trnh t nh sau:
1) Ban au th xoa tat ca d lieu trong cac khoi.
2) Tnh t thi iem TD_Stable len 1(dn v la chu ky clock 27MHz) :
Sau 1132461.5: tch cc RST0 e kch hoat khoi SDRAM BUFFER,
Sau 1698692.5: tch cc RST1 e kch hoat khoi Desize Horizon
Sau 2264923.5: tch cc RST2 e kch hoat khoi x ly anh YUV vaVGA Controller.
3) Gi nguyen gia tr ngo ra cho en khi co tn hieu RESET he thong th lap lai.
iem can chu y ay la khi Desize Horizon hoat ong th se xuat
DATA_VALID cho phep ghi d lieu vao SDRAM BUFFER. Roi phai ch 1 khoang thi
gian e ghi u so d lieu can thiet mi kch hoat VGA Controller e xuat d lieu t
SDRAM BUFFER. Nh ta a biet 1 frame anh do ADV7181B xuat ra bao gom 900900
byte (525 line, moi line co 1716 byte) hay e truyen het 1 frame se mat 900900 chu ky.
Do xung clock tren chan LLC e truyen cac byte la 27 MHz nen ta kiem tra lai cac thi
iem nay nh sau:
Lay goc thi gian la khi bat au frame au tien
TD_Stable len 1 khi Frame au tien a phat c 9 line: 9 x 1716 = 15444 chu ky.
Frame th 3 c bat au tai thi iem 2 x 900900 = 1801800
Khoi Desize Horizon c kch hoat tai thi iem 1714136.5 (= 15444 + 1698692.5)
tc la trc khi frame th 3 bat au. am bao rang khoi se xuat ra DATA_VALID = 1
toan bo cac Active Pixel cua frame th 3.
Khoi VGA controller c kch hoat tai thi iem 2280367.5 (=15444 + 2264923.5)
nen oRequest c xuat ra tai thi iem 2315727.5 (= 2280376.5 + 35360 ). Vi 35360
chu ky la khoang thi gian t khi khoi c reset cho en khi oRequest len 1. Vay viec
oc t SDRAM BUFFER c kch hoat khi frame th 3 a bat au c 1 khoang thi
gian la 513927.5 (= 2315727.5 - 1801800). ieu nay am bao cho viec xuat ra ung tng
frame t SDRAM BUFFER ma ta se e cap ky hn phan mo ta SDRAM BUFFER.
Cau truc va thiet ke cua khoi nay tng oi n gian nen ta khong a lu o giai
thuat va code thc thi ma ch mo ta s lc.
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Chng 7: Khoi Desize Horizon
Trang 44
CHNG 7: KHOI DESIZE_HORIZON
7.1 S O KHOI
Hnh 7.1: S o cua khoi Desize Horizontal
Ten Mo ta
CLK_27 Xung clock 27Mhz t kit DE2
RST_N Reset he thong
TD_DATA[7:0] D lieu hnh anh t ADV7181B
ACLR Tn hieu xoa bat ong bo do khoi Timer tr hoan cung cap
CLK
Xung clock 27MHz t chan TD_CLK cua ADV7181B
So chia = 9 So chia cung cap cho bo chia do ngi thiet ke nhap vao
TV_X[9:0]
V tr cua Pixel trong hang hien hanh ong thi cung la so
b chia cung cap cho bo chia
Thng [9:0] Thng cua phep chia TV_X cho 9
So d [9:0] So d cua phep chia TV_X cho 9
DATA_VALID ong bo cho oYCbCr e a vao SDRAM_Controller
oYCbCr[15:0] Chuoi d lieu anh ngo ra
DATA_VALID: mc 1 th se cho phep Pixel i kem c ghi vao SDRAM thong
qua SDRAM_Controller. Do frame ma ADV7181B xuat ra co dang 720x480 e a ve
chuan 640x480 ma hnh anh khong b xen th vi moi 9 pixel lien tiep ta se loai bo Pixel
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Chng 7: Khoi Desize Horizon
Trang 45
au tien: khong cho phep ghi vao SDRAM bang cach a DATA_VALID xuong mc 0
(lay ra 8 Pixel trong 9 Pixel :
8
640 720
9
= )
ong thi e am bao c chuoi a vao SDRAM_controller van co dang chuoi
CbYnCrYn+1 lien tiep th phai hoan oi gia 2 thanh phan Cb va Cr c sau 2 lan loai bo 1
Pixel.
Hnh 7.2: V tr cac Pixel trong chuoi
Nh hnh tren X la v tr cac Pixel b loai bo (b bo qua khi hien th len man hnh),
khi o chuoi Pixel tai S1 la Cb4Y8Cb5 Y10 va tai E1 la Cr8Y17Cr9Y19 v vay e am bao
chuoi ra co dang CbYCrY lien tiep th phai hoan oi v tr gia Cb va Cr trong khoang Cb5
Y10 .... Cr8Y17.
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Chng 7: Khoi Desize Horizon
Trang 46
7.2 LU O GIAI THUAT
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Chng 7: Khoi Desize Horizon
Trang 47
7.3 MO TA
TD_DATA la chuoi Pixel c phat ra theo chuan Video ITU656. Ta co the xem
mot frame thc s bat au vi Odd Field khi bit F (bit 6 trong Byte cuoi cua trng SAV
hay EAV) chuyen t 1 ve 0, vay e xet ieu kien bat au cua 1 frame ta phai i en
trng SAV hay EAV roi mi kiem tra gia tr cua bit F:
Window <= {Window[15:0],iTD_DATA};
if(Window==24'hFF0000)
//khi phat hien trng SAV (EAV) th gan gia tr bit V cho FVAL va bit F cho Field
begin
FVAL <= !iTD_DATA[5];
Field <= iTD_DATA[6];
end
//kiem tra ieu kien bit F chuyen t 1 ve 0 e bat au 1 frame nh sau:
Pre_Field <= Field;
if({Pre_Field,Field}==2'b10)
Start <= 1'b1;
//phat hien trng SAV
Assign SAV = (Window==24'hFF0000)&(iTD_DATA[4]==1'b0);
//khi ong bo em cont e xac nh so byte cua chuoi Pixel trong 1 hang
if(SAV)
begin
Cont <= 18'h0;
Active_video <= 1b0;
end
else if(Cont<1440)
Cont <= Cont+1'b1;
//c 2 byte 1 Pixel c nen khi xac nh v tr Pixel trong hang th phai chia Cont cho 2:
assign oTV_X = Cont>>1;
e thc hien phep chia oTV_X cho 9 ta s dung bo chia t th vien cua Quartus:
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Chng 7: Khoi Desize Horizon
Trang 48
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom
mi, at ten la DIV; chon phan Arithmetic >> LPM_DEVIDE. V oTV_X s 720 nen chon
o rong bit cua so b chia (Numerator) la 10, o rong bit cua so chia (denominator) la 4,
kieu d lieu khong dau. V so chia can nhap la 9 nen ta ghep vao khoi tong the nh sau:
DIV u5 ( .aclr(!DLY0),
.clock(TD_CLK),
.denom(4'h9),
.numer(TV_X),
.quotient(Quotient),
.remain(Remain));
Trong o quotient, remain la thng va so d, ta nhap cac ieu kien oTV_X co chia
het cho 9 vathng la so le thong qua cac chan iSkip va iSwap_CbCr bang cach khai bao:
Desize_Horizontal u4 ( .iTD_DATA(TD_DATA),
.oTV_X(TV_X),
.oYCbCr(YCbCr),
.oDVAL(TV_DVAL),
.iSwap_CbCr(Quotient[0]),
.iSkip(Remain==4'h0),
.iRST_N(DLY1),
.iCLK_27(TD_CLK) );
Sau o ghep 1 Y vi 1 Cr hay 1 Y vi 1 Cb ong thi hoan oi v tr cua Cr va Cb tai
cac v tr can thiet:
if(iSwap_CbCr)
begin
case(Cont[1:0]) //hoan oi Cb Va Cr
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cr};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cb};
endcase
end
else
begin
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Chng 7: Khoi Desize Horizon
Trang 49
case(Cont[1:0]) // khong can hoan oi
0: Cb <= iTD_DATA;
1: YCbCr <= {iTD_DATA,Cb};
2: Cr <= iTD_DATA;
3: YCbCr <= {iTD_DATA,Cr};
endcase
end
Sau o xet them ieu kien Cont[0] e am bao viec ghep 1 byte Y vi 1 byte Cr hay
1 byte Y vi 1 byte Cb a hoan thanh e xuat DATA_VALID :
if(Start && FVAL && Active_Video && Cont[0] && !iSkip )
Data_Valid <= 1'b1;
else
Data_Valid <= 1'b0;
Nh vay Data_Valid ch len 1 Active Pixel e ieu khien s ghi vao SDRAM BUFFER.
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Chng 8: Khoi SDRAM BUFFER
Trang 50
CHNG 8: KHOI SDRAM BUFFER
8.1 S O KHOI
Gom 2 khoi PLL va SDRAM Controller:
Hnh 8.1: S o cua khoi SDRAM BUFFER
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Chng 8: Khoi SDRAM BUFFER
Trang 51
Ten Mo ta
RESET Tn hieu Reset he thong
CLK_27 Xung clock 27Mhz t kit DE2
CLK
Xung clock 81MHz PLL a ra cho cac ngo vao CLK cua khoi
SDRAM Controller ( chnh la tan so oc cua SDRAM WRITE
FIFO, ghi cua SDRAM READ FIFO1 va SDRAM READ FIFO2)
SDR_CLK Xuat xung clock 81MHz cho SDRAM
WR_LOAD
RD1_LOAD
RD2_LOAD
Lan lt la tn hieu e xoa bat ong bo SDRAM WRITE FIFO,
SDRAM READ FIFO1 va SDRAM READ FIFO2 lay t chan
RST0 cua khoi Timer tr hoan ban au.
WR_DATA D lieu anh a vao SDRAM WRITE FIFO do Desize horizon cap
WR
Cho phep ghi vao SDRAM WRITE FIFO lay t chan
DATA_VALID cua khoi Desize horizon
WR_CLK Xung clock 27MHz t chan LLC(TD_CLK) cua ADV7181B
RD_WRFIFO Cho phep oc d lieu t SDRAM WRITE FIFO
WRITE_SIDE[8:0] So t (Word) hien co trong SDRAM WRITE FIFO
DATA_IN
D lieu t SDRAM WRITE FIFO a vao Control Center e ghi
SDRAM.
DATA_OUT[15:0]
D lieu Control Center oc t SDRAM e xuat ra ngoai qua 1
trong 2 FIFO: SDRAM READ FIFO1, SDRAM READ FIFO2
RD1
RD2
RD1 = ~ RD2: Lan lt cho phep oc d lieu t SDRAM READ
FIFO1, SDRAM READ FIFO2 vi s ieu khien cua khoi VGA
Cotroller thong qua chan Request va VGA_Y.
RD1_CLK
RD2_CLK
Tan so oc cua SDRAM READ FIFO1 va SDRAM READ FIFO2
c la 27MHz t KIT DE2
READ_SIDE1[8:0] So t (Word) hien co trong SDRAM READ FIFO1
READ_SIDE2[8:0] So t (Word) hien co trong SDRAM READ FIFO2
WR_RDFIFO1 Cho phep ghi d lieu SDRAM READ FIFO1
WR_RDFIFO2 Cho phep ghi d lieu SDRAM READ FIFO2
RD1_DATA[15:0]
RD2_DATA[15:0]
D lieu ngo ra cung cap cho khoi x ly anh YUV
Cac chan DQ[15:0], SA[11:0], CKE, CAS_N, RAS_N, SDR_CLK, WE_N, BA[1:0],
CS_N[1:0], DQM[1:0] th c noi tng ng vao chip SDRAM co san tren kit DE2.
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Chng 8: Khoi SDRAM BUFFER
Trang 52
8.2 LU O GAI THUAT
Lu o danh cho viec ghi va xuat tng khoi d lieu xen ke t SDRAM.
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Chng 8: Khoi SDRAM BUFFER
Trang 53
Lu o e xuat hoac ghi dong d lieu vao cac FIFO: ng vi tng thao tac oc hay
ghi tren ma ta co lu o giai thuat tao a ch truy cap SDRAM nh sau:
8.3 MO TA
Nh ta a biet 1 frame anh theo chuan ITU656 bao gom Odd Field va Even Field:
khi xuat ra man hnh th cac line thuoc Odd Field se c hien th hang le, con cac line
thuoc Even la hang chan. Nen cac line cua 2 Field nay phai c xuat xen ke nhau nhng
trong chuoi video ITU656 do ADV7181B xuat ra th 2 Field c xuat lien tu c: xuat xong
Odd Field roi mi ti Even Field (cac frame khi ghi vao SDRAM th thanh 2 Field lien
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Chng 8: Khoi SDRAM BUFFER
Trang 54
tuc) nen e xuat ra cac line xen ke th ta phai tuan t xuat 1 line t a ch ma Odd Field
c lu gi roi lai xuat tiep 1 line t a ch ma Even Field c lu gi.
D lieu trong mot frame anh se c ghi lan lt vao SDRAM t a ch 0 en a
ch 324480 (324480 = 640 x 507, 507 chnh la so line cua frame c ghi vao SDRAM ,ta
bo qua 18 line co bit V =1 ), luc nay phan d lieu can xuat ra t SDRAM chia thanh 2
phan (trong 1 frame theo chuan ITU656 thc s co ti 487 active line, ta xen bt 7 active
line e giam so line ve chuan hien th la 480):
- Phan 1: T a ch 8320 (640 x 13) en 161920 (640 x 253) se la cac Pixel thuoc
Odd Field. ay chnh la 240 line t 23 en 262 trong frame goc.
- Phan 2: T a ch 170880 (640 x 267) en 324480 (640 x 507) la cac Pixel thuoc
Even Fiel. ay chnh la 240 line t 286 en 525 trong frame goc.
SDRAM ho tr che o truy cap d lieu theo tng kho i (Burst) vi chieu dai khoi co
the thay oi c nh vao cai at gia tr 3 bit cuoi (BL) cua thanh ghi mode register bang
cach truy cap che o load mode roi nhap gia tr cho thanh ghi nay qua cac chan a ch:
ay ta oc va ghi theo tng khoi 128 Word 16 bit nen nhap BL = 111: chieu dai
cua Burst la full page (tc la 256 word vi viec s dung SDRAM di dang 4Mx16) ; WT
= 0: truy xuat tuan t (Sequential) d lieu trong khoi; LTMODE = 011: thi gian ch
(latency) cho tn hieu RAS la 3 chu ky;
Cac Burst d lieu cua 2 phan tren se c xuat xen ke nhau. Ta khi tao va truy
xuat a ch cho cua cac phan nay nh sau:
if(!RESET_N)
begin
rWR_ADDR <= 0;
rWR_MAX_ADDR <= 640*507;
rRD1_ADDR <= 640*13;
rRD1_MAX_ADDR <= 640*253;
rRD2_ADDR <= 640*267;
rRD2_MAX_ADDR <= 640*507;
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Chng 8: Khoi SDRAM BUFFER
Trang 55
//chieu dai cua khoi can truy xuat
rWR_LENGTH <= 128;
rRD1_LENGTH <= 128;
rRD2_LENGTH <= 128;
end
else
begin
//neu a thc hien xong tac vu mWR_DONE , mRD_DONE va co c bao thc hien tac vu
mi oi vi 1 khoi WR_MASK[0], RD_MASK[0], RD_MASK[1] th tang a ch khoi len
1 khoi va lap lai cho en khi vt qua a ch toi a th quay ve a ch ban au
//ghi vao SDRAM
if(WR_LOAD)
begin
rWR_ADDR <= WR1_ADDR;
rWR_LENGTH <= WR1_LENGTH;
end
else if(mWR_DONE&WR_MASK[0])
begin
if(rWR_ADDR<rWR_MAX_ADDR-rWR_LENGTH)
rWR_ADDR <= rWR_ADDR+rWR_LENGTH;
else
rWR_ADDR <= WR_ADDR;
end
//oc d lieu t phan 1
if(RD1_LOAD)
begin
rRD1_ADDR <= RD1_ADDR;
rRD1_LENGTH <= RD1_LENGTH;
end
else if(mRD_DONE&RD_MASK[0])
begin
if(rRD1_ADDR<rRD1_MAX_ADDR-rRD1_LENGTH)
rRD1_ADDR <= rRD1_ADDR+rRD1_LENGTH;
else
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Chng 8: Khoi SDRAM BUFFER
Trang 56
rRD1_ADDR <= RD1_ADDR;
end
//oc d lieu t phan 2
if(RD2_LOAD)
begin
rRD2_ADDR <= RD2_ADDR;
rRD2_LENGTH <= RD2_LENGTH;
end
else if(mRD_DONE&RD_MASK[1])
begin
if(rRD2_ADDR<rRD2_MAX_ADDR-rRD2_LENGTH)
rRD2_ADDR <= rRD2_ADDR+rRD2_LENGTH;
else
rRD2_ADDR <= RD2_ADDR;
end
end
Trc het can tao mot khoi ieu khien viec ghi va oc SDRAM xen ke nhau, moi
lan oc hay ghi d lieu se thao tac tren tng Burst co chieu dai la 128 t (Word) theo th
t u tien (ch thao tac hien thi hoan thanh roi mi thc hien thao tac tiep theo):
oc 1 khoi t SDRAM roi ghi vao SDRAM READ FIFO1 e xuat chuoi Pixel
thuoc Odd Frame
oc 1 khoi t SDRAM roi ghi vao SDRAM READ FIFO2 e xuat chuoi Pixel
thuoc Even Frame
Ghi 1 khoi t SDRAM WRITE FIFO vao SDRAM.
tren ta thc hien 3 thao tac xen ke nhau, v vay e d lieu co the ong bo nhap,
xuat d lieu vi cac khoi khac th phai cung cap tan so lam viec cho SDRAM va tan so
truy xuat d lieu gia cac khoi FIFO va SDRAM gap 3 lan tan so clock cua cac khoi khac.
e tao cac xung clock nay ta s dung th vien cua Quartus e tao khoi PLL :
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao mot
custom mi, at ten la SDRAM_PLL, chon phan I/O >> ALTCLKlLOCK, ta khong s
dung cac chan ong bo ma ch nhap cac thong so cho tan so ngo vao va tan so, pha ngo ra
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Chng 8: Khoi SDRAM BUFFER
Trang 57
nh sau :inclk0 la 27MHz; c0 chon tan so la 81MHz vi pha ban au la 0; c1 tan so la 81
MHz vi pha ban au tre 3ns (bu tr vi khang thi gian ieu khien cac tn hieu ong bo
e truy cap SDRAM).
Chan c0 se cung cap tan so oc tan cho SDRAM WRITE FIFO e ghi d lieu vao
SDRAM, tan so ghi cho SDRAM READ FIFO1 va SDRAM READ FIFO2 e ghi d lieu
c xuat ra t SDRAM. Chan c1 cung cap tan so lam viec cho SDRAM.
ong thi khi thc hien 1 tac vu ta can phai tr hoan cac tac vu khac mot khoang
thi gian c mo ta theo gian o sau (cha xet tac ong cua RD1 va RD2):
Hnh 8.2: Gian o nh th cho chu ky truy xuat gia SDRAM va cac FIFO
V vay e am bao truy xuat ung d lieu th can phai co cac FIFO co chieu dai 384
( tc la 128 x 3 ). Tuy nhien trong th vien cua Quarus ch khong co FIFO dai 384 Word
nen se tao mot FIFO dai 512 Word nh sau:
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao mot
custom mi, at ten la SDRAM_WRITE_FIFO, chon phan Memory Compiler >> FIFO
chon o rong d lieu la 16bit, chieu dai ( deep ) la 512 Words. Lam tng t e tao cac
khoi SDRAM_READ_FIFO1 va SDRAM_READ_FIFO2.
Chu y la: Khi s dung FIFO dai 512 Word ta phai co 1 so thay oi trong thiet ke, tuy
nhien cac thay oi nay tng oi n gian nh tang tan so xung clock len 108 MHz, s
dung them 1 tac vu ghi trong (WR2) e am bao d lieu xuat ra ung theo yeu cau.
Thc hien ghi va xuat tng khoi d lieu xen ke t SDRAM nh sau:
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Chng 8: Khoi SDRAM BUFFER
Trang 58
// Ghi vao SDRAM READ FIFO1 cac Pixel thuoc line Odd frame
if( (READ_SIDE1< rRD1_LENGTH) )
begin
mADDR <= rRD1_ADDR;
mLENGTH <= rRD1_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b01;
mWR <= 0;
mRD <= 1;
end
// Ghi vao SDRAM READ FIFO2 cac Pixel thuoc line Even frame
else if( (READ_SIDE2< rRD2_LENGTH) )
begin
mADDR <= rRD2_ADDR;
mLENGTH <= rRD2_LENGTH;
WR_MASK <= 2'b00;
RD_MASK <= 2'b10;
mWR <= 0;
mRD <= 1;
end
// oc d lieu t SDRAM WRITE FIFO va ghi vao SDRAM
else if( (WRITE_SIDE>= rWR_LENGTH)&& (rWR_LENGTH!=0) )
begin
mADDR <= rWR_ADDR;
mLENGTH <= rWR_LENGTH;
WR_MASK <= 2'b01;
RD_MASK <= 2'b00;
mWR <= 1;
mRD <= 0;
end
end
if(mWR_DONE)
begin
WR_MASK <= 0;
mWR <= 0;
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Chng 8: Khoi SDRAM BUFFER
Trang 59
end
if(mRD_DONE)
begin
RD_MASK <= 0;
mRD <= 0;
end
Xet ieu kien so Word co trong cac FIFO e khi tao lenh oc va ghi SDRAM. Roi
dung bien em ST (bat au t 0) e thiet lap khoang thi gian can thiet cho 1 tac vu bao
gom: thi gian ch bus am bao ranh hoan (oi vi lenh oc la SC_CL+SC_RCD+1, ghi
la SC_CL-1, phu thuoc vao cau truc cua SDRAM: SC_CL = SC_RCD = 3 c khai bao
trong tap tin Sdram_Params.h ), thi gian thc hien tac vu (mLENGTH = 128).Tao tn
hieu ieu khien viec ghi oc cac FIFO va c bao a oc hay ghi xong nh sau:
if(Read)
begin
//OUT_VALID la tn hieu dung e ieu khien cho phep ghi vao cac SDRAM READ FIFO
if(ST==SC_CL+SC_RCD+1)
OUT_VALID <= 1;
else if(ST==SC_CL+SC_RCD+mLENGTH+1)
begin
OUT_VALID <= 0;
Read <= 0;
mRD_DONE <= 1;
end
end
else
mRD_DONE <= 0;
if(Write)
begin
//IN_REQ la tn hieu dung e ieu khien cho phep oc t SDRAM WRITE FIFO
if(ST==SC_CL-1)
IN_REQ <= 1;
else if(ST==SC_CL+mLENGTH-1)
IN_REQ <= 0;
else if(ST==SC_CL+SC_RCD+mLENGTH)
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Chng 8: Khoi SDRAM BUFFER
Trang 60
begin
Write <= 0;
mWR_DONE <= 1;
end
end
else
mWR_DONE<= 0;
Cau hoi at ra la vi chu ky truy xuat nh gian o tren th lng d lieu xuat ra se
gap 2 lan lng d lieu ghi vao SDRAM. Tuy nhien qua trnh tren con chu anh hng cua
cac ngo vao RD1 va RD2, (tac ong en cac gia tr READ_SIDE1 va READ_SIDE2) se
ieu khien cac thao tac xuat d lieu t SDRAM vao SDRAM READ FIFO nh sau:
+RD1 = ~RD2 = 1: ngng tac vu xuat d lieu t SDRAM vao SDRAM READ FIFO2 tc
la ch xuat cac line cua Odd Field
+RD1 = ~RD2 = 0: ngng tac vu xuat d lieu t SDRAM vao SDRAM READ FIFO1 tc
la ch xuat cac line cua Even Field.
Do RD1, RD2 c tch cc lan lt sau 640 chu ky (tng ng vi 1 line) nen cac
line se c xuat xen ke nhau. Nh vay trong 1 chu ky truy xuat thc s ch co 128 Word
c xuat vao 1 FIFO, am bao c s ong bo d lieu cua SDRAM vi he thong.
Van e cuoi cung can phai giai quyet la xac nh cac thi iem truy xuat SDRAM
BUFFER tc la tnh toan khoang thi gian ke t khi bat au ghi d lieu vao(WR=1) va ti
khi bat au xuat chung ra e am bao cac pixel c xuat ra la cung thuoc 1 frame:
- Neu khoang thi gian nay khong u ln: chan RD2 tch cc bat au truy xuat d
lieu cua Even Field t a ch 170880 cho en 324480, ma d lieu trong cac a ch nay lai
cha c cap nhat nen dan en cac line xuat ra se khong co gia tr hoac la cac line cua
frame trc.
- Neu khoang thi gian nay qua ln: do toc o tang a ch cua qua trnh ghi gap
oi qua trnh oc (do a ch ghi c tang lien tuc con ch oc lan lt la a ch e xuat
xen ke cac line thuoc Odd Field va Even Field nen cung ch c tang lan lt), nen xay
ra trng hp khi ang xuat d lieu thuoc 1 frame th qua trnh ghi a nhap d lieu cua
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Chng 8: Khoi SDRAM BUFFER
Trang 61
frame tiep theo vao SDRAM BUFFER, khi o RD1 tch cc th co the xuat ra 1 line thuoc
frame mi nay ch khong phai la line cua frame hien hanh.
Nh a noi trong phan mo ta khoi Timer tr hoan ban au, viec oc t SDRAM
BUFFER c kch hoat sau 1 khoang thi gian la 513927.5 chu ky tnh t khi frame th 3
bat au: khi cac Pixel tren line th 300 cua frame goc ( ~513872.5 1716; vi1716 la so
byte cua 1 line trong frame goc) tng ng vi line th 282 (bo qua18 line co bit V =1)
ang c ghi vao SDRAM BUFFER, th bat au xuat xen ke cac line. ieu kien RD2
truy xuat ung Even frame c thoa man, xet cac line ma RD1 xuat ra:
- Khi WR ghi lien tuc t line 282 en line 507 vao SDRAM BUFFER th hien nhien
la RD1 truy xuat ung. Luc nay line ma RD1 ang xuat la 13 + (507 - 282) 2 = 125.5
- Xet frame tiep theo: phai ch het 9 line au tien mi bat au ghi t line 0. Luc o
RD1 se truy xuat line th 125.5 + 9 : 2 = 130; nh vay cho en khi RD1 xuat line xong line
th 253 th WR mi ch ghi ti line (253-130)2 = 246. am bao d lieu c xuat van la
cua frame hien thi.
Ngoai ra trong khoi Control Center con co cac khoi command, control interface e
tao va ong bo cac lenh lam ti (refresh), tch nap (Precharge), chon che o oc, ghi,
truyen khoi, ong thi ma hoa va giai ma lenh cho SDRAM theo mo ta cac che o truy
cap SDRAM Bang 1.2 vi cau truc kha phc tap. Trong khuon kho luan van nay ta
khong e cap en ma ch tham khao va s dung code verilog t cong ty Altera va hang
san xuat KIT DE2 la Terasic.
Khi ghep vao trong khoi tong the ta se dung cau truc e xuat d lieu nh sau:
.RD1_DATA(m1YCbCr), .RD2_DATA(m2YCbCr), roi chon d lieu e a vao khoi x
ly anh YUV : assign mYCbCr_d = !VGA_Y[0]? m1YcbCr : m2YCbCr; vi !VGA_Y[0]
la do khoi VGA Controller a ra cho biet line ang xuat tren man hnh v tr le hay
chan e chon d lieu xuat ra tng ng.
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Chng 9: Khoi X ly anh YUV
Trang 62
CHNG 9: KHOI X LY ANH YUV
9.1 S O KHOI
Hnh 9.1: S o cua khoi x ly anh YUV
Ten Mo ta
CLK Xung clock 27Mhz t kit DE2.
RESET Reset he thong.
mYCbCr_d[15:0] D lieu hnh anh ngo vao.
oRequest
Tn hieu ieu khien do VGA Controller cung cap: yeu
cau xuat d lieu.
iX[0]
Tn hieu ieu khien do VGA Controller cung cap, cho
biet v tr cua Pixel la chan hay le (bit 0 trong gia tr cua
bo em v tr Pixel)
oRequest
Tn hieu ieu khien do VGA Controller cung cap: yeu
cau xuat d lieu.
iYCbCr Pixel anh sau qua Image Process x ly.
oY[7:0] Thanh phan o sang (Luma) cua Pixel c tach ra.
oCb[7:0] Thanh phan Cb cua Pixel c tach ra.
oCr[7:0] Thanh phan Cr cua Pixel c tach ra.
Resgister[1..9][15:0] 9 thanh ghi tng ng vi ca so 3x3 pixels.
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Chng 9: Khoi X ly anh YUV
Trang 63
9.2 MO TA
Khoi Line Buffer: la bo em e lu lai cac gia tr cac Pixel can thiet
Xet ca so 3x3 Pixel: trong chuoi d lieu ngo vao v tr cac pixel nay nh sau:
e ca pixel nay xuat hien cung luc trong 1 ca so th phai can co cac bo em ( cac
thanh ghi va line buffer) e lu lai cac gia tr cua P1, P2, P3, P4, P5, P6, P7, P8 cho en
khi P9 xuat hien:
Hnh 9.2 : S dung cac Line_buffer va Register e tao ca so 3x3 pixel
Line_Buffer co the la 1 FIFO hoac la 1 thanh ghi dch(shift register), nhng trong th
vien cua Quartus khong co FIFO vi chieu dai 640 Words, nen ta s dung thanh ghi dch:
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom
mi, at ten la Line_Buffer, chon phan Memory Compiler >> shift register ( RAM-Based).
Ta chon o rong d lieu la 8bits, chieu dai (distance between Taps) la 640, so Tap la 1, va
anh dau chon e s dung chan clock enable. Nh vay ta c ca so Pixel:
P1 P2 P3
P4 P5 P6
P7 P8 P9
| |
|
|
|
\ .
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Chng 9: Khoi X ly anh YUV
Trang 64
Khoi x ly anh: ta chon 1 trong hai che o lam viec:loc trung bnh va tach bien.
- Loc trung bnh: thc hien phep tng quan ca so pixel vi mat na
1 2 1
1
2 4 2
16
1 2 1
| |
|
|
|
\ .
Tuy nhien d lieu vao la 16 bit vi 8 bit cao la thanh phan Y va 8 bit thap la Cb hoac
Cr. Nen ta s dung khai bao e tach ra tng thanh phan roi x ly:
Loc_trung_binh Loc_trung_binh_0 ( clock,
reset,
register1[7:0],
register2[7:0],
register3[7:0],
register4[7:0],
register5[7:0],
register6[7:0],
register7[7:0],
register8[7:0],
register9[7:0],
out2
);
Loc_trung_binh Loc_trung_binh_1 ( clock,
reset,
register1[15:8],
register2[15:8],
register3[15:8],
register4[15:8],
register5[15:8],
register6[15:8],
register7[15:8],
register8[15:8],
register9[15:8],
out1
);
e thc hien phep tng quan gia ca so Pixel vi mat na loc, ta tien hanh theo
cac bc:
-Nhan cac thanh phan tng ng cua 2 ca so lai vi nhau: mat na loc ch co cac he so
1, 2, 4 (de thay ket quala cac so 10 bit )
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Chng 9: Khoi X ly anh YUV
Trang 65
k = 1 th gi nguyen: : multi_1 <= { 2'b00, register1};
k = 2 th dch trai 1 bit : multi_2 <= { 1'b0, register2,1b0};
k = 4 th dch trai 2 bit: multi_5 <= { register5,1b00};
-Lay tong cac tch va tm c (tong nay la so 12 bit):
assign multi1 = multi_1 + multi_3 + multi_7 + multi_9;
assign multi2 = multi_2 + multi_4 + multi_6 + multi_8;
assign multi = multi1 + multi2 + multi_5;
-Chia tong tren cho 16 tng ng vi viec lay 8 bit cao:
assign out = multi[11:4];
- Tach bien: tng t nh tren ta cung tach d lieu 16bit ra tng thanh phan e x ly
vi cac bc thc hien nh sau :
1)Tnh |
x
G | va |
y
G |: Chap ma tran ca so 33 pixels anh cua frame vi hai mat na loc
theo phng phap gradient vi mat na loc Prewitt :
(
(
(
1 0 1
2 0 2
1 0 1
(
(
(
1 2 1
0 0 0
1 2 1
Mat na loc ch co cac he so 0, 1, 2 , -1 va -2 ( k =1, 2 a xet phep loc tring bnh)
k = 0 th multi <= 0;
k =-1 th lay bu 2: multi = ~{3'b000,register} + 1;
k =-2 dch trai 1 bit roi lay bu 2: multi = ~{2'b00,register,1'b0} + 1;
Vi register [7:0] nhan vi so [1:0] so [9:0] them bit dau thanh so [11:0], tc la
12 bits. Sau o cong tat ca cac thanh phan cua ca so thu c roi lay 8 bit cao trong gia
tr tuyet oi ta co ket qua la |
x
G | va |
y
G |
2)Tnh gia tr ngo ra cua pixel theo cong thc
2 2
x y
G = G + G :
- Tnh gia tr bnh phng cua
x
G va
y
G vi bo nhan t th vien cua Quartus:
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom
mi, at ten la MULT2, chon phan Arithmetic >> LPM_MULT. Chon o rong bit ngo vao
la 8 bit. Sau khi tong hp ta c mot khoi vi khai bao nh sau:
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Chng 9: Khoi X ly anh YUV
Trang 66
module MULT2 ( dataa,
datab,
result);
e lay phep bnh phng ta nhap cung mot gia tr cho 2 ngo vao dataa va datab
- Dung bo lay can bac 2 t th vien cua Quartus e tnh G t tong hai ket qua tren:
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom mi, at
ten la SQUARE, chon phan Arithmetic >> ALTSQRT. Chon o rong bit ngo vao la 16
bit.Sau khi tong hp ta c mot khoi vi khai bao nh sau (trong o radical la d lieu 17
bit ngo vao, q la ket qua 9 bit cua phep lay cant,t a khong s dung chan remainder):
module SQUARE ( radical,
q,
remainder);
Thc chat khoi x ly anh ch la cac cap khoi loc bien, loc trung bnh c ghep song
song nhau. Moi khoi trong cap x ly tren tng 8 bit d lieu, sau o ghep chung lai vi
nhau (out3, out 4 tng t la cac ngo ra cua cac khoi loc bien)
assign out_pixel = (!reset)? 16'b0 : out;
assign out = select_process? {out1,out2} : {out3,out4};
Khoi se xuat ra gia tr cua pixel anh tng ng vi gia tr pixel anh nam chnh gia
ca so. Co 1 van e c at ra ay la khi mot frame va bat au th ca so cha co u
9 Pixel nhng bo x ly anh van thc hien loc va xuat pixel se dan en sai so bien anh.
ong thi khoi Image Process can co 1 so chu ky xung clock e x ly xong anh. Tuy
nhien vi 1 frame kch thc 640 x 480 th cac sai lech nay co the chap nhan c.
Khoi Extract YCrCb to Y, Cr, Cb : n gian ch la tach chuoi d lieu 16 bit dang
YCrCb lien tiep ra 3 thanh phan Y, Cr, Cb. Da vao tn hieu iX[0] do VGA controller a
ra e biet v tr cua Pixel trong hang la chan hay le(16 bit nay la YCb hay la YCr):
if(iX[0])
{mY,mCr} <= iYCbCr;
else
{mY,mCb} <= iYCbCr;
Nh vay d lieu 16 bit ngo vao a c x ly va tach ra 3 thanh phan Y, Cr, Cb.
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Chng 10: Khoi Convert YcrCb to RGB
Trang 67
CHNG 10: KHOI CONVERT YCRCB TO RGB
10.1 S O KHOI:
Hnh 10.1: S o cua khoi Convert YCrCb to RGB
Ten Mo ta
CLK Xung clock 27Mhz t kit DE2.
RESET Reset he thong.
iY[7:0] Thanh phan o sang (Luma) cua Pixel c tach ra.
iCb[7:0] Thanh phan Cb cua Pixel c tach ra.
iCr[7:0] Thanh phan Cr cua Pixel c tach ra.
Red[9:0] Thanh phan Red cua Pixel tng ng.
Green[9:0] Thanh phan Green cua Pixel tng ng.
Blue[9:0] Thanh phan Blue cua Pixel tng ng.
10.2 MO TA
Khoi nay chuyen oi t dang d lieu anh YCrCb 8 bit sang dang RGB 10 bit cho phu
hp vi yeu cau ngo vao cua VGA DAC la ADV7123. Di ay la cong thc chuyen oi
sang dang RGB 8 bit:
R = 1.164 ( Y - 16 ) + 1.596 ( Cr 128 ) ;
G = 1.164 ( Y - 16) - 0.392 ( Cb - 128 ) - 0.813 ( Cr - 128 ) ;
B = 1.164 ( Y - 16 ) + 2.017 ( Cb 128 ) ;
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Chng 10: Khoi Convert YcrCb to RGB
Trang 68
Sau o e co dang RGB 10 bit th ta dch trai 2 bit ( nhan 4 ) nen co cong thc mi:
R = 4.656 ( Y - 16 ) + 6.384 ( Cr - 128 ) ;
G = 4.656 ( Y - 16 ) - 1.568 ( Cb - 128 ) - 3.252 ( Cr - 128 );
B = 4.656 ( Y - 16 ) + 8.068 ( Cb - 128 ) ;
Do cac he so co dang thap phan, trong khi o cac phep toan cua phan cng c
tong hp ch thc hien tren so nguyen nen khi lam tron va tnh toan th sai so kha ln, v
vay ta phai nhan bieu thc tren vi mot so nguyen H nao o e giam bt sai so khi lam
tron cac he so, sau o tnh toan bieu thc roi chia lai cho H. So nguyen H ta chon co dang
k
2 th thay v thc hien phep chia cho A ta ch can dch phai k bit. ay ta chon k = 7 hay
H = 128 th o chnh xac cua he so se en ch so th 2 sau dau phay. Ta co cong thc cuoi
cung (a lam tron e tnh toan tren cac so nguyen) :
oR = (596 Y + 817Cr 114131) : 128 ;
oG = (596 Y 200Cb 416Cr + 69370) : 128 ;
oB = (596 Y + 1033Cb 141781) : 128 ;
e thc hien cong thc tren ta tien hanh theo cac bc:
1)Nhan cac thanh phan Y, Cb, Cr vi cac he so tng ng roi cong chung lai, s dung bo
tong hp cong nhan ( ALTMULT_ADD ) trong th vien cua Quartus :
Phan Menu >> Tools >> MegaWizard Plug_in Manager >> Create tao custom
mi, at ten la MAC3; chon phan Arithmetic >> ALTMULT_ADD. Vi cac thong so c
chon nh sau:
+ Tnh oG can 3 phep nhan : so lng bo nhan la 3.
+ Y,Cb,Cr la so 8 bit dng: o rong ngo vao A la 8, kieu d lieu khong dau (Unsigned)
+ Trong cac he so co so am nen, gia tr ln nhat la 1033 (so 11 bit) : o rong ngo vao B la
11, kieu d lieu co dau (signed)
+ Chon ham gia hai bo nhan au tien (first pair of multiplier) la phep cong (Add).
Khi tong hp xong ta c mot khoi vi khai bao nh sau :
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Chng 10: Khoi Convert YcrCb to RGB
Trang 69
module MAC_3 (dataa_0,
dataa_1,
dataa_2,
datab_0,
datab_1,
datab_2,
result,
aclr0,
clock0);
Trong o:
+ Ngo vao ieu khien : xoa bat ong bo aclr0 va xung clock lam viec clock0,
+ Cac ngo vao d lieu la dataa_0; dataa_1; dataa_2 la cac so 7 bit khong dau; datab_0;
datab_1; datab_2 la cac so 11 bit co dau;
+ Ngo ra la d lieu 21 bit co dau:
result = (dataa_0 datab_0) + (dataa_1 datab_1) + (dataa_2 datab_2)
Chu y: data_b0, data_b1, data_b2 la cac he so cong thc a tnh tren:
d h
596 =254 ,
d h
817 =331 ,
d h
-200 =F38 (so bu hai),
d h
-416 =E60 (so bu hai),
d h
1033 =409 .Vay e thc
hien bc nay ta se goi cac khoi MAC_3 nh sau:
MAC_3 u0( iY, iCb, iCr,
11'h254, 11'h000, 11'h331,
X, iRESET, iCLK);
MAC_3 u1( iY, iCb, iCr,
11'h254, 11'hF38, 11'hE60,
Y, iRESET, iCLK);
MAC_3 u2( iY, iCb, iCr,
11'h254, 11'h409, 11'h000,
Z, iRESET, iCLK);
2)Sau o tr (cong) vi cac so hang con lai roi chia cho 128 bang cach dch phai 7 bit:
X_OUT <= ( X - 114131 ) >>7;
Y_OUT <= ( Y + 69370 ) >>7;
Z_OUT <= ( Z - 141787 ) >>7;
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Chng 10: Khoi Convert YcrCb to RGB
Trang 70
Tuy nhien khi cac gia tr R, G, B c tnh theo cong thc tren th co the la so am
hoac vt qua1023 (10 bit ) v vay ta gii han lai gia tr vao trong khoang 0 en 1023:
if(X_OUT[13])
oRed<=0;
else if(X_OUT[12:0]>1023)
oRed<=1023;
Thc hien tng t vi 2 thanh phan con lai th d lieu khoi xuat ra se la dang RGB
phu hp vi yeu cau at ra.
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Chng 11: Khoi VGA Controller
Trang 71
CHNG 11: KHOI VGA CONTROLLER
11.1 S O KHOI
Hnh 11.1 : S o cua khoi VGA Controller
Ten Mo ta
CLK Xung clock 27Mhz t kit DE2.
RESET Tn hieu reset do khoi Timer tr hoan ban au cung cap
oRequest
Tn hieu ieu khien cho phep xuat d lieu t SDRAM BUFFER
va lu cac gia tr cua Line Pixel vao khoi Line Buffer
oVGA_BLANK
oVGA_SYNC
oVGA_VS
oVGA_HS
Cac chan nay c gan tng ng vao chip giai ma ADV7123 va
cong VGA tren kit DE2 e ong bo viec xuat ra monitor cac
frames anh. Do xuat anh theo chuan VGA 640x480 nen chan
VGA_SYNC luon phai at mc cao e am bao viec ong bo.
VGA_X[0]
Cho biet v tr cua Pixel la chan hay le e ieu khien viec tach
cac thanh phan Y, Cr, Cb trong khoi x ly anh YUV
VGA_Y[0]
Cho biet Line se hien th tren man hnh la thuoc Odd Frame hay
Even Frame e chon d lieu a ra t SDRAM BUFFER
Cac chan d lieu iRed, iGreen, iBlue c noi trc tiep vi ngo ra VGA_R, VGA_G,
VGA_B. Ngo ra oVGA_CLOCK la nghch ao cua ngo vao CLK .
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Chng 11: Khoi VGA Controller
Trang 72
11.2 LU O GIAI THUAT
Giai thuat tao tn hieu ong bo e giao tiep vi VGA la tao cac bo em vi cac
thong so chuan e tao ra cac tn hieu ong bo theo gian o thi gian:
Hnh 11.2: Vung hien th trong 1 chu ky quet vi tn hieu reset t he thong
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Chng 11: Khoi VGA Controller
Trang 73
T cac thong so nh th cho chuan VGA 640x480 60Hz tren , do xung clock trong
thiet ke co tan so 27MHz nen ta chon cac gia tr tng ng cho cac thong so nh sau:
1) oi vi VGA_HS (tn hieu ong bo quy nh thi gian hien th 1 hang trong 1 chu
ky quet ngang): H_FRONT = 16, H_SYNC = 96, H_BACK = 48, H_ACT = 640. Nh vay
khi hien th xong 1 hang th phai ch 1 khoang thi gian la H_BLANK = H_FRONT +
H_SYNC + H_BACK = 160 (n v la so chu ky xung clock) th hien th hang mi. Luc
nay thi gian quet ngang la: H_TOTAL = H_BLANK + H_ACT = 800.
Lu o giai thuat tao VGA_HS :
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Chng 11: Khoi VGA Controller
Trang 74
2) oi vi VGA_VS(tn hieu ong bo quy nh thi gian hien th 1 frame trong 1 chu
ky quet toan bo man hnh): V_FRONT = 11; V_SYNC = 2; V_BACK = 31; V_ACT = 480.
Nh vay khi hien th xong 1 frame th phai ch 1 khoang thi gian la V_BLANK =
V_FRONT+V_SYNC+V_BACK = 44 (n v la chu ky xung quet ngang VGA_HS) th
hien th frame mi. Thi gian quet man hnh la V_TOTAL = V_BLANK + V_ACT= 524.
Lu o giai thuat tao VGA_VS cung c thc hien tng t ch khac la V_Cont
c em len sau moi canh len cua VGA_HS.
11.3 MO TA
Khoi se tao cac tn hieu ieu khien cho ADV 7123 va ong bo viec truy xuat, x ly
d lieu vi cac khoi khac da tren cac tn hieu nh th quet ngang va quet doc sao:
+ Tao tn hieu quet ngang VGA_HS vi bo em len H_Cont :
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if( H_Cont < H_TOTAL )
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
//a VGA_HS ve 0 tng ng vi khoang thi gian Horizontal SYNC
if(H_Cont == H_FRONT-1)
oVGA_HS <= 1'b0;
if(H_Cont == H_FRONT+H_SYNC-1)
oVGA_HS <= 1'b1;
end
end
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Chng 11: Khoi VGA Controller
Trang 75
+Tao tn hieu quet doc VGA_VS vi bo em V_Cont theo canh len cua VGA_HS:
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end
else
begin
if(V_Cont < V_TOTAL)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
//a VGA_HS ve 0 tng ng vi khoang thi gian Horizontal SYNC
if(V_Cont == V_FRONT-1)
oVGA_VS <= 1'b0;
if(V_Cont == V_FRONT+V_SYNC-1)
oVGA_VS <= 1'b1;
end
end
+Sau o xuat cac tn hieu ieu khien khac:
//Tch cc tn hieu BLANK e xoa cac Flicker:
assign oVGA_BLANK = ~((H_Cont < H_BLANK) || (V_Cont < V_BLANK));
//oRequest len 1 thi gian hien th frame trong 1 chu ky quet man hnh:
assign oRequest = ( ( H_Cont >= H_BLANK && H_Cont < H_TOTAL )
&& ( V_Cont>=V_BLANK && V_Cont<V_TOTAL ) );
//tnh toan v tr X, Y cua Pixel trong frame (X : v tr pixel trong hang va Y : v tr hang
trong frame):
assign oCurrent_X = (H_Cont>=H_BLANK)? H_Cont-H_BLANK : 11'h0;
assign oCurrent_X = (V_Cont>=V_BLANK)? V_Cont-V_BLANK : 11'h0;
Nh vay ke t khi bat au quet 1 frame th phai ch 1 khoang thi gian co o dai la
(V_BLANK H_TOTAL) + H_ BLANK = 35360 (chu ky) th oRequest mi c tch cc.
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Tong ket
Trang 76
PHAN IV: TONG KET
ANH GIA KET QUA
a cau hnh va s dung c chip ma hoa ADV7181B
S dung c SDRAM 4Mx16 e lu tr d lieu.
a hien th c len VGA anh video vi kch thc chuan 640x480
Thiet ke c bo loc trung bnh, bo loc bien theo phng phap Sobel (ma tran
anh trt qua hai ca so loc ngang va doc) bang ngon ng Verilog HDL.
HAN CHE
Phng phap x ly anh con n gian
Thiet ke ch phu hp vi cac chuan tn hieu video Analog ma ADV7181B ho tr
HNG PHAT TRIEN E TAI
M rong e tai len x ly anh vi tn hieu vao la camera, Webcam
S dung cac phng phap noi suy e nang cao o phan giai anh so vi ngo vao
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