A LOW-DISTORTION CLASS-AB AUDIO AMPLIFIER WITH HIGH POWER EFFICIENCY

BY CHAITANYA MOHAN, B.Tech

A thesis submitted to the Graduate School in partial fulllment of the requirements for the degree Master of Sciences, Engineering

Specialization in: Electrical Engineering

New Mexico State University Las Cruces, New Mexico March 2011

A Low-Distortion Class-AB Audio Amplier with High Power Eciency, a thesis prepared by Chaitanya Mohan in partial fulllment of the requirements for the degree, Master of Sciences has been approved and accepted by the following:

Linda Lacey Dean of the Graduate School

Dr. Paul M. Furth Chair of the Examining Committee

Date

Committee in charge: Dr. Paul M. Furth Dr. Jaime Ramirez-Angulo Dr. Jerey Beasley

ii

DEDICATION

Dedicated to my father Chandolu Rama Mohan Rao, mother Chandolu Hemalatha, sister Srujana Mohan Rao.

iii

ACKNOWLEDGMENTS

First I would like to thank my parents Chandolu Rama Mohan Rao and Chandolu Hemalatha, sister Srujana Mohan Rao and brother-in-law DeepakNadh Tammana for supporting me at every level of my life. They are the reason behind my success at every corner in the journey of life. Srujana has been more of a friend, guide and advisor than a sister. Dr. Paul M. Furth, the coach of VLSI V6 team is man behind the success of this thesis. I can proudly say, the knowledge I acquired from him in Electronics is more than what I have earned in my entire bachelors. The approach towards every problem and level of analyzing things before hand is what I would like to get from him. I would also like to thank Dr. Jaime Ramirez-Angulo for imparting knowledge on analog concepts. A special note of thanks to my childhood friend Hareesh Gottipati (Nani), Vidhul Dev and Arka who are more than just friends. I still remember the ghts we had on every other day on almost every topic. The topics included more of politics, movies, places and almost every current situation, but the discussion never involved studies. Swetha Peri is one other person in my life who is more than a friend. She had the patience to hear everything and take any situation casually with a calm

iv

mind. I would like to thank Swetha for being such a great friend and who always supported my every decision. A thanks is just not enough for Harish Valapala. I cannot forget the help that I got from him, every time when I was supposed to meet the deadline. I would also like to thank Alex from math department for giving an opportunity to work as a math tutor in the nal semester. He has been very humble during my defense and allowed me to work based on my availability, which was very helpful Finally I would like to thank all my friends and roommates: Sravan (Buggi), Varun (Jaa), Lalith (Makku bro), Venu, Madhusudhan Nagireddy (Madhu), Suresh (Debri), Nikhilesh (Hadavidi) and especially the V6 group Punith (the buss), Rajesh, Ramesh, Venkat and Harish.

VITA

December 17, 1986

Born in Hyderabad, India. Education

2004 - 2008 2009 - 2010 Since 2008

B.Tech. Electronics and Communication Engineering, Jawaharlal Nehru Technological University, India Teaching Assistant, New Mexico State University,USA M.S in Electrical Engineering, New Mexico State University, USA Awards and Achievments

2008 - 2011 March - 2011

In-State Tuition, NMSU,USA. Third place in Graduate Research and Arts Symposium, NMSU, USA. Field of Study

Major Field:

Electrical Engineering (Analog Microelectronics/VLSI Design)

vi

ABSTRACT

A LOW-DISTORTION CLASS-AB AUDIO AMPLIFIER WITH HIGH POWER EFFICIENCY

BY CHAITANYA MOHAN, B.Tech

Master of Sciences, Engineering Specialization in Electrical Engineering New Mexico State University Las Cruces, New Mexico, 2011 Dr. Paul M. Furth, Chair Place: Thomas & Brown Room-207 Date: 03/17/2011 Time: 2:00 PM

A low-distortion three-stage Class-AB audio amplier is designed to drive a 16- headphone speaker. High power eciency in the design was achieved by using fully-dierential internal stages with local common-mode feedback networks and replica biasing of the output stage. The threshold voltage of NMOS transistors were made comparable to PMOS transistors by biasing the p-substrate in order to achieve high linearity. The stability of the amplier is achieved using multiple compensation techniques. The audio amplier is designed to drive widely varying capacitive loads from 10 pF to 5 nF. The peak power delivered to the load is vii

93.8mW. The quiescent power of the amplier is 1.43mW. The output signal swing is 2.45Vpp for 1.5V supply. The THD of the amplier is measured as 79dB. The design has been implemented in a 0.5m CMOS process and occupies 0.35 mm2 of area.

viii

TABLE OF CONTENTS

LIST OF TABLES LIST OF FIGURES 1 INTRODUCTION 2 BASE FOR AUDIO AMPLIFIERS 2.1 Audio Amplier Specications . . . . . . . . . . . . . . . . . . . . 2.1.1 2.1.2 2.1.3 2.2 Headphone Speaker Load . . . . . . . . . . . . . . . . . . . Total Harmonic Distortion in an Amplier . . . . . . . . . Power Eciency of an Amplier . . . . . . . . . . . . . . .

xii xiii 1 4 4 5 5 6 7 7 9 9 11 11 13 14 15 16

Output Stage Classication . . . . . . . . . . . . . . . . . . . . . 2.2.1 2.2.2 2.2.3 Class-A Ampliers . . . . . . . . . . . . . . . . . . . . . . Class-D Amplier . . . . . . . . . . . . . . . . . . . . . . . Class-AB Amplier . . . . . . . . . . . . . . . . . . . . . .

2.3

Multi-Stage Ampliers . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 2.3.2 Pseudo Class-AB Amplier . . . . . . . . . . . . . . . . . True Class-AB Amplier . . . . . . . . . . . . . . . . . . .

2.4 2.5

Common-Mode Feedback Network . . . . . . . . . . . . . . . . . . Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 Miller Compensation . . . . . . . . . . . . . . . . . . . . . ix

2.5.2 2.6

Reverse-Nested Miller Compensation . . . . . . . . . . . .

17 18 18 19 20

Three-Stage Class-AB Amplier from [1] . . . . . . . . . . . . . . 2.6.1 2.6.2 Design from [1] . . . . . . . . . . . . . . . . . . . . . . . . Experimental Results from [1] . . . . . . . . . . . . . . . .

2.7

Replica Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 DESIGN OF THE THREE-STAGE CLASS-AB AUDIO AMPLIFIER 23 3.1 3.2 3.3 3.4 3.5 Architecture and Key Aspects of the Audio Amplier . . . . . . . Transistor Level Three-Stage Design . . . . . . . . . . . . . . . . 23 25 25 29 30 31 32 33 35 36 40 43 44 44 48 51 54 x

Bias circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Second-Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 3.5.2 PMOS dierential amplier . . . . . . . . . . . . . . . . . NMOS dierential amplier . . . . . . . . . . . . . . . . .

3.6 3.7 3.8 3.9

Output-Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compensation used in the Design . . . . . . . . . . . . . . . . . . Small-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . Pole-Zero Analysis . . . . . . . . . . . . . . . . . . . . . . . . . .

4 SIMULATION RESULTS 4.1 4.2 4.3 4.4 DC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . THD analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 HARDWARE TESTING

5.1 5.2 5.3 5.4 5.5

Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . DC Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . Transient Measurements . . . . . . . . . . . . . . . . . . . . . . . THD Measurements . . . . . . . . . . . . . . . . . . . . . . . . . .

54 54 56 57 58 69 74 75 85 88 95

6 DISCUSSION AND CONCLUSION APPENDICES A. HARDWARE TEST PROCEDURE B. POLE/ZERO ANALYSIS USING MAPLE C. MATLAB CODE TO PLOT WAVEFORMS REFERENCES

xi

LIST OF TABLES

2.1 3.1 3.2 4.1 4.2 4.3 5.1 6.1 6.2 6.3 6.4 6.5 6.6

Comparison of measured results . . . . . . . . . . . . . . . . . . . Transistor Dimensions . . . . . . . . . . . . . . . . . . . . . . . . Poles and Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . AC Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . Transient Simulation Results . . . . . . . . . . . . . . . . . . . . . Hardware Measurements . . . . . . . . . . . . . . . . . . . . . . . Summary of Hardware Test Results . . . . . . . . . . . . . . . . . Comparison of results with state-of-the-art ([1]) . . . . . . . . . . Simulation vs Hardware (LIQ) . . . . . . . . . . . . . . . . . . . . Simulation vs Hardware (LTHD) . . . . . . . . . . . . . . . . . . Simulation vs Hardware (MIQ) . . . . . . . . . . . . . . . . . . . Simulation vs Hardware (HCL) . . . . . . . . . . . . . . . . . . .

20 26 42 43 46 52 68 69 70 71 72 72 73

xii

LIST OF FIGURES

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

Schematic of a Class-A amplier . . . . . . . . . . . . . . . . . . . Basic design of a Class-D amplier . . . . . . . . . . . . . . . . . Schematic of a Class-AB amplier . . . . . . . . . . . . . . . . . . Schematic of a three-stage pseudo class-AB amplier . . . . . . . Schematic of a three-stage true class-AB amplier . . . . . . . . . Schematic of a fully-dierential amplier with common-mode feedback network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture of Miller compensation for two-stage amplier . . . . Architecture of Reverse-Nested Miller compensation for three-stage amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Architecture of the three-stage class-AB amplier of [1] . . . . . .

7 9 10 12 13 15 16 17 19 21 24 27 28 30 31 32 34

2.10 (a) Schematic of two-stage pseudo class-AB amplier (b) Replica bias circuit to control quiescent at the output stage . . . . . . . . 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Architecture of the proposed three-stage class-AB amplier . . . . Schematic of the three-stage class-AB audio amplier . . . . . . . Schematic of the bias circuit . . . . . . . . . . . . . . . . . . . . . Schematic of the rst-stage . . . . . . . . . . . . . . . . . . . . . . Schematic of the second-stage PMOS dierential amplier . . . . Schematic of the second-stage NMOS dierential amplier . . . . Schematic of the output-stage . . . . . . . . . . . . . . . . . . . . xiii

3.8 3.9

(a) Left-half of the input-stage (b) small-signal model for left half.

36

(a) Right-half of the input-stage (b) small-signal model for right-half. 37 38 39

3.10 (a) PMOS dierential amplier (b) small-signal model PMOS differential amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 (a) NMOS dierential amplier (b) small-signal model NMOS differential amplier. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 (a) Schematic of output-stage (b) small-signal model for output-stage 40 3.13 Small-signal model of the designed three-stage class-AB audio amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 Schematic of the DC test-bench . . . . . . . . . . . . . . . . . . . DC-analysis output . . . . . . . . . . . . . . . . . . . . . . . . . . Schematic of the AC test-bench . . . . . . . . . . . . . . . . . . . AC output of LIQ circuit . . . . . . . . . . . . . . . . . . . . . . . AC output of LTHD circuit . . . . . . . . . . . . . . . . . . . . . AC output of MIQ design . . . . . . . . . . . . . . . . . . . . . . AC output of HCL circuit . . . . . . . . . . . . . . . . . . . . . . Schematic of the Transient test-bench . . . . . . . . . . . . . . . . Transient output of LIQ circuit . . . . . . . . . . . . . . . . . . . 41 44 45 46 47 47 48 49 49 50 50 51 52 53 53 55 56 57

4.10 Transient output of LTHD circuit . . . . . . . . . . . . . . . . . . 4.11 Transient output of MIQ circuit . . . . . . . . . . . . . . . . . . . 4.12 Transient output of HCL circuit . . . . . . . . . . . . . . . . . . . 4.13 Schematic for THD measurement . . . . . . . . . . . . . . . . . . 4.14 Transient output for measuring THD . . . . . . . . . . . . . . . . 5.1 5.2 5.3 Layout of LIQ amplier . . . . . . . . . . . . . . . . . . . . . . . Layout of LTHD amplier . . . . . . . . . . . . . . . . . . . . . . Layout of MIQ amplier . . . . . . . . . . . . . . . . . . . . . . . xiv

5.4 5.5 5.6 5.7 5.8 5.9

Layout of HCL amplier . . . . . . . . . . . . . . . . . . . . . . . Layout of the frame with two LIQ and MIQ. . . . . . . . . . . . . Layout of the frame with two LTHD and HCL. . . . . . . . . . . . Micrograph of the chip. . . . . . . . . . . . . . . . . . . . . . . . . Transient response of LIQ design (an oset of 900mV is added intentionally for visibility) . . . . . . . . . . . . . . . . . . . . . . Transient response of LTHD design (an oset of 900mV is added intentionally for visibility) . . . . . . . . . . . . . . . . . . . . . .

58 59 60 61 62 62 63 63 64 65 66 67

5.10 Transient response of MIQ design (an oset of 900mV is added intentionally for visibility) . . . . . . . . . . . . . . . . . . . . . . 5.11 Transient response of HCL design (an oset of 900mV is added intentionally for visibility) . . . . . . . . . . . . . . . . . . . . . . 5.12 THD measurement for LIQ design . . . . . . . . . . . . . . . . . . 5.13 THD measurement for LTHD design . . . . . . . . . . . . . . . . 5.14 THD measurement for MIQ design . . . . . . . . . . . . . . . . . 5.15 THD measurement for HCL design . . . . . . . . . . . . . . . . .

xv

Chapter 1

INTRODUCTION

The size of portable devices are decreasing with advances in technology; similarly battery size is also decreasing [2],[3],[4]. The portable devices available in the present day market such as laptops, cellphone, iPods and other music players require audio ampliers that are capable of driving small resistive loads and wide range of capacitive loads (headphone speakers). Audio ampliers require high current at the output stage to drive low resistive loads [5]. The main features of audio ampliers are low power dissipation, high output power and low distortion[1],[2],[5],[6],[7]. The ideal choice for audio ampliers are class-AB and class-D ampliers [6]. Though class-D ampliers have high eciency, low power dissipation and low distortion [5], class-AB ampliers are preferred for designing audio ampliers because they have better power supply rejection ratio (PSRR) than class-D ampliers [2],[6]. Moreover, class-D ampliers are subject to electromagnetic interference [1],[5],[7]. A three-stage pseudo class-AB amplier from [3] experiences a large quiescent current when the output stage current increases. An adaptive biasing technique is used to transform the pseudo class-AB amplier to a true class-AB amplier [3],[4]. However, the gain experienced by the load through PMOS output transistor is dierent from the gain experienced by the NMOS output transistor. This results in asymmetry at the output, which in turn causes severe distortion. Although, the bias current of the amplier is low, the distortion is large. 1

In order to obtain symmetry at the output, the load must experience the same gain through both the NMOS and PMOS output transistors. Biasing the output transistors at a low quiescent current is achieved using replica bias. The replica biasing circuit is used to generate the required bias voltages at the gates of the output transistor [8]. A local common-mode feedback network is used for symmetrical gain and to generate a desired common-mode output voltage. Thus it simultaneously improves the power eciency and reduces distortion. As the number of stages in an amplier increases, the stability starts to degrade [3],[4],[9],[10],[11]. Thus compensation networks are used to improve the stability of a multi-stage amplier. Some of the commonly used compensations are Miller compensation with nulling resistor, nested Miller compensation and reverse-nested Miller compensation for multi-stage ampliers. Miller compensation with nulling resistor proposed in [10] is used to create a RHP zero to split poles. Reverse-nested Miller compensation is more desirable for multi-stage ampliers than nested Miller compensation as it improves the bandwidth [3],[9],[10]. Based on the class-AB amplier in [3],[4], this thesis reports on the design of a new three-stage class-AB amplier. The class-AB amplier has fully-dierential internal stages. A common-mode feedback network is used to provide the symmetrical gain and to generate a common-mode voltage at the output. Low quiescent current at the output-stage is obtained using the replica bias circuit. Substrate biasing technique is used to attain linearity at the output. Chapter 2 describes specications for designing an audio amplier, the types of output stages that can be used in the design of an audio amplier, the purpose of using using multi-stage ampliers, the stability issues of multi-stage ampliers, and the compensation networks that are used to improve the stability, bandwidth and transient response of the multi-stage ampliers. A summary of 2

architecture and experimental results of three-stage class-AB amplier from [1] is described. The results of [1] are used as basis for designing a new three-stage class-AB amplier with improved gure of merit (FOM). Chapter 3 explains the architecture of each stage of a three-stage class-AB amplier designed in this thesis. The working of replica bias circuit to generate low quiescent currents at the output stage is discussed. The compensation networks used for stabilizing the amplier and the small signal models that explain how the variation in compensation capacitor values improve the stability is also explained. Chapter 4 discusses the results that determine the functionality of the amplier. The test-benches for DC, AC and transient analysis are explained. A comparison of results for four designs with variation in compensation capacitor values is summarized. A test-bench for measuring the total harmonic distortion (THD) is explained. Chapter 5 explains the hardware implementation of the three-stage classAB audio amplier. The layout of the design is discussed and the test-setup of the design for determining the quiescent current is explained in the DC testing. The hardware testing results obtained are compared with simulation results. Chapter 6 discusses about the gure of merit (FOM) of the designed amplier. A summary of results obtained in [1] are compared with the hardware testing results obtained in chapter 5. APPENDICES contains the test procedure for testing the circuit in realtime, the Maple work that determines the poles and zeros in an amplier based on the small-signal model and the code used for plotting the waveforms.

Chapter 2

BASE FOR AUDIO AMPLIFIERS

This chapter give an introduction to specications of audio ampliers, types of amplier output-stage, multi-stage ampliers and compensation networks. 2.1 Audio Amplier Specications Ampliers are used in every electronic device. Though general purpose op-amps can be used to drive a variety of loads but driving small resistive loads is a tough task. The modern portable devices such as laptops, cellphones, Ipods and other music players require audio ampliers for driving headphone speakers. The resistance of headphones is small. It can vary from 32- to a much smaller value depending on the supply voltage. The device dimensions and supply voltages are decreasing with advances in technology. In order to provide nearly constant output power, corresponding to the human perception of loudness, reduced voltages necessitate reduced headphone speakers. The output power POU T is given as
2 VRM S RL

POU T =

(2.1)

Thus for small device dimensions and supply voltages, the load resistance must be made small to maintain a constant output power. The important aspects in an audio amplier are load, total harmonic distortion and power eciency.

2.1.1

Headphone Speaker Load The output resistive load for an audio amplier in portable devices is very

small. As the supply voltage in these devices is very small, the resistance of the headphone must be made small to provide constant output power as shown in (2.1). If the resistance of the headphone speaker is made large, then for small supply voltages the output power of the amplier decreases. Thus the loudness is reduced. Modern day headphone speakers have resistance as small as 8-. The quiescent current is small for small supply voltages. The distortion in an amplier is inversely proportional to the quiescent current. As the quiescent current decreases, the distortion in an amplier increases. 2.1.2 Total Harmonic Distortion in an Amplier Total harmonic distortion is very important for ampliers that drive large capacitive loads and low resistances such as audio ampliers. Harmonic distortion occurs in ampliers when the AC component of the drain current id is comparable to DC component of the drain current ID [12]. Every amplier produces harmonics for a given fundamental frequency. The level, or amplitude, of these harmonics is smaller than the amplitude, or level, of its fundamental frequency. The total harmonic distortion is an important amplier specication. It is given by
2 V22 + V32 + V42 ........ + Vn RM S RM S RM S RM S

T HD =

V1RM S

(2.2)

where V1RM S is the rms voltage of the fundamental frequency and VnRM S is the rms voltage of the nth harmonic. The total harmonic distortion is measured in percentage (%). The lower the value better the sound quality. Audio ampliers with a THD of less than 0.5% produce an audio signal with noise which is hardly perceived by the human

ear. Thus audio ampliers must be designed with a THD less than 0.5% for high sound quality. In order to reduce distortion, feedback networks are used. Apart from distortion, another important feature of an audio amplier is power eciency. The power eciency of an audio amplier is made high by lowering the quiescent current in the amplier. This is discussed in the next section. 2.1.3 Power Eciency of an Amplier The battery life of a portable system is very important [1]. There will always be demand in the market for systems that run for longer time. Thus in order to have an ecient battery life, the quiescent power of the system should be minimized. The power eciency of the amplier is dened as the ratio of power delivered to the load to power supplied by the battery [1],[12]. The power delivered to the load is given in (2.1). The power eciency ( ) of the amplier is given by POU T 100 PS

% =

(2.3)

where PS is the power supplied by the battery given by

PS = IQ (VDD VSS )

(2.4)

Thus, from (2.3) and (2.4), if PS is reduced, the eciency of the amplier will be improved. In order to reduce PS , the quiescent current (IQ ) can be reduced. As supply voltages are smaller for new technologies, multi-stage ampliers are used to drive the load. The quiescent current increases with increase in number of stages. The quiescent current also depends on the type of amplier. The linearity in the operational region and low power dissipation are important aspects 6

for audio ampliers. Thus two types of ampliers that provide either of the two properties or both are discussed in the following sections- Class-A and Class-AB ampliers 2.2 Output Stage Classication The output stage of ampliers are classied based on the circuit conguration and the type of operation [8]. Three output stage classications of an amplier are discussed in the following sections. 2.2.1 Class-A Ampliers The high linearity in the operational range of class-A ampliers make them ideal for audio applications. Owing to their high power dissipation these ampliers are replaced with class-AB ampliers for audio applications. Thus class-A ampliers are limited to applications that require only small changes in the output voltage, as the power consumption can be very low for small output signals. The schematic of the class-A amplier is shown in Fig. 2.1.

VB M2 VIN

IB VOUT M1 RL

Figure 2.1: Schematic of a Class-A amplier

The gate of the transistor M2 is connected to a DC bias voltage (VB ). This turns the transistor M2 ON and a constant current (IB ) is sourced from VDD to bias transistor M1 . Thus it acts as a current source. The input for a class-A amplier is at the gate of transistor M1 . The gain of the amplier is Gm1 Ro , where Gm1 is the transconductance of the transistor M1 and Ro is the resistance at the output node given by Ro = ro1 ro2 RL . The current from transistor M1 increases when the gate experiences a large signal at the input. The sinking current in the amplier is not limited but the sourcing current is limited to IB as shown in Fig. 2.1. The upper-half cycle at the output observes distortion [8]. Moreover the eciency of the class-A amplier is low. The eciency of an amplier is given in (2.3). For class-A ampliers the load power is given as
2 VOU T 2RL

PL =

(2.5)

and the power from battery PS is given as

PS = 2ID (VDD VSS )

(2.6)

The eciency is maximum when VOU T = ID RL = (VDD - VSS ). The eciency of class-A amplier accounts to 25% [13] using equations (2.3), (2.5), (2.6). Hence makes it hard to be used in present day market of audio ampliers. To overcome the problem of low eciency, class-AB ampliers are preferred over class-A ampliers. The class-AB ampliers have low power dissipation and low distortion. The other classication of output stage amplier known as class-D amplier, also provides low power dissipation and low distortion. This is explained in the following section.

2.2.2

Class-D Amplier Class-D ampliers nd applications in audio ampliers and pulse genera-

tors [8]. The basic design of a class-D amplier is shown in Fig. 2.2. The output of a Class-D amplier is a sequence of pulses. The frequency of the output signal is higher than input signal frequency. Passive lters are used at the output-stage to eliminate undesired harmonics.

A1

+
Precision triangular Wave generator

Vout RL

Figure 2.2: Basic design of a Class-D amplier

The amplitude of the output pulses is xed. The conduction of switching devices occurs during the transition of states. Hence, the power dissipation is reduced as the transition is only for a short duration. Though class-D ampliers have an eciency up to 95%, the power supply rejection ratio is higher when compared to class-AB ampliers, as one of the supply voltage is the output voltage [8]. Hence, variations in supply voltage create variations at output. Thus class-AB ampliers are preferred for audio applications, as they have higher power supply rejection ratio over class-D ampliers. 2.2.3 Class-AB Amplier The basic schematic of the class-AB amplier is shown in Fig. 2.3. The transistor MN is ON for the negative half cycle of the output signal and the transistor MP is ON for the positive half cycle. Thus, only one transistor sources 9

current for each half cycle while other is turned OFF. This kind of operation provides a push-pull action. This minimizes the quiescent current of the amplier. The Vbat is used to turn ON both MN and MP for the short time when the output signal is near zero. Thus it acts as a class-A amplier for very small output signals. The result is minimized crossover (crossing through zero) distortion.

MN VIN
Vbat Vbat

VOUT MP RL

Figure 2.3: Schematic of a Class-AB amplier

The eciency of the class-AB amplier is determined using (2.3). The load power is given in (2.5). The power from the battery is the total average power drawn through the power supplies given by 2 VOU T (VDD VSS ) + 2IQ (VDD VSS ) ( + ) RL

PS =

(2.7)

where IQ (VDD - VSS ) is the quiescent power (VOU T = 0) per transistor and ( + ) is the conduction angle in radians, ( + ) 2 . Thus the maximum eciency accounts to 50% 78.5% [13]. The push-pull action, low distortion and high power eciency of class-AB ampliers make them ideal choice for audio applications. 10

A single stage class-AB amplier does not provide the enough gain to drive the load. Thus multi-stage ampliers are used for driving small loads. As the number of stages increase, the stability starts to degrade. To stabilize these multi-stage ampliers compensation networks are used. The following sections focus on multi-stage ampliers and compensation networks. 2.3 Multi-Stage Ampliers In the past, a single-stage amplier was sucient for providing large gain. As the device dimensions were large, voltage levels were large to drive resistive loads. A single-stage amplier has only one pole, thus single-stage ampliers are highly stable. Advances in technology has made the device dimensions smaller. Low voltages are required to operate these transistors. Hence a single-stage gain is not sucient to drive resistive loads. In order to overcome this problem, two or more stages are cascaded together to provide a gain that is the product of each gain stage [14],[15],[16].As the number of stages increase, the stability starts to degrade. A compensation network is required to provide stability. The compensation network becomes more complex when the number of stages increases beyond four. A large number of multi-stage ampliers are proposed in the literature [9],[10],[11],[13]. A multi-stage pseudo class-AB amplier proposed in [17] is used as the basis for audio amplier designed in this work. 2.3.1 Pseudo Class-AB Amplier The schematic of a multi-stage amplier is shown in Fig. 2.4. The rststage is a folded cascode dierential amplier formed with transistors N15 and P14 . The gain of the rst-stage at node V1 is given by GM3 R1 , where R1 is the output resistance at V1 . The second-stage is realized using a NMOS commonsource amplier N6 . 11

P1

Vb2

P2

Vb2 Vb3

P5 P7 P6 Cm1 Vout P8

P3

Vb3

P4 Rm3 Cm3 Ccb V1 V2 N6 N7 N8 Cm2 Rm1 V3 RL CL

Vin-

N2

N3

Vin+

Vb1

N1

N4

N5

Figure 2.4: Schematic of a three-stage pseudo class-AB amplier

The output stage for sinking the current is designed using a NMOS commonsource amplier N8 . The third-stage or the output stage for sourcing the current is realized using N7 common-source amplier and P7 and P8 current mirror. Thus the push-pull action is provided by P8 and N8 transistors. The gain in the rst-stage is a inverting gain. The common-source ampliers N6 and N8 of second-stage have inverting gain conguration. The gain of the third stage realized with transistors N7 and P78 is a non-inverting gain. As the two-stages of inverting gain from P8 and N7 common-source ampliers are cascaded to obtain a non-inverting gain. Thus the overall gain from Vin+ to Vout is non-inverting. This multi-stage pseudo class-AB amplier is a low voltage design for driving small loads. Though it can drive small resistive loads, it cannot be used as audio amplier. As stated earlier, the low power dissipation and low distortion are the main features of audio ampliers. The quiescent current in this amplier increases with increase in current at the output stage. Thus the power dissipation of the ampli-

12

er is large. In order to reduce the high quiescent current in this amplier a new technique called adaptive biasing has been proposed in [3],[4]. 2.3.2 True Class-AB Amplier To minimize the current through the transistor P7 in Fig. 2.4, two resistors Rad1 and Rad2 are used, as shown in Fig. 2.5. The diode connected transistor P7 and the resistors Rad1 and Rad2 form the adaptive biasing network [3],[4]. The value of the resistors Rad1 and Rad2 are made large to minimize the current through transistor P7 .
Adaptive biasing Vb2 Vb2 Vb3 P3 Vb3 P4 Rm3 VinN2 N3 Vin+ V1 Vb1 N1 N4 N5 Cm3 Cm2 Ccb V2 N6 N7 N8

P1

P2

P5 P6 P7 Rad2

Rad1 P8

Rm1 V3

Cm1 Vout RL CL

Figure 2.5: Schematic of a three-stage true class-AB amplier

The transistor P7 is in cuto region when the output current is very low. The load at node V3 is simply Rad2 . The phase margin of the amplier is improved with the presence of resistor Rad2 and it moves the non-dominant pole to high frequencies [3],[4]. When the load experiences a large sourcing current through the transistor P8 , the transistor P7 moves to the saturation region. Now, the load experienced
1 by node V3 is ( GM + Rad1 )
7

Rad2 . For large values of resistors, the gain at the

node V3 in Fig. 2.5 is large compared to the gain at node V3 in Fig. 2.4 [3],[4]. 13

Thus the power eciency and gain of the amplier are improved. Though the amplier has good power eciency but it cannot be used for audio amplication, as the distortion in the amplier is high. The gain experienced by the load through P8 common-source is a three-stage gain, whereas the gain experienced by the load through N8 common-source amplier is a two-stage gain. This creates non-linearity at the output and leads to distortion. To attain low distortion, load must experience same gain through the push-pull transistors. One way to achieve this is by using fully dierential internal stages. The fully dierential ampliers require additional circuitry to attain balanced outputs. This additional circuitry is a common-mode feedback network. The working of the common-mode feedback network is explained in the following section. 2.4 Common-Mode Feedback Network A common-mode feedback network is used for generating a known voltage at the output of a fully-dierential amplier [12] as shown in Fig. 2.6. The dierence between the inverting terminal and the average of non-inverting terminals of the common-mode feedback amplier are amplied with a gain at the output. If the dierence between Vb2 and the average of Vout+ and Vout- is large, then the voltage VCM F B increases. This increases the VGS of transistors N1 and N4 and the current through them. Thus the voltage at the output nodes reach close to Vb2. Hence a known voltage is obtained at the output. The circuit also works for dierential inputs. If one of the input voltage moves above the other then one of the output goes above Vb2 by a small amount and the other output moves down the Vb2 by the same amount. There also exist some concerns while using these feedback networks. The stability of the amplier changes and it requires compensation networks to sta-

14

P1

Vb2 P2

Vout+ + CMFB

Vout+

Vin-

N2

N3

Vin+

N1

VCMFB

N4

Figure 2.6: Schematic of a fully-dierential amplier with common-mode feedback network

bilize the dierential amplier, as well as common-mode feedback network. The following section gives an introduction to compensation. 2.5 Compensation Stability is an important aspect for ampliers. The ampliers with single stage are highly stable as they have single dominant pole. In multi-stage ampliers the number of dominant poles are not limited to one. Thus the stability goes

15

down. Compensation networks are used, to improve the stability of multi-stage ampliers. Two types of compensation networks are reported in the following sections. 2.5.1 Miller Compensation A Miller compensation uses a resistor and a capacitor in series between the input and output of an inverting stage [9],[11]. The architecture of the Miller compensation is shown in Fig. 2.7.
CM RM

-gm1 VIN -Av1 R1 C1 -Av2

-gm2 VOUT RL

Figure 2.7: Architecture of Miller compensation for two-stage amplier

If the two poles of the two-stage amplier are near each other, then a Miller compensation can be used to split the poles. The dominant pole is moved towards the low frequencies and the non-dominant pole is moved towards the high frequencies. The series resistor RM and capacitor CM create a zero. The dominant pole is given by P3dB = P2 =
RM +GM2 R1RL , CL (R1+RM )RL 1 , CM (RM +GM2 R1RL ) 1 (RM G 1 )CM

the non-dominant pole is

and the zero is

1 GM2

. Thus the RHP zero can be

M2

eliminated by selecting RM =

[9],[11], [13].

16

2.5.2

Reverse-Nested Miller Compensation A two-stage amplier is designed by cascading two inverting stages. Sim-

ilarly, a three-stage amplier is designed by cascading two inverting stages and a non-inverting stage. In a three-stage amplier design the rst stage is inverting stage that is implemented using a dierential amplier and the next stages are implemented with common-source ampliers. If the second stage is made noninverting, then nested Miller compensation is used. Likewise, if the second-stage is implemented with inverting gain conguration and third-stage with non-inverting gain conguration, then reverse-nested Miller compensation can be used to stabilize the amplier. The architecture of the reverse-nested Miller compensation is shown in Fig. 2.8.

RM CM2 -gm1 VIN -Av1 R1 C1 -Av2 R2 C2 -gm2

CM1

gm3 VOUT Av3 RL

Figure 2.8: Architecture of Reverse-Nested Miller compensation for three-stage amplier

The dominant pole for this compensation is given by 1 CM1 GM2 GM3 R1 R2 RL

P3dB =

(2.8)

The transfer function adapted from [9] is given by

17

Arnmc =

2 GM1 GM2 GM3 R1 R2 RL (1 s( GM + M 2

(1 +

s CM GM G1 )[1 R R R 1 2 M3 1 2 L

CM2 CL s( G M C 3 M1

CM1 C 1 CM2 ) s2 GM ) GM2 GM3 R2 M2 GM3 C 2 C 2 CM1 CL + GM ) + s2 G M GM ] G M2 M3 2 M3

(2.9) The equation 2.9 shows that the amplier has three poles and two RHP zeros. The dominant pole is given in equation 2.8. The other two poles are high frequency poles. Thus in any amplier after the required compensation scheme is applied, the values of compensation capacitors and resistors are determined to move the non-dominant poles and zeros to high frequencies. This stabilizes the circuit and improves the bandwidth. A large number of compensation techniques are proposed to stabilize the multi-stage ampliers [9],[10],[11],[15],[16],[17]. These multi-stage ampliers are used in a wide range of applications. A three-stage class-AB amplier is proposed by [1] to drive 16- headphone speakers. The design and results are summarized in the following section. This design is taken as a reference to compare the results with our work. 2.6 Three-Stage Class-AB Amplier from [1] The architecture of the proposed design is shown in Fig. 2.9. It is a threestage class-AB amplier that drives 16- headphone speakers and a wide range of capacitive loads. 2.6.1 Design from [1] The rst stage is implemented using a folded-cascode amplier with an inverting gain conguration. The second-stage is implemented using commonsource ampliers with positive gain conguration. A damping factor control stage is used in the ampliers that drive large capacitive loads [1],[11]. The damping factor control stage is used in ampliers that have large swing to improve 18

RC CC CC2

VIN

-Gm1

Gm2

-Gm3 CL

VOUT RL

CD

CD2

VB

RB GmD

Figure 2.9: Architecture of the three-stage class-AB amplier of [1]

the bandwidth and transient response [11]. The output stage is designed with common-source ampliers to provide the required push-pull action. The output stage of the amplier is biased at 1V, and the rest of the amplier is biased at 0.6V. 2.6.2 Experimental Results from [1] The total quiescent current of the amplier is 730 A. The THD of the design is -84.8dB for 1.4VP P , 1 kHz sine-wave output. A gure of merit (FOM) was dened to compare with other designs. The gure of merit dened by [1] is the ratio of peak output power to the supply power. A comparison of measured results is shown in Table 2.1. Taking the above design as a reference, a new three-stage amplier is designed. The concept of replica biasing is used in the design to generate the bias

19

Table 2.1: Comparison of measured results Parameter Technology Capacitance load Supply THD+N @ max. output Total compensation capacitance Quiescent power FOM [18] 0-300 pF 3.0V -90dB 12.0mW 8.1 [19] 0.35 m CMOS 0-300pF 0.8V -69dB 2.5mW 1.3 [20] 65 nm CMOS 0-12 nF 2.5V -68dB 35pF 12.5mW 4.3 [1] 130nm CMOS 1 pF - 22 nF 1.2V/2.0V -84dB 14pF 1.2mW 33.3

voltages for the output stage. The following section gives a brief introduction to replica biasing. 2.7 Replica Biasing A replica bias circuit is used for generating bias voltages for the output stage [21]. A replica bias circuit can be used in a class-AB amplier to bias the common-source ampliers of the output stage. The bias voltages generated by the replica bias circuit acts as Vbat as shown in Fig. 2.3. When no input signal is present, transistors of the output stage are in ON state but in a non-linear region. The quiescent current in the output stage is set by the current through the replica bias circuit [8]. The output stage acts as a class-A amplier, as the output transistors are either sourcing or sinking current all the time. This eliminates the dead band region and minimizes the distortion in class-AB ampliers.

20

The schematic of a two-stage pseudo class-AB amplier and the replica bias circuit to control quiescent current adapted from [8] are shown in Fig. 2.10.
VCTRL M4 M11 CC RLarge M8 VI x M2 VB y M3 2IB M1 M10 M9 M7 VI+ RC CC Vout M5 M6

(a)

M5C M6C Vref M3C IB M1C RC CC VB MP VCTRL

VB

IB MB MN

(b)

Figure 2.10: (a) Schematic of two-stage pseudo class-AB amplier (b) Replica bias circuit to control quiescent at the output stage

The two-stage pseudo class-AB amplier has a fully-dierential rst-stage. The transistors M6 and M7 are common-source ampliers that provide the pushpull action. The replica bias circuit is used for controlling the quiescent current through output-stage transistors M6 and M7 . The transistors M5C , M3C , M1C and M6C are replicas of M5 , M3 , M1 and M6 respectively. The transistor MB 21

is biased at a voltage VB such that the current through MB is IB . The current through transistors MP , M5C and M5 are similar, as they have same VSG . Thus, the voltage at the drain of M5C is similar to the voltage at node y. This causes the current through M6 to be same as the current through M6C (IB ). Hence, a quiescent current of known value is obtained at the output of a two-stage pseudo class-AB amplier. A feedback network is used along with the replica bias circuit to generate bias voltages for the output-stage. Three-stage class-AB amplier designed in our work use the concept of replica bias to generate bias voltages and control quiescent current at the output stage. The design of the amplier is discussed in Chapter. 3.

22

Chapter 3

DESIGN OF THE THREE-STAGE CLASS-AB AUDIO AMPLIFIER

A three-stage class-AB audio amplier is designed to drive 16- headphone speakers. The audio amplier has high power eciency and low distortion, and it is also capable of driving a wide range of capacitive loads. This chapter deals with the design of the three-stage class-AB amplier. It is organized as follows: The key aspects and architecture of the audio amplier is discussed in the rst section. It is followed by the design of each stage with small signal models. The last section of the chapter deals with the stability of the amplier that is analyzed with poles and zeros. 3.1 Architecture and Key Aspects of the Audio Amplier The architecture of the designed three-stage class-AB audio amplier is shown in Fig. 3.1. The design is implemented using fully-dierential internal stages. The rst stage is a fully-dierential folded cascode amplier with an inverting gain conguration. The second-stage is implemented with two two differential ampliers. A non-inverting gain conguration is used in this stage. The third stage is implemented with PMOS and NMOS common-source ampliers for the push-pull action. The gain experienced by the load at the output through NMOS and PMOS common-source ampliers is same. The symmetry in gain is achieved using two dierential ampliers in the second-stage. In the absence of input signal, a dead band region is created at the output, as the NMOS and PMOS common-source 23

Cc1

Rc1

2Cc3 + A2 - + 2Cc3 Cc2

Vo2P+

-A3

Vin+ Vin

+ A1 - +

Vo1 Vo1+

Rc2

Vout
Cc2 Cc3

+ A2

- A3

Vo2N+

Cc3

Figure 3.1: Architecture of the proposed three-stage class-AB amplier

ampliers are turned OFF. This leads to crossover distortion. To minimize the distortion, a common-mode feedback network is used in combination with replica bias in the second-stage to generate bias voltages for the third-stage . This turns ON the transistors of the third-stage and the dead band region is eliminated. The linearity in the design is achieved using a technique called substrate biasing. The threshold voltage of all NMOS transistors are made comparable to threshold voltage of the PMOS transistor. This is attained by connecting the bulk of the NMOS transistor to a voltage lower than source voltage. This is explained in detail in the following sections.

24

3.2

Transistor Level Three-Stage Design The transistor level schematic of the three-stage class-AB audio amplier

is shown in Fig. 3.2. The rst stage is a fully-dierential folded cascode amplier realized with transistors M1 -M12 . The transistors M13 -M20 in combination with resistors R1 and capacitors CS form the common-mode feedback network. The second-stage is realized using two dierential ampliers. A NMOS dierential amplier is formed with transistors M40 -M47 and the PMOS dierential amplier is formed with transistors M21 -M28 . The transistors M37 -M39 and M56 -M58 are replica bias circuits. The output-stage is realized with transistors MP and MN . A Miller compensation is used from the output of third-stage to negative output terminal of the rst-stage. A reverse-nested Miller compensation is used between input and output of the second-stage. The transistor dimensions are given in Table 3.2. In this work, four designs are implemented. The dierence in each design is the dimensions of the transistors M39 and M58 , the value of compensation capacitors and resistors, and the input bias current. A trade-o has been observed between the total harmonic distortion and quiescent current. This is discussed in Chapter 4. The design of each stage is explained in the following sections. 3.3 Bias circuit The schematic of the bias circuit is shown in Fig. 3.3. The bias circuit internally generates four bias voltages Vb1, Vb2, Vb3 and Vb4. The voltage Vb2 is one VSG below VDD . This is generated by diode connecting the transistor M1A as shown in Fig. 3.3. Similarly the voltage Vb1 is generated. A long L (length) diode connected transistor is created by connecting the gates of transistors M4P 1 -M4P 5 as shown in Fig. 3.3. The voltage Vb3 at the gate of transistor M3A is 2VDSSAT + VT HP . The current through this transistor is given 25

Table 3.1: Transistor Dimensions Device M1A , M1B , M1C , M19 , M20 , M35 , M36 , M50 , M51 M11 , M12 , M27 , M28 , M48 , M56 M1 M47 M2C , M17 , M18 , M33 , M34 M9 , M10 , M31 , M32 , M49 , M57 M2 M46 M4A , M4B , M4C , M54 , M55 , M15 , M16 , M31 , M32 M4 , M5 , M13 , M29 , M37 , M5 , M6 , M21 , M40 , M41 , M44 , M45 M23 , M26 M3A , M3B , M3C , M52 , M53 M7 , M8 , M14 , M30 , M38 M22 , M42 , M43 M4P 1 , M4P 2 , M4P 3 , M4P 4 , M4P 5 M1N 1 , M1N 2 , M1N 3 , M1N 4 , M1N 5 M39 MN M58 MP 26 Dimensions
20m 1.2m 20m 1.2m , m = 2 20m 1.2m , m = 4 20m 1.2m , m = 8 20m 0.9m 20m 0.9m , m = 2 20m 0.9m , m = 4 20m 0.9m , m = 8 60m 1.2m 60m 1.2m , m = 2 60m 1.2m , m = 4 60m 1.2m , m = 6 60m 0.9m 60m 0.9m , m = 2 60m 0.9m , m = 4 30m 1.2m 10m 1.2m 150m 0.6m , m = 4,6 150m 0.6m , m = 40 300m 0.6m , m = 4,6 300m 0.6m , m = 40

Bias circuit
Vb2 M4B M3B Vb3 M3C CS M1N1 Vin+ Vo1 + Vo1M1N2 R1 R1 Vb4 M10 M12 M19 M17 Vb4 M1N3 Vb4 M2C Vb4 M2 M1 M11 M9 Vb1 M1C Vb1 M1N4 M1B M1N5 M3 M4 VinVo1+ Rc2 M18 M20 Cc2 CS Vc M15 M16 Vr Cc2 M7 M8 Vb3 Vb3 M14 M4C Vb3 Vb4 Vb2 M5 M6 M13 Vb2 Vb2

First-stage

M4A

Vb2

M4P5

M3A

Vb3

M4P4

M4P3

M4P2

Vo2P+

M4P1

Vo2N+

Vbias

M1A

Replica-bias

Vb2 M29 M40 Vb3 M30 M42 Vo1+ M31 CS R2/2 M44 Vb4 Vrn M39 Vb1 Vo2P! 2Cc3 Vo1! M33 M34 M36 M35 Vb4 M32 Cc3 Vrc CS R2/2 M45 Vb3 M43 Vb3 M38 M41 M37

Vo2P+

Vo2N!

R2 M26 M28

R2

Vo2N+

27
Vrs 2Cc3 Vo1+ M46 M47

M21

Vb2

Vb2

M54 M52 Vb3

M55 M53

Vrp

Vo2P+ M58

MP

Vb3

M22

Vo1!

M23

M24

Vo1! Rc1 Cc1 M51 M50 Vout

Cc3

CS

CS

M25

Vb4

Vb4 Vb1

M49 M48

Vb4 Vb1

M57 Vo2N+ M56 MN

M27

Replica-bias

Second-stage

Third-stage

Figure 3.2: Schematic of the three-stage class-AB audio amplier

M4A M3A

Vb2 Vb3

M4P5 M4P4 M4P3 M4P2 M4P1 Vb3

Vb2 Vb3 Vb4

M4B M3B

Vb2

M4C

Vb3

M3C

M1N1 M1N2 M1N3 M1N4 M1N5 Vb1 Vb4

IB1 M1A

Vbias

IB2 M1B

M2C M1C

Figure 3.3: Schematic of the bias circuit

by ID = As the current IB 1 = IB 2 (3.2) N COX W3A (VGS VT HP )2 2 L3A (3.1)

The current through the Long L transistor formed by the transistors M4P 1 -M4P 5 is given by N COX W4P ((2VDSSAT + VT HP ) VT HP )2 2 L4P

ID =

(3.3)

This equation can be rewritten in terms of VGS as N COX W4P 4(VGS VT HP )2 2 L4P 28

ID =

(3.4)

Thus from (3.1), (3.2) and (3.4) we obtain W4P 1 W3A = L4P 4 L3A

(3.5)

The transistor M4A is biased at the edge of the saturation region, thus pulling more current from transistor M4A , moves it from saturation to triode region [12]. Hence, the length of the long L transistor is assumed ve times the length of M3A rather than four times. This generates a voltage Vb3 that is VSDSAT away from Vb2. Similarly, the voltage Vb4 is generated that is VDSSAT away from Vb1. The bias voltages are replicated to others stages of the amplier through transistors M1C -M4C . The current through the branch M1C -M4C is mirrored to the next stages based on the aspect ratio of the current mirror. 3.4 Input-Stage The rst stage of the amplier is realized using a fully-dierenatial folded cascode amplier, as they have wide swing and high gain. The schematic of the rst stage is shown in Fig.3.4. Transistors M1 -M12 represent the folded cascode amplier. The transistors M13 -M20 in combination with resistors R1 and capacitors CS form the common-mode feedback network. A common-mode feedback network is used for generating a known voltage Vr at the output of the folded cascode amplier. The operation of the rst-stage is as follows. The voltage Vr is set to 0V, this allows the current to pass through the transistor M16 . The voltage at the node VX increases. The transistors M20 , M11 and M12 form the current mirror. The current through the transistors M11 and M12 depends on the aspect ratio

29

M5

Vb2

M6

Vb2 Vb3

M13
Common-mode Feedback network

M14 Vr

M7

Vb3 CS CS

M8 Vc Vo1+ M15 M16

Vin+

Vo1-

M3

M4

VinR1 R1 Vb4

VX Vb4

Vb4 Vb1

M2 M1

M9 M11

M10 M12

M17 M19

M18 M20

Figure 3.4: Schematic of the rst-stage

of the mirror. Hence the voltages Vo1+ and Vo1- are pulled towards VSS . The voltage Vc acts as virtual ground, as it is the center voltage of Vo1+ and Vo1-. The gain of the rst-stage is determined by the gm4,3 resistors R1, as R1 ro of the transistors. The tail of the folded cascode amplier and common-mode feedback network are cascoded to provide better matching between the transistors and to obtain good precision in matching the currents. Under equilibrium condition, the voltage Vo1+ and Vo1- are approximately at 0V. This voltage is used for biasing the second stage. The implementation of second-stage is explained in the following section. 3.5 Second-Stage The second stage of the amplier is implemented using a NMOS dierential amplier and a PMOS dierential amplier. The NMOS dierential amplier is used for biasing PMOS common-source amplier of the third-stage and the PMOS 30

dierential amplier is used for biasing NMOS common-source amplier of the third-stage. 3.5.1 PMOS dierential amplier The schematic of a PMOS dierential amplier is shown in Fig. 3.5

Vb2

M21

Vb2

M29

CMFB

Vb2

M37

Vb3 Vo1 Cc3 Vo2N CS R2

M22 M24 Vo1+ Cc3 Vo2N+ CS R2 Vb4 Vrc

Vb3

M30 M32

Vb3

M38

M23

M31

M25 M27

M26 M28

M33 M35

Vb4

M34 M36 Vrn M39

Replica bias

Figure 3.5: Schematic of the second-stage PMOS dierential amplier

Transistors M21 -M28 form the PMOS dierential amplier. The commonmode feedback network (CMFB) is realized with transistors M29 -M36 and resistors R2 and capacitors CS . Transistors M37 -M39 form the replica bias circuit. The current through this circuit is determined by the current source formed by transistors M37 and M38 . The voltage Vrn is at VGS above VSS . The common-moded feedback network generates the known voltage Vrn at the output of the PMOS dierential amplier. The gain of the amplier is determined by resistors R2 and the transconductance gm23,24 . 31

Under equilibrium, the common-mode voltage Vrc is equal to V o2N + . This voltage is used as the input for the NMOS common-source amplier of the thirdstage. Since, V o2N + is equal to Vrn, transistors M39 and MN form a virtual current mirror. Thus, the quiescent current of the output stage is determined by the current through M39 . The ratio of currents depends on the ratio of multiplicity of transistor dimensions. 3.5.2 NMOS dierential amplier The NMOS dierential amplier is similarly designed. The schematic of the NMOS dierential amplier is shown in Fig. 3.6.
Replica bias Vrp

M40 M42 Vo2P CS R2/2 M44 Vb3 CS R2/2 M45

M41

M54 Vb3

M55

M58

M43 Vo2P+

Vrs

M52

M53

2Cc3 Vo1

2Cc3 Vo1+ M50 M51

Vb4 Vb1

M46 M47

Vb4 Vb1 CMFB

M49

Vb4 Vb1

M57 M56

M48

Figure 3.6: Schematic of the second-stage NMOS dierential amplier

Transistors M40 -M47 form the NMOS dierential amplier. The commonmode feedback network (CMFB) is realized with transistors M48 -M55 and resistors
R2 2

and capacitors CS . Transistors M56 -M58 form the replica bias circuit. The 32

current through this circuit is determined by the current-source formed by transistors M56 and M57 . The voltage Vrn is at VSG below VDD . The common-moded feedback network generates the known voltage Vrp at the output of the NMOS dierential amplier. The gain of the amplier is determined by resistors the transconductance gm44,45 . Under equilibrium, the common-mode voltage Vrs is equal to V o2P + . This voltage is used as the input for the PMOS common-source amplier of the thirdstage. Since V o2P + is equal to Vrp, transistors M58 and MP form a virtual current mirror. Thus, the quiescent current of the output stage is determined by the current through M58 . The ratio of currents depends on the ratio of multiplicity of transistor dimensions. The dimensions of the transistors M46 and M47 are doubled to obtain twice the bias current than the current through M21 and M22 of Fig. 3.5. Thus, the
2 , which is equivalent to the PMOS gain of the NMOS dierential pair is 2gm44,45 R 2 R2 2

and

dierential amplier gain gm23,24 R2. The gain of the PMOS dierential amplier is made equal to the NMOS dierential amplier to attain symmetry at the output of the amplier. Unlike the rst-stage, the second-stage is a single-ended dierential amplier. The output of the NMOS and PMOS dierential ampliers are the inputs for PMOS and NMOS common-source ampliers of the third-stage, respectively. The design of the third-stage is discussed in the next section. 3.6 Output-Stage The output-stage of the amplier is implemented with huge PMOS and NMOS common-source ampliers. In order to have same current ID through transistors MP and MN , the dimensions of the PMOS transistor MP is made twice the size of NMOS transistor MN , as the mobility of the electrons is approximately 33

about 2.5 times the mobility of holes. The schematic of the output-stage is shown in Fig. 3.7

Vo2P+
MP

Vo1
Rc1 Cc1

Vout

Vo2N+

MN

Figure 3.7: Schematic of the output-stage

The input capacitance CGS associated with transistor MP is twice the capacitance CGS of the transistor MN , as dimensions of the transistor MP is twice the size of transistor MN . The pole of the second-stage PMOS dierential amplier is approximately at
1 R2CGSN

. In order to have the same pole at the output

of NMOS dierential amplier, the resistance R2 is halved and the compensation capacitance is doubled. The pole of NMOS dierential amplier is approximated as
1
R2 (2CGSN ) 2

34

Output swing at the second-stage NMOS dierential amplier must be equal to the output swing of PMOS dierential amplier to attain linearity at the output. The swing at the output of second-stage is determined by voltages Vrn and Vrp shown in Fig. 3.5 and Fig. 3.6. The voltage Vrn is made equal to Vrp to obtain same swing at the input of third-stage and this is achieved by biasing the bulks of NMOS transistors at a voltage lower than VSS . This increases the threshold voltage of NMOS transistors. Hence, more voltage is required at the gate of transistor M39 to allow the current from transistors M37 and M38 to pass through. Thus, VGS of transistor M39 increases and this is comparable to Vrp. The designed amplier has three stages. Hence, the stability of the amplier cannot be achieved without a compensation network. Miller compensation and reverse-nested Miller compensation are used to stabilize the three-stage classAB amplier. A brief description of the compensation network used in this design is given in the following section. 3.7 Compensation used in the Design The rst-stage is an inverting gain conguration and second stage is a noninverting gain conguration. The output-stage is implemented with an inverting gain conguration. A Miller compensation network is applied between the output of rst-stage and the output of the third-stage. Reverse-nested Miller compensation is used across the second-stage for NMOS and PMOS dierential ampliers as shown in Fig. 3.1. A symmetry is maintained while using the compensation networks at the second-stage. This simplies the small-signal model of the amplier. The smallsignal model of each stage is discussed in the next section.

35

3.8

Small-Signal Models The small-signal model of a symmetric folded-cascode amplier is repre-

sented with a current source and a resistor parallel to it. The input-stage in this design is not symmetric, as the compensation capacitor CC 1 is connected to Vo1and there is no compensation capacitor to Vo1+. Hence, the circuit is divided into two equivalent circuits. The left-half of the folded-cascode amplier and its corresponding small signal model is shown in Fig. 3.8, where gm1 is the transconVb2

M5

Vo1Vb3

M7 CS

Vin+

M3

Vo1-

R1
R1

gm1Vin/2
Vb4

Vb4

M2 M1

M9 M11

Vb1

(a)

(b)

Figure 3.8: (a) Left-half of the input-stage (b) small-signal model for left half.

ductance of the transistor M3 . The input signal is assumed as

V in , 2

since Vin =

(Vin+ - Vin-) and Vin+ is only half of the signal Vin. The resistor R1 ro . Thus R1 is the output resistance at node Vo1-. One end of the resistor R1 is connected to node Vo1- and the other end is at virtual ground. Similarly, the small-signal model for right-half of the folded cascode amplier is as shown in Fig. 3.9, where gm1 is the transconductance of M4 and Rc2 is the compensation resistor. Under quiescent conditions the current through M3 36

Vb2

M6

Vb3

M8 CS M4 VinR1

Vo1+
Vo1+ Rc2

Rc2

Vx

Vx

gm1(-Vin/2)

R1

M2 M1

Vb4

Vb4

M10 M12

Vb1

(a)

(b)

Figure 3.9: (a) Right-half of the input-stage (b) small-signal model for right-half.

is equal to current through M4 . Thus the gm s are equal. The signal Vin- is represented as
V in . 2

The resistor R1 is approximately equivalent to resistor R1

shown in Fig. 3.8(a). The second-stage is implemented with NMOS dierential amplier and PMOS dierential amplier. Thus for each amplier, the small-signal models are drawn separately. The PMOS dierential amplier has symmetry at compensation, hence only the output side of the dierential amplier is considered for drawing the small-signal model as shown in Fig. 3.10. The transconductance of the transistor M24 is gm2. The resistor R2 is the output resistance at node V o2n+ . Cc2 and Cc3 are compensation capacitors. Capacitor C2 in Fig. 3.10(b) is the input capacitance CGS of the transistor MN of the output-stage. The voltage Va is (Vo1+ - Vo1-) and the voltage Vo1+ is represented as
Va . 2

37

Vb2

M21

Vb3

M22 M24
Vo1+ Cc3

CS
R2 Vb4

Cc2 Vx
Vo2n+ M26 M28
Cc2 Vx

Cc3 Vo2n+ R2 C2 Vo1+

gm2Va/2

(a)

(b)

Figure 3.10: (a) PMOS dierential amplier (b) small-signal model PMOS dierential amplier.

The part of NMOS dierential amplier and it corresponding small-signal model are shown in Fig. 3.11. Similar to the PMOS dierential amplier, the compensation in NMOS dierential amplier is symmetric. The input capacitance C2 of the transistor MP of output-stage is twice the input capacitance of NMOS transistor MN of the output-stage, as the size of PMOS transistor MP is twice the NMOS transistor MN . Thus to provide the same pole frequency at the output of second-stage the common-mode feedback resistor is made
R2 2

and the compensation capacitor Cc3 is doubled. The transconductance

of the transistor M45 is 2gm2, as the current through the transistor M45 is twice the current through transistor M24 in Fig. 3.10. The signal Vo1+ is current through current source in Fig. 3.11(b) is given by 2gm2
Va 2 Va . 2

The

38

M41
Vb3

M43 Vo2p+
Cc2

Vx

R2/2 2Cc3

M45
Vo1+

2Cc3 Vo1+ Vo2p+

Cc2 Vx

Vb4

M46 M47

gm2Va R2/2

2C2

Vb1

(a)

(b)

Figure 3.11: (a) NMOS dierential amplier (b) small-signal model NMOS dierential amplier.

The third stage is implemented with NMOS and PMOS common-source ampliers. These transistors provide the required push-pull action for the class-AB output-stage. The schematic of output-stage and its corresponding small-signal model are shown in Fig. 3.12. The transconductance of transistors MN and MP is gm3, as the quiescent current through transistors MN and MP is same. Cc1 and Rc1 are the Miller compensation capacitor and nulling resistor across the outputs of input-stage and output-stage. Cout is the load capacitance. Rout is the output resistance of the amplier and is given by

Rout = RL roN roP

(3.6)

39

Vo2P+
MP

Vo1
Rc1 Cc1

Vout

Cc1 Vout-

Rc1 Vout Rout gm3Vop+ Cout gm3Von+

Vo2N+

MN

(a)

(b)

Figure 3.12: (a) Schematic of output-stage (b) small-signal model for output-stage

Rout RL as RL

roN,P

The complete small-signal model of the designed three-stage class-AB audio amplier is shown in Fig. 3.13. The equations for current at each node are put in a software Maple to determine the poles and zeros in the amplier. The equation of the currents at each node and equations used to determine the pole/zero frequencies is shown in APPENDIX B. 3.9 Pole-Zero Analysis The gain of the amplier is determined from the equations in APPENDIX B as Gain = gm1 R1 gm2 R2 gm3 Rout (3.7)

The designed audio amplier has six poles and ve zeros. The poles and zeros obtained are shown in Table 3.2. The fourth pole is at high frequency, hence the last two high frequency poles are neglected. The third zero is a RHP zero. The 40

Rc2 2Cc3 Vo1+ Vx gm2Va 2C2 R1 gm1(-Vin/2) R2/2 gm2Va/2 R2 C2 gm3Vo2P+ Vo2P+ Cc2 Vo2N+ Cc2 Cc3

Cc1

Rc1

Vo1-

Vout Rout gm3Vo2N+ Cout

R1

41

gm1Vin/2

Figure 3.13: Small-signal model of the designed three-stage class-AB audio amplier

other two zeros are high frequency zeros, thus neglected. The rst zero (Z 1 ) is used, to cancel the second pole (P 2 ). Similarly the second zero Z 2 cancels third pole P 3 . Thus the system acts as a two-pole system, where the fourth-pole is considered as second-pole. Table 3.2: Poles and Zeros Poles / Zeros P 1 P 2 P 3 P 4 Z 1 Z 2 Z 3
2 gm2R1R2(2Cc2+2gm3Rout Cc1+3Cc3) 2Cc2+2gm3Rout Cc1+3Cc3 Cc1(2gm3Rout R2C 2+2R1Cc2+3R1Cc3) 2gm3Rout R2C 2+2R1Cc2+3R1Cc3 R1R2C 2(6gm3Rout Cc3+4gm3Rout Cc2+2Cc2+3Cc3) gm2(2gm3Rout +1) CoutRout gm2+2C 2 2 Cc1R1+2R2C 2 1 R2C 2

2 Cc1R1

gm2 2Cc3

42

Chapter 4

SIMULATION RESULTS

To test the functionality of the designed three-stage class-AB audio amplier, the amplier is subjected to DC, AC and transient analysis tests. The following sections discuss the response of the of the amplier. The obtained waveforms are plotted using the Matlab code given in APPENDIX C. Four designs have been implemented by varying the input bias current, dimensions of M39 and M58 shown in Fig. 3.2, compensation capacitor and resistor values and its corresponding results are plotted. The designs are named after their performance as LIQ (Low quiescent current), LTHD (Low THD), MIQ (Moderate quiescent current) and HCL (High load capacitance). The design parameters of the four designs are given in Table 4.1. Table 4.1: Design Parameters Design HCL LTHD MIQ LIQ IB 8 A 9 A 9 A 8 A Rc1 1 k 1 k 1 k 1 k Rc2 1 k 2 k 2 k 2 k Cc2 500 fF 200 fF 200 fF 300 fF Cc3 500 fF 300 fF 300 fF 300 fF M39 & M58 m = 4 m = 4 m = 6 m = 6

43

The bulk terminal of all the NMOS transistors are connected to -3V for all the tests performed. 4.1 DC analysis The DC analysis determines the symmetry and linearity of the amplier. The test-bench for DC analysis of the amplier is shown in Fig 4.1. The input is a DC voltage varied from -2mV to 2mV. To obtain the dierential input voltage, two voltage controlled voltage sources (VCVS) are used. One VCVS is with 0.5 gain and the other is with -0.5 gain. The input bias current of the amplier is 8A.

vdd Ibias
+
+ vdd

Vinegain= -0.5

Vbias Vin+
Vb2

Vout RL= 16 CL

Vin
+ +

+
+ egain= 0.5

Vr vss vss_sub

vss_sub

vss

Figure 4.1: Schematic of the DC test-bench

The simulation results obtained for a resistive load of 16- and capacitive load of 500 pF are shown in Fig 4.2 The maximum current through the NMOS and PMOS transistors of the output stage is 83.5mA. The maximum swing at the output is observed as 1.25V. 4.2 AC analysis The AC analysis determines the stability of the amplier. The test-bench for the AC analysis is shown in FIg. 4.3. Input is a 1V AC signal given at positive input terminal of the amplier. A large resistor and capacitor are used in the feedback network to provide open-loop operation. 44

1.5 1 Output Voltage (V) 0.5 0 !0.5 !1 !1.5 !2 100 80 ID, MN 60 40 20 0 !2 !1.5 !1 !0.5 0 DC Input (mV) 0.5 1 1.5 2 ID, MP MN = ON MP = ON

MN = OFF MP = ON

MN = ON MP = OFF

!1.5

!1

!0.5

0.5

1.5

Output!Stage Current (mA)

Figure 4.2: DC-analysis output

The simulation results of the LIQ design is given in Fig. 4.4. The circuit has input bias current of 8A. The open loop gain of the amplier is 48.4 dB The input bias current of the LTHD design is made 9A. The magnitude and phase plots of the design is given in Fig. 4.5. The open-loop gain of the amplier is 53.7 dB. The MIQ design is tested with a input bias current of 9A. The simulation results of the design is given in Fig. 4.6 and open-loop gain of the amplier is 50.6 dB

45

1G

vdd
+

Ibias Vin1F
+

vdd

Vbias Vin+ 1Vac Vr vss vss_sub

Vb2

Vout RL= 16 CL

vss_sub

vss

Figure 4.3: Schematic of the AC test-bench

Table 4.2: AC Simulation Results Design HCL LTHD MIQ LIQ Gain 51.5 dB 53.7 dB 50.6 dB 48.4 dB Phase Margin 72.04 70.8 70.3 70.7 Gain Margin 15.52 dB 11.5 dB 14.5 dB 16.4 dB Gain Bandwidth 1.23 MHz 2.03 MHz 1.56 MHz 1.24 MHz

The simulation results of the HCL design is given in Fig. 4.7. The circuit has input bias current of 8A.The open loop gain of the amplier is 51.5 dB The open loop gain, gain margin, phase margin and unity gain frequency of four designs are tabulated and given in Table 4.2. The gain-bandwidth product of the LTHD design is 2.03 MHz. MIQ design has the highest phase-margin among the four designs.

46

50

Gain (dB)

!50

!100 0 10 100 0 Phase (deg) !100 !200 !300 !400 0 10

10

10

10

10

10

10

10

10

10

10

10

10 Frequency (Hz)

10

10

10

10

Figure 4.4: AC output of LIQ circuit

60 40 20 Gain (dB) 0 !20 !40 !60 !80 0 10 100 0 Phase (deg) !100 !200 !300 !400 0 10 10
1

10

10

10

10

10

10

10

10

10

10

10 Frequency (Hz)

10

10

10

10

Figure 4.5: AC output of LTHD circuit

47

60 40 20 Gain (dB) 0 !20 !40 !60 !80 0 10

1 2 3 4 5 6 7 8

10

10

10

10

10

10

10

10

100 0 Phase (deg) !100 !200 !300 !400 0 10

10

10

10

10 Frequency (Hz)

10

10

10

10

Figure 4.6: AC output of MIQ design

4.3

Transient analysis The transient analysis determines the time domain response of a amplier.

A square wave of 100mV and 50kHz frequency is given at the negative input terminal. The rise time and fall time of the input is 10 nS. The amplier has a inverting gain of 4. The test-bench for transient analysis is shown in Fig. 4.8. The simulation result for LIQ is shown in Fig. 4.9. The load capacitance of the amplier is varied from 10 pF to 1.5 nF. LTHD design has no ringing at the output up-to 1 nF. The output of the amplier for dierent load capacitances is shown in Fig. 4.10.

48

60 40 20 Gain (dB) 0 !20 !40 !60 !80 0 10 100

10

10

10

10

10

10

10

10

0 Phase (deg)

!100

!200

!300

!400 0 10

10

10

10

10 Frequency (Hz)

10

10

10

10

Figure 4.7: AC output of HCL circuit

40K

vdd
+ +

Ibias 10K Vinvdd

Va=100mV Freq=50KHz

Vbias Vin+ Vr vss vss_sub

Vb2

Vout RL= 16 CL

vss_sub

vss

Figure 4.8: Schematic of the Transient test-bench

49

0.1 Input (V) 0 !0.1 5 2.5 10 15 20 25

CL = 1.5 nF

1.5

Output (V)

CL = 500 pF

0.5

CL = 10 pF

10

15 Time (S)

20

25

Figure 4.9: Transient output of LIQ circuit

0.1 Input (V) 0 !0.1 5 2.5 10 15 20 25

CL = 1 nF

1.5

Output (V)

CL = 500 pF

0.5

CL = 10 pF

10

15 Time (S)

20

25

Figure 4.10: Transient output of LTHD circuit

50

The simulation result for MIQ is shown in Fig. 4.11. The load capacitance of the amplier is varied from 10 pF to 1 nF.
0.1 Input (V) 0 !0.1 5 2.5 10 15 20 25

CL = 1 nF

1.5

Output (V)

CL = 500 pF

0.5

CL = 10 pF

10

15 Time (S)

20

25

Figure 4.11: Transient output of MIQ circuit

The load capacitance for HCL design is varied from 10 pF to 5 nF, and there was no ringing at the output. The slew-rate of the design is 1.25 V/S. The simulation result for HCL design is shown in Fig. 4.12. 4.4 THD analysis A transient analysis has been performed on the amplier to determine the total harmonic distortion. The amplier is connected in inverting gain conguration with gain 1. The input is a sine wave of 2.45VP P and frequency of 1kHz. The test-bench for the measuring THD is shown in Fig. 4.13. The input has a dead time of 10 S. The quiescent power of the amplier is determined at 5 S, when there is no input signal. The THD of designs is measured by using the THD-option of the simulator for a sample of the output signal. To 51

Input (V)

0.1 0 !0.1 5 2.5 10 15 20 25

CL = 5 nF

1.5

Output (V)

CL = 500 pF

0.5

CL = 10 pF

10

15 Time (S)

20

25

Figure 4.12: Transient output of HCL circuit

Table 4.3: Transient Simulation Results Design HCL LTHD MIQ LIQ CLOAD 10 pF - 5 nF 10 pF - 1 nF 10 pF - 1 nF 10 pF - 1.5 nF THD -77 dB -80.89 dB -78.56 dB -77.29 dB Quiescent Peak Power Power 1.77 mW 1.98 mW 1.66 mW 1.47 mW 97.6 mW 97.6 mW 97.6 mW 97.6 mW FOM 55.23 49.27 59.40 66.25

measure the THD precisely, the time step parameters have been modied. The step is given as 1 and Max. step as 1. The output waveform for measuring the THD is shown in Fig. 4.14. The THD and quiescent power measurements for four designs are shown in Table 4.3. 52

40K

vdd
+ +

Ibias 40K Vinvdd

Va=1.25V Freq=1KHz

Vbias Vin+ Vr vss vss_sub

Vb2

Vout RL= 16 CL

vss_sub

vss

Figure 4.13: Schematic for THD measurement

1.5 1 0.5 Input (V) 0 !0.5 !1 !1.5 0 1.5 1 0.5 Output (V) 0 !0.5 !1 !1.5 0

0.5

1.5

2.5

0.5

1 Time (mS)

1.5

2.5

Figure 4.14: Transient output for measuring THD

53

Chapter 5

HARDWARE TESTING

The three-stage class-AB audio amplier is fabricated in ON-SEMI 0.5m process through MOSIS. The hardware test is the real-time test for determining the functionality of the amplier. This chapter describes the layout techniques used in the design, the experimental setup used for testing and the tests performed to determine the operation of the audio amplier. 5.1 Layout The layout of four designs is implemented using the virtuso environment of Cadence. A common-centroid technique is used to attain matching between devices. The current at the output-stage is huge, hence strapping technique is used for the huge current to ow through the transistor of the output-stage. In order to avoid noise that can be coupled with bias voltage, the bias voltage Vb1 and Vb4 are shielded with substrate biasing voltage and Vb2 and Vb3 are shielded with VDD . The layout of the four designs are shown in Fig. 5.1, Fig. 5.2, Fig. 5.3 and Fig. 5.4. The designs are arranged in the frame of 40 pins. The layout of the frame with the designs is shown in Fig. 5.5 and Fig. 5.6. The micrograph of the chip is shown in Fig. 5.7. 5.2 Experimental Setup The following apparatus are used for measuring the outputs:

54

Figure 5.1: Layout of LIQ amplier

1. Oscilloscope: Hewlett Packard: 54600B: 100MHz, Digital Storage Oscilloscope. The oscilloscope is used for plotting the input and output waveforms for a transient response. 2. Function Generator: Agilent: 33120A: 15 MHz Function/Arbitary Waveform Generator. The function generator is used for generating the input signals/waveforms. 3. Digital Multimeter: Agilent: 34401A: 6 1 Digit Multimeter. 2 55

Figure 5.2: Layout of LTHD amplier

The Digital multimeter is used in this work for determining the DC voltages AC voltages and DC currents. 4. Stanford Research System: SR770 FFT Network Analyzer. The Stanford research system is used to determine the THD in the design. The DC, Transient and THD measurements are obtained using the above apparatus. The test procedure for these measurements is given in APPENDIX A. 5.3 DC Measurements The amplier is connected as a voltage follower and both input terminals of the amplier are connected to ground. The output voltage is measured using 56

Figure 5.3: Layout of MIQ amplier

the digital multimeter. Under quiescent conditions the voltage obtained at the output is oset voltage. The oset voltages of all the designs are discussed in Chapter 6. The quiescent current is measured with the digital multimeter by creating an open circuit between the VDD and the VDD pin of the chip. 5.4 Transient Measurements The test-setup for transient measurements is similar to the test-bench used in Fig. 4.8. The results obtained for each design for dierent capacitive loads are plotted using the Matlab code given in APPENDIX C.

57

Figure 5.4: Layout of HCL amplier

5.5

THD Measurements The amplier is used in inverting gain conguration with a gain of 1. A in-

put signal of 2.45VP P and 1kHz frequency is applied at the negative input terminal of the amplier. The output amplitude is measured using a digital multimeter. The output is connected to the Stanford research system (SRC) to measure the THD at the output. The SRC gives the amplitude of fundamental frequency and its harmonics. The amplitude of rst 10 harmonics for each design are shown in Fig. 5.12, Fig. 5.13, Fig. 5.14 and Fig. 5.15.

58

MIQ

LIQ

Figure 5.5: Layout of the frame with two LIQ and MIQ.

The noise oor is at -106dB. The hardware measurements for all the designs are shown in Table 5.1.

59

LTHD

HCL

Figure 5.6: Layout of the frame with two LTHD and HCL.

60

Figure 5.7: Micrograph of the chip.

61

100 Input (mV) 0 !100 0 5 10 15 20 25

2000

CL = 2 nF
1500

Output (mV)

1000

CL = 500 pF
500

CL = 10 pF

!500 0

10 Time (S)

15

20

25

Figure 5.8: Transient response of LIQ design (an oset of 900mV is added intentionally for visibility)

Input (mV)

100 0 !100 0 5 10 15 20 25

2000

CL = 750 pF
1500

Output (mV)

1000

CL = 500 pF
500

CL = 10 pF

!500 0

10 Time (S)

15

20

25

Figure 5.9: Transient response of LTHD design (an oset of 900mV is added intentionally for visibility)

62

100 Input (mV) 0 !100 0 5 10 15 20 25

2000

CL = 1 nF
1500

Output (mV)

1000

CL = 500 pF
500

CL = 10 pF

!500 0

10 Time (S)

15

20

25

Figure 5.10: Transient response of MIQ design (an oset of 900mV is added intentionally for visibility)

100 Input (mV) 0 !100 0 5 10 15 20 25

2000

CL = 5 nF
1500

Output (mV)

1000

CL = 500 pF
500

CL = 10 pF

!500 0

10 Time (S)

15

20

25

Figure 5.11: Transient response of HCL design (an oset of 900mV is added intentionally for visibility) 63

20

!20

Magnitude (dBv)

!40

!60

!80

!100

!120 0

6 Frequency (KHz)

10

12

Figure 5.12: THD measurement for LIQ design

64

20

!20

Magnitude (dBv)

!40

!60

!80

!100

!120 0

6 Frequency (KHz)

10

12

Figure 5.13: THD measurement for LTHD design

65

20

!20

Magnitude (dBv)

!40

!60

!80

!100

!120 0

6 Frequency (KHz)

10

12

Figure 5.14: THD measurement for MIQ design

66

20

!20

Magnitude (dBv)

!40

!60

!80

!100

!120 0

6 Frequency (KHz)

10

12

Figure 5.15: THD measurement for HCL design

67

Table 5.1: Hardware Measurements Design HCL Oset 1.2 mV Quiescent Current 475 A 837 A 391 A 520 A SR+ SROutput Voltage 0.885 Vrms 0.883 Vrms 0.882 Vrms 0.882 Vrms THD 11.34 m% 11.74 m% 11.85 m% 11.20 m%

1.35 V/s 1.47 V/s 1.23 V/s 1.23 V/s 1.28 V/s 1.07 V/s 1.35 V/s 1.80 V/s

LTHD 6.66 mV MIQ LIQ 2.51 mV 6.6 mV

68

Chapter 6

DISCUSSION AND CONCLUSION

A low distortion and high power eciency three-stage class-AB audio amplier was designed in 0.5 m CMOS process. The parameter dimensions in the design were varied and a trade-o between total harmonic distortion (THD) and quiescent current (IQ ) was observed. As the quiescent current in the amplier was increased, the distortion of the amplier decreased. To determine the power eciency of an amplier, a gure of merit (FOM) was dened by [1] as P eak power delivered to the load quiescent power

F OM =

(6.1)

The gure of merit for each design was measured and tabulated in Table 6.1.

Table 6.1: Summary of Hardware Test Results Peak Design Quiescent current Capacitive Load (CL ) FOM Power HCL LTHD MIQ LIQ 475 A 827 A 391 A 520 A 93.78 mW 94.54 mW 89.88 mW 93.79 mW 65.81 38.10 76.63 60.12 10 pF - 5 nF 10 pF - 750 pF 10 pF - 1 nF 10 pF - 2nF

69

The designed three-stage class-AB audio amplier (HCL) was compared with state-of-the-art. It was observed, [1] works for wide range of capacitive loads. The FOM of this work is greater than [1] by a factor of 2. Table 6.2 shows the comparison results between state-of-the-art and this work. Table 6.2: Comparison of results with state-of-the-art ([1]) Parameter [18] [19] 0.35-m CMOS 0-300 pF [20] 65-nm CMOS 0-12 nF [1] 130-nm CMOS 1 pF-22 nF This Work 0.5-m CMOS 1 pF-5 nF

Technology Capacitance Load Resistive Load Supply Output Voltage THD+N Total Compensation Capacitance Quiescent Power FOM

0-300 pF

16

16

16

16

16

3.0 V

0.8 V

2.5 V

1.2 V/2 V

3.0 V

2.5 VP P

0.45 VP P

1.85 VP P

1.60 VP P

2.45 VP P

-90 dB

-69 dB

-68 dB

-84 dB

-78.90 dB

35 pF

14 pF

14.5 pF

12.0 mW

2.5 mW

12.5 mW

1.2 mW

1.43 mW

8.1

1.3

4.3

33.3

65.6

@ Maximum Output

70

In order to attain similar results for simulation and hardware testing, the quiescent currents for all the designs in testing were made equal to the corresponding simulation results. The THD of designs observed in hardware testing were lower than their corresponding simulation results by approximately 5%. The comparison table for all four designs are shown in Table 6.3, Table 6.4, Table 6.5 and Table 6.6. Table 6.3: Simulation vs Hardware (LIQ) LIQ Parameter IQ PQ PP eak VSSSU B FOM THD Simulation Result 490 A 1.47 mV 97.6 mW -3V 66.25 -77.29 dB Testing result 490 A 1.47 mV 97.6 mW -3V 66.25 -72.63 dB

The design and hardware issues encountered while testing the amplier are discussed below: 1. As two designs were inscribed in one chip, the transistors of the output stage can generate current even without the input. This unwanted current could not be accounted when calculating the quiescent current. Hence, a switch was used to turn OFF one design while testing the other. 2. While measuring the quiescent current, an oset was observed at the output. As the load resistance is very small at the output node, a small oset 71

Table 6.4: Simulation vs Hardware (LTHD) LTHD Parameter IQ PQ PP eak VSSSU B FOM THD Simulation Result 660 A 1.98 mV 97.6 mW -3V 49.27 -80.89 dB Testing result 660 A 1.98 mV 97.6 mW -3V 49.27 -74.34 dB

Table 6.5: Simulation vs Hardware (MIQ) MIQ Parameter IQ PQ PP eak VSSSU B FOM THD Simulation Result 553 A 1.66 mV 97.6 mW -3V 58.83 -78.58 dB Testing result 556 A 1.67 mV 96.8 mW -3V 57.96 -73.76 dB

generates a current through the load. This current cannot be accounted for quiescent current calculation, hence a small voltage was applied at the input to obtain an oset of 0V. This turns OFF any current to the load. 72

Table 6.6: Simulation vs Hardware (HCL) HCL Parameter IQ PQ PP eak VSSSU B FOM THD Simulation Result 590 A 1.77 mV 97.6 mW -3V 55.23 -77 dB Testing result 590 A 1.77 mV 97.6 mW -3V 55.23 -77.15 dB

3. The THD of the output of an amplier depends on the THD of input. The input THD of the signal from the function generator was 13m% when the expected output was 13m%. Thus to attain a lower distortion at the input, a RC low-pass network was used. The chips were tested successfully by countering every issue that occurred. The designed ampliers have a Figure of Merit higher than state-of-the-art ([1]). Future work involves 1. Design modications to drive smaller resistive load (8-) headphone speakers available in the market. 2. Improvisation of the design is required to use this class-AB amplier for other applications.

73

APPENDICES

APPENDIX A HARDWARE TEST PROCEDURE

Project Name: Project Author: Submitted: Fabrication: Apparatus:

Audio Amplifier Chaitanya Mohan July 26, 2010 0.5!m AMI double-poly n-well with 3 metal layers Oscilloscope, PCB board, DMM, Function Generator, DC Voltage source Description: First stage is a fully differential folded cascode amplifier with local common mode feedback and replica biasing. A NMOS differential pair and PMOS differential pair with local common mode feedback and replica biasing forms the second stage. The third stage of the design is a common source amplifier. 3330883148, 445119 128.123.131.87

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Design 84045 status: WAITING FOR LAYOUT Design name: Audio Amplifier E-mail address: chaits@nmsu.edu Phone number: 575-405-1232 Technology: SCN3ME_SUBM, lambda = 0.3 Fabrication restricted to AMI only. Fill to be added: No This project can be fabricated on a AMI_C5F run. Layout file: not present Intended disposition: RESEARCH Requested quantity: 5 Requested packaging: DIP40 [MOSIS to generate bonding diagram] (5 parts) Maximum die size: 7620 x 7620

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Design 84045 status: IN TRANSIT Design name: Audio Amplifier E-mail address: chaits@nmsu.edu Phone number: 575-405-1232 Technology: SCN3ME_SUBM, lambda = 0.3 Fabrication restricted to AMI only. Fill to be added: No This project can be fabricated on a AMI_C5F run. Layout format: CIF Layout file: waiting for your ftp Waiting for ftp transfer of design file from host "128.123.131.87" into file "chaits_audio_amplifier.cif" within 11 h 59 min 56 s Intended disposition: RESEARCH Requested quantity: 5 Requested packaging: DIP40 [MOSIS to generate bonding diagram] (5 parts) Maximum die size: 7620 x 7620

Mosis Reply Id: 00363789 -001-001 Table 1: Pin No: 1 2 3 4 5 6 7 8 Name vss_B vss_B Vout_B Vout_B Vout_B Vdd_B Vdd_B Vdd_B Type protect protect protect protect protect protect protect protect Description -1.5V to power the circuit B -1.5V to power the circuit B Output connect to load Output connect to load Output connect to load +1.5V to power circuit B +1.5V to power circuit B +1.5V to power circuit B 77

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Vdd_B Vr_B Vb2_B Vbias_B Vin+ B Vin- B NC NC Stand-by_A Vss_sub Vss_A Vss_A Vss_A Vss_A Vout_A Vout_A Vout_A Vdd_A Vdd_A Vdd_A Vdd_A Vr_A Vb2_A Vbias_A Vin+ A Vin- A NC NC Stand-by_B Vss_sub Vss_B Vss_B

protect protect protect protect protect protect pad_vdd pad_vss protect pad_bare protect protect protect protect protect protect protect protect protect protect protect protect protect protect protect protect protect protect protect Pad_bare protect protect

+1.5V to power circuit B 0V External resistor to generate bias current External resistor to generate bias current Connect to Ground Connect to external resistors 1.5V to protect IC -3V to protect IC (Short to pin 18) 1.5V or -1.5V to turn ON/OFF circuit A -3V substrate biasing (short to pin 38) -1.5V to power the circuit A -1.5V to power the circuit A -1.5V to power the circuit A -1.5V to power the circuit A Output of circuit A Output of circuit A Output of circuit A 1.5V to power the circuit A 1.5V to power the circuit A 1.5V to power the circuit A 1.5V to power the circuit A 0V External Resistor to generate bias current External Resistor to generate bias current Connect to 0V Connected to external resistors No Connection No connection -1.5V or 1.5V to turn ON/OFF circuit B -3V substrate biasing (short to pin 18) -1.5V to power the circuit B -1.5V to power the circuit B

Suggested Test Procedure: (I) Connect pad_vdd (pin 15) to 1.5V, pad_vss (pin 16) and Vss_sub (pin 18, 38) to 3V to protect the IC. The circuit should not draw any current. (II) Electrical Testing; Circuit A Power Supplies: Vdd_A = +1.5 V, Vss_A = -1.5 V, 78

Vr = 0V (Reference voltage) The stand-by_A (pin 17) should be connected to -1.5V and stand-by_B (pin 37) to 1.5V, such that no digital inputs are floating. To power the circuit A connect VDD to pins 26,27,28,29 and VSS to pins 19,20,21 and 22. Check for excess heat dissipation and smoke. If there is smoke, then the chip is fried. Testing the Transient response 1. Put a resistor RB between pins 31 and 32. RB " 88k# 2. Measure the voltage between pins 31 and 32 using a DMM. From the figure below and the equations determine the value of RB

a. $V = ____________ ($V = Vb2-Vbias : from DMM) b. Measure the current IB through the resistor RB. IB = $V/RB = _____________ c. Adjust the value of RB to attain a current IB of 8A. Measure RB = ______________ (using DMM) Note: Internal resistance of DMM has no effect on the current as RIN || RB and RIN >> RB 3. Attach a bias resistor RB determined above between Vb2_A (pin 31) and Vbias_A (pin 32). 79

4. Short the audio amplifier outputs Vout_A (pin 23, 24 and 25). Attach one end of the 40k# resistor (R2) to the Vout_A and other end to Vin- A (pin 34). Add a 10k# resistor (R1) to Vin- A. The other end of the 10k# resistor is connected to the function generator. Measure R2 = ____________ (using DMM ; Tolerance 1%) R1 = ____________ (using DMM ; Tolerance 1%) Ratio = R2/R1 = _________ (Matching 0.2%, i.e 3.992<4<4.008) 5. Connect Vr_A (pin 30) to 0V. The positive input terminal of the amplifier Vin+ A is connected to ground. 6. Attach one end of a 16-# resistor (RL) and 500pF capacitor (CL) to the output of the amplifier Vout_A. The other end of the resistor and capacitor goes to ground. Measure RL = __________ (Tolerance 0.5%) CL = __________ (Tolerance 10%) 7. Initially ground the floating end of the 10k# resistor in step 4. Measure the current (IVDD) from the positive power supply to the circuit (pin 26, 27, 28 and 29) using DMM. IVDD = ______________ The quiescent power of the audio amplifier is PQ = IVDD * 3 = ____(Total supply voltage is vdd-vss = 1.5-(-1.5)=3V) 8. Set the function generator output to 100mV amplitude square wave signal that has a frequency of 50kHz. Remove the ground and attach this signal to the floating end of 10k# resistor in 4. 9. Use a 1x probe to connect the input to channel A of the scope. Use a 10x probe to connect the output Vout_A to channel B of the scope. The output should have a frequency equal to the input signal. The amplitude of the output signal must be 40mV because of the 10x probe. Measure the output amplitude and slew-rate. Store the input and output waveforms obtained on the scope digitally to a disk. 10. Change the load capacitance value 500pF in step 4 to 1nF and observe the output on scope. The output should be similar to that in 6. Store the obtained waveforms.

80

Output waveforms:

Test for Measuring THD of the amplifier 1. Replace the 10k# resistor (R1) attached between the function generator and Vin- A (pin 34) with 40k# resistor. Measure R1 = _________ (Using DMM; Tolerance 1%) Ratio = 0.999<1<1.001) R2/R1 = ________ (Matching 0.1%, i.e

2. Switch the load capacitance CL back to the same from step 6 (Testing Transient Response) 500pF from 1nF attached between Vout_A and ground. 3. Set the function generator output to 1.25V amplitude sine wave signal that has a frequency of 1kHz. Attach this signal to the floating end of 40k# resistor in step 1. 4. Use a 10x probe to connect the output Vout_A to scope. The output should be a sine wave that has a frequency equal to the input signal. Set the scope such that it measures the output signal amplitude in rms. Determine the amplitude of the output signal Vrms = ___________ Vout =Vrms * %2 = ___________ Store the input and output waveforms obtained on the scope digitally on a disk. 5. Compute the peak power to the load using the following equation and enter the value in the Table 2. Ppeak = Vout2/RL = ____________ 6. Follow the procedure below to set the Stanford Research System (SRS) spectrum analyzer to measure THD a. Turn ON the SRS network analyzer while holding the backspace button till it runs all the tests. 81

b. Turn ON the function generator and set the frequency and amplitude as required. Connect the function generator to channel A of the SRC network analyzer using 1x probe. c. On top right of the SRS network analyzer screen select the <span> soft-key and set its value (12.5KHz) d. Select <Auto Range> option under ENTRY. e. Under the Marker select <Max/Min>. This moves the marker to max value. f. Now set <Auto Scale> and then select <Analyze>. Use the soft keys on the right side of the screen to set fundamental frequency and Harmonics (10 harmonics). g. Select <Average> under MENU and set the <Number averages> to 100 using soft-key. h. Hit <Start> under CONTROL option to compute the average. i. The THD of the signal is displayed on the left of the screen. 7. Connect the input signal from the function generator directly to the SRS network analyzer using a 1x probe to measure the THD. THDI_IN = ___________ 8. Connect the input signal from the function generator to the input of the amplifier using a 1x probe and connect the same to SRS network analyzer and measure the THD THDIN = ___________ 9. Now connect the output of the audio amplifier to the Stanford Research System using a 1x probe. Measure the THD of the output signal. Enter this value in table 2 below to compare the result with the simulated result. THDOUT = ____________ 10. Change the load capacitance value 500pF in 2 to 1nF and observe the output on scope. The output should be similar to that in step 4. Store the output waveform obtained on the scope digitally on a disk. Output waveforms:

82

NOTE : Now turn OFF the circuit A by switching the stand-by_A (pin 17) from 1.5V to 1.5V and turn ON the circuit B by connecting -1.5V to stand-by_B (pin 37). Repeat the procedure for all the four designs and measure the output power as in 5, THD in 9 and quiescent power as in 7 (Testing the Transient response). Enter these values in the table below. Store the waveforms of all the designs digitally on a disk. Table 2 : Designs and its corresponding outputs Input Bias Quiescent Design Peak power Current power A B C D

THD

83

/,!(.2"(.!(.& !"%.'&

!"#$%& '(!!)*& +$,$%-./",& 01/!&

!!!!! !!!!!!!!!Figure 2: Test setup of the chip

APPENDIX B POLE/ZERO ANALYSIS USING MAPLE

collect solve

Vout K Voutn gm1$Vin Voutp ,K C C Ic2 1 2 R1 Rc1 C s$Cc1 2$Voutpp C Ic3 C Ic4 = 0, gm2$ Voutp K Voutn C C Voutpp$s$2$ C2 = Ic4 C Ic5, R2 gm2$ Voutp K Voutn 2
= C

gm1$Vin Voutn C = Ic1, Ic1 = 2 R1

Voutnp C Voutnp$s$C2 = Ic3 C Ic6, Ic2 = Ic5 C Ic6, Ic2 R2

Voutp K Vx , Ic5 = Vx K Voutpp $s$Cc2, Ic6 = Vx K Voutnp $s$Cc2, Ic4 = Voutp Rc2 Vout K Voutpp $s$2$Cc3, Ic3 = Voutp K Voutnp $s$Cc3, gm3$Voutpp C gm3$Voutnp C Rout
C Vout$s$Cout C Ic1 = 0 , Vout, Voutp, Voutn, Voutnp, Voutpp, Vx, Ic1, Ic2, Ic3, Ic4, Ic5, Ic6 ,

s = 0, Vout = gm1 R1 Rout gm3 gm2 R2

(1)

solve

2 gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 4 wp1 = , wp1$wp2 = , gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 Coefficient of S2

wp1 =

(2)

wp1, wp2

2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 2 solve wp1 = , wp2 gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 4 = , wp1$wp2$wp3 = , Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 Coefficient of S3

wp2 =

(3)

wp1, wp2, wp3

2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 R1 R2 C2 6 gm3 Rout Cc3 C 4 gm3 Rout Cc2 C 2 Cc2 C 3 Cc3

wp3 =

(4)

86

solve

2 , wp2 gm2 R1 R2 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 2 Cc2 C 2 gm3 Rout Cc1 C 3 Cc3 = , wp3 Cc1 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 2 gm3 Rout R2 C2 C 2 R1 Cc2 C 3 R1 Cc3 = , wp1$wp2$wp3$wp4 R1 R2 C2 6 gm3 Rout Cc3 C 4 gm3 Rout Cc2 C 2 Cc2 C 3 Cc3 4 = , wp1, wp2, wp3, wp4 4 Coefficient of S

wp1 =

wp4 =

gm2 2 gm3 Rout C 1 Cout Rout gm2 C 2 C2

(5)

solve

solve

8 gm3 gm2 R2 wz1 = K , wz1 K 4 gm3 Cc1 gm2 R2 R1 K 8 gm3 gm2 R2 2 C2 2 wz1 = Cc1 R1 C 2 R2 C2 2 8 gm3 gm2 R2 wz1 = , wz1$wz2 =K , wz1, wz2 Cc1 R1 C 2 R2 C2 Coefficient of S2

(6)

solve

1 2 C (7) R2 C2 Cc1 R1 2 1 2 8 gm3 gm2 R2 wz1 = , wz2 = C , wz1$wz2$wz3 =K , 3 Cc1 R1 C 2 R2 C2 R2 C2 Cc1 R1 Coefficient of S

wz2 =

wz1, wz2, wz3

1 gm2 wz3 = K 2 Cc3

(8)

87

APPENDIX C MATLAB CODE TO PLOT WAVEFORMS

To plot THD of all Circuits: LIQ

1 2 3 4 5 6 7 8 9 10
clc; clear all; close all; a1 = csvread(CKT-A); plot (a1(:,1)/1000,a1(:,2),b); axis ([0 12.5 -120 20]) xlabel(Frequency (KHz)); ylabel(Magnitude (dBv)); grid on;

LTHD
1 2 3 4 5 6 7 8 9 10
clc; clear all; close all; a1 = csvread(CKT-B); plot (a1(:,1)/1000,a1(:,2),k); axis ([0 12.5 -120 20]) xlabel(Frequency (KHz)); ylabel(Magnitude (dBv)); grid on;

MIQ
1 2 3 4 5 6 7 8 9 10
clc; clear all; close all; a1 = csvread(CKT-C); plot (a1(:,1)/1000,a1(:,2),k); axis ([0 12.5 -120 20]) xlabel(Frequency (KHz)); ylabel(Magnitude (dBv)); grid on;

89

HCL
1 2 3 4 5 6 7 8 9 10
clc; clear all; close all; a1 = csvread(CKT-D); plot (a1(:,1)/1000,a1(:,2)-13.974,r); axis ([0 12.5 -120 20]) xlabel(Frequency (KHz)); ylabel(Magnitude (dBv)); grid on;

Code to plot Transient Results

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
clc; clear all; close all;

q = 25; H = 0:q/999:q; H1 = transpose(H); a1=csvread(84046/CKT_D/input/input1.csv); a2=csvread(84046/CKT_D/input/input2.csv); a3=csvread(84046/CKT_D/input/input3.csv); a4=csvread(84046/CKT_D/input/input4.csv); a5=csvread(84046/CKT_D/input/input5.csv); a6=csvread(84046/CKT_D/input/input6.csv); a7=csvread(84046/CKT_D/input/input7.csv); a8=csvread(84046/CKT_D/input/input8.csv); a9=csvread(84046/CKT_D/input/input9.csv); a10=csvread(84046/CKT_D/input/input10.csv); a11=csvread(84046/CKT_D/input/input11.csv); a12=csvread(84046/CKT_D/input/input12.csv); a13=csvread(84046/CKT_D/input/input13.csv); a14=csvread(84046/CKT_D/input/input14.csv); a15=csvread(84046/CKT_D/input/input15.csv); a16=csvread(84046/CKT_D/input/input16.csv);

a(:,1)=(a1(:,1)+a2(:,1)+a3(:,1)+a4(:,1)+a5(:,1)+a6(:,1)+a7(:,1)+a8(:,1) +a9(:,1)+a10(:,1)+a11(:,1)+a12(:,1)+a13(:,1)+a14(:,1)+a15(:,1) +a16(:,1))/(16); a(:,1)=(a(:,1)*0.8)*1000;

b1=csvread(84045/CKT_A/single_pulse_10pF/output1.csv);

90

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

b2=csvread(84045/CKT_A/single_pulse_10pF/output2.csv); b3=csvread(84045/CKT_A/single_pulse_10pF/output3.csv); b4=csvread(84045/CKT_A/single_pulse_10pF/output4.csv); b5=csvread(84045/CKT_A/single_pulse_10pF/output5.csv); b6=csvread(84045/CKT_A/single_pulse_10pF/output6.csv); b7=csvread(84045/CKT_A/single_pulse_10pF/output7.csv); b8=csvread(84045/CKT_A/single_pulse_10pF/output8.csv); b9=csvread(84045/CKT_A/single_pulse_10pF/output9.csv); b10=csvread(84045/CKT_A/single_pulse_10pF/output10.csv); b11=csvread(84045/CKT_A/single_pulse_10pF/output11.csv); b12=csvread(84045/CKT_A/single_pulse_10pF/output12.csv); b13=csvread(84045/CKT_A/single_pulse_10pF/output13.csv); b14=csvread(84045/CKT_A/single_pulse_10pF/output14.csv); b15=csvread(84045/CKT_A/single_pulse_10pF/output15.csv); b16=csvread(84045/CKT_A/single_pulse_10pF/output16.csv);

b(:,1)=(b1(:,1)+b2(:,1)+b3(:,1)+b4(:,1)+b5(:,1)+b6(:,1)+b7(:,1) +b8(:,1)+b9(:,1)+b10(:,1)+b11(:,1)+b12(:,1)+b13(:,1)+b14(:,1) +b15(:,1)+b16(:,1))/(16); b(:,1)=(b(:,1)*0.8)*1000;

c1=csvread(84045/CKT_A/single_pulse_500pF/output1.csv); c2=csvread(84045/CKT_A/single_pulse_500pF/output2.csv); c3=csvread(84045/CKT_A/single_pulse_500pF/output3.csv); c4=csvread(84045/CKT_A/single_pulse_500pF/output4.csv); c5=csvread(84045/CKT_A/single_pulse_500pF/output5.csv); c6=csvread(84045/CKT_A/single_pulse_500pF/output6.csv); c7=csvread(84045/CKT_A/single_pulse_500pF/output7.csv); c8=csvread(84045/CKT_A/single_pulse_500pF/output8.csv); c9=csvread(84045/CKT_A/single_pulse_500pF/output9.csv); c10=csvread(84045/CKT_A/single_pulse_500pF/output10.csv); c11=csvread(84045/CKT_A/single_pulse_500pF/output11.csv); c12=csvread(84045/CKT_A/single_pulse_500pF/output12.csv); c13=csvread(84045/CKT_A/single_pulse_500pF/output13.csv); c14=csvread(84045/CKT_A/single_pulse_500pF/output14.csv); c15=csvread(84045/CKT_A/single_pulse_500pF/output15.csv); c16=csvread(84045/CKT_A/single_pulse_500pF/output16.csv);

c(:,1)=(c1(:,1)+c2(:,1)+c3(:,1)+c4(:,1)+c5(:,1)+c6(:,1)+c7(:,1)+c8(:,1) +c9(:,1)+c10(:,1)+c11(:,1)+c12(:,1)+c13(:,1)+c14(:,1)+c15(:,1) +c16(:,1))/(16); c(:,1)=(c(:,1)*0.8)*1000;

e1=csvread(84045/CKT_A/single_pulse_2nF/output1.csv); e2=csvread(84045/CKT_A/single_pulse_2nF/output2.csv);

91

86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119

e3=csvread(84045/CKT_A/single_pulse_2nF/output3.csv); e4=csvread(84045/CKT_A/single_pulse_2nF/output4.csv); e5=csvread(84045/CKT_A/single_pulse_2nF/output5.csv); e6=csvread(84045/CKT_A/single_pulse_2nF/output6.csv); e7=csvread(84045/CKT_A/single_pulse_2nF/output7.csv); e8=csvread(84045/CKT_A/single_pulse_2nF/output8.csv); e9=csvread(84045/CKT_A/single_pulse_2nF/output9.csv); e10=csvread(84045/CKT_A/single_pulse_2nF/output10.csv); e11=csvread(84045/CKT_A/single_pulse_2nF/output11.csv); e12=csvread(84045/CKT_A/single_pulse_2nF/output12.csv); e13=csvread(84045/CKT_A/single_pulse_2nF/output13.csv); e14=csvread(84045/CKT_A/single_pulse_2nF/output14.csv); e15=csvread(84045/CKT_A/single_pulse_2nF/output15.csv); e16=csvread(84045/CKT_A/single_pulse_2nF/output16.csv);

e(:,1)=(e1(:,1)+e2(:,1)+e3(:,1)+e4(:,1)+e5(:,1)+e6(:,1)+e7(:,1) +e8(:,1)+e9(:,1)+e10(:,1)+e11(:,1)+e12(:,1)+e13(:,1)+e14(:,1) +e15(:,1)+e16(:,1))/(16); e(:,1)=(e(:,1)*0.8)*1000;

subplot(2,1,1); plot(H1(:,1),a(:,1),k); axis([0 25 -125 125]); ylabel(Input (mV)); grid on; subplot(2,1,2); plot(H1(:,1),b(:,1),b,H1(:,1),c(:,1)+900,g,H1(:,1),e(:,1)+1800,r); axis([0 25 -500 2300]); xlabel(Time (\muS)); ylabel(Output (mV)); grid on;

92

Code to Simulation Results: DC Plots

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
clc; clear all; close all; a1 = csvread(DC_A.csv); subplot (2,1,1); hold on; plot (a1(:,1)*1000,a1(:,4),k); ylabel (Output Voltage (V)); grid on; subplot (2,1,2); plot (a1(:,1)*1000,a1(:,2)*1000,r); axis([-2 2 -10 100]); hold on plot (a1(:,1)*1000,a1(:,3)*1000,b); axis([-2 2 -10 100]); xlabel(DC Input (mV)); ylabel(Output-Stage Current (mA)); grid on;

AC Plots
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
clc; clear all; close all; a1 = csvread(AC_A.csv); subplot (2,1,1); semilogx (a1(:,1),a1(:,2),k); axis([1 10^8 -100 60]); grid on; ylabel(Gain (dB)); subplot (2,1,2); semilogx (a1(:,1),a1(:,3),k); axis([1 10^8 -400 100]); xlabel(Frequency (Hz)); ylabel(Phase (deg)); grid on;

93

THD Plots
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
clc; clear all; close all; a1 = csvread(THD.csv); subplot (2,1,1); plot (a1(:,1),a1(:,2),k); %axis([1 10^8 -100 60]); grid on; ylabel(Input); subplot (2,1,2); plot (a1(:,1),a1(:,3),k); %axis([1 10^8 -400 100]); xlabel(Time); ylabel(Output); grid on;

Transient Plots
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
clc; clear all; close all; a1 = csvread(TR_A_10pf.csv); a1(:,1)=(a1(:,1)*1000000); a2 = csvread(TR_A_500pf.csv); a2(:,1)=(a2(:,1)*1000000); a3 = csvread(TR_A_1_5nf.csv); a3(:,1)=(a3(:,1)*1000000); subplot (2,1,1); plot (a1(:,1),a1(:,3),k); axis([5 25 -0.15 0.15]); grid on; ylabel(Input (V)); subplot (2,1,2); plot(a1(:,1),a1(:,2),b,a2(:,1),a2(:,2)+0.9,g,a3(:,1),a3(:,2)+1.8,r); axis([5 25 -0.45 2.5]); xlabel(Time (\muS)); ylabel(Output (V)); grid on;

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