5 Nickel

Memristor Materials Engineering:
From Flash Replacement Towards a Universal Memory
Janice Nickel Hewlett Packard Laboratories, nanoElectronic Research Group IEDM Advanced Memory Technology Workshop 4 December 201 1
Copyright 2011 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.
Outline
Memory and HP Introduction to memristors Challenges facing realization of memristor memory Engineering solutions CMOS compatible fabricated memristors Alternate Emerging Memories comparison The Team
2 Copyright 2011 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.
HP Confidential and Restricted Distribution Internal Use Only.
Why memory?
Whats in it for HP?
HPs needs
Reliable supply of scalable memory technology
FLASH scalability is approaching its limit

Control of charge placement deteriorates with reduced oxide thickness Multi-level cells have low realistic endurance Relying on Through Silicon Vias to increase capacity
DRAM is fast approaching theirs

Control of trench widths deteriorates with depth DRAM architectures and circuitry are adapted to 25 fF cell capacitance Shrinking geometries threaten industry ability to maintain 25fF Taller cell capacitor <32 nm: 50:1 aspect ratio / / Thinner cell dielectric < 3 Angstroms
Currently no physical mechanism to create such large trenches with such high precision
Replacement Technology
Considerations
CMOS compatibility Materials Yield Non-volatility Speed Latency Bandwidth Endurance Retention Operating Temperature Forming Cell size Die Size Energy Device non-linearity
Cost
Access Device Idle Power
Fabrication
Performance
Considerations
CMOS compatibility Materials Yield Non-volatility Speed
Utilize current infrastructure Compatible w/ Si technology >95 % per mask
Latency Bandwidth Endurance
Cost
Limits scalability
10 Years 95*C
Retention Operating Temperature
Forming Cell size Die Size Energy Device non-linearity
Considerations
CMOS compatibility Materials Yield
Yes R: W: 25 ms 200ms < 20-50 s
Non-volatility Speed Latency Bandwidth Endurance Retention Operating Temperature Forming Energy
Cost
$1/Gbyte Yes 1 mW/Gb 4-6 F2 64 Gbit
FLASH
10,000 pJ/op
> 25 Mb/s ~ 105 cycles years Burn in
Cell size Die Size
Device non-linearity
Enables true crossbar structures
Why are memristors candidate replacements?
Does not require transistors or other access devices Removes Silicon requirement Stack arrays on top of each other: cell sizes < 4F2 Improve density Reduce power consumption Integrate with compute processors Reduce total area
Feature size = Litho node F
Cell Size = 4 F2 P Pitch = 2F for cross bars
HP memristor opportunities
RAM Flash Hard Disk Optical disk Floppy Disk
Memristor CHIP DEVELOPMENT FLASH REPLACEMENT SOLID STATE DISK DRAM REPLACEMENT UNIVERSAL MEMORY NEURAL COMPUTING
TIME
WE ARE HERE
Introduction
What is a Memristor?
The Memristor:
Fourth Fundamental Two Terminal Circuit Element

Leon Chua U.C. Berkeley v q i
Predicted
d/dt = v
v Ohm 1827 i
dq /dt = i
RESISTOR dv = R di
CAPACITOR dq = C dv q
Von Kleist 1745
1831 Faraday
INDUCTOR d = L di
MEMRISTOR d = M dq
1971 Chua
The Memristor:
Dynamical Non-Linear Behavior
Fundamentally Different
Generalized Memristor (Memristive system):
v = M ( w, i )i
dw = f ( w, i ) dt
L. Chua and S. M. Kang, Proceedings of the IEEE, Vol. 64, No. 2, February 1976
The Memristor:
Reduced to Practice in 2008
Found
R. Stanley Williams HP Laboratories

D. B. Strukov, et al., vol 453, 1 May 2008, doi:10.1038/nature06932
What makes a memristor fundamental?

Inability to duplicate properties with the other passive circuit elements
CURRENT VOLTAGE
RESISTOR
CURRENT
CAPACITOR
dv = R di
dq = C dv
INDUCTOR
CURRENT
MEMRISTOR
d = L di
d = M dq
VOLTAGE
14 Copyright 2011 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. 14
VOLTAGE
What exactly is it?
Cross-bar device with multivalent oxide

Top Electrode (TE)
..
Switching Layer Multi-Valent Oxide
Bottom Electrode (BE)
BE
Nano-devices 1x17
TE
oxide
How does it work?
Semiconducting Bipolar Switch
Oxygen Vacancies
TiO2 highly resistive TiO2 region a conductive TiO2-x region specific electrodes
contains positively charged O+ vacancies
Under positive bias voltage: O vacancies drift to the BE Narrows the tunneling gap Reduces resistance.
Under negative bias voltage: O vacancies to drift to the TE Increases tunneling gap Increases resistance
Previously: Now:
Fixed semiconductor structure and only electronic motion Ionic motion dynamically modulates the semiconductor structure controlling the electronic current.
Memristor Challenges and Solutions

Controlling the system through device engineering
Considerations
CMOS compatibility Materials Yield Non-volatility Speed Latency Bandwidth Endurance Retention Operating Temperature Forming Cell size Array Size Energy Device non-linearity
Cost
Access Device Power
Current (mA)
Creating Oxygen Vacancies

Pt Pt TiO2
Electroforming
0.2 0.1 0
forming 1st ON switching 1st OFF switching
0.1 Device Voltage (V)
Vacancies formed by: rip O2 from TiO2 evolve O2 gas

+ V on TE
O2 gas disappears as voltage is removed

+ V removed
Physical Damage occurs when Creating Vacancies by Electroforming
+V O O2- 2O2O2TiO2 -V
Bubbles appear with application of +V
Bubbles disappeared immediately when the +V is removed
Some small permanent deformations remain
Electroforming
Physical Mechanism
Ti4O7 diffraction
Rings show known Pt and Anatase polycrystalline diffraction Remaining diffraction peaks correspond to Ti4O7 Magneli phase, Room temperature metallic suboxide of TiO2!!
J.P. Strachan et al., Advanced Materials, Volume: 22, Issue: 32, Pages: 3573-3577
Experimental Observation of Magneli Phase
Electroforming
-D. H. Kwon et. al, Nature Nanotechnology, 17 Jan 2010
Eliminating electroforming
Engineer Vacancy Reservoir into Device

1.5 1 Current (mA) TiO2 Ti4O7 Pt Pt 0.5 0 1st ON switching Forming 1st OFF switching
4nm TiO2/35 nm Ti4O7
0.5 1
1.5 1.0 0.5 0 0.5 Device Voltage (V)
Eliminating electroforming
AFM images before and after forming
Pt Pt TiO2
forming
TiO2 Ti4O7 Pt
Pt
forming
Endurance
A History
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
Pt Pt TiO2
Endurance (cycles)
Requires electro-forming
2008
2009
2010 Year
2011
2012
Nanotechnology 22 (201 1) 254026
Endurance
A History
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
TiO2 Ti4O7 Pt Pt
Endurance (cycles)
No electro-forming Unstable states
2008
2009
2010 Year
2011
2012
Appl. Phys. Lett. 97, 232102 (2010)
Endurance
A History
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
Pt Pt TaOx
Endurance (cycles)
Requires electro-forming
2008
2009
2010 Year
2011
2012
Endurance
A History
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
Ta Pt
Ta2O5
Endurance (cycles)
No electro-forming Stable states
2008
2009
2010 Year
2011
2012
Appl. Phys. Lett. 97, 232102 (2010);
Endurance
A History
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
Ta2O5-x TaO2 Pt Pt
Endurance (cycles)
SAIT results
HP Labs results
2008
2009
2010 Year
2011
2012
Myong-Jae Lee et al., nature materials, doi:10.1038
Endurance
A Future
1015 1014 1013 1012 1011 1010 109 108 107 106 105 104 103
DRAM consumer replacement
Endurance (cycles)
SAIT results
HP Labs results
2008
2009
2010 Year
2011
2012
Endurance
a) 10
Resistance (ohm)
4
An Understanding
Ti 1nm /Pt 100nm/TiOx 29nm/Ti4O7 100nm 3
10
Resistance (ohm)
103
Ron Roff
Ron Roff
102 100
10
10
10
10 10 10 switching cycles
102
2.0x109 4.0x109 6.0x109 8.0x109 1.0x1010 1.2x1010
switching cycles
Ta
TiO2 Ti4O7 Pt
Pt Pt
Ta2O5

Endurance
10
6
An Understanding
TiOx
)
Resistance(Ohm)
104
TaOx
Resistance (Ohm)
105 104 103 102 -4 -3 -2 -1 0 1 Voltage (V) 2 3
103
102 -4 -3 -2 -1 0 1 Voltage (V) 2 3
TiO2 Ti4O7 Pt
Pt Pt
Ta
Ta2O5

Endurance
106 TiOx
An Understanding
Resistance (Ohm)
Magnelli Phases
105 104 103 102 -4 -3 -2 -1 0 1 Voltage (V) 2 3
Ti
4
TiO2
Resistance (ohm)
TiO2 Ti4O7 Pt
Pt
a) 10
Ti 1nm /Pt 100nm/TiOx 29nm/Ti4O7 100nm
103
Ron Roff
32
TinO2n-1 channel 101 multiple states Copyright 2011 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice.
102 100
102
103
Endurance
)
Resistance(Ohm)
104 TaOx
An Understanding
103
102 -4 -3 -2 -1 0 1 Voltage (V) 2 3

g y
Ti 1nm /Pt 100nm/TaOx 12nm/Ta 100nm
Ta Pt
Ta2O5
b)
Resistance (ohm)
103
Ron Roff
Ta (O) channel in equilibrium
102 0 10
101
102
103
107
108
109
Understanding Mechanisms Results in Device Improvements

Electroforming Requires large voltages not compatible w/ CMOS Physically damages devices Results in low yield Reduces the endurance of the device Improved by systematic understanding of the system Moores law improvement in endurance ~102.5 /year Fast approaching endurance usable for consumer DRAM replacement Understanding of materials properties and physical mechanisms essential to improving device properties
Materials and Device Engineering
Endurance
Considerations
CMOS compatibility Materials Yield Non-volatility Speed Latency Bandwidth Endurance Retention Operating Temperature Forming Cell size Array Size Energy Device non-linearity
Cost
Access Device Power
Device Non-Linearity
Pt 100 nm /12 nm TaOx /Ta 100 nm
0.4
Ta Pt
Ta2O5
Current (mA)
ON OFF
--0.4 --0.8
-0.8
-0.4
Voltage (V)
0.4
Pt 35nm /Ti4O7/4 nm TaOx /Pt
Current (mA)
1 0 -1 -1
Ti4O7 TaOx Pt
Ta
Voltage (V)
Current Sneak Paths

Half Select Problem
Cross bar challenges

Current Sneak Paths
+ Sense amps
threshold
0 or 1

Current Sneak Paths
+ Sense amps
threshold
0 or 1

Current Sneak Paths
+ Sense amps
threshold
0 or 1

Current Sneak Paths
+ Sense amps
threshold
0 or 1

Current Sneak Paths
Current ON OFF
Voltage
V
+ + Sense amps threshold

0 or 1

Current Sneak Paths
ON Current OFF
Voltage
V
+ + Sense amps threshold

0 or 1
Understanding Mechanisms Results in Device Improvements

Device Nonlinearity Negate the need for an access device Reduce current requirement Increase the possible array size Enable integration of memristors with processors Enable increased density by stacking layers
Materials and Device Engineering
CMOS compatible fabricated memristors

300 mm wafer fabrication at 130 nm node
CMOS compatibility
Fabrication Friendly Materials and Processes
M2 Via Bit M1
Current (mA)
0.5 0.0 -0.5
Reset Set
-0.8
TiO2 Ti4O7 TiN
TiN
1ST 300 mm wafer produced by HP Utilizes industry standard processes and materials Independently defined working memristor bits
Device Voltage (V)
-0.4
0.0
0.4
Memristor vs. Other Emerging Technologies
How does it stand up as a memory?
Dynamical and Non-Linear Enables True Cross-point
Memristor Density (F2) Energy per bit (pJ) Read time (ns) Write time (ns) Retention Endurance (cycles) 4 0.13 <10 ~20* years >1012
PCM 816 227 2070 50500 years 107
STTRAM 1464 0.1 1030 1395 weeks? 1015
DRAM 610 2 1050 1050 <<second 1016
Flash 46 10000 25000 200000 years 103 - 106
HDD 2/3 110x109 58x106 58x106 years 1015
* 0.2 nm switching in laboratory devices observed
Memristor as a Candidate FLASH replacement

Meets or Beats FLASH on all fronts
CMOS compatibility
Yield
Cost
Access Device
Idle Power
FLASH
Materials Speed Latency Forming Cell size Energy Size Device non-linearity
Nonvolatility
Bandwidth Endurance
Retention
Operating Temperature
HP memristor opportunities
RAM Flash Hard Disk Optical disk Floppy Disk
Memristor CHIP DEVELOPMENT FLASH REPLACEMENT SOLID STATE DISK DRAM REPLACEMENT UNIVERSAL MEMORY NEURAL COMPUTING
TIME
WE ARE HERE
The Team
nanoElectronics Research Group
Thank you
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Memristor Materials Engineering:

From Flash Replacement Towards a Universal Memory

HP Confidential and Restricted Distribution Internal Use Only.

Reliable supply of scalable memory technology

FLASH scalability is approaching its limit

DRAM is fast approaching theirs

Access Device Idle Power

Latency Bandwidth Endurance

Access Device Idle Power

Retention Operating Temperature

Forming Cell size Die Size Energy Device non-linearity

$1/Gbyte Yes 1 mW/Gb 4-6 F2 64 Gbit

Access Device Idle Power

> 25 Mb/s ~ 105 cycles years Burn in

Cell size Die Size

Enables true crossbar structures

Why are memristors candidate replacements?

Feature size = Litho node F

Cell Size = 4 F2 P Pitch = 2F for cross bars

RAM Flash Hard Disk Optical disk Floppy Disk

Fourth Fundamental Two Terminal Circuit Element

Von Kleist 1745

Dynamical Non-Linear Behavior

Generalized Memristor (Memristive system):

Reduced to Practice in 2008

R. Stanley Williams HP Laboratories

What makes a memristor fundamental?

What exactly is it?

Cross-bar device with multivalent oxide

Switching Layer Multi-Valent Oxide

Bottom Electrode (BE)

How does it work?

Semiconducting Bipolar Switch

Memristor Challenges and Solutions

Access Device Power

Creating Oxygen Vacancies

forming 1st ON switching 1st OFF switching

0.1 Device Voltage (V)

Vacancies formed by: rip O2 from TiO2 evolve O2 gas

O2 gas disappears as voltage is removed

Physical Damage occurs when Creating Vacancies by Electroforming

Bubbles appear with application of +V

Bubbles disappeared immediately when the +V is removed

Some small permanent deformations remain

Experimental Observation of Magneli Phase

-D. H. Kwon et. al, Nature Nanotechnology, 17 Jan 2010

Engineer Vacancy Reservoir into Device

4nm TiO2/35 nm Ti4O7

1.5 1.0 0.5 0 0.5 Device Voltage (V)

AFM images before and after forming

Nanotechnology 22 (201 1) 254026

No electro-forming Unstable states

Appl. Phys. Lett. 97, 232102 (2010)

No electro-forming Stable states

Appl. Phys. Lett. 97, 232102 (2010);

No electro-forming Stable states

DRAM consumer replacement

2.0x109 4.0x109 6.0x109 8.0x109 1.0x1010 1.2x1010