SHIRDI SAI ENGINEERING COLLEGE

SHIRDI SAI ENGINEERING COLLEGE

SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE
f
I
I
r =
0)
'0
Z
;:
l
t
o
c.
E
~~~~
~~~l l l It5
USN
EC835
Eighth Semester B.E. Degr ee Examination, December 2010
Embedded System Design
Time: 3 hr s. Max. Mar ks: 100
Note: 1.Answer any FIVEfull questions.
2. Standard notations are used.
3. Missing data may be suitably assumed.
1 a. Whatar ethe char acter istics of anembedded systemdesign? Listthe design metr ics used to
compar e them. (07Mar ks)
b. Deter mine ther evenue l oss, if thepr oduct's l ifetime is74 weeks and thedel ay inthemar ket
is6weeks. Der ive thefor mul a used for thecal cul ation. (07Mar ks)
c. For apar ticul ar pr oduct, deter mine theNRE costand unitcostto be the fol l owing for the
thr eel isted IC technol ogies:
FPGA ($10000, $50): ASIC ($50000, $10)
VLSI ($200000, $5)
Deter mine thepr ecise vol umes for which eachtechnol ogy yiel ds thel owesttotal cost.
(06 Mar ks)
2 a. Devel op an efficient al gor ithm for GCD. Conver t itto FSMD and show the optimized
FSMD. (10Mar ks)
b. Withaneatdiagr am, expl ain thear chitectur e of agener al pur pose pr ocessor . (10Mar ks)
3 a. Define thefol l owing: (04 Mar ks)
i) Cr oss compil er ii) Emul ator iii) Debugger iv) Incir cuitsimul ator
b. Differ entiate between:
i) Singl e pur pose and gener al pur pose pr ocessor s
ii) Har var d and von-Neumann ar chitectur e (06 Mar ks)
c. With a neat diagr am, expl ain how the pul se width modul ator wor ks. What ar e the
consider ations in sel ecting the cl ock, the pr escal ar and the counter ? Assuming an 8-bitup
counter , cal cul ate the countto be l oaded in the 'cycl e-high' r egister to getpul ses of duty
cycl e75%. (10Mar ks)
4 a. Given an anal og inputsignal whose vol tage r anges fr om 0 to 5 v and an 8-bitdigital
encoding, cal cul ate the cor r ect encoding for 3.5 v and then tr ace the successive
appr oximation appr oach tofind thecor r ectencoding. (08Mar ks)
b. Whatiscachemapping? Expl ain thedir ectmapping techniques for cache. (08Mar ks)
c. Expl ain theter ms wr iteabil ity and stor ageper manence. (04Mar ks)
5 a. Expl ain two l evel mul ti busar chitectur e, withaneatdiagr am. (06 Mar ks)
b. Compose l Kx 8ROMs into2K x 16ROM. (06Mar ks)
c. Given the fol l owing thr ee cache designs, find the one with the bestper for mance, by
cal cul ating theaver age costof access. Show al l cal cul ations.
i) 4K byte, 8-way-setassociative cache, with a6% miss r ate; cache hitcosts onecycl e,
cache miss costs 12cycl es
ii) 8K byte, 4-way-set associative cache with a4% miss r ate; cache hitcosts 2cycl es,
cache miss costs 12cycl es
iii) 16K byte, 2-way-set associative cache with a2% miss r ate; cache hitcosts 3cycl es,
cache miss costs 12cycl es. (08 Mar ks)
10f2
SHIRDI SAI ENGG COLLEGE
6 a.
b.
c.
7 a.
b.
c.
8 a.
b.
c.
d.
...
EC835~
Whatisinter r uptl atency? Whatar ethefactor s affecting it? (08Mar ks)
Expl ain withanexampl e, how theRound-Robin ar chitectur e wor ks. When isitnotsuitabl e?
(08 Mar ks)
Whatisar eentr antfunction? Givethethr eer ul es todecide r eentr antfunctions. (04Mar ks)
Whatissemaphor e? Expl ain RTOS semaphor e. (10Mar ks)
Differ entiate between har d and softRTOS highl ighting theadvantages and disadvantages of
~h. ~~~
Expl ain 'deadl y embr ace'. (04 Mar ks)
Whatisanevent? Givethr eestandar d featur es of anevent. (05 Mar ks)
Giveacompar ison of methods for inter task communication. (04 Mar ks)
Expl ain thetwo r ul es, thattheinter r uptr outines mustfol l ow, inRTOS envir onment. Whatis
theeffectof bl ocking oninter r upts? Expl ain withadiagr am. (08 Mar ks)
Expl ain ther ol eoftimer function inRTOS. (03Mar ks)
* * * * *
20f2
SHIRDI SAI ENGG COLLEGE
Eighth Semester B.E. Degree Examination, May/June 2010
Embedded System Design
Note: Answer any FIVE full questions, selecting
. at least TWO questions from each part.
1 a.
b.
c.
2 a.
b.
c.
3 a.
b.
c.
Mention thecharacteristics and briefly list thedesign metrics of anembedded system.
(08 Marks)
Determine thepercentage of revenue loss if theproducts lifetime is 86 weeks and thedelay
inthemarket is8weeks. Derive theformula used for this calculation. (06 Marks)
Explain how thetop-down design process improves theproductivity. (06 Marks)
Briefly explain thepurpose of thedatapathand controller inasingle purpose processor.
(06 Marks)
Write anefficient algorithm for finding theGCD of two integer numbers. Also explain how
theFSMD for this canbeoptimized. (08 Marks)
Explain various addressing modes that arecommonly used byprocessors, withanexample.
(06 Marks)
Explain how DART isused for communication. List its advantages. (08 Marks)
What is awatch dog timer? List its uses. A 16 bit timer operates at a clock frequency of
12MHz. Determine theresolution and rangeof this timer. .. (06 Marks)
The analog input range for a8-bit ADC isfrom-2.5V to 8.5V. Determine theresolution of
ADC and digital output in hexadecimal, when the input voltage is 1.2V. Trace successive
approximation steps and show thebinary output of theADC. (06 Marks)
4 a. What is memory hierarchy? How does the cache operate? Discuss the cache mapping
techniques. List their merits and demerits. (10 Marks)
b. Briefly explain OTPROM, EEPROM, RDRAM and FPM DRAM. (10Marks)
5 a. Explain theneed for interrupts inprocessors and mention briefly thevarious events that take
placewhen aprocessor isinterrupted. (10Marks)
b. Explain the problems of shared-data interrupts and suggest the solution to solve the
problems. (10Marks)
6 a. Explain with anexample, how theRound-Robin architecture works. What is its limitation?
(12Marks)
b. List the characteristics of four software architectures available for building embedded
software. (08 Marks)
a. Mention the two rules of interrupt routines in an RTOS environment. With an example,
briefly explain, what happens when eachruleisviolated. (15 Marks)
b. Describe theuseof message queues. (05 Marks)
a. What ismeant byencapsulating thesemaphores? Bring out theneed for it.
b. Explain any six problems of semaphores.
c. Explain themethods tosolvememory spaceand methods tosavepower.
(08 Marks)
(06 Marks)
(06 Marks)
SHIRDI SAI ENGG COLLEGE
Eighth Semester B.E. Degree Examination, May/June 2010
Embedded System Design
o
()
'~ Note: Answer any FIVEfull questions.
0-
g 1 a. Define an Embedded system. Explain any three important characteristics of an embedded
~ system. (06Marks)
'E b. What is a Watchdog Timer? Why it is so called? Explain its role in the design of any
C < i
~ embedded system. (06Marks)
<I i Q)
~.D c. Determine the percentage revenue loss if theproduct lifetime is 74 weeks and thedelay in
oj=:
~'~ themarket is 6weeks. Derive theformula used. (08Marks)
6
::c'; 2 a. Explain theconcept of 'datapath' as applied toan embedded system. Give an example.
en
,5 '!f (06Marks)
,~~ b. Explain the role of a Finite State Machine (FSM) model in the design of an embedded
~~ system using a suitable example. (06Marks)
.s ~ c. Assume an 8bit encoding of input voltage in the range -5V to+5V. C alculate theencoding
'~ for 1,2V and trace the successive approximation approach to find the correct encoding.
,~ What is theresolution of theconversion? (08Marks)
:;.~
1350 Explain the steps involved in designing ageneral purpose processor. (06Marks)
ti Q)
OJ 0 Explain theconcept ofPWM speed control circuit as applied toan embedded system.
:; (06Marks)
enc
:6 ~ Define thefollowing: i) Assembler ii) C ross compiler iii) Emulator iv) Simulator.
~.8 (08Marks)
~. 2
~ ~ Differentiate between: i) PSRAM and NVRAM ii) SRAM and DRAM
' .8 iii) FLASH and EPROM. (06Marks)
</} -
]. [ Briefly describe theprinciples used in three replacement policies normally employed during
- cachememory operation. (06Marks)
() 0
i, In a hierarchy design of memory, the cache miss rate is 15%, cost of memory access is 20
Q) - -
~~ cycles and cost of cache access is 2 cycles. Determine theaverage cost of access. (08Marks)
; ~ Show an interface of2kx16ROM from lkx8ROM. Explain thedecoding logic used.
>-. '+-< (06Marks)
en
o
.~r Explain the features of the following bus architecture : i) C AN bus ii) IEEE - 802.11.
0. ~ (06Marks)
~ What is multi - level bus architecture? Explain its need and also thereasons toimprove the
<5 t processor performance by this architecture. (08Marks)
3 a.
b.
c.
4 a.
b.
c.
5 a.
b.
c.
a. What is interrupt latency? Explain thefactors affecting it.
b. Describe Round Robin architecture with an example.
c. Define semaphore and critical sections as applied to real time operating system.
a. Describe the function of ascheduler with asuitable transition diagram.
b. Explain theuseof message queues with an example.
c. Explain therole of timer function in RTOS.
a. Discuss briefly Hard Real time scheduling considerations.
b. What is meant by encapsulating asemaphores? Mention its applications.
c. Write abrief note on: i) Deadly Embrace ii) Priority Inversion.
(06Marks)
(06Marks)
(08Marks)
(06Marks)
(06Marks)
(08Marks)
(06Marks)
(06Marks)
(08Marks)
SHIRDI SAI ENGG COLLEGE




SHIRDI SAI ENGG COLLEGE

SHIRDI SAI ENGG COLLEGE
SHIRDI SAI ENGG COLLEGE