USMAN INSTITUTE OF TECHNOLOGY

HAMDARD UNIVERSITY

DEPARTMENT OF ELECTRICAL ENGINEERING


VLSI DESIGN (EE-411)
SPRING-2014

Engr. Zohaib Jawaid
Engr. Kashif Ali Arshad
Engr. S. Aimen Naseem
Engr. Sameer Ahmed





EXPERIMENT # 02: Introduction to Gate level Modeling in Verilog



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GATELEVELMODELINGINVERILOG
Each Verilog model is of a particular "level." The level of a model depends on statements and
constructs it contains. The levels of Verilog models are:
Gate (Predefined primitives are directly used in codes such as and, or)
Data Flow (It describes the design in terms of expressions instead of primitive gates.
Expressions, operators, and operands form the basis of dataflow modeling.)
Behavioral (It describe design functionality in an algorithmic manner)
Verilog supports basic logic gates as predefined primitives. They can be instantiated like
modules and do not need a module definition.
Two classes of basic gates in Verilog
And/or gates
Buf/not gates

AND/OR GATES
Have one scalar output and multiple scalar inputs.
The first terminal in the port list is connected to the output and other terminals are to
inputs
The output is evaluated as soon as one of the inputs changes
The and/or gates available in Verilog
and, or, xor, nand, nor, xnor

BUF/NOT GATES
Have one scalar output and one scalar input
The last terminal in the port list is connected to the input and other terminals are to
outputs
Two basic buff/not gates primitives in Verilog buff and not.











Example-: 2 input AND Gate

VERILOG CODE

module AND(out,in1,in2);
input in1,in2;
output out;

and g1(out,in1,in2);
endmodule

TEST BENCH



LABTASK
1) Write the verilog gate level module for OR, NOR, NAND, XOR and XNOR Gates and
verify its output using test bench and waveforms. Also implement these gates on trainer.


module test_and;

reg a,b;
wire out1;

AND test_and1(a,b,out1); // call the module AND.
initial begin // apply the stimulus, test data
a=0; b=0; // initial value
#100 a=0; b=1; // 100ns delay, then change a=1.
#100 a=1; b=0;
#100 a=1; b=1;
end