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Data Flow M
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VERILOG
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Zohaib Jawa
Kashif Ali Ar
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Sameer Ahm
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DATA FLOW MODELING IN VERILOG:

For small circuits, the gate-level modeling approach works very well because the number of
gates is limited and the designer can instantiate and connects every gate individually. Also, gate-
level modeling is very intuitive to a designer with a basic knowledge of digital logic design.
However, in complex designs the number of gates is very large. Thus, designers can design more
effectively if they concentrate on implementing the function at a level of abstraction higher than
gate level. Dataflow modeling provides a powerful way to implement a design. VERILOG
allows a circuit to be de- signed in terms of the data flow between registers and how a design
processes data rather than instantiation of individual gates. With gate densities on chips
increasing rapidly, dataflow modeling has assumed great importance. No longer can companies
devote engineering resources to handcrafting entire designs with gates.

Assign

A continuous assignment is the most basic statement in dataflow modeling, used to drive a value
onto a net. This assignment replaces gates in the description of the circuit and describes the
circuit at a higher level of abstraction. The assignment statement starts with the keyword assign.
The left hand side of an assignment must always be a scalar or vector net or a
concatenation of scalar and vector nets.
The operands on the right-hand side can be registers or nets or function calls. Registers or
nets can be scalars or vectors.
wire i1, i2;
assign out =i1 & i2;
Dataflow modeling describes the design in terms of expressions instead of primitive gates.
Expressions, operators, and operands form the basis of dataflow modeling.

Operators
Operators act on the operands to produce desired results. VERILOG provides various types of
operators. VERILOG HDL operators can be divided into several groups.
Operator Description
+- ! ~ Unary
* / % Arithmetic
+- (binary) Binary
<<>> Shift
<<=>=> Relational
==!====!== Equality
& ~& AND NAND
^~^^~ XOR XNOR
| ~| or nor
&& Logical and
|| Logical or
?: Conditional operator
Logical operators

The logical operators are used to connect expressions.


Reduction operators
The reduction operator produces a 1-bit result. This result is calculated by recursively applying
bit-wise operation on all bits of the operand. At each step of this recursive calculation the logical
bit-wise operation is performed on the result of a previous operation and on the next bit of the
operand. The operation is repeated for all bits of the operand.
Equality operators
The equality operators are used to compare expressions. If a comparison fails, then the result will
be 0, otherwise it will be 1.
If both operands of logical equality (==) or logical inequality (!=) contain unknown (x) or a high-
impedance (z) value, then the result of comparison will be unknown (x). Otherwise it will be true
or false.
If operands of case equality (===) or case inequality (!==) contain unknown (x) or a high-
impedance (z) value, then the result will be calculated bit by bit.
Arithmetic operators
The arithmetic operators can be used with all data types.
Operator Description
a + b a plus b
a - b a minus b
a * b a multiply by b
a / b a divide by b
a % b a modulo b






Operator Description
a & b a and b
a | b a or b
~ a not a
Relational operators
The relational operators are used to compare expressions. The value returned by the relational
operators is 0 if the expression evaluates to false and 1 if expression evaluates to true.
Operator Description
a < b a less than b
a > b a greater than b
a <= b a less than or equal to b
a => b a greater than or equal to b

Bit-wise operators
The bit-wise operators calculate each bit of results by evaluating the logical expression on a pair
of corresponding operand bits.
& 0 1 x z
0 0 0 0 0
1 0 1 x x
x 0 x x x
z 0 x x x
EXAMPLE:

Consider the example of a XOR logic function z=xy+xy through dataflow modeling the
VERILOG code will be:-
module lab4(z,x,y);
input x,y;
output z;
assign z=(~x&y)|(x&~y);
endmodule
LAB TASK:-
Write the VERILOG data flow module for AND, OR, NAND, NOR and XNOR Gates and verify
its output using test bench and waveforms. Also implement these gates on trainer.