Silicon-Nanowire MOSFETs

B. Yang, K. D. Buddharaju, S. H. G. Teo, J. Fu, N. Singh, G. Q. Lo, and D. L. Kwong

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), 11 Science Park Road,
Singapore Science Park II, Singapore 117685
Corresponding Author: N. Singh, navab@ime.a-star.edu.sg; Phone: (+65) 6770-5710

Abstract We present vertical Gate-All-Around (GAA)
silicon nanowire transistors on bulk silicon wafer utilizing
fully CMOS compatible technology. High aspect ratio (up
to 50:1) vertical nanowires with diameter down to ~ 20
nm are achieved from lithography and dry-etch defined
Si-pillars with subsequent oxidation. The surrounding
gate length is controlled using etch back of the sacrificial
oxide. n- and p-MOS devices thus fabricated with gate
length ~ 120 nm to 150 nm showed excellent transistor
characteristics with large drive current per wire, high
I
on
/I
off
ratio (~ 10
7
), good subthreshold slope (~ 80mV/
dec) and low DIBL (~ 20mV/ V). Along with good
electrical characteristics, the use of low cost bulk wafers,
and simple gate definition process steps could make this
device a suitable candidate for next generation technology
nodes.

I. INTRODUCTION
Gate-allaround (GAA) nanowire FET has attracted much
attention for better electrostatic control as compared to other
gate designs such as double or tri-gated transistors [1-3]. The
scaling of lateral nanowire devices however seems limited by
process related issues; it is challenging to obtain small channel
lengths out of relatively long nanowires and thus resulting in
devices with high extension resistance. Defining uniform gate
is another challenge as the shadowing effects in plasma
etching may not allow clearing the gate stringer beneath the
lateral non-gated regions. In this regard, vertical GAA
nanowire transistors are anticipated to be promising candidates
while still leveraging on conventional CMOS fabrication
techniques [4]. Vertical GAA transistor has the potential to
combine good performance with high device density [5]. The
application of vertical transistors in memory devices is
especially sought after, not only because of its potential in
shrinking individual devices, but also for its capability of
multilevel memory structures 3-dimensionally [6,7].
Most proposed vertical transistor structures [6-9] utilize
thick pillars. The patterning of small dots for making
nanowires is challenging due to high background transmission
in the mask. Lifting of the tiny dots during rinse process can
also be a serious problem. Therefore, the direct patterning and
etch process cannot result in vertical nanowire structure with
good yield. Non-lithographic methods such as vapor-liquid-
solid (VLS) mechanism and molecular beam epitaxy can
produce very thin nanowires [10-11]. However nanowires thus
produced are randomly distributed and complicated processes
are required to assemble them into functional devices [11-13].
In this study, we utilize the reduced oxidation rate of
silicon at high concave curvature surface [14-15] to produce
robust nanowires using bulk silicon wafers. Lithographically
patterned vertical Si-pillars are partially oxidized not only to
reduce the diameter of the pillars to desirable size, but also to
create a small footing that stabilizes the nanowire formed.
This technique provides a flexible approach in making ultra-
narrow vertical silicon nanowires of different diameters. With
these nanowires, we developed the top-down approach to
make GAA vertical nanowire transistors. N- and PMOS
Transistors with gate length down to 150 nm, determined by
etch back of the sacrificial oxide layer, are demonstrated.
II. NANOWIRE FORMATION AND DEVICE
FABRICATION
The schematics of the fabrication process steps are shown
in Figs. 1 (a-h). Circular resist dots of different diameters
(from 160nm to 600nm) were patterned on the 8 bulk Si
wafer followed by 1m deep Si etch with SF
6
chemistry under
SiN hard mask. Pillars were then oxidized at 1150C to
convert into nanowires. High temperature was used to
decrease the viscosity of grown oxide, ensuring smooth
cylindrical Si core at the center of the pillar. The oxidation rate
at the bottom of the pillar was low due to increased stress at
high curvature [20, 21], as a result smoothly controlled Si
footing is formed after oxidation. The grown oxide was then
stripped in DHF. The SEM image of dense and isolated
nanowire thus fabricated are shown in Fig. 2(a), (b) and (c)
respectively.
After vertical nanowire formation, a 250 nm thick layer of
HDP oxide was deposited, followed by wet etch-back using
dilute HF (1:25). The HDP deposition resulted in thicker oxide
on the bottom surface and thinner oxide along the nanowire
side walls due to the non-conformal deposition. After wet
etch-back ~ 150 nm thick oxide remains to cover the footing
of the vertical standing wire. This technique separates the gate
electrode from the source extension pad and thus reduces the
gate to source fringing capacitance. Gate oxide of ~5 nm was
then thermally grown on the exposed wire surface, followed
by deposition of 30 nm poly-Si, which serves as the gate
CMOS Compatible Gate-All-Around Vertical
978-1-4244-2364-4/08/$25.00 2008 IEEE. 318
electrode. Gate pad was then patterned and etched under resist
mask which covers the nanowire and provide a poly extension
for gate contact as shown in Fig. 3 (a). After gate pad etching,
the process of HDP oxide deposition followed by wet etch
back was repeated to access the poly on top of nanowire while
protecting the gate pad defined earlier. The exposed poly-Si
was then isotropically etched by low RF power SF
6
plasma.
The oxide on the wafer was then completely stripped in DHF
(Fig. 3(b)) and As (1 10
15
cm
-2
/ 10keV) for NMOS and BF
2

(1 10
15
cm
-2
/ 10keV) for PMOS was implanted at separate
wafers four times from four directions, 90 degrees apart, with
large tilt angle (45 degree), It was followed by a rapid thermal
annealing and standard metallization process. Shown in Fig. 3
(c) is the TEM image taken at the side wall of a large vertical
pillar illustrating the oxide thickness which is about 70 . The
large pillar for the TEM was selected as nanowire could not be
cut.
III. RESULTS AND DISCUSSION
Vertical surround gate n-MOSFET of various diameters
ranging from ~ 20 nm to 450 nm are characterized first. Fig. 4
shows the typical characteristic from devices with diameter
~25 nm. Device display very good performance with fast turn-
on (SS~ 75- 100 mV/dec), strong gate electrostatic control
(extremely low DIBL (10~50 mV/V)) and high I
on
/I
off
ratio
(~10
7
). The I
d
-V
d
curves in both S/D polarities (substrate side
of the wire or top of the wire as source) are compared with
different gate voltages (Fig 5). Interestingly, the drain current
is about 30% larger when the substrate side of the wire serves
as the drain, illustrating the asymmetrical nature of the device.
This asymmetry could be due to shadowing effect of the gate
during As-implant resulting in relatively low doping in
nanowire extension on the bottom side. The vertical doping
just after nanowire formation can help in eliminating such
asymmetry.
For a fully depleted cylindrical GAA transistor the SS and
DIBL depend on the scaling factor = L
eff
/2, where L
eff
is the
effective gate length and the natural length of the transistors
defined as [16]:
ox
si ox
si
ox
si
si
t
t
t
t

16
)
2
1 ln( 2
2 2
+ +
=

where,
si
and
ox
are the dielectric constants of silicon and
silicon oxide respectively; t
si
and t
ox
are the diameter of the
nanowire/pillar and thickness of the gate dielectric
respectively. The simulated results [16] show an exponential
increase of SS and DIBL with decreasing scaling parameter .
Our experimental results on the impact of nanowire diameter
on SS and DIBL are plotted in Fig 6, which qualitatively
agrees with the reported simulation [16]. The inability to do a
more quantitative analysis is partly due to the nature of device
structure in which direct inline metrology could not be
implemented and also the determination of physical
parameters of the device is challenging from TEM. Besides
accurate channel length measurement where expected typical
variation is up to 20 nm across the wafer, the geometry of the
channel can play a part as the nanowires have an overall
tapering geometry (Fig. 2). Though our gate excludes most of
the footing of the pillar, the channel width for most devices is
still non-uniform. This is equivalent to multiple channels
connected in series, which renders a single diameter device
analysis insufficient in characterizing the channel.
Shown in Fig 7 is the typical PMOS transfer characteristic
from devices with diameter ~40nm and gate length of
~120nm. The SS and DIBL are ~85mV/dec and 25mV/V
respectively, while the on-off ratio is ~10
7
. The performance
of p-MOS seems comparable to n-MOS.
IV. CONCLUSION
We presented a CMOS-compatible fabrication method for
nano-scale vertical GAA silicon nanowire transistor with
good device performance. Our method is simple and flexible
for further scaling of transistor devices. The measurement
results are found qualitatively in agreement with the
simulation based on semi-classical theory, which suggests
that further reduction of channel diameter improves the
performance. An improved fabrication technology currently
under development will allow us to quantitatively analyze the
carrier mobility, SS and DIBL with different device
parameters.
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Fig.1: Process flow for pillar and transistor formation: (a) Si pillar formed by dry etch with SiN hardmask (b) and high
temperature oxidation trim. (c) A spacer layer of HDP oxide was formed by deposition followed by wet etchback. (d)
Polysilicon gate deposition and (e) Gate patterning followed by HDP Oxide deposition; (f) Removal of top oxide and top
polysilicon to expose the drain; (g) Implantation to form source and drain junction; (h) Metal contact formation.



Fig.2: Tilted view SEM image of ~ 20 nm thick, 1 m tall vertical nanowires: (a) dense array at a pitch of 500 nm, (b)
higher magnification image of dense array shown in (a); (c) Isolated single vertical nanowire with diameter ~20nm, out of
which the transistor is made.

320

(a) (b) (c) (a) (b) (c)

Fig.3: Tilted view SEM images: (a) after gate patterning; the silicon pillar is wrapped in polysilicon gate (notice the space
between the gate and wafer substrate as a result of HDP filling to reduce parasitics); (b) the drain (tip) is exposed after
polysilicon etching; (d) . TEM image of a nearby wider pillar, showing oxide thickness ~70A.


Fig 4: I
d
-V
g
curve, the threshold voltages at V
d
= 1.2V and
V
d
= 0.05V are -0.25V and -0.23V respectively; the gate
length is ~150nm



Fig 5: I
d
-V
d
curve of the same device; each pair of curves
contains I
d
-V
d
of the same gate voltage. The upper curve is
obtained when the nanowire tip serves as the source, while
the lower curve is obtained when the nanowire tip serves as
the drain

.
Fig 6: Dependence of DIBL and Subthreshold slope (SS)
on nanowire diameter. In total, about 30 devices were
measured and the error bar is estimated by the spread of the
data. There are variations of gate lengths (up to +/- 20nm)
of devices with same channel diameters.

Fig 7: I
d
-V
g
curve of PMOS, the threshold voltages at V
d
=
1.2V and V
d
= 0.05V are 0.43V and 0.4V respectively; the
gate length is ~120nm


321