IMEC 2011

Nanoelectronics
and
More-than-Moore
at IMEC
M. Heyns
IMEC Fellow
IMEC 2011
Cost scaling
Improved performance
IMEC 2011

Node-to-Node Transistor scaling requires:
50% area reduction
25% performance increase @ scaled V
dd

20% power reduction
Repeats every 2-3 years

3
IMEC 2011
10
1
1990 1995 2000 2005
0.35 um
0.25 um
0.18 um
90nm
Moores law & transistor scaling
Lithography Enabled Scaling
2002-2003
~ 90 nm
4
IMEC 2011
Lord Rayleigh
k
1
factor
Exposure wavelength ()
436nm : g-line
365nm : i-line
248nm : Deep-UV (KrF)
193nm : Deep-UV (ArF)
157nm : Vacuum UV (F2)
13.5nm: Extreme UV (EUV)
Projection lens NA

Dry lithography : 0.93
Immersion lithography : 1.35

EUV lithography: 0.25 0.32NA
Low k
1
lithography (k1 0.25)
Resolution enhancement techniques,
process control.
NA
Wavelength
Rayleigh equation defines litho roadmap
NA
k resolution

.
1

5
IMEC 2011
CRITICAL ISSUES: source power, masks and resists
What is EUV lithography ?
The EUV radiation (13.5nm) is strongly absorbed by all known
materials and gases. As a consequence:
The optics must be reflective and
fully contained in vacuum
The reticle must be reflective too,
and no pellicle can be used to keep
the possible defects out of focus.
All mirrors (including the reticle) use an alternating
stack of Mo/Si layers with a theoretical maximum
reflectivity (under normal incidence) of only 74%.
Keeping the mirror count to a minimum is a priority.
Lots of EUV intensity is lost (high power is needed).

Absorber
Buffer
Low thermal expansion
substrate
Absorber
Buffer
Multilayer
Low thermal expansion
substrate
Absorber
Buffer
Multilayer of
Mo and Si
7
IMEC 2011
Good process window for 28nm L/S
Good photo speed and good resist profiles
14.8mJ/cm
2
LES = 15nm
12.4mJ/cm
2
LER = 4.2nm
11.8mJ/cm
2
Local CDU: 1.2nm
EUV performance
28nm L/S
30nm IL 32nm LES 32nm CH
8
IMEC 2011
EUV extendability
Self-aligned double patterning
30 nm L/S 15 nm L/S
9
IMEC 2011
10
1
1990 1995 2000 2005
0.35 um
0.25 um
0.18 um
90nm 65nm 45nm
Moores law & transistor scaling
~ 16 - 14 nm ~ 90 nm
Materials Enabled Scaling
Lithography Enabled Scaling
10
IMEC 2011
MOSFET
SiN Passivation
LOCOS
Ion implant
Plasma Etch
i-line Steppers
LDD
Silicide
KrF scanners
CMP
Ext / HALO
Cu metal
ArF scanners
SiON
Spike RTA
Channel strain
USJ co-I/I
Immersion litho
GL: HK / MG
70 80 90 00 60
HK / MG
Multi-Gate
SMO
TSV
EUV scanner
FBRAM
Super-HK
VFET
III-V channel
Mask-less
Air-gap
RRAM
3D-NAND
TANOS
SAM
HTFET
CNT
Graphene
SystemCircuitTechno
10
Technology complexity increases
Many options still to be researched
Combination of new materials & architectures
System/Circuit-level implications
Research challenges
11
IMEC 2011 12
IMEC 2011

1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
0.5 1 1.5 2 2.5 3
EOT (nm)
J
G


@


(
V
G
-
V
T
)

=

1
V


(
A
/
c
m
2
)SiO2, RTO/ISSG
ISSG/RTO + RPN
ISSG + DPN
V
d
Si substrate
source
drain
GATE
V
g
Gate dielectric
Gate
leakage
Gate oxide leakage or tunneling current
As oxide thins down leakage increases
exponentially
Need new materials and/or new architectures !
Device power
From switch to dimmer
13
IMEC 2011
IEDM 2003, W.Tsai et al, IMEC
Solution new materials
e.g. high-K dielectric
Device power
How to tackle the problem?
Year
1
10
100
1000
1980 1985 1990 1995 2000 2005 2010
A
t
o
m
i
c

L
a
y
e
r
s

~ 90 Layers
3 Layers
SiO
2
SiON

~ 5 nm

2020
Constant Capacitance Density
C =
0

SiO2
/t
SiO2 =

0

hk
/t
hk

t
high-k
=
hk
/
SiO2
* t
SiO2
1 nm

(schematic)
High-k

Direct tunneling
Oxides < 3nm
14
IMEC 2011


High-k / metal gate
Gate First High-k/Metal Gate
Gate Last High-k/Metal Gate
La-cap
High k High k
Metal
Gate
Metal
Gate
pMOS
nMOS
Al-cap
4 6 8 10 12 14 16
4.0
4.2
4.4
4.6
4.8
5.0
5.2








E
W
F

(
e
V
)

EOT ()
N-EWF
P-EWF
RMG
uncapped high-k dielectric
La-cap (n-EWF)
AlO-cap (p-EWF)
GF
15
IMEC 2011
V
d
Si substrate
source
drain
GATE
V
g
Gate dielectric
Sub-V
T

leakage
Subthreshold leakage
Short channel forms no effective barrier
Threshold voltage not scaling as fast
as V
DD
Device power
From switch to dimmer
Need new materials and/or new architectures !

tunneling
BTB
E
VB
E
CB
emission
Thermionic
QM



tunneling



Drain Source
L
gate
S
u
m

=

I
o
f
f

C
h
a
n
n
e
l

l
e
a
k
a
g
e


16
IMEC 2011
-200
-150
-100
-50
0
50
100
150
200
20 40 60 80 100
L
g
(nm)
D
I
B
L

(
m
V
/
V
)
Wfin = 17 nm
Wfin = 14 nm
Wfin = 10 nm
Wfin = 6 nm
Wfin < 5 nm
nMOS
pMOS
Solution New Architecture
e.g., Fully Depleted Devices
for better short-channel control
Fully depleted devices





17
IMEC 2011 19
IMEC 2011
L=35nm
SiGe
L=35nm L=35nm
SiGe
strain
USJ
silicide
90-65-45
32-22/20
FUSI
Gate-first
Gate-last
FinFET
time
22/20-15
Strain,
USJ (F,C co-implant, )
Performance
(power x delay)
Multi-gate
High-k, Metal Gate
11-7
Ge/III-V, VFET, TFET,
NW, Graphene
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Ge/IIIV
nanowires
Tunnel FET
VFET
Graphene
>130
Device scaling roadmap
20
IMEC 2011


Strain engineering and high-mobility channels

Si

Ge

GaAs

InAs
1600

3900

9200

40000
430

3900

400

500
Hole
mobility
(cm
2
/Vs)
Electron
mobility
(cm
2
/Vs)
IFQW SiGe 45%
+ epi S/D booster 25%
REF IFQW
SiGe 45%

0 200 400 600 800 1000
10
-6
10
-4
10
-2
10
0


W=10um, V
DD
=-1V
I
o
f
f
_
d
r
a
i
n

@

V
G
=
0
V

(
u
A
/
u
m
)

Ion @ VG=-1V (uA/um)
I
ON
=1mA/um
Device performance
21
10 100 1000
0
50
100
150
200
250
300
REF. SiGe-45% with implants
REF. IFQW SiGe 45%
IFQW SiGe 45% + eSiGe
W=10um
V
DD
= -20mV / -1V
D
I
B
L

[
m
V
/
V
]
LG_physical [nm]


IMEC 2011


Strain engineering and high-mobility channels

Si

Ge

GaAs

InAs
1600

3900

9200

40000
430

3900

400

500
Hole
mobility
(cm
2
/Vs)
Electron
mobility
(cm
2
/Vs)
IFQW SiGe 45%
+ epi S/D booster 25%
REF IFQW
SiGe 45%

0 200 400 600 800 1000
10
-6
10
-4
10
-2
10
0


W=10um, V
DD
=-1V
I
o
f
f
_
d
r
a
i
n

@

V
G
=
0
V

(
u
A
/
u
m
)

Ion @ VG=-1V (uA/um)
I
ON
=1mA/um
Device performance


22
IMEC 2011
Key Characteristics
ART (Aspect-Ratio-Trapping) with InP-on-Si buffer
MOCVD 8 Epi (AIXTRON), with raised (n+)-InGaAs S/D
InP
Si
Ge
Gate
N+ InGaAs
Cu
W Plug
InGaAs channel
STI
Selective (in STI trenches) III/V QW MOSFET
1
st
functional transistor characteristics !
Work on-going for further improvement in buffer defectivity and doping (insulation)
0
200
400
600
-3 0 3
I
d
(

A
/

m
)
V
gs
(V)
L
g
= 0.13 m
V
ds
= 1V
I
on
= 565 A/m
-3 0 3
V
gs
(V)
600



400



200



0
I
d

(
m
A
/
m
m
)

Si
STI
InP
InAlAs
InGaAs
S
D
Defects trapped at trench edges
ART
(Aspect Ratio Trapping)
Gate
~
2
5
0
-
3
0
0
n
m

23
IMEC 2011
1. Selective growth of (Si)Ge and/or III/V in STI trenches
2. High-k gate stack for low EOT
3. Self-aligned doped raised S/D for contacts
4. Further strain engineering for mobility boost












Strained (Si)Ge or III/V QW Strained InGaAs QW
Si substrate

IF-QW p
with high-k gate
IF-QW n
with high-k gate
Ge
Si CMOS
High mobility channel materials
Co-integration with standard Si CMOS
High Performance CMOS
24
IMEC 2011
p QW FET

SI-InP(001)
AlSb
GaSb
AlSb
InAs(Be)
GaSb
Buffer
Band alignment of
GaSb AlSb InAs
1.58
0.73
0.36
E
g
InP(001) substrate
Buffer
QW
AlSb
InAs
GaSb
AlSb
GaSb
AlSb
InAs
Y. Zhang et al., J. Appl. Phys. (2010)
High hole mobility for III-Sb p-channel
InSb followed by GaSb has the largest hole
mobility compared to Ge, InGaAs and GaAs
Optimized structural stack quality
The AlSb interfacial layer plays a key role
in the growth of high quality QW stack

25
IMEC 2011
III/V & Ge
channels
2003
(2007)
45nm
2005
(2009)
32nm
2007
(2011)
22nm
2009
(2013)
15nm
2011
(2015)
11nm
2013
(2017)
7nm
2015
(2019)
5nm
Node
Year
(in production)
G
a
t
e

s
t
a
c
k

E
l
e
c
t
r
o
s
t
a
t
i
c

c
o
n
t
r
o
l

T
r
a
n
s
p
o
r
t

e
n
h
a
n
c
e
d

Poly
SiON
Si-subst.
stressors
bulk
gate
Hard
mask
16nm
fin
40nm gate
Hard
mask
16nm
fin
40nm gate
oxide
Si-substrate
Fin
Multi-gate
MG
High-k
III/V ch.
Si-subst.
MG
High-k
Si substrate
MG
High-k
Si substrate
MG
High-k
Si-subst.
Whats next ?
?
26
IMEC 2011
Heterojunction TFET boosts the ON current by
increasing the source tunneling efficiency by using
low bandgap material in the source
Ge
E
c
E
v
~ 4 nm
In-Ga-As
E
c
E
v
~ 4 nm
HTFET schematic view
Tunnel-FET basic idea: use the band-to-band tunneling in p-i-n device as an
energy filter to overcome the 60mV/decade subthreshold slope limitation
ON/OFF switching determined by band-to-band tunneling at source side
Exploratory devices: TunnelFETs
27
E
F
E
F
0 1
0 1
V
g
a
t
e

p

i


n
n

i


p
InAs-source
(In
0.6
Ga
0.4
As)
p-TFET
: silicon
: germanium
: indium-arsenide
Ge-source
n-TFET
IMEC 2011
Extensive modeling effort to calibrate tunneling efficiency (using P-i-N diodes)
Enable exploration of new device concepts
Integration of demonstrators (vertical & horizontal) in progress
Exploratory devices: TunnelFETs
drain

source
SiGe source
Vertical Planar or Finfet Hybrid
Si
Ge III-V
ox
E
max
10
6
V/cm E
max
3 10
6
V/cm
28
IMEC 2011
The pinch-off nanowire MOSFET
A junctionless device

Negative gate voltage will push the majority carriers
(electrons) to the middle of the wire. For sufficient
negative gate voltage the channel is pinched off.
No source and drain needed
Bulk (volume) transport vs interface transport
Difference in charge density leads to difference in transport type DIBL (nPOFET) DIBL (nMOSFET) 177 mV/V
SS ( nPOFET) SS (nMOSFET) 60 mV/dec
30
IMEC 2011
~1x1 cm
2
die w/TaN markers
E-beam lithography
Liftoff metallisation
O
2
plasma etching
SiO
2
Si
metal
SiO
2
Si
metal
graphene
C
x
H
y
1200 1500 1800 2100 2400 2700


Raman shift [cm
-1
]
20 mm
20 mm
in collaboration with Panasonic


Integration of CVD graphene

31
IMEC 2011
CMP Metallization
Catalyst Dep.

Structure
13 nm
CNT growth
D
shell
=1.510
12
cm
-2
;

d
CNT
=8 nm

300 nm
CNT bundle
After
encapsulation
and CMP
Particle free area
TiN substrate
Chiodarelli N. et al., J. Electrochem Soc, 157 (10) (2010)
CNT Growth Encapsulation
Integration of CNTs in interconnects

Demonstration of CNT interconnects in VIAs and contacts
32
IMEC 2011
DRAM Capacitor scaling: EOT and physical thickness scaling at target
leakage current
Source: Qimonda
DRAM scaling challenges
New high-k dielectrics with k > 100 and noble metal electrodes with
large WF required to enable DRAM scaling below 20 nm node
33
IMEC 2011
FG
Channel
Gate
Floating Gate scaling: cell interference and coupling ratio (CR) reduction are
the major issues when scaling and planarizing the floating gate (FG) Flash
memory cell
Source: Micron
FLASH scaling challenges
High-k dielectrics for Inter Poly Dielectric to increase CR & FG stack
engineering required to enable Flash scaling below 20 nm
35
IMEC 2011


10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
0.0001
0.001
-2.5 -2 -1.5 -1 -0.5 0
V
FG
(V)
L
g
=55nm
V
DS
=1.5V
V
BG
=2.5V
Program
Window
( 0.7V )
'0' State
'1' State
Holding State
Sense Margin
(4~5 orders)
Trigger Voltage
(V
Tr
)
Temp=25C
Trigger Point
WL1
Si
WL2
V
DS
=1.5v demonstrated with
double wordline cell architecture
FBRAM
2010
37


3D- FLASH
Bottom Implant
Anneal
Si-substrate
n
+
Implant
1
ONO etch
Undoped Si deposition
C
h
a
n
n
e
l
Drain
BOTOX
CG
TOPOX
O
N
O
+
S
i
Si-substrate
n
+
4
Bottom Junction anneal
Top Junction Implant
Activation anneal
5
BOT
Junction
T O P
J u n c t i o n
S
i
l
c
o
r
e
T
u
n
n
e
l

O
X
N
i
t
r
i
d
e
B
l
o
c
k
i
n
g

O
X
CG
2
CG stack
Memory Hole etch
BOTOX
TOPOX
Si-substrate
n
+
3
O
N
O

+

S
i
ONO + Silcore
Deposition
(a) (b)
-2
-1
0
1
2
3
4
5
6
1 10 100 1000 10
4
program
erase
V
t h
s
h
i f
t
(
V
)
Number of P/E cycles
-2
-1
0
1
2
3
4
5
10
0
10
1
10
2
10
3
10
4
10
5
10
6
25C
200C
V
t
h

s
h
i
f
t

(
V
)
Time (s)
10k cycles and retention on
22nm Si diameter demonstrated


1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TiN: 9 nm 3:1 STO
TiN: 0.5 nmTiO2 - 9 nm 3:1 STO
TiN: 0.5 nmTiO2 - 8 nm 3:1 STO
Series14
Series20
Series22
Series24
Series28
Series27
Series29
Series31
JG @ +1V
JG @ +1V
Series5
Series3
Series1
EOT [nm]
J
G
[
A
/
c
m
2
]
1V
TiN/STO/TiN
Oct 09
RuOx/STO/TiN
62% Sr-rich STO
0.5 or 1 nm TiO
2
RuOx
Best in class EOT/Jg with
IMECs engineered stack
DRAM
2010


Applying TDDB know how to
RRAM filament formation
RRAM
2010
Memory program: some achievements
37
IMEC 2011
Materials Enabled Scaling
Lithography Enabled Scaling
~ 16-14 nm
3D Enabled Scaling
Moores law & transistor scaling
38
1965 2002-2003
~ 90 nm
IMEC 2011
3D stacked interconnect
39
IMEC 2011
I
T
S
V

I
T
S
V

Impact TSV proximity on transistor
1
2
3
4
5
S1
S2
S3
S4
S5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
D
e
l
t
a

I
o
n

v
s

r
e
f

[
%
]
Columns
Rows
Single TSV at 1.7um
~ 0.6% Ion variation near
TSV, limited impact on DAC
1
2
3
4
5
S1
S2
S3
S4
S5
-5
-4
-3
-2
-1
0
1
2
3
4
5
D
e
l
t
a

I
o
n

v
s

r
e
f

[
%
]
Columns
Rows
Relative Ion change, 1TSV @ 1.7u on two sides
nMOS
pMOS
~ 4% Ion variation near TSV,
causes DAC disfunctions
i
TSV
AR 8:1 TSV
Keep-Out-Zone
determined to
minimize TSV
impact on CMOS
device using
TCAD model in
combination with
experimental data
40
IMEC 2011
Path-finding
Fast prototyping tool
trades accuracy for
rapid turn-around
Based on early compact
models and design rules
Output spatially aware
estimate of performance
and power
Output data for cost and
thermal evaluation
Output specs for design
authoring tools

3D Design path finding tool
41
IMEC 2011
1 Tbps
1 Gbps
1 Mbps
1 Pbps
1 mm 1 m 1 km 1Mm
COPPER
INTERCONNECT
WAN
Intra-
Chip
LAN
Intra-
Package
Intra-
Board
Inter-
Board
optical cables/fiber integrated waveguides
Optical interconnects roadmap
Transition driven by:
Signal integrity
Power
Form factor
Cost

OPTICAL
BACKBONE
43
IMEC 2011


1 Tbps
1 Gbps
1 Mbps
1 Pbps
OPTICAL
BACKBONE
1 mm 1 m 1 km 1Mm
COPPER
INTERCONNECT
WAN
Intra-
Chip
LAN
Intra-
Package
Intra-
Board
Inter-
Board
optical cables/fiber integrated waveguides

System
in
Package
Optical interconnects roadmap
45
Silicon Interposer:
Chips Stacking
Optical Connectivity
IMEC 2011
PHOTONICS
MODULATORS PLC, MUX DETECTORS
(Optional)
OPTICAL I/O
DRIVERS HEATERS
CMOS
TIAs SERDES
LASERS
E-O-E transceiver : Key Features
Single platform integrating all optical functionalities
CMOS-like fabrication processes
Small photonics component footprint
3D connectivity to CMOS wafers for improved O-E performance
Si photonics
46
IMEC 2011
All devices are fabricated on the same platform
Ring resonator
-17
-16
-15
-14
-13
-12
0 5 10 15 20 25
number of crossings
t
r
a
n
s
m
i t
t
e
d

p
o
w
e
r

[
d
B
m
]
-0.15dB/crossing
Crossing
2m
AWG Mux/Demux
-40
-35
-30
-25
-20
-15
-10
-5
0
1545 1550 1555 1560 1565 1570 1575 1580
Polarization rotator
Si photonics
Passive components library
47
IMEC 2011
CMOS
CMOS Scaling
CMORE
Multi-functional SOC/SIP
L=35nm
SiGe
L=35nm L=35nm
SiGe
NiSi
25 nm
NiSi
25 nm
FUSI FUSI
strain strain
HfO
2
high high - -k k
metal gate metal gate
FinFET FinFET
USJ USJ
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Active Area
Gate Field
Spacers
Ge Ge/IIIV /IIIV
silicide silicide
time F
E
O
L

D
e
v
i
c
e

r
o
a
d
m
a
p
Low k
k=3.0
Low k
k=3.0
Low k
k=2.7
Low k
k=2.7
Low k
k=2.5
Low k
k=2.5
3D SIP 3D SIP 3D SIP 3D SIP
Air gap Air gap
3D TSV 3D TSV
Cu Cu
I
n
t
e
r
c
o
n
n
e
c
t
s
Memory
Processor
RF Chip
DNA Chip
MEMS
Battery
Image
Sensor
Memory Memory
Processor Processor
RF Chip RF Chip
DNA Chip
MEMS MEMS
Battery Battery
Image
Sensor
Source SAMSUNG
CMOS
Bio-
Electronic
interface
Optical
detectors
Thermal
sensors
Chemical
sensors
Micro
Mirrors

Si
Photonics
100nm
x
-s
e
c
tio
n
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2


V
O
U
T

(
V
)
V
IN
(V)
0.099m
2
6T-SRAM
VDD
VSS
VDD
VSS
WL
BL BLB
WL
PG
PD
PU
PG
VDD VDD
VSS VSS
WL WL
BLB BL
VDD
VSS
VDD
VSS
WL
BL BLB
WL
PG
PD
PU
PG
VDD
VSS
VDD
VSS
WL
BL BLB
WL
PG
PD
PU
PG
VDD VDD
VSS VSS
WL WL
BLB BL
SC22 SC22
AL080409/D22
More Moore vs More than Moore
50
IMEC 2011
SIP: 3D vias
MEMS
Interconnect
pitch
~ 50 um

~10um ~10um ~1um
Interconnect
parasitics
few pF >100fF <100fF few fF
SIP: Stacked die
CMOS
MEMS
CMOS
MEMS
SIP: F2F
IC
MEMS MEMS
CMOS
SoC: monolithic
CMOS
MEMS
CMOS
MEMS
Monolithic approach:
Most compact solution
Best solution when needing high density interconnect and low parasitics
Requires compatible die sizes
3D stacking
Wirebond, flip chip, TSV depending on interconnect density and parasitics
Offers more choices in MEMS technologies and die size combinations
InvenSense
MEMS technology options
For tight integration with driver IC
51
IMEC 2011

Poly-SiGe:
better mechanical properties than Al: higher strength and Q factor
better reliability properties than Al: less creep and fatigue
52
Post CMOS
integration
yes yes
Fracture strength
[GPa]
0.2 > 2
Mechanical Q low > 10.000
Reliability creep: hinge
memory effect
No creep
Al Poly-SiGe
Different above CMOS
MEMS approaches
IMEC MEMS last technology

IMEC 2011
4.6cm
2
.
2
c
m

4.6cm
2
.
2
c
m

0.18um HV CMOS
M6
M5
M4
M3
M1
M2
SG1
SG2
11 Mega pixel micro mirror chip


11M pixel MEMS + CMOS integration
8x8 m pitch on SiGe platform (Al coating)
6 kHz update rate
Analog tilt angle control
Extreme mirror flatness <10 nm
No mirror fatigue & creep


53
IMEC 2011
March 1, 2010
The 2010 Trend Watch Sensor Survey Results

Sensors everywhere

55
McKinsey: Get Ready For Sensor-Driven Business Models (March 3, 2010)
Underlying the Internet of Things are technologies such as RFID, sensors and smart-phones

IMEC 2011
Mission statement:
Development of ultra-low power micro/nanosensors for (bio-) chemical detection
including the required read-out and driver circuits implemented in standard
cleanroom environment
Main targets
Increased sensitivity and/or selectivity
Ultra-low-power (< 20mW)
energy autonomous
Miniaturized integrated sensors
Cost-effective fabrication
S
10mW
A
10mW
Front
End
20mW
DSP
20mW
Radio
20mW
Micropower System - 100mW
mP
20mW
Thermal, Vibrational, RF, Light
Non
Electrical
World
Vision for sensor development

56
IMEC 2011
Necklaces/patches Watch-type Headsets Base Stations
Body area networks examples
Personal healthcare & lifestyle solutions

57
IMEC 2011
Human olfactory system e-nose: array of non-specific, cross-reactive sensors
combined with an information processing system
e-Nose
Advanced sensing in complex environments

Adsorption
Swelling
Stress
Extra mass
Lower
Frequency
Beam
polymer
Vapors

Frequency
A
m
p
l
i
t
u
d
e

o
f

M
o
t
i
o
n

Df
n
Dm a
n
Ds
58
IMEC 2011
Die = 8.8 mm x 8.8 mm, 160 resonators
e-Nose: low power is the key

e-Nose: from vision to reality:

w = 65 m
L = 750 m
h = 500 nm
Coating: PMMA
Transduction:
Piezoelectric actuation/detection
Power = 0.00017 mW
(170 nW)
w = 100 m
L = 500 m
h = 8 m
Coating: PMMA
Detection: Optical Beam
Power = 2 mW
IBM
10.000 times more power efficient
260 times responsivity increase
10
-5
frequency shift / %EtOH 2.6 10
-3
frequency shift / %EtOH
59
IMEC 2011
Energy storage

Storage for micro systems:
- All Solid-State devices (integrated systems)
- Microelectronic fabrication techniques
Size determines total capacity:
- High energy density even more important for small
form systems

0.01
0.1
1
10
100
1000
10 100 1000 10000
Power Density (W/kg)
E
n
e
r
g
y

D
e
n
s
i
t
y

(
W
h
/
k
g
)
High E-density
Low P-density
Low E-density
High P-density
0.2V- 1V
10 hours
2V- 3V
1 sec
2V- 4V
1 hour
Batteries
Double-layer cap.
Fuel
cells
LIB
Ultra cap.
Super-Capacitors
Double-layer caps= electrolytic
Ultra-capacitors = solid-state
FC
* Low retention time i.e.
no long term storage
Ragone plot
Miniature Portable Mobile
disposable &
autonomous
systems
portable
electronics
automotive
transportation
<~1g
<~0.1cm
3
10uAh-1mAh
~10-100g
1-10cm
3
10mAh-1Ah
~1kg-100kg
0.1-1m
3
10Ah-100Ah
Tesla-Roadster (340km)
Li-ion battery pack:
450kg (200kW)
375V, 56kWh (eq. 8L gaz)
6800 cells (18mmx65mm)
Li-ion battery pack:
8cells
14.4V, 73Wh
(5A.h)
Emerging
Technologies
~1 cm
2
; 1mAh
Thin film Battery packs
60
IMEC 2011
3D charge storage roadmap and
application drivers

3D-TF battery
half-cell (wet)
3D-TF Ucap
Solid
electrolytes
SS 3D-TFB
Integrated
batteries
Application drivers:
R
o
a
d
m
a
p

Module development:
Microsystems
Autonomous wireless sensors (WATS)

Decaps on interposer (3D)
Solid-State Ultracapitors
Prismatic Battery cells targeting high-P
with competitive E-density
Battery cells targeting durability and
safety (extended temperature window)
Battery on foil (large area)
small-form batteries, micro batteries
Smart solar modules
61
IMEC 2011
Nano-electronics will continue to drive innovation
in many fields.

Societal progress will be enabled by the merger of
nano-electronics, nano-technologies, bio sciences
and energy efficient technologies.

Global collaboration including entire value chain is
required to address the huge R&D challenges.
Conclusions