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1.1. "#nto$ %$&phic'
1.1.1 (v#$vi#)
Mentor Graphics is a technology leader in electronic design automation
(EDA), providing sot!are and hard!are design solutions that ena"le
companies to send "etter electronic products to mar#et aster and more cost$
eectively% &he company oers innovative products and solutions that help
engineers overcome the design challenges they ace in the increasingly
comple' !orlds o "oard and chip design $!here deep su"micron (D(M)
technology and (ystem$on$)hip ((o)) design multiply the challenges o
getting great product ideas to mar#et%
- *u"licly held (+A(DA,- ME+&)
- .ounded 1/01, head1uartered in 2ilsonville, 3regon
- 4,566 employees
- 7evenue in last reported 18 months- appro'imately 9:66 million
- 2orld$class research and development
- ;igh$touch, glo"al distri"ution channel $ sites in :: locations !orld!ide
- (trategic partnerships !ith leading electronics manuacturers,
semiconductor and electronic design suppliers or development o ne!
design solutions and methodologies
- 2orld 2ide 2e" address $ !!!%mentor%com
Areas of Focus:
*+'t#m,on,Chip -#$i.ic&tion
Mentor Graphics provides its customers !ith critical tools or solving the
increasingly complicated pro"lems o veriying that today<s comple' chip
designs actually unction as intended% 2ith its mar#et$leading positions in ;D=
simulation, hard!are>sot!are co$veriication, multi$core em"edded system
de"ugging, design$or$test, and emulation, Mentor helps customers tame the
design challenges they are acing today, and the ones they are "eginning to ace
!ith tomorro!<s designs%
Best$in$class products include- (eamless or early and accurate hard!are and
sot!are co$veriication? the +ucleus real$time operating system, the code@
la"A development environment or em"edded systems? B7AC, the sot!are
l
de"ugger or pre$ and post$silicon? .ormal*roA or ormal veriication?
*latorm E'pressA or rapid coniguration o (o) designs? a ull suite o
design$or$test tools including the ground"rea#ing &estDompressA, !hich
dramatically reduces the cost o test ? and E(tationA and )elaroA or
hard!are emulation%
/0 &n1 23%! #'ign
2ith its mar#et leadership in E;D= and mi'ed ;D= simulation, .*GA
synthesis, and design capture and management, Mentor Graphics is the
mar#et<s single vendor source or an integrated solution or multi$million$gate
ield$programma"le gate array (.*GA) design% Fn addition, Mentor has point$
tool e'cellence in high$end ;D= design !ith simulation and design capture and
management%
Best$in$class products include- Model(im digital simulation? ;D= Designer
(eriesA or design entry, analysis and management? and *recision (ynthesisA
to ma'imiGe perormance o programma"le logic devices and ne't$generation
ield$programma"le systems$on$chip%
3h+'ic&l #'ign &n1 !n&l+'i'
&he relentless drive to D(M technology has opened the door to a host o
challenging physical eects that designers need to !or# around "eore they can
realiGe their designs in silicon% 2ith a leading position in physical veriication,
Mentor provides a suite o tools that allo! designers to pro"e their designs to
discover and correct the critical errors that occur in shrin#ing geometries%
Best$in$class products include- )ali"re, the astest and most accurate physical
veriication tool or deep$su"micron designs? )ali"re 3*) and *(M or su"$
!avelength optical process correction and phase$shit mas#ing? the )ali"re
MD* product line or converting F) layout into mas# !riter ormat? ADEance
M(A or mi'ed$signal design? EldoA transistor$level simulation and Eldo7.
or radio re1uency analysis? and F) (tation or ull$custom F) design and
visualiGation%
4o&$1 &n1 *+'t#m #'ign
Mentor provides the tools and li"raries used "y many o the !orld<s "iggest
system designers today% 2ith recent investments in this product line, Mentor is
poised to help its customers transition to ne't$generation system design tools
and methodologies that !ill assist customers needing to rapidly create designs
even under the pressure o e'ploding design comple'ity%
Best$in$class products include- the Board (tation series, the enterprise design
environment !ithout limits? E'peditionA (eries, the design environment or
the individual or small group designer? and AutoActive 7E, the "est$in$class
routing environment "ringing immediate productivity gains integrated in
2
E'pedition and Board (tation? and the DM( products or design data
management%
Con'ulting, *#$vic#' &n1 *uppo$t
3rganiGed into our Dno!ledge )enters
(M
, Mentor<s )onsulting division has
the "readth and depth o e'pertise to assess each customer<s situation, sort
through the options and recommend the "est set o inrastructure and
methodology actions to deploy% &hese our Dno!ledge )enters are- (ystem$on$
)hip, Design 7euse, (ystem Eeriication and ;igh *erormance (*)B)
(ystems% Fn addition to leading customers through the deployment o their
recommended solutions, Mentor )onsulting provides the added "eneit o the
transer o #no!ledge through its uni1ue Dno!ledge$(ourcing
(M
model%
Dno!ledge (ourcing ocuses on solving the customer<s immediate design
challenges !hile simultaneously empo!ering their organiGation to solve
similar challenges in the uture%
Mentor<s Education (ervices is dedicated to providing the "est and most
comprehensive training or improving electronic design productivity%
Education (ervices oers a "road range o courses to e1uip customers !ith the
right s#ills, at precisely the right time%
Mentor<s a!ard$!inning )ustomer (upport organiGation delivers
#no!ledgea"le technical help through a choice o communication channels,
including !e"$"ased support, as !ell as ongoing sot!are enhancements to
protect customers< sot!are investment%
2o$ mo$# in.o$m&tion, pl#&'# cont&ct5
7y (ch!ar#
Mentor Graphics
564$:05$HH0/
Dean 7odgers
2e"er (hand!ic#
564$558$4H86
Mentor Graphics, (eamless, B7AC,, Model(im, )ali"re, F) (tation, Board
(tation, +ucleus and AutoActive are registered trademar#s o Mentor Graphics
)orporation% *recision (ynthesis, .ormal*ro, *latorm E'press, &estDompress,
ADEance M(, Eldo, code@la", E(tation and E'pedition are trademar#s o
Mentor Graphics )orporation% Dno!ledge )enters and Dno!ledge$(ourcing
are service mar#s o Mentor Graphics )orporation%
1.1.6. 3$o1uct' 7+ C&t#go$+
3C4 *+'t#m'

Automatic routing
Design tools
Digital high$speed
*)B home
7.>Mi'ed signal
(imulation and analysis
3
Fntegration, interaces I vie!ers
=ayout
,uic#Jse *art 7e1uest and
&rac#ing (ystem

&t& "&n&g#m#nt *+'t#m'

Data management systems I
li"raries
,uic#Jse Development (ystem

#'ign,.o$,8#'t

(can I A&*G
Em"edded Deterministic &est
Memory &est
=ogic BF(&
Boundary (can

23%! 9 30

Fntegrated Design Methodology
Design Entry I Management
Design creation
(ynthesis
Digital (imulation

*+'t#m #'ign : -#$i.ic&tion

*latorm Design
;ard!are>(ot!are )o$Eeriication
Design Entry I Management
Accelerated system veriication
.ormal Eeriication
Design$.or$&est
Emulation (ervices
(peedGate D(E

IC #'ign : -#$i.ic&tion

Analog>Mi'ed signal
)ustom F) Design
;igh capacity circuit simulation
E'traction
*hysical veriication I
manuactura"ility
*hysical optimiGation
*lace I 7oute
7esolution enhancement
technologies
(3*), *(M)

/&$n#'' *+'t#m'

)omplete ;arness .lo! (olutions
=ogical ;arness Design
;arness Manuacture
;arness Analysis

Em7#11#1 *+'t#m'

)ompilers
De"uggers
Em"edded (ystems home
*rocessors
7eal$time operating systems

4
Int#ll#ctu&l 3$op#$t+
.G*A > )*=D &argeted 7&= )ores
5
1.6 C&1#nc#
1.6.1 (v#$vi#)
As mar#et demand drives electronics companies to pac# more perormance and
unctionality into chips manuactured at ever$smaller geometries, designers
"egin to hit a !all o comple'ityKespecially as !e enter the nanometer era%
&oday<s semiconductors and electronic systems are so comple' that creating
them !ould "e impossi"le !ithout electronic design automation (EDA)%
)adence Design (ystems is the !orld<s largest supplier o EDA technologies
and engineering services% )adence helps its customers "rea# through their
challenges "y providing a ne! generation o electronic design solutions that
speed advanced F) and system designs to volume%
1.6.6. 8#chnolog+
.J+)&F3+A= EE7F.F)A&F3+
By employing the !orld<s irst single$#ernel architecture, the )adence
FncisiveA unctional veriication platorm delivers the astest and most
eicient !ay to veriy large, comple' chips%
&he challenges acing veriication teams have gro!n in parallel !ith the siGe
and comple'ity o chips and em"edded sot!are% Dealing !ith today<s
multimillion$gate designsKand the ineiciencies o multiple, unrelated
toolsetsKyou struggle to s1ueeGe in enough cycles to provide reasona"le
assurance that unctional "ugs !ill not surace in silicon% &o eectively veriy
highly comple' digital, (o), and mi'ed$signal F)s re1uires replacing the
current ragmented process !ith a ne!$generation approach that uniies tools,
standards, and methodologies% And, to avoid putting your design schedules at
ris#, you need an approach you can phase in over time%
&he Fncisive platorm employs a single$#ernel architecture that overcomes
ragmentation "y uniying multiple veriication techni1ues around a single
engine% Ft natively supports Eerilog, E;D=, (ystem), *(=>3E=,
(ystemEerilog and analog>mi'ed$signal veriication% &he same platorm
delivers Acceleration$on$Demand, transaction$level support, ;D= analysis
(linting), coverage, de"ug and analysis, and test generation% +ot only is
Fncisive designed so you can adopt these technologies incrementally, "ut it can
also deliver the speed and eiciency re1uired to compress overall veriication
time "y as much as 56 percent%
6
Incisive verification platform
DE(FG+ &A(D(
4lock v#$i.ic&tion
Bloc# veriication ensures unctional correctness o a design "y veriying "ase
design units as they are "eing developed% Bloc# veriication is typically
perormed in tandem !ith "loc# development, using the same design languages
to encourage tighter integration throughout the design and provide more
relia"le veriication results%
*+'t#m' v#$i.ic&tion
(ystems veriication provides early unctional design conidence and assures
veriication reuse throughout the "loc#$level veriication process "y developing
top$do!n veriication along !ith the design% Ft is typically perormed in
tandem !ith system development using the same design languages to
encourage tighter integration throughout the design and provide more relia"le
veriication results%
4uil1ing &n #mul&tion #nvi$onm#nt
As designs gro! larger and more comple', design teams must !or# !ith
numerous emerging technologies% )ompanies designing chips or high$end
!ireless, multimedia and net!or#ing, applications ace large gate$counts,
e'tremely long simulation run$times, and comple' protocols re1uiring many
veriication cycles to validate% )adence *alladiumA helps address these
challenges and accelerate time$to$mar#et or leading$edge products%
23%! 2ull Chip -#$i.ic&tion
.*GA .ull )hip Eeriication delivers shorter development times "y inding
"ugs "eore the chip is on the "oard% &oday<s advanced .*GAs are too
complicated to "e eectively de"ugged !ith pro"es on a "oard% &he Fncisive
Jniied (imulator allo!s designers to ind o"scure timing "ugs and unctional
7
errors in the simulator using the ull po!er o assertions and (imEision to gain
visi"ility that is impossi"le in the la"%
DFGF&A= F) DE(FG+
&he )adence EncounterA digital F) design platorm provides the proven tools
and methodologies or implementing e'ceedingly comple', high$perormance
chips%
Beore the advent o nanometer$scale process nodes, conventional design tools
let you achieve airly predicta"le resultsKand schedules% +ot anymore% 2ith
today<s geometries, the percentage o total delay due to !ire delay increases
signiicantly% &his ma#es traditional linear design lo!s o"solete, "ecause you
cannot aord to go all the !ay "ac# and change the architecture or logic each
time you encounter a pro"lem at the physical implementation level% +anometer
design also e'acer"ates physical eects #no!n to introduce signiicant
pro"lemsKnota"ly signal integrity ((F) eects and F7 (voltage) drop%
Eiolations can surace late in the design cycle, delaying completion "y !ee#s
and re1uiring tedious manual repairs%
Fmplementing nanometer designs re1uires a ne!$generation approach that puts
L!ires irstL and incorporates several ne! technologies and methodologies that
reduce errors and prevent e'cessive iterations% Fn addition, it re1uires a ne!
metric or speed, area, po!er, and test% ,uality o (ilicon (,o() is the ne!
generation standard or measuring these 1ualities ater !ires are completed in
the design%
&he Encounter platorm replaces traditional linear design lo!s !ith a
completely ne! design strategy that minimiGes time to !ires and ull$chip
iteration time% &he platorm also ensures the highest ,o(% Ft provides a
nanometer router that optimiGes !ire creation or perormance and
manuactura"ility? a uniied data"ase !ith massive capacity o up to 56 million
gates? and eicient e'tensi"ility% ;ighly accurate silicon virtual prototyping
technology also ma#es it ast and easy to model ho! very comple', high$
perormance chips !ill !or# in silicon% &his prototyping allo!s you to e'plore
the eects o changes and implement placement, loorplanning, and other
critical "ac#$end unctionsKin a raction o the time re1uired using physical
design tools%
Encount#$ 1igit&l IC 1#'ign pl&t.o$m
8
)J(&3M F) DE(FG+
(ilicon that<s right, on time% &he Eirtuoso platorm ena"les the !orld<s
astest, most silicon$accurate analog, custom digital, 7., and mi'ed$signal
design%
&oday<s advanced custom design teams are tac#ling designs on an order o
magnitude more comple' than Must a e! years ago% &hey must do so !hile
addressing a gro!ing num"er o physical eects in the pac#age, po!er grid,
interconnect, devices, and su"strate% ;o!ever, the design teams eiciency and
eectiveness have "een undamentally limited "y inade1uate design
environments%
&he Eirtuoso platorm is a comprehensive system that ena"les design teams to
deliver silicon that meets all speciications, as !ell as their schedules% Ft
includes a speciication$driven environment, multi$mode simulation,
accelerated layout, advanced silicon analysis, and a ull$chip integration
environment% &he Eirtuoso platorm ena"les a Lmeet$in$the$middleL
methodology that com"ines the speed o top$do!n design !ith the silicon
accuracy o "ottom$up design%
-i$tuo'o cu'tom 1#'ign pl&t.o$m 1i&g$&m
9
DE(FG+ .37 MA+J.A)&J7F+G
)adence design or manuacturing (D.M) technologies ena"le you to veriy
and optimiGe layouts in digital and custom F) designs, !hile providing a
relia"le !ay to achieve manuacturing sign$o "eore tape$out%
&o successully get nanometer$scale designs to mar#et, semiconductor
companies must address a gro!ing array o challengesKrom ever$more
stringent design rules to increasing chip layout comple'ity% Cou must also
contend !ith the physical eects that "ecome much more trou"lesome at
these smaller geometries% )omple' com"inations o voltage drop, signal
cross$coupling, and circuit parasitics interact to stretch design cycles and orce
re$spins% *rocess variations across the die, !aer, and "atch aect yield,
perormance, and relia"ility% Fn addition, "urgeoning volumes o parasitic data
strain storage acilities and cho#e chip analysis sot!are%
)adence recogniGes these challenges and has created the most comprehensive
Design or Manuacturing (D.M) solutions in the industry% By addressing the
t!o #ey aspects o the design lo!Kphysical veriication and sign$o
electrical veriicationKthe )adence D.M solution oers e'cellent choices or
veriying and optimiGing layouts in "oth digital and custom F) designs% Ft also
provides you a relia"le !ay to achieve manuacturing sign$o "eore tape$out%
A==EG73 (C(&EM F+&E7)3++E)& DE(FG+ *=A&.37M
&he )adence Allegro system interconnect design platorm reduces costs and
accelerates time to mar#et "y ena"ling a constraint$driven colla"orative
design across F), pac#age, and *)B domains%
Note: The silicon-package-board product line is now contained in the Allegro
platform, and all product names have been changed. Please check the pre-
platform technologies reference grid to view name changes.
&he system interconnect is the logical, physical, and electrical connection o a
signal, its associated return path, and the po!er delivery system% Design teams
ace unprecedented challenges in designing the system interconnect o today<s
comple' designs% 2ith the gro!ing integration o F)s, chip F>3s and pac#age
l0
pin counts are rapidly increasing% GigahertG$speed data rates also translate into
"listeringly ast *)Bs and systems% At the same time, the average *)B siGe is
decreasing and po!er delivery re1uirements are heating up as chips transistor
counts s#yroc#et%
&he need to solve these comple' pro"lems and deal !ith increasing time$to$
mar#et pressures ma#es the traditional approachKdesigning systems
components in isolationKo"solete% Achieving !or#ing system interconnect in
comple' systems re1uires a ne! generation approach, one that allo!s design
teams to ocus on achieving eiciencies in the system interconnect spanning
all three system domains%
Jsing the platorm<s co$design methodology, engineers can 1uic#ly optimiGe
the system interconnect$$"et!een F>3 "uers and across F)s, pac#ages, and
*)Bs $ eliminating hard!are re$spins and reducing "oth hard!are costs and
design cycles% &he constraint$driven Allegro lo! includes advanced
capa"ilities or design capture, signal integrity, and physical *)B design%
.rom designs or high$speed, high$perormance products to commodity
mar#ets, )adence provides easy integration !ith e'isting technology,
allo!ing you to incrementally enhance your e'isting design lo! !ith updates
and "est$o$"reed technology to support all mar#et sectors% And "ecause it is
supported "y the )adence Encounter and Eirtuoso platorms, the Allegro co$
design methodology ena"les eective design chain colla"oration%
*ilicon 1#'ign,in kit'
Fn addition to providing the industry<s dominant technologies or constraint$
driven F) pac#aging and high$speed *)B design and analysis, )adence also
pioneered the concept o silicon design$in #its% (ilicon design$in #its speed
time to proit "ecause they allo! F) companies to shorten ne! device
adoption time and systems companies to accelerate *)B system design cycles%
An integrated technolog platform supports the !"I# model, IP availabilit, and
silicon design-in technolog
ll
1.6.; #'ign *olution
3C4 #'ign
/igh,'p##1 3C4 #'ign : !n&l+'i'
IC 3&ck&ging : !n&l+'i'
($c&1 3C4 #'ign
PCB Design
Cour designs are gro!ing in comple'ity% Eective colla"oration "et!een teams
is paramount to your success% Based on industry$leading Allegro layout,
(*E))&7A autorouter, and )oncept ;D= schematic capture, )adence
oers t!o highly integrated, ront$to$"ac# design solutions% 3ur studio series is
ideally suited or small to medium siGed teams !ho re1uire an initial cost
conscience solution $ !ith the opportunity to scale as technology challenges
increase% &he e'pert series is a complete solution or advanced high$speed,
constraint$driven *)B designs% *)B Design E'pert eatures )onstraint
Manager, the only constraint management solution that allo!s you to manage
electrical constraints across the design lo! as one seamless concurrent process%
*)B Design (tudio
(cala"le, cost$conscious *)B design suite or small to medium team
environments
*)B Design E'pert
Advanced, constraint$driven, high$speed *)B design suite or large design
teams
High speed PCB Design
l2
)ontemporary high$speed designs introduce contemporary high$speed design
challenges $ timing analysis, crosstal#, and po!er delivery to name a e!%
&oday<s cutting$edge designs re1uire these challenges "e addressed collectively
and continuously across the entire design lo! rom parts selection and electrical
constraints development, to driving the constraints do!nstream to the layout
process% (*E))&7A,uestA (F E'pert and *)B Design E'pert provide a
complete and integrated environment or the simultaneous design and analysis
o high$speed digital systems% )onstraint Manager ma#es this collective process
possi"le "y providing a uniied spreadsheet interace or capturing, managing,
and veriying electrical constraints across the entire design lo!%
(*E))&7A,uest (F E'pert
Fntegrated design and analysis environment or high$speed digital *)Bs
*)B Design E'pert
;igh$speed design suite integrated !ith )onstraint Manager
IC Packaging & Analysis
l3
&oday it<s not uncommon to have design teams develop F), pac#age, and *)B
systems alone in a vacuum $ o"livious to the impacts% &his uncoordinated
approach results in costly and time$consuming iterations% Advanced *ac#age
Engineer (A*E) and Advanced *ac#age Designer (A*D) are the irst tools to
address this pro"lem% &hese complementary tool suites institute ground"rea#ing
techni1ues or integrating electrical analysis and physical design through all the
phases o development $ providing the only true silicon$pac#age$"oard design
solution on the mar#et today% And "ecause A*D automatically generates all data
needed or *)B$level loorplanning and layout, users have an eicient hando
to *)B system$level designers or superior team design capa"ilities%
F) *ac#aging
)enterpiece to the )adence *)B design silicon$pac#age$"oard solution
*)B Design E'pert
Fntegrated design and analysis environment or F) pac#aging capa"ilities
Orcad PCB Design
l4
3rcad *)B solutions are the industry<s de acto standard or delivering
unprecedented value in easy$to$use design tools% 3rcad Jnison (uite
(illustrated a"ove) is a "undled *)B design solution or individuals !or#ing on
prototypes or limited$production "oards% .eaturing 3rcad )apture schematic,
the !orld<s most popular design entry tool, *(pice analog and mi'ed$signal
simulator, 3rcad =ayout place and route, and the advanced (*E))&7A
autorouter, 3rcad Jnison (uite is an aorda"le solution to complete *)B
designs% As your team or "usiness needs e'pand, 3rcad Jnison oers
convenient scala"ility options to additional 3rcad products% Cou can also #eep
your investment and resources intact "y upgrading to )adence Allegro
solutions%
(*E))&7A
&he mar#et$leading solution or interconnect routing
3rcad Jnison (uite
Fntegrated suite o ne!ly enhanced 3rcad products
1.6.< Co$# t#chnolog+
!n&log9igit&l -#$i.ic&tion
Con't$&int "&n&g#m#nt
0i7$&$+ "&n&g#m#nt
*ign&l : 3o)#$ Int#g$it+
Analog/Digital Verification
l5
)adence oers electrical engineers an array o veriication solutions rom the
advanced, ull$eatured capa"ilities o +)$(im $ an industry leader is digital
simulation, to the !orld<s most popular analog and mi'ed$signal solution,
*(pice simulator% *)B Analog and Mi'ed$signal E'pert ("ased on Analog
2or#"ench) is the recogniGed leader in analog and mi'ed$signal *)B
simulation% +e! *(pice Advanced Analysis option "rings eatures originally
availa"le in the Analog 2or#"ench design environment (Jni') to *(pice users
on 2indo!s% And *(pice (tudio com"ines *(pice A>D !ith *(pice Advanced
Analysis giving design engineers signiicant improvements in design
perormance, cost eectiveness, and relia"ility% 2ithout 1uestion, )adence
oers a po!erul arsenal o veriication technologies or "oth mainstream and
high$end *)B design%
*)B Analog and Mi'ed$signal E'pert
Advanced high$speed veriication
*(pice (imulator
A ull$eatured simulator or "oth analog and mi'ed$signal designs
Constraint Management
l6
2ith gro!ing high$speed content and shrin#ing design cycle times, designers o
comple' high$speed *)Bs ace a ne! challenge $ high$speed constraints% Fn act,
the percentage o nets on a "oard that have high$speed constraints is gro!ing
rapidly !ith some "oards having more than H5N o nets "eing constrained%
)adence is the irst to develop a truly integrated, hierarchical constraint
management system that is consistent across the entire design lo!% 2or#ing
throughout the design process, )onstraint Manager provides a consistent !ay to
create, manage, and validate design intent% Ft presents electrical constraints in a
uniied, spreadsheet$li#e interace that can "e accessed rom )oncept ;D=
E'pert schematic capture, (*E))&7A,uestA (F E'pert signal analysis,
Allegro E'pert *)B layout, and Advanced *ac#age Designer%
)oncept ;D= E'pert
7o"ust and highly integrated schematic capture or high$speed *)B
)onstraint Manager
)onstraint Manager unctionality "ased in Allegro E'pert
i!rary Management
Eisi"ility into consistently relia"le component data increases the chances o
getting a 1uality product to mar#et on time% Enorcing "est practices during the
development, validation, and management o component data also ensures
integrity and maintains the relia"ility o all part data% E1ually important is
reducing the manual re$entry o data% &his is achieved "y leveraging Fnternet$
derived manuacturing speciications through a process that is ast, eicient, and
re1uires very little eort to deploy% )adence oers li"rary proessionals the
conidence o an uninterrupted transition throughout the entire design lo! !ith
our comprehensive li"rary management solution%
l7
*)B =i"rarian
Development o li"rary parts re1uired or *)B design
*)B Design E'pert
Development, veriication and management o parts or *)B design
"ignal & Po#er Integrity
)ontemporary high$speed issues $ timing analysis, signal integrity, crosstal#,
po!er delivery, and EMF can no longer "e addressed individually% &oday<s
cutting$edge designs re1uire these issues "e addressed collectively and
continuously throughout the design process% &he integrated design and analysis
environment o (*E))&7A,uestA (F E'pert allo!s electrical engineers to
e'plore and resolve these challenges in all stages o the design cycle $ including
design and analysis o F) *ac#aging% (*E))&7A,uest *o!er Fntegrity, an add$
on option to (*E))&7A,uest (F E'pert, is an integrated environment or
po!er delivery systems design% Ft com"ines proven technology rom (un
Microsystems into the )adence design and analysis environment to address
po!er delivery issues in high$speed *)B systems design%
(*E))&7A,uest (F E'pert
Fntegrated design and analysis environment or high$speed digital *)Bs
(*E))&7A,uest *o!er Fntegrity
,uantiies and controls noise !hen addressing po!er delivery issues
l8
l9
1.;. *ilv&co
1.3.1 Overview
(ilvaco Fnternational is a leading provider o electronic design automation
(EDA) sot!are or analog and mi'ed$signal integrated circuit design% .ounded
in 1/0O, the company delivers proven products or &)AD process and device
simulation, (pice parameter e'traction, circuit simulation, and custom F)
design>veriication% &he company integrates these "est$in$class products !ith
e'perienced support and engineering services to provide complete analog
semiconductor process, device and design automation solutions in )M3(,
Bipolar, (iGe and compound technologies% 2orld!ide customers include
leading a"less semiconductor companies, integrated semiconductor
manuacturers, oundries, universities and designers o analog integrated circuits
!ho re1uire the utmost accuracy%
&he company is privately held, internally unded, de"t$ree, and o!ns all o its
oice "uildings% Ft is head1uartered in (anta )lara, )aliornia, !ith 11 oices
!orld!ide to support its international customer "ase !ith #no!ledgea"le and
e'perienced applications engineers%
1.3.2. Solution
3$o1uct'
(ilvaco delivers a comprehensive set o EDA tools that ena"le companies
around the !orld to design analog and mi'ed$signal integrated circuits%
(emiconductor technology engineers use our &)AD products to develop and
optimiGe their semiconductor processes% F) designers use our F) )AD products
to design and simulate analog circuits% )losure "et!een manuacturing and
20
design depends on accurately e'tracted device models and accurate circuit
simulation%
$CAD
(ilvaco &)AD tools start !ith understanding the physics o the "asic
semiconductor, dielectric, and conducting materials% &he Eirtual 2aer .a"
technology simulation environment ena"les the A&;E+A process technology
simulators and the A&=A( device technology simulators to prepare, run,
optimiGe, and analyGe semiconductor e'periments to achieve optimal process
recipes and device targets%
3$o1uct 2&mil+5
E2.- Fntegrated &)AD Environment
A&;E+A- *rocess (imulation .rame!or#
A&=A(- Device (imulation .rame!or#
ME7)J7C- .ast Device (imulation .rame!or#
#'ign 2lo)'5
&.& &echnology
(3F &echnology
(iGe>(iGe) &echnology
A%AO& & MI'(D "I&%A
(ilvaco analog and mi'ed signal tools include (mart(pice Analog )ircuit
(imulator or the highest accuracy, convergence, and perormance, and the
!orldPs largest selection o modeling solutionsKoundry$supplied models, ree
2l
do!nloada"le Eerilog$A source models, J&M3(& Modeling (ot!are, and
complete model e'traction services
3$o1uct 2&mil+5
J&M3(&- FFF (pice Modeling (ot!are
Gate!ay- (chematic Editor
E'pert- =ayout Editor
(mart(pice- )ircuit (imulator
Guardian- *hysical Eeriication products
)=EEE7 - *hysics$"ased *arasitic E'tractor
C)"$OM IC CAD
(ilvacoPs custom F) design environment is a complete, integrated design lo!
!ith Gate!ay schematic editor or design capture, Eerilog or ast digital and
mi'ed$signal simulation, (mart(pice circuit simulator or analog accuracy,
E'pert layout editor !ith *)E==s, Guardian D7) >=E(>=*E or physical
veriication and )=EEE7 physics$"ased parasitic e'tractor all supported "y
oundry process design #its (*DD)s%
22
3$o1uct .&mil+5
)E=EB7F&C- F) Design and Eeriication *latorm
Gate!ay - (chematic Editor
E'pert- =ayout Editor
Guardian- *hysical Eeriication products
;F*EB- .ull$)hip *arasitic )haracteriGation
PA*A"I$IC ('$*AC$IO%
(ilvacoPs parasitic e'tractors use physics$"ased 8D and 4D ield solvers to
directly convert mas# data and relevant process inormation into (*F)E netlists,
"ac# annotated !ith interconnect capacitance and resistance parasitics at your
choice o accuracy and capacity%
3$o1uct 2&mil+5
DF()3EE7C *hysics$Based *arasitic E'traction &ools
EBA)& Fnterconnect *arasitic )haracteriGation
,JE(& ;igh .re1uency *arasitic E'traction
)=EEE7 *hysics$"ased *arasitic E'tractor
(&E==A7 )haracteriGation o (tandard cell *arasitics
O&IC V(*I+ICA$IO%
3riginally developed "y (imucad in 1/0: and ac1uired "y (ilvaco in 8664, the
(F=3( Eerilog (imulator is an easy$to$use FEEE$14:O$8661 compliant
simulator that provides todayPs most productive logic design environment%
;yper.ault Mi'ed$=evel .ault (imulator is a Eerilog FEEE$14:O$8661
compliant ault simulator that analyses test vectorsP a"ility to detect aults%
23
3$o1uct 2&mil+5
;armony$AM( Analog>Mi'ed$(ignal (imulator
(F=3( Eerilog (imulator
&ur"o=int *rogramma"le ;D= )hec#er
;yper.ault Mi'ed$=evel .ault (imulator
1.3.3 Products


TCAD Driven CAD Environment
&his ully integrated set o sot!are tools "rings the po!er o physical
semiconductor technology into all phases o the F) design process including-
simulation o process and device technologies, generation and development o (pice
models, e'tremely accurate characteriGation o interconnect parasitics, physically$
"ased relia"ility modeling, and traditional )AD%
&he integration o all o these capa"ilities into a uniied rame!or# provides
designers !ith immediate eed"ac# descri"ing the impact o changes at any stage o
the design cycle on the perormance, manuactura"ility and relia"ility o the
complete design
24
.rom this page you can vie! product inormation, do!nload "rochures in pd ormat
or "ro!se a collection o ree do!nloada"le posters%
8C!
3$oc#'' 8#chnolog+ *imul&tion
!8/E=! *rocess &echnology (imulation
Elit# 8D Deposition and Etch (imulator
"C #po9Etch 8D Monte )arlo Deposition and Etch (imulator
**up$#m< 1D>8D *rocess (imulation (ot!are or (ilicon &echnologies
"C Impl&nt 1D>8D Monte )arlo Fmplantation (imulator
2l&'h , 196
)ompound (emiconductor *rocess
(imulator
(ptolith 8D 3ptical =ithography (imulator
**up$#m; 1D *rocess (imulation
*34 (ilvaco<s *rocess Data"ase
#vic# 8#chnolog+ *imul&tion
!80!* Device &echnology (imulation
*,3i'c#' 8D (ilicon Device (imulation
828 6 Amorphous and *olycrystalline Device (imulator
2#$$o .erro Electric .ield Dependent *ermitivity Model
4l&># Device (imulator or Advanced Materials
0&'#$ (emiconductor =aser Diode (imulation
*i%# (ilicon Germanium Module
*IC (ilicon )ar"ide Module
-C*E0*
4l&>#; Device (imulator or Advanced Materials
Common mo1ul#'
?u&ntum (imulation Models or ,uantum )oninement Eects
0uminou' 3ptoelectronic Device (imulator
%ig& +on$Fsothermal Device (imulation
"i@#1"o1# )om"ined Device and )ircuit (imulator
#vic# ;
828 ; Amorphous and *olycrystalline Device (imulator
2&'t 2E8 *imul&tion
"EACBAC .ast .E& (imulation
2&'t4l&># Jltra$.ast ME(.E& and ;EM& Device (imulator
"oc&'im Monte )arlo &ransport *arameter Generator

!n&log *olution'
25
3&$&m#t#$ E@t$&ction &n1 *pic#
"o1#ling

B8"(*8 Data Ac1uisition I *arameter E'traction
*3!C= (tatistical *arameter I Cield Analysis
*;6<D! "(* =oi'# !mpli.i#$
*;<<E! *(I =oi'# !mpli.i#$
Ci$cuit *imul&tion
*m&$t*pic#
Multi$platorm Advanced Analog )ircuit
(imulator
-EAI0(%,! (mart(pice EE7F=3G$A Fnterace
*3ICE "o1#l'
-4IC Gummel$*oon 7eplacement
"#@t$&m General *urpose Bipolar Model
"o1#ll& =ateral *+* Bipolar Model
/ICB" ;igh (peed Bipolar Model
4*I";v;.6.< Fndustry (tandard Deep (u"$Micron M3(.E& Model
4*I"< v6.1
Fndustry (tandard (u"$6%14 Micron M3(.E&
Model
4*I";*(I 3
v6.6.6
=o!$*o!er M3(.E& Model
4*I";*(I 2 v6.1 =o!$*o!er M3(.E& Model
4*I";*(I v6.1 =o!$*o!er M3(.E& Model
/i*I" (urace *otential$Based M3(.E& Model
EF- v6.G =o! *o!e M3(.E& Model
*pic# "o1#ling *#$vic#'

C!
Int#$conn#ct 3&$&'itic E@t$&ction
I*C(-EAC Fnterconnect *arasitic E'traction
EH!C8 Fnterconnect )haracteriGation
C0E-EA )ustom )ell =*E
?BE*8 ;igh .re1uency *arasitic E'traction

CE0E4AI8C )ircuit Design and Eeriication
*chol&$ (chematic Editor
E@p#$t Advanced )ustom J=(F =ayout Editor
*&v&g# Design 7ule )hec#er
"&v#$ick ;ierarchical +etlist E'tractor
%u&$1i&n ;ierarchical =E( Eeriication
26
Int#g$&tion
8C! Fnteractive &ools
-I2 Automation &ools
-I2 *roduction &ools
#'ign 2lo)'
828 8#chnolog+
*(I 8#chnolog+
27
1.< Hilink
1..1. Overview
2hile the rest o the industry !as moving to!ards layos and sha#ing$o
e'cessive inventory, Bilin' !as "usy innovating, colla"orating, and introducing
ne! products to mar#et% Jnli#e many o our counterparts, Bilin' vie!ed the
do!nturn as an opportunity to ocus on research and development, streamline
operations, and deliver ne! products that !ould change the .*GA landscape%
&his last year, Bilin' decisively separated itsel rom our competition% .or the
irst time in our history, !e secured over 56N o the *=D mar#et share and are
"igger than all other pu"lic *=D companies com"ined% 2e avoided layos and
!ere ran#ed "y .ortune magaGine as the si'th "est company to !or# or%
&hrough the po!er o innovation and partnerships, Bilin' also too# the .*GA$
"ased value chain to a ne! level% By teaming !ith technology leaders in silicon
a"rication, design automation, system level tools, F*, and design services, !e
delivered a complete value chain and strengthened our position as a strategic
partner or our customers% Delivering this complete value chain ena"les the
astest innovation !hile reducing total development and system costs or our
customers% Ft also reduces time to mar#et and increases time in mar#et or our
customer<s products%
Fn March 8668, through partnering !ith industry leaders FBM, 2ind7iver
(ystems, and )one'ant, Bilin' delivered the Eirte'$FF *roA programma"le
system solution% &he solution is the irst o its #ind and is the most le'i"le tool
ever invented or a designer% &he Eirte'$FF *ro .*GA includes programma"le
logic a"ric !ith high$speed em"edded *o!er*) processors and integrated
4%185 giga"it 7oc#etF3A serial transceivers supported "y leading design tools%
7ecent additions to the amily and lo!er price points have no! made the
Eirte'$FF *ro solution the de$acto standard or all programma"le logic users%
&he Eirte'$FF *ro solution responds to the issues acing design teams and their
corporations% By delivering "oth high$perormance processing and high
"and!idth connectivity on a single device, many design challenges associated
!ith integration, high$speed interacing, high perormance processing, and ne!
design methodologies are eectively solved% &he rapid rate o change in
technology and standards demands a solution that is completely le'i"le and
reduces inventory ris#s and +7E costs $ the Eirte'$FF *ro solution delivers%
Bilin' is a company "uilt on delivering ma'imum customer value and ongoing
innovation throughout all o our product lines% Fn this last year alone, Bilin'
revamped all o its products rom the ne! (partan$FFE cost$optimiGed .*GA
solution to the )ool7unner$FF 7ealDigital )*=D solution, the Eirte'$FF *ro
platorm or programma"le systems, and the Eirte'$FF Easy*ath solution or
28
cost management% 2e also introduced the !orld<s astest and most productive
sot!are tool suite !ith our F(E O%8i sot!are release, numerous intellectual
property cores, and the technical training necessary to decrease time$to$
#no!ledge or the rapid assimilation o this ne! technology% 2e continue to
ocus on raising the "ar "y adding more value in every category o the value
chain%
&hrough the years, Bilin' has evolved into a solutions company rather than
remaining Must a chip company% 2e can only "e "etter tomorro! than !e are
today "y !or#ing closely !ith our customers and anticipating their needs%
Bilin'<s Mo" is to continue to e'pand our capa"ilities and our partnerships, so !e
can continue to "e a strategic partner or our client companies%
Bilin' is an innovation engine and our employees are the #eys to our
innovation% (uch innovation re1uires personnel policies that allo! employees to
ma#e their o!n decisions and ta#e ris#s% 3ur company values and corporate
culture promote team!or# and very open communication% 2e #no! that
#eeping employees satisied leads directly to innovation, customer satisaction,
and ultimately, increased proits% 3ur employees are inspired and #no! they
ma#e a real dierence%
&his uni1ue !or# environment has resulted in "rea#through technology,
mar#eting and community achievements% .or e'ample, Bilin' continues to
support local schools through our (toc# or (tudents program and made a 91
million donation to the American 7ed )ross% Also, Bilin' !as the irst
semiconductor company to simulcast training in +orth America and Europe
through industry events li#e *rogramma"le 2orld 8668%
2ith a com"ination o innovative products, !orld$class partners, inspired
employees and the recognition o the "alance "et!een "usiness and community,
our clients have ta#en Bilin' solutions, management, and employees to heart%
&his is a reminder that good people ultimately do come in irst !hen they are
inspired and empo!ered to "e leaders%
1..2. Solution and Products
*ilicon 3$o1uct' : *olution'
Eirte'$O .*GAs (partan$4 .*GAs
Easy*ath (olutions (partan$FFE .*GAs
Eirte'$FF *ro I Eirte'$FF *ro B
.*GAs
)*=D *ortolio
Eirte'$FF .*GAs )oniguration (olutions
7oc#et*;C 16 G"ps &ransceivers
*#$vic#'
Bilin' Design (ervices B*A *ac#aged (olutions
29
Education (ervices *remium (upport
&itanium Dedicated Engineering 4rd *arty 7esources
#'ign A#'ou$c#'
F* )enter F(E Design &ools
Memory )orner )hip(cope *ro
D(* )entral *lanAhead .loorplanner
*rocessor )entral Development Boards
)onnectivity )entral Em"edded (ot!are Design
;igh (peed (erial (olutions
Co$po$&t# *olution'
,uality =o! )ost (olutions
*"$.ree (olutions *roduct Demos, eaturing
*rocess &echnology Dr% )hris Dic# on D(*
Environmental, ;ealth I (aety
30
6. Cc nh cung cp cng ngh o lng th nghim IC
6.1 !gil#nt 8#chnologi#'
2.1.1. Gii thiu v hng Agilent Technologies
Agilent Technologies l mt trong nhng hng hng
u trong cc lnh vc vin thng v khoa hc phc
v i sng. T lnh vc vin thng cp quang v
khng dy n nghin cu Y hc v Nghin cu
khm ph, Agilent a cc sn phm v cng ngh mi
nht ca mnh ti khch hng trn ton th gii. Cc
cng ty hng u th gii nh: cc nh sn xut thit
b vin thng, cc nh cung cp dch v lnternet, v
cc cng ty chuyn v lnh vc ho dc, thit b y t v cc ngnh, lnh vc
rng ln khc da trn v t nilm tin vo trn 20.000 cc thit b th
nghim, thit b o lng, thit b gim st, cc sn phm bn dn, cc cng
c phn tYch ho hc ch gip cc iu khin giao tip v khoa hc
phc v i sng. V tt c cc cc nghin cu, cc thit b, cc cng ngh
v cc cng hin ca Agilent lun mong mi em n cho nhn loi mt th
gii hin i hn.
Agilent
cung cp sn
phm cho hn
40 quc gia
trn th gii v pht trin sn xut cc
sn phm ca mnh ti M, Trung
Quc, c, Nht Bn, Singapore,
Australia v Anh Quc. Ngoi cc tr
s phng thY nghim chYnh ti Palo
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phng thY nghim khc t ngay ti
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Trung Quc.
Vi xp x 43.000 nhn vin trn th
gii, hng Agilent ang khng ngng
phc v cc khch hng trn l20 quc
gia. Hn mt na khon li dng (net
revenue) Agilent thu c l ngoi nc
M. Chng ti mi thit lp cc tr s
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chYnh l tr s u tin ca Hewlett-
Tinh thn
tin phong
ca Agilent
c xc
nh ngay t nhng nm 40, khi hai
k s - Bill Hewlett v Dave Packard
- sng to ra tng lai ngay trong
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khi Hewlett-Packard nhng Agilent
vn duy tr cc nghuyn tc ca hai
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t c nhiu thnh cng trong
nhiu lnh vc gp phn hnh
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vch ra: ton vn, on kt, nim
tin, tn trng, tinh thn tp th.
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ch to v cung cp cc h! th"ng t#ch h$p cc gi%i php ki& tr' i!n t( v
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nghi!p +n /0n, i!n t(, truy1n thng. Agilent cung cp cc
gi%i php ki& tr' ton /i!n, +'o g2& cc h! th"ng ki& tr',
cc thit +, ki& tr' t 3ng, cc cng c4 phn &1&, cc
thit +, ki& sot v )u%n l5 i!n t(. 6c lnh vc ki& tr'
v o l-ng ch#nh +'o g2&7
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Kim tra cc trm di ng, Bluetooth, kim tra nhn v pht tYn hiu, ti u
mng truyn thng.
9ng truy1n thng7
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Fax/Voice/Video, phn tYch truyn thng, kim tra gim st ci t.
Truy1n thng +:ng r3ng, v! tinh, cp v T;7
DSL, v tinh, TV cp, truy xut bng thng rng, kim tra tYn hiu video s ..
B m, b sinh hm, ng h o LCR, ng h a tham s:
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k ...
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truyn thng, thit b o bc sng, chuyn mch
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v tYn hiu.
32
>i& tr' cc s%n ph?& +n /0n v &ch in7
Kim tra bng quang hc v tia X, kim tra mch trong khi hot ng, kim
tra chc nng, kim tra tham s, kim tra b nh, kim tra lC khng dy,
kim tra chip tYch hp.
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cng nghi!p sinh /$c h*c, &i tr-ng v cng nghi!p ho
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thit +,, h! th"ng cDng nh /,ch v4 cho php thu thEp
v ph8n t#ch cc kt )u% nghiBn cFu sinh h*c GgienH
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hi!u sut c'o, chi ph# thp v /K s( /4ng so vCi cc
s%n ph?& thng th-ng cAng loi.
Cc gii php truyn thng
Agilent Technologies cung cp cc cng ngh!, cc ti!n
#ch cDng nh cc /,ch v4 t vn L chuyBn gi' cho php cc
cng ty hng u v1 truy1n thng nJ& +Jt cM h3i v
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nghi!& l'u n:& v cng ngh! hng u, Agilent c= th
giOp cc cng ty gi%& gi thnh, t:ng l$i nhuEn v chi&
lnh th, tr-ng.
Cc sn phm bn dn
Agilent l nh cung cp hng u cc gi%i php +n /0n
cho truy1n thng v tuyn v hPu tuyn, Q( l5 thng tin,
hRnh %nh, ,nh v, )u'ng h*c v cc s%n ph?& chiu
sng th rJn, +'o g2& cp )u'ng, '/'pter n=ng, h2ng
33
ngoi, gi%i php kt n"i /i 3ng, chuyn &ch )u'ng, S6 lCp vEt l5 v S6 lCp
gi'o thFc, vi s=ng ...
6.1.6 3$o1uct'
Test ! "easurement E#ui$ment
Basic I General *urpose
Fnstruments
7. I Micro!ave
Fnstruments I (ystems
2ireless )ommunications
3scilloscopes, =ogic
AnalyGers I Digital &est
&est (ystems I (ystem
)omponents
&est I Measurement
(ot!are and )onnectivity
EDA (ot!are
*recision Measurement $
Distance, &ime,
.re1uency, 3ptics,
*hysical
=ight!ave I *hotonic
Measurement (olutions
2ireline )ommunications
&est
&est Accessories,
)a"inets, )a"les
7epair, )ali"ration I
Applications (ervices
Jsed Agilent &IM
E1uipment
Discontinued &est I
Measurement E1uipment
QDiscontinuedR
Semiconductor Products
A(F)s
)amera Modules and
Fmaging *roducts
.i"er 3ptics
.i"re )hannel Adapters
Fllumination and )olor
Management
Fnrared and Barcode
=EDs (=ight Emitting
Diodes)
Motion )ontrol
3ptical +avigation
3ptocoupler
*hysical =ayer F)s
*rotocol F)
7. I Micro!ave
(!itch I Bridge F)s
(Fnini"and, *)F E'press)
%ife Sciences&C'emical
)apillary Electrophoresis
)olumns I Accessories
Data (ystems
D+A Microarrays
G) I G)>M(
F)*$M(
=a"$on$a$)hip
=) I =)>M(
(ervices
&echnical (upport
JE$Eis
Communications "ana(ement ! Test S)stems
3(( +et!or#, 7evenue I
(ervice Management
(olutions
2ireless )ommunications
2ireline )ommunications
&est
Enterprise (olutions
=ight!ave I *hotonic
Measurement (olutions
)ommunications (ervices
and (upport
Automated Test E#ui$ment *ATE+
(emiconductor &est
E1uipment
.lat *anel Display &est
(ystem$on$a$)hip ((3))
&est on the /4666 (3)
7.F) &est
(emiconductor &est
(ervices
*rinted )ircuit Board &est
and Fnspection
Fn$circuit &est
=ead$.ree &est and
Fnspection
Manuacturing &est
(ot!are (olutions
34
(eries
Memory &est
*arametric &est
Automated 3ptical
Fnspection
Automated B$ray
Fnspection
*)B &est and Fnspection
(ervices
35
6.6 =&tion&l In't$um#nt
6.6.1. (v#$vi#)
+ational Fnstruments is a technology pioneer and leader in virtual
instrumentation $$ a revolutionary concept that has changed the !ay engineers
and scientists approach measurement and automation% =everaging the *) and its
related technologies, virtual instrumentation increases productivity and lo!ers
costs or customers !orld!ide through easy$to$integrate sot!are, such as the
+F =a"EFE2 graphical development environment, and modular hard!are, such
as *BF modules or data ac1uisition, instrument control and machine vision% +F
customers include engineers, scientists, and technical proessionals in a !ide
range o industries% .rom testing DED recorders to researching advanced
medicines, customers use +F sot!are and hard!are to deliver a diverse set o
products, aster and at a lo!er cost%
6.6.6 *olution'
+F oers a !ide assortment o tools, "undles, and services to help you "uild the
"est solution or your application needs%
Fndustry (olutions $$ =earn ho! engineers in your industry are solving
applications using our tools% Get a Mump start on your ne't application using our
common coniguration product "undles%
Aerospace
Automotive
=ie (ciences
Fndustrial Measurements and
)ontrol
)ommunications
Electronics
(emiconductor
Academic *rograms $$ )hec# out our special academic products and programs
or educators and researchers% (hare ideas and course!are !ith others in the
academic community%
Alliance *rogram $$ (earch or a systems integrator to "uild you a customiGed
solution% Bro!se or third$party systems, services, and products "ased on our
tools%
)ustomer (olutions $$ 7ead technical accounts o real$!orld solutions rom our
customers%
E=E)&73+F)(
.rom research and development to manuacturing and A&E applications,
=a"EFE2, *BF, data ac1uisition, and signal conditioning help you develop
complete, customiGed measurement and automation solutions%
A#comm#n1#1 Con.igu$&tion'
Get a head start on creating your electronics test solution !ith the +F (ound
36
*o!er (ystem, a lo!$cost, ready$to$run solution or noise emission testing in
ree$ield test environments%
+F Display &est $$ "ased on +F hard!are and sot!are products such as *BF,
FMA, Eision, &est(tand, and =a"EFE2, you can 1uic#ly and accurately
inspect lat panel displays% 2ith +F<s le'i"le computer$"ased approach, you can
easily adapt to changing mar#et and technological demands%
El#ct$onic' Cu'tom#$ !pplic&tion'
El#ct$onic' 'olution' 1#v#lop#1 7+ =&tion&l In't$um#nt' !lli&nc# 3$og$&m
m#m7#$'5
- AlautomaGione $ Multimedia &est (ystem
- t%e%s%t &)M $ &emperature )ham"er Monitoring (ystem
&empEFE2 $ .ull (urace &hermal Fmaging (ystem
Ee#tre' D&7:>0 $ Automated 7ecorder &est (ystem
(EMF)3+DJ)&37
.rom circuit and device testing to actory automation applications, =a"EFE2,
image ac1uisition, data ac1uisition, and signal conditioning help you develop
complete, customiGed measurement and automation solutions%
A#comm#n1#1 Con.igu$&tion'
Get a head start on creating your semiconductor test solution% 2e<ve developed
conigurations or the ollo!ing semiconductor test applications-
- 2aer &hic#ness &est
- (emiconductor &est
- &hin$.ilm Deposition )ontrol
- *#micon1ucto$ Cu'tom#$ !pplic&tion'
*#micon1ucto$ 'olution' 1#v#lop#1 7+ =&tion&l In't$um#nt' !lli&nc#
3$og$&m m#m7#$'5
- t%e%s%t &)M $ &emperature )ham"er Monitoring (ystem
- Fntelligent *rocess )ontrol $ Materials and )hemical *rocessing
(olution &empEFE2 $ .ull (urace &hermal Fmaging (ystem
3$o7#$ $iv#$'
- Electroglas pro"er driver "y )al$Bay (ystems $$ =a"EFE2 driver that
supports the most utiliGed commands or Electroglas 86'' series pro"e
stations
- )ascade *ro"er Driver "y Micro(ys
- Darl (uss pro"er driver "y Bloomy )ontrols
- =ucas (ignatone *ro"er Driver "y AB)DE.irm $$&he =a"EFE2 *ro"er
Fnterace !as !ritten "y AB)DE. speciically or control o the
(ignatone pro"ers% &he Fnterace is compati"le !ith +ational
Fnstruments =a"EFE2 :%6 and higher% DDE, G*FB and ActiveB
37
versions are availa"le% &he DDE and ActiveB versions allo! the
computer controlling the pro"er to also perorm test unctions%
Alternatively, a separate computer !ith a G*FB interace allo!s greater
po!er dedicated to the test processing%
6.6.; 3$o1uct' &n1 *#$vic#
Measurement and Automation (ot!are
Data Ac1uisition (DA,)
Modular Fnstruments
7eal$&ime Measurement and )ontrol
(ignal )onditioning
(!itches
Fndustrial )ontrol and Distri"uted F>3
Machine Eision
Motion )ontrollers and Motor Drives
*BF and )ompact*)F
G*FB, (erial, and Fnstrument )ontrol
(ound and Ei"ration Measurement and Analysis
EBF and EME
Fndustrial )ommunications
(ervices and &raining
&emperature Measurements
7econigura"le F>3 )ontrol and Ac1uisition
Academic *roducts
38
6.; ?u&l m&$k
6.;.1 (v#$vi#)
(*E)F.F) (3=J&F3+( &3 MEE& (*E)F.F) +EED(
,ualMar# )orporation !as ounded speciically to provide the electronic
manuacturing industry !ith Accelerated &esting e1uipment and services that
result in "ringing product to mar#et on time !ith reduced design and !arranty
costs, and improved relia"ility%
D+32=EDGE =EADE7 F+ A))E=E7A&ED &E(&F+G ME&;3D(
,ualMar# products and services are designed and reined as a result o
continual and e'tensive research and development% 2ith more than O,666 tests
conducted in ,ualMar#<s la" acilities, and installation and maintenance o over
566 cham"ers in 10 countries, ,ualMar# has earned the position as the
Dno!ledge =eader in Accelerated &esting Methods%
MADF+G (J7E C3J DEE* *A)E 2F&; &E);+3=3GC
ADEA+)EME+&(
(ome o the "iggest manuactures o consumer products, some mem"ers o the
.ortune 566 and the .ortune 1666 such as Dell, )ompa1, Ericsson, ;e!itt
*ac#ard, FBM, (amsung, and Microsot, have partnered !ith ,ualMar# to
implement and manage corporate$!ide testing programs $ *rograms driven "y
mar#et demand to provide relia"le products !hose timely releases #eep pace
!ith technology advancements%
=earn more a"out ,ualMar#<s Accelerated &esting product and services%
6.;.6 *olution &n1 p$o1uct'
,ualMar# !as ounded speciically to provide the industry !ith Accelerated
&esting systems that have a uni1ue com"ination o high rate, li1uid nitrogen
cooled thermal systems and !ide "and!idth, and si' degree o reedom
vi"ration% &hroughout the years our continuous engineering eorts have
improved the vi"ration and thermal characteristics o the systems !hile ma#ing
them more economical to operate%
,JA=MA7D &C*;33+ );AMBE7(
,ualMar#<s line o &yphoon )ham"ers incorporate li1uid nitrogen cooling into
a high ramp rate thermal system, !ith an integral si' degree o reedom
repetitive shoc# vi"ration system% .rom our smallest &yphoon$1%5 system, !ith
a 10L ' 10L vi"ration ta"le, to our largest &yphoon$O%6, !ith a O0L ' O0L
vi"ration ta"le, they all use ,ualMar#<s control system to guarantee ease o use%
2e also oer customer siGe and customer conigured systems%
! 'i># to .it +ou$ n##1'
&yphoon$1%5 !ith a 10L ' 10L vi"ration ta"le
&yphoon$8%6 !ith a 8OL ' 8OL vi"ration ta"le
&yphoon$8%5 !ith a 46L ' 46L vi"ration ta"le
39
&yphoon$4%6 !ith a 4:L ' 4:L vi"ration ta"le
&yphoon$O%6 !ith a O0L ' O0L vi"ration ta"le
&;E .=EBFBF=F&C 3. A EFB7A&F3+ 3+=C (C(&EM(
F you need a ta"le$top vi"ration system or trou"leshooting or depot repair, or
!ant to add a small vi"ration system to an e'isting thermal cham"er, then loo#
at our 3mni Ei"ration &a"le &op (3E&&) system% &his 10L ' 10L vi"ration
ta"le is housed in a patented sound reducing enclosure, ma#ing it suita"le or
use in a typical la", "ut it can also "e operated inside o a thermal cham"er%
40