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Line Harmonics On Systems Using Reduced DC-link Capacitors
Line Harmonics On Systems Using Reduced DC-link Capacitors
Line Harmonics On Systems Using Reduced DC-link Capacitors
capacitors
Hernan Miranda Delpino and Dinesh Kumar
Danfoss Power Electronics A/S
Ulsns 1, Gr sten, Denmark
a
I. I NTRODUCTION
Power electronics are a core component of most manufacturing processes, they are involved in areas such as motion control, refrigeration, heating, ventilation, among others. The most
common power electronics device is a diode bridge rectier
tied to a three-phase inverter through a DC-link capacitor. A
regular industrial facility may have around a hundred of these
drives. This is why researchers are continuously looking for
improvements in terms of robustness, dynamic performance,
life-time, etc. One particular aspect of interest for this kind of
drives is the use of a large DC-capacitor to obtain a constant
DC-link voltage.
The available literature indicates that a reduction on the DClink capacitance value has benecial aspects such as increased
life-time, less power losses, volume reduction and better grid
performance due to lower current harmonic content [1], [2].
On the downside, a reduced DC-link capacitor affects the drive
stability margin when it comes to handle constant power loads
(negative resistance loads). Most research available is regarded
to increase the stability of the system [3]-[5] taking for granted
that the line harmonics are effectively reduced.
Based on the existing literature and the clear indications
that line harmonics are reduced by use of a reduced DC-link
capacitor a study was perform to assess the harmonics of
an industrial size installation. The installation was simulated
using Saber and the harmonics compared to standard DClink capacitors drives. The results of the comparison were
surprising since not only the reduced DC-capacitor did not
improve the system harmonics, but it actually made them
signicantly higher.
This article provides the simulation results comparing the
system harmonics produced by reduced and standard DC-link
capacitor drives. A theoretical explanation is provided on why
the line harmonic prole changes as the number of drives
connected increases. Experimental results are provided where
it is shown that already for a number of drives as little as
ve the harmonics pattern experiences drastic changes. The
harmonic pattern obtain for ve drives running in parallel
resembles the harmonics of a standard DC-link capacitor
drives. This leads to the conclusion that line harmonics in
large installations are not improved by use of reduced DC-link
capacitance.
II. S YSTEM DESCRIPTION
The system under study is composed of an arbitrary number
of drives connected in parallel to the same point of common
coupling (PCC). This is the primary side of a properly sized
step-down transformer. The drives are characterized by having
a diode bridge rectier at the line side, a reduced DC-link
capacitor and a standard two-level inverter on the motor side.
The drives can be loaded differently with output powers
ranging from 0 to 7.5 [kW].
The system impedance under consideration are the transformer impedance and the grid impedance. The primary side
voltage is rated at 3.3 [kV] and the secondary side voltage at
440 [V]. The system frequency is 60 [Hz]. The grid inductance
is 53.8 H, the transformer inductance 22.8 H and a threephase 230 H inductive lter has also been included to reduce
harmonics (these inductance values are 4.7%, 2% and 20 %
of the base impedance respectively).
Figure 1 shows a diagram of the system to be studied. An
total number Nd = 60 drives are connected in parallel to the
secondary side of the step-down transformer. The DC-link
capacitance of each drive is Cdc . The capacitance value of
a standard drive is Cdc = 500F, while a reduced DC cap
drive will have Cdc = 30F. The transformer will be modelled
as ideal, with no magnetic saturation and having a series
impedance Lt . The grid is modeled as an ideal three-phase
voltage source Vg and a line inductance of Lg . The inductive
lter impedance is named L f .
Lg
Cdc
Nd
Cdc
Power [kW]
3.8
5.0
7.5
6.5
6.7
5,8
Nr. Drives
3
4
3
2
3
2
Power [kW]
1.6
1.1
1.0
0.4
0.9
0.3
of
drives.
Nr. Drives
9
11
9
2
3
4
Cdc
0.04
0.02
10
15
20
25
30
Harmonic order
35
40
45
50
0.6
0.4
0.2
0
10
15
20
25
30
Harmonic order
35
40
45
50
jCdc
=
(1)
1
1 22 LgCdc
2 jLg +
jCdc
The system presents a resonance at a frequency r =
1/ 2LgCdc where it is expected that the current and voltage
Yin =
1 drive
10 drives
20
Lg
30 drives
60 drives
100 drives
10
Nd
Admittance [dB]
0
-10
-20
-30
-40
-50
10
100
1000
Frequency [Hz]
10000
Lg
1 drive
10 drives
20
Nd Cdc
30 drives
60 drives
100 drives
10
jNd Cdc
1 22 Lg Nd Cdc
(2)
1
2LgCdc Nd
(3)
0
Admittance [dB]
-10
-20
-30
-40
-50
10
100
1000
Frequency [Hz]
10000
20
Lf
Cdc
Iload
total current A
Lg
10
0
-10
-20
-30 0
Figure 5: Single drive diagram including a three-phase inductor lter, the darker path indicates how the impedances are
connected within a commutation period.
A. Harmonic mitigation
An immediate reaction to solve harmonic problems is to add
a passive element that will lter the harmonics by increasing
the series or reducing the parallel impedances. The rst
alternative is normally realized by the introduction of a series
inductor. The second alternative is done in its simplest form by
adding a parallel capacitor. Of these two, the inductor solution
is usually preferred because it does not present the resonance
issue that appear with the use of capacitors.
Let us consider that in order to reduce the harmonics
produced by use of reduced DC-capacitance drives an inductor
L f is placed in front of each diode bridge rectier as shown in
g. 5. Using an choke inductor after the diode bridge is also
a good option, but for the analysis performed here, these two
solutions can be considered equivalent.
A series inductor has an impedance jL f that provides a
high impedance path to current harmonics. This impedance
will also reduce the voltage harmonics by a ratio close to
L f /Lg because it acts as a tension divider with the grid
impedance. It is expected then that the system harmonics will
be reduced with the use of this lter.
Let us analyze the inductance lter performance when used
in a system with Nd parallel drives. The admittance of a single
drive as seen from the grid will be given now by (4).
Yin =
1
1
2 jLg + 2 jL f +
jCdc
jCdc
(4)
1 22 (Lg + L f )Cdc
0.01
0.015
0.02
time s
0.025
0.03
0.035
0.005
0.3
0.2
0.1
0
500
1000
1500
2000
Frequency [Hz]
2500
Figure
6:
Experimental
result:
Single
drive
Ptotal = 5.8kW ,
Lg = 158H,
L f = 0,
Cdc = 30F,
fres = 1.635 kHz (theoretical)
using an inductor lter) we can see that for a sufciently large
number of drives, the resonance frequency, thus the voltage
and current harmonic patterns, will be almost the same.
res =
1
Lf
2 Lg +
Nd
(6)
Cdc Nd
This all means that a series inductor will not provide any
improvement to the harmonic performance in large systems
and we will only be left with the inductors size, power loss
and cost on the downside.
V. E XPERIMENTAL VERIFICATION
In order to verify that the admittance analysis is capable of
predicting the harmonics behavior thus supporting our statements on reduced DC-capacitance providing a worse system
harmonic performance than standard drives (as opposed to
the reviewed literature) a laboratory test was performed. Due
to practical limitations the total number of drives running in
parallel was reduced to 5, three of them working at a maximum
of 9kW, the other two at a maximum of 6kW.
The drives are connected in parallel to a 50Hz, 400Vrms grid,
with an estimated inductance of 30H. To model the stepdown transformer impedance, the drives have been connected
to a series inductance of 128H. This makes the total grid
impedance Lg = 158H.
The operation of a single drive with load power of 5.8kW
is shown in g. 6. The current waveform in 6(a) has the
50
total current A
total current A
50
0
-50
-100 0
0.005
0.01
0.015
0.02
time s
0.025
0.03
0.035
0
-50
-100
0.005
0.3
0.2
0.1
0
500
1000
1500
2000
Frequency [Hz]
0.015
0.02
time s
0.025
0.03
0.035
0.01
2500
0.3
0.2
0.1
0
500
1000
1500
2000
Frequency [Hz]
2500
The values used to model the grid and step-down transformer in the previous have a rather low per unit impedance,
the transformer impedance is 1% and the grid impedance 0.2%
of the base impedance (using as base the maximum system
power, 5 drives consuming 40kVA). To study the effect of a
higher inductance, representing a weaker grid a test was made
using a series inductance inductance of 524H. The results
are shown in g. 8.
It can be seen in g. 8(a) that the current presents hardly
any resonance after the commutation takes place. The current
spectrum in g. 8(b) strongly resembles the one of a drive
equipped with standard DC-capacitance value. This means
that for a weaker system the harmonic advantages of a
reduced DC-capacitance value are already lost and that the
strongest harmonic components are the 5th and 7th , resembling
a standard drive harmonic pattern.
The previous results come from tests where three of the
drives run at full capacity and two drives run at 5 kW (around
55% power load). A test with only three drives running full
load was done to test the effect on harmonics, the results are
shown in g. 9. It can be seen that the harmonic content is
even higher than in the case of ve drives with two running at
a reduced load shown in g. 7. This indicates that the reduced
DC capacitance drives do have better harmonic performance
when running on partial loads, since the harmonics, specially
the 5th harmonic, are certainly reduced (in per unit).
total current A
50
0
-50
-100
0.005
0.01
0.015
0.02
time s
0.025
0.03
0.035
0.3
0.2
0.1
0
500
1000
1500
2000
Frequency [Hz]
2500
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