Department of Electrical and Computer Engineering

Vishal Saxena -1-

SAR, Algorithmic and Integrating
ADCs
Vishal Saxena, Boise State University
(vishalsaxena@boisestate.edu)
Vishal Saxena -2-
2
Successive Approximation ADC
Vishal Saxena -3-
Successive Approximation ADC
3
Binary search algorithm N*T
clk
to complete N bits
Conversion speed is limited by comparator, DAC, and digital logic
(successive approximation register or SAR)
Vishal Saxena -4-
Binary Search Algorithm
4
DAC output gradually approaches the input voltage
Comparator differential input gradually approaches zero
Vishal Saxena -5-
Charge Redistribution SA ADC
5
4-bit binary-weighted capacitor array DAC (aka charge scaling DAC)
Capacitor array samples input when
1
is asserted (bottom-plate)
Comparator acts as a zero crossing detector
Vishal Saxena -6-
Charge Redistribution (MSB)
6
( ) ( )

= =
R i R
i R X 4 X 3 2 1 0 X i
V 8C- V 16C V
V 16C= V - V C - V C +C +C +C V - V
16C 2
Start with C
4
connected to V
R
and others to 0 (i.e. SAR=1000)
Vishal Saxena -7-
Comparison (MSB)
7
If V
X
< 0, then V
i
> V
R
/2, and MSB = 1, C
4
remains connected to V
R
If V
X
> 0, then V
i
< V
R
/2, and MSB = 0, C
4
is switched to ground
X
i
R
X
V
2
V
V : TEST MSB =
Vishal Saxena -8-
Charge Redistribution (MSB1)
8
( )

= = =
R i
i R X X X R i
V 12C V 16C 3
V 16C V V 12C V 4C V V V
16C 4
SAR=1100
Vishal Saxena -9-
Comparison (MSB1)
9
If V
X
< 0, then V
i
> 3V
R
/4, and MSB-1 = 1, C
3
remains connected to V
R
If V
X
> 0, then V
i
< 3V
R
/4, and MSB-1 = 0, C
3
is switched to ground
( )
=
X R i
3
MSB-1 TEST: V V V
4
X
Vishal Saxena -10-
Charge Redistribution (Other Bits)
10
Test completes when all four bits are determined w/ four charge
redistributions and comparisons
SAR=1010, and so on
Vishal Saxena -11-
After Four Clock Cycles
11
Usually, half T
clk
is allocated for charge redistribution and half for
comparison + digital logic
V
X
always converges to 0 (V
os
if comparator has nonzero offset)
X
Vishal Saxena -12-
Summing-Node Parasitics
12
If V
os
= 0, C
P
has no effect eventually; otherwise, C
P
attenuates V
X
Auto-zeroing can be applied to the comparator to reduce offset
Vishal Saxena -13-
SAR ADC Summary
13
High accuracy achievable (12+ Bits)
Low power and linear as no Opamp is required
Relies on highly accurate comparator
Moderate speed (10 MHz)
Regaining interest in scaled CMOS processes
Vishal Saxena -14-
SAR ADC Limitations
14
Conversion rate typically limited by finite bandwidth of RC network
during sampling and bit-tests
For high resolution, the binary weighted capacitor array can become
quite large
E.g. 16-bit resolution, C
total
~100pF for reasonable kT/C noise contribution
If matching is an issue, an even larger value may be needed
E.g. if matching dictates C
min
=10fF, then 2
16
C
min
=655pF
Commonly used techniques
Implement "two-stage" or "multi-stage" capacitor network to reduce array
size [Yee, JSSC 8/79]
Split DAC or C-2C network
Calibrate capacitor array to obtain precision beyond raw technology
matching [Lee, JSSC 12/84]
Vishal Saxena -15-
15
Algorithmic (Cyclic) ADC
Vishal Saxena -16-
Algorithmic (Cyclic) ADC
16
Essentially same as pipeline
But a single MDAC stage is used in a cyclic fashion for all operations
Need many clock cycles per conversion
Vishal Saxena -17-
Algorithmic (Cyclic) ADC
17
Input is sampled first, then circulates in the loop for N clock cycles
Conversion takes N cycles with one bit resolved in each T
clk
Sample
mode
Vishal Saxena -18-
Modified Binary Search
18
If V
X
< V
FS
/2, then b
j
= 0, and V
o
= 2*V
X
If V
X
> V
FS
/2, then b
j
= 1, and V
o
= 2*(V
X
-V
FS
/2)
V
o
is called conversion residue
RA = residue amplifier
Conversion
mode
Vishal Saxena -19-
Modified Binary Search
19
Constant threshold (V
FS
/2) is used for each comparison
Residue experiences 2X gain each time it circulates the loop
X
i
FS
clk
FS
Vishal Saxena -20-
Loop Transfer Function
20
Comparison if V
X
< V
FS
/2, then b
j
= 0; otherwise, b
j
= 1
Residue generation V
o
= 2*(V
X
- b
j
*V
FS
/2)

V
X
V
o
V
FS
/2 0 V
FS
V
FS
b
j
=0 b
j
=1
Vishal Saxena -21-
Algorithmic ADC
21
Hardware-efficient, but relatively low conversion speed (bit-per-step)
Modified binary search algorithm
Loop-gain (2X) requires the use of a residue amplifier, but greatly simplifies
theDAC 1-bit, inherently linear (why?)
Residue gets amplified in each circulation; the gain accumulated makes the
later conversion steps insensitive to circuit noise and distortion
Conversion errors (residue error due to comparator offset and/or loop-gain
non-idealities) made in earlier conversion cycles also get amplified again
and again overall accuracy is usually limited by the MSB conversion step
Redundancy is often employed to tolerate comparator/loop offsets
Trimming/calibration/ratio-independent techniques are often used to treat
loop-gain error, nonlinearity, etc.
Vishal Saxena -22-
Offset Errors
22
Ideal RA offset CMP offset
V
o
= 2*(V
i
- b
j
*V
FS
/2) V
i
= b
j
*V
FS
/2 + V
o
/2
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b=0 b=1
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b=0 b=1
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b=0 b=1 V
os
V
os
V
i
D
o
V
FS
/2 0 V
FS V
i
D
o
V
FS
/2 0 V
FS V
i
D
o
V
FS
/2 0 V
FS
Vishal Saxena -23-
Redundancy (DEC, RSD)
23
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b
j
=0 b
j
=1
V
FS
/2
B
j+1
=0
B
j+1
=1
V
i
D
o
V
FS
/2 0 V
FS
00
01
10
11
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b
j
=0 b
j
=1
V
FS
/2
B
j+1
=0
B
j+1
=1
B
j+1
=-1
B
j+1
=2
V
i
D
o
V
FS
/2 0 V
FS
00
01
10
11
1 CMP 3 CMPs
RSD= Redundant Signed Digit
Vishal Saxena -24-
Loop Transfer Function
24
Original w/ Redundancy
Subtraction/addition both required to compute final sum
4-level (2-bit) DAC required instead of 2-level (1-bit) DAC
V
i
V
o
V
FS
/2 0 V
FS
V
FS
b=0 b=1
V
i
V
o
V
FS
/2 0 V
FS
b=0 b=1 b=-1 b=2
Vishal Saxena -25-
Comparator Offset
25
Max tolerance of
comparator offset is
V
FS
/4 simple
comparators
Similar tolerance also
applies to RA offset
Key to understand
digital redundancy:

j
o
o
i
j
FS
V
V = +
2
b
2
V
V
b
Vishal Saxena -26-
Modified 1-Bit Architecture
26
1-b/s RA transfer curve
w/ no redundancy
One extra CMP
added at V
R
/2
0
V
R
/2
-V
R
/2
V
i
V
o
-V
R
/2 V
R
/2 -V
R
V
R
V
R
0
V
R
/2
-V
R
/2
V
i
-V
R
/2 V
R
/2 -V
R
V
R
V
R
b=0 b=1 b=0 b=1 b=0.5
Vishal Saxena -27-
From 1-Bit to 1.5-Bit Architecture
27
-V
R
/4 V
R
/4
0
V
R
/2
-V
R
/2
V
i
-V
R
V
R
V
R
b=0 b=1 b=0.5
-V
R
/4 V
R
/4
0
V
R
/2
-V
R
/2
V
i
-V
R
V
R
V
R
b=0 b=2 b=1
V
o
A systematic offset V
R
/4
introduced to both CMPs
A 2X scaling is performed
on all output bits
Vishal Saxena -28-
The 1.5-Bit Architecture
28
3 decision levels
ENOB = log
2
3 = 1.58
Max tolerance of comparator
offset is V
R
/4
An implementation of the
Sweeny-Robertson-Tocher
(SRT) division principle
The conversion accuracy
solely relies on the loop-gain
error, i.e., the gain error and
nonlinearity
A 3-level DAC is required ( )

o i R
V = 2 V - b-1 V
Vishal Saxena -29-
The Multiplier DAC (MDAC)
29
2X gain + 3-level DAC + subtraction all integrated
A 3-level DAC is perfectly linear in fully-differential form
Can be generalized to n.5-b/stage architectures
V
o
V
i
0
-V
R
V
R
Decoder

1
C
1

1
C
2

1e
A

2
-V
R
/4
V
R
/4
( )
R
1
2
i
1
2 1
o
V
C
C
1 b V
C
C C
V
+
=
( )

o i R
V = 2 V - b-1 V
Vishal Saxena -30-
A Linear 3-Level DAC
30
b = 0 b = 1 b = 2
( )
R i
T B
1
2
i
1
2 1
o o o
V V 2
V V
C
C
V
C
C C
V V V
+ =

+
=
=
+
( )
i
CM CM
1
2
i
1
2 1
o o o
V 2
V V
C
C
V
C
C C
V V V
=
+
+
=
=
+
( )
R i
B T
1
2
i
1
2 1
o o o
V V 2
V V
C
C
V
C
C C
V V V
=

+
=
=
+
V
o
-
C
1
C
2
V
o
+
C
1
C
2
A
V
T
V
B
V
o
-
C
1
C
2
V
o
+
C
1
C
2
A
V
CM
V
CM
V
o
-
C
1
C
2
V
o
+
C
1
C
2
A
V
T
V
B
Vishal Saxena -31-
Alternative 1.5-Bit Architecture
31
Ref: E. G. Soenen and R. L. Geiger, An architecture and an algorithm for fully digital
correction of monolithic pipelined ADCs, IEEE Trans. on Circuits and Systems II, vol.
42, issue 3, pp. 143-153, 1995.
-V
R
/2 V
R
/2
0
V
i
-V
R
V
R
V
R
b=0 b=2 b=1
V
o
How does
this work?
Vishal Saxena -32-
Error Mechanisms of RA
32
Capacitor mismatch
Op-amp finite-gain error and
nonlinearity
Charge injection and clock
feedthrough (S/H)
Finite circuit bandwidth
( )

o i R
V = 2 V - b-1 V
( )
( )
( ) ( )
( )
+
= =
+ +
+ +
1 2 2
o S/H i R
1 2 1 2
1 1
o o
C C C
V t f V b 1 V
C C C C
C C
A V A V
V
o
V
i
0
-V
R
V
R
Decoder

1
C
1

1
C
2

1e
A

2
-V
R
/4
V
R
/4
Vishal Saxena -33-
RA Gain Error and Nonlinearity
33
Raw accuracy is usually limited to 10-12 bits w/o error correction
R R
R
R
i
R
R
R
o
i R R
o
Vishal Saxena -34-
Static Gain-Error Correction
34
( )
+
= =
+ +
+ +
1 2 2
o i R i R
1 2 1 2
1 1
1 2
C C C
V V b V V - b V
C C
ka ka
C C
C C
A A
+
+
| | | |
= +
| |
+ +
\ . \ .
1 2
1 2
1
o i 2
i o
R 1 2 R 1 2
C C
C
V V C
A
b D = D + b
V C C V C C
kd kd
Analog-domain method:
Digital-domain method:
Do we need to correct for kd
2
error?
Vishal Saxena -35-
RA Gain Trimming
35
Precise gain-of-two is achieved by adjustment of the trim array
Finite-gain error of op-amp is also compensated (not nonlinearity)
C
1
/C
2
= 1 nominally
( )
( )
+
=
+
+

+
+
1 2
o i
1 2
1
2
R
1 2
1
C C
V V
C C
C
A
C
b 1 V
C C
C
A
V
o
-
V
o
+
i
+
i
-
X
+
X
-
1 2
1 2
Vishal Saxena -36-
Split-Array Trimming DAC
36
Successive approximation utilized to find the correct gain setting
Coupling cap is slightly increased to ensure segmental overlap
2C 1.2C
8C 4C 2C C 8C 4C 2C C
2C 1.2C
8C 4C 2C C 8C 4C 2C C
V
X
+
V
X
-
V
i
+
V
i
-
8-bit gain
1-bit sign
Vishal Saxena -37-
Digital Radix Correction
37
( )
( ) ( )
( ) ( ) ( )
( ) ( ) ( ) ( )





2 1
2 1 2 1
2 1
j j j+1
j j+1 j+2
2
j j+1 j+2
2 3
j j+1 j+2 j+3
2 3
j j+1 j+2
2 1
2 1 2 1 2 1
2 1 j+3 2 1 2 1 2
kd kd
kd kd kd kd
kd kd kd kd
kd kd kd kd kd kd
kd kd kd kd
D = b + D
= b + b + D
= b + b + D
= b + b + b + D
= b + b + b kd kd kd + b +...
+
+
| | | |
= +
| |
+ +
\ . \ .
1 2
1 2
1
o i 2
i o
R 1 2 R 1 2
C C
C
V V C
A
b D = D + b
V C C V C C
kd kd
Unroll this:
Vishal Saxena -38-
38
Integrating ADC
Vishal Saxena -39-
Single-Slope Integration ADC
39
Sampled-and-held input (V
i
)
Counter keeps counting until comparator output toggles
Simple, inherently monotonic, but very slow (2
N
*T
clk
/sample)
i
f
clk o
X
Y
Vishal Saxena -40-
Single-Slope Integration ADC
40
INL depends on the linearity of the ramp signal
Precision capacitor (C), current source (I), and clock (T
clk
) required
Comparator must handle wide input range of [0, V
FS
]
(

(

(
(

| |
(
|
(
\ .

1
i 1 o
clk
i
o
clk
clk
t I
V = t , D =
C T
V
D = ,
I T
C
I T
LSB=
C
Vishal Saxena -41-
Dual-Slope Integration ADC
41
RC integrator replaces the I-C integrator
Input and reference voltages undergo the same signal path
Comparator only detects zero crossing
i
f
clk
o
X
R
Vishal Saxena -42-
Dual-Slope Integration ADC
42
Exact values of R, C, and T
clk
are not required
Comparator offset doesnt matter (what about its delay?)
Op-amp offset introduces gain error and offset (why?)
Op-amp nonlinearity introduces INL error

( (

( (

i R
m 1 2
i 2 2
o
R 1 1
o 2 1
V V
V = t = t
RC RC
V t N
D = = =
V t N
or D =N for fixed N
X
1 2
m
os
Vishal Saxena -43-
Op-Amp Offset
43
V
i
= 0 V
i
= V
R
N
2
0 Offset Longer integration time!

V
i
D
o
0 V
R
Actual
Ideal
D
os
Vishal Saxena -44-
Subranging Dual-Slope ADC
44
MSB discharging stops at the immediate next integer count past V
t
Much faster conversion speed compared to dual-slope
Two current sources (matched) and two comparators required
V
i
Control
Logic
SHA
Cnt 1
(8 bits)
MSBs
V
X
Cmp
2
I
C
S
I
256
Cmp
1
V
t
Cnt 2
(8 bits)
LSBs
f
clk
Carry
Vishal Saxena -45-
Subranging Dual-Slope ADC
45
Precise V
t
is not required if carry is propagated
Matching between the current sources is critical
if I
1
= I, I
2
= (1+)I/256, then || 0.5/256
Itd be nice if CMP 1 can be eliminated ZX detector!
( )
( )
=
=
X
X
dV 1
I
,
dt C
dV 2
I
dt 256C
2 1 o
N W N D + =
X
1 2
t
Vishal Saxena -46-
Subranging Dual-Slope ADC
46
CMP 1 response time is not critical
Delay from CNT 1 to MSB current shut-off is not critical
constant delay results in an offset (why?)
CMP 2 response time is critical, but relaxed due to subranging
Vishal Saxena -47-
Subranging Multi-Slope ADC
47
i
X
S
f
clk
Ref: J.-G. Chern and A. A. Abidi, An 11 bit, 50 kSample/s CMOS A/D converter cell
using a multislope integration technique, in Proceedings of IEEE Custom Integrated
Circuits Conference, 1989, pp. 6.2/1-6.2/4.
Vishal Saxena -48-
Subranging Multi-Slope ADC
48
Single comparator detects zero-crossing
Comparator response time greatly relaxed
Matching between the current sources still critical
( )
( )
( )
=
=
=
X
X
X
dV 1
I
,
dt C
dV 2
I
,
dt 16C
dV 3
I
dt 256C
3 2 2 1 1 o
N W N W N D + =
Vishal Saxena -49-
Subranging Multi-Slope ADC
49
Comparator response time is not critical except the last one
Delays from CNTs to current sources shut-off are not critical
constant delays only result in offsets
Last comparator response time is critical, but relaxed due to multi-
step subranging
Vishal Saxena -50-
References
1. Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters, 2
nd
Ed., Springer, 2005..
2. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
3. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.