Challenges in CMOS

Miniaturization
Muhammad Amin Qureshi
GSSE
PAF-KIET
Why Scaling?
Increase chip packing density
Better performance (speed)
Response to switching signals
Reduced cost per transistor
Low-power consumption
Light-weight products
Increase current drive (transconductance)
Why Scaling?
Because it was Moores prediction
Number of transistors in a given chip area would
double every two years
Industry and academia have been working
hard to save Moores law
Moores Law
How to Scale?
How to Scale?
Dennards Scaling Theory Constant Electric Field
Problems in Scaling
The basic need was to reduce channel length
Short-Channel Effects
Voltage scaling
Doping scaling
Constant Electric Field voltage per unit dimension
Scaling could not follow Dennards theory
precisely, but came along nicely
Reaching physical limits


Problems in Scaling
Short-Channel Effects
Threshold voltage lowering
Depletion regions bulge
Electrostatic charge sharing between gate and
drain/source
Requires lesser gate charge
to start inversion

Problems in Scaling
Drain-Induced Barrier Lowering (DIBL)
Unintended charge sharing between drain and
source
Increase in V
DS
pulls the drain conduction band
down
Drain-to-channel depletion width expands
The potential barrier at source is lowered
Significant leakage current (I
off
)
V
T
is lowered

Problems in Scaling
DIBL

Problems in Scaling
Channel-length modulation
In saturation, I
DS
is independent of V
DS
.
The depletion region of p-n junction at drain
expands because excess V
dsat
drops across the
drain junction depletion region.
Effective channel length decreased
Current increases with V
DS

Problems in Scaling
Gate Oxide Thickness issue
T
ox
must be reduced to avoid short-channel effects
Inherits some more problems
Only a few atomic layers thick
Quantum-mechanical activity occurs
Exponentially increasing gate leakage currents
Direct Tunneling of electrons beyond gate in to the channel
Use of High-K Oxide or Metal Gate
Metal gates are back because no depletion
Implementation challenges at sub-100nm regime
Problems in Scaling
Gate Oxide Issues
The gate might damage due to the flowing
currents
Problems in Scaling
Subthreshold Leakage
Current in channel does not abruptly becomes
zero below threshold
Or.. the more thermally energetic electrons
overcome the potential barrier to enter the
channel while the V
GS
< V
TH

Subthreshold conduction

Problems in Scaling
Heavy doping to reduce DIBL and SCE
Results in:
Increased Lateral Electric Field
GIDL
BTBT
Low mobility of electrons due to impurity
scattering
Larger capacitance in high depletion-charge
channel; reduced on current

Problems in Scaling
Band-to-Band Tunneling
Heavy doping causes higher electric fields
BTBT happen near drain and make a bendbending
of 1-2V for 100 distance
Gate-Induced Drain Leakage
Gate overlaps the drain
Gate at negative voltage; drain at high voltage
High doping = Narrow depletion region
Tunneling of electrons from the channel to drain
Problems in Scaling
Mobility Degradation
Due to high doping and thus high electric fields
Carriers are pushed towards the Si-SiO
2
interface
Surafce scattering
Imputrity scattering the dopants
Random Dopant Distribution
Doping in channel is highly random
Only a few hundred dopants in sub-100nm
devices
Random dopants in a retrograde channel doping
Trends

Trigate Transistor 22nm (Intel)
Trigate Benefits
Power
Power was not discussed
A bottle-neck for higher performance
Static power governed by subthreshold leakage
and gate leakage
Dynamic power governed by switching
Though Dennards theory maintained power
density per chip, it increased in implementation
Millions/billions of transistors per chip
Though only a few percent switch at a time
Still a lot of power
Limit the operation frequency
Conclusion
Moores law and Dennards theory are going to
end, for the current CMOS technology at least
New technologies required to cope up with the
performance requirements and packing more
logic into the chips
Intels trigate transistor is a revolutionary
invention
Silicon and CMOS will stay a bit longer
Early introduction of 22nm in 2012