MC9232-MICROPROCESSOR AND ITS APPLICATIONS

UNIT I -THE 8086 PROCESSOR - SOFTWARE ASPECTS

PART-A
1.What i !i!"#i$i$%&
Fetching the next instruction while the current instruction executes is called pipelining.
2.What a'" th" i%$a# i$()#("* i$ +"+)', -a$. "#"/ti)$ i$ 8086 +i/')!')/")'&
Entire memory is divided into two memory banks : bank
0
and bank
1
. Bank
0
is selected only when A
0

is ero and Bank
1
is selected only when B!E is ero .A
0
is ero "or all even addresses. #o bank
0
is
usually re"erred as even addressed memory bank.B!E is used to access higher order memory
bank $ re"erred to as odd addressed memory bank.
3.H)0 /#)/. i%$a# i %"$"'at"* i$ 8086& What i th" +a1i+2+ i$t"'$a# /#)/. 3'"42"$/, )3
8086&
%he crystal oscillator in &'&( generates a s)uare wave signal at the same "re)uency as the crystal .
%he maximum internal clock "re)uency o" &0&* is +,h
5.What i th" 2" )3 MN6M7 i%$a# i$ 8086&
-t is used to operate the microprocessor in two operating modes i.e. maximum and minimum mode.
%he minimum mode is used "or small systems with a single processor and maximum mode is "or
medium sie to large systems$ which include two or more processors.
8.H)0 +a$, *ata #i$" a$* a**'" #i$" a'" a(ai#a-#" i$ 8086&
Address lines. '0 bit address bus
/ata lines. 1* bit data bus
6.What i$3)'+ati)$ i /)$(","* 0h"$ 91 a$* 90 a'" 01&
0s
1
and 0s
0
are output signals that re"lect the status o" the instruction )ueue. 1hen 0s1 and 0s0 are
01 $ then )ueue has "irst byte o" an opcode.
:.What i th" a**'"i$% +)*" )3 MO; A7< 88H =>7? =SI? &
,23 A4$ ++! 5B46 5#-6 7 Base -ndexed memory addressing mode.
8.What ha!!"$"* i$ 8086 0h"$ DEN @0 a$* DTR@1 &
%his signal in"orms the transceivers that the 89: is ready to send data.
9.What i th" 2" )3 I$t'2/ti)$ 92"2" i$ 8086 +i/')!')/")'&
%he )ueue operates on the principle o" "irst in "irst out5F-F26. #o that the execution unit gets the
instruction "or execution in the order they "etched .Feature o" "etching the next instruction while the
current instruction is executing is called pipelining which will reduce the execution time.
10.What a'" th" i%$a# 2"* i$ 8086 +a1i+2+ +)*" )!"'ati)$&
0s
1
$0s
0
$ s
0
$s
1
$ s
'
$ ;28<$ =0>?%
1
$ =0>?%
0
are the signals used in &0&* maximum mode operation.
11.W'it" th" iA" )3 !h,i/a# +"+)', a$* (i't2a# +"+)', )3 8086 +i/')!')/")'.
9hysical addresses are "ormed when the le"t shi"ted segment base address is added to the o""set
address. %he combination o" segment register base addresses and o""set address is the logical address
in memory.
#ie o" physical memory.'
'0
.1,B
#ie o" virtual memory.'
1*
.*( <B
12.What a'" th" "%+"$t '"%it"' )3 8086&
8#@ 8ode segment$ /#@/ata segment$ E#@Extra segment$ ##@ #tack segment.
13.Lit th" a*(a$ta%" )3 2i$% "%+"$t '"%it"' i$ 8086.
-t allows the memory addressing capacity to be 1,B even though the address associated
with individual instruction is only 1*@bit.
-t "acilitates use o" separate memory areas "or program $ data and stack.
-t allows the program to be relocated which is very use"ul in multiprogramming.
15.E1!#ai$ th" >HE a$* LOCB i%$a# )3 8086
BHE (Bus High Enable): ;ow on this pin during "irst part o" the machine cycle indicates that at least
one byte o" the current trans"er is to be made on higher byte A/1+@A/&.
LOCK: %his signal indicates that an instruction with a ;28< pre"ix is being executed and the bus is
not to be used by another processor.
18.Na+" a$, 3)2' 3#a% )3 8086.
Auxiliary carry "lag5AF6$ 8arry "lag58F6$ /irection "lag5/F6$ -nterrupt "lag5-F6$ 2ver"low "lag52F6$
9arity "lag69F6$
#ign "lag5#F6$ %rap "lag5%F6$ Aero "lag5AF6.
16.H)0 th" !h,i/a# a**'" 3)' 3"t/hi$% th" $"1t i$t'2/ti)$ t) -" "1"/2t"*< i )-tai$"* i$
8086&
%he physical address is obtained by appending "our eros to the content present in 8# register and
then adding the content o" -9 register with the above value .
For example$ assuming the content o"
8# . 1'00 !
-9 . 0B(+ !
8#. 0001 0010 0000 0000 0000
0000 0011 0100 0101
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
0001 0010 0011 0100 0101 7 9hysical address.1'B(+ !
1:.I3 th" "1"/2ti)$ 2$it %"$"'at" "33"/ti(" a**'" )3 53A2 H a$* th" DS '"%it"' /)$tai$
5000 H. What 0i## -" th" !h,i/a# a**'" %"$"'at"* -, th" >IU& What i th" Ma1i+2+ SiA"
)3 th" *ata "%+"$t&
E""ective address . (BA' !
9hysical address . (0000 !
@@@@@@@@@@@@@
((BA' !
,aximum sie o" /# . '
1*
. *( <B
18. D"3i$" +i/')!')/")'&
A microprocessor is a multipurpose$ programmable$ clock@driven$ register 7based
electronic device that reads binary instructions "rom a storage device called memory . Accepts
binary data as input and processes data according to instructions$ and provides result as
output.
19.What i th" *i33"'"$/" -"t0""$ O!/)*" a$* O!"'a$*&
2pcode is the part o" an instruction that identi"ies a speci"ic operation.
2perand is a part o" an instruction that represents a value on which the instruction acts.
Example: ,3- A $1&!
,3- A is 2pcode and 1& ! is 2perand.
20.What i Sta/. a$* S2-')2ti$"&
#tack @-t is a reserved area o" the memory in the =A, $ where temporary in"ormation may be stored.
#ubroutine@-t is a group o" instructions written "rom the main program to per"orm a "unction that
occurs repeatedly in the main program.
21.Wh, a**'" -2 i 2$i*i'"/ti)$a#&
-t is a 1* bit communication line5A0@A1+6.-t is used to indicate the location o" data . #ince the data
"lows "rom ,9: 5microprocessor unit6 to 9eripheral devices$ the address bus is unidirectional.
22.Wh, *ata -2 i -i-*i'"/ti)$a#&
%he microprocessor has to "etch 5read6 the date "rom memory or input device "or processing and
a"ter processing $ it has to store 51rite 6 the data to memory or output device. !ence the data bus is
bi@directional. i.e. data "low "rom the ,9: 5microprocessor unit 6to peripherals or peripherals to
,9:.
23.What i 3"t/h a$* "1"/2t" /,/#"&
%he "etch cycle is executed to "etch the opcode "rom memory.
%he Execute cycle is executed to decode the instruction and to per"orm the work instructed by the
instruction.
25.What i a$ i$t"''2!t&
-nterrupt is a signal send by an external device to the processor so as to re)uest the processor to
per"orm a particular task or work.
28.D"3i$" =a?I$t'2/ti)$ C,/#" =-? M6C C,/#" =/? T-tat"
Instruction cycle : %ime re)uired to complete the execution o" an instruction. 2ne instruction cycle
consists o" B to * machine cycles.
Machine cycle: %ime re)uired to complete one operation o" accessing memory or ->2 device.2ne
machine cycle consists o" B to * %@states.
!"tate: %he portion o" the operation per"ormed in one clock period.
PART->
1. /raw the &0&* "unctional block diagram and explain its architectural "eatures.
'. Explain the classi"ication o" the instruction set o" &0&* microprocessor with suitable examples.
B. Explain in detail about the various addressing modes used in &0&* processorC ?ive examples.
(./iscuss in detail about the interrupts and -nterrupt #ervice =outine 5-#=6 with interrupts cycle o"
&0&*.
+.1hat are assembler directivesC Explain
UNIT II -8086 SCSTEM DESIDN
1.M"$ti)$ th" 32$/ti)$ )3 SI a$* DI '"%it"'.
#-: #ource -ndex
-t is used to hold the index value o" source operand 5data6 "or string instructions.
/-: /estination -ndex
-t is used to hold the index value o" destination operand 5data6 "or string instructions .-t is used "or
single stepping through a program.
2.Na+" a$, 8 !')/")' /)$t')# i$t'2/ti)$.
8;8$ 1A-%$ 8,8$ !;%$ #%8$ ;28<$ #%/$ D29.
20.What i +"a$t -, )3t0a'" i$t"''2!t i$ 8086&
%he so"tware interrupts are program instructions. %hese instructions are inserted at desired locations
in a program. 1hile running a program $ i" a so"tware interrupt is encountered then the processor
executes an interrupt service routine 5-#=6.
3.What i th" 32$/ti)$ )3 TF<DF <IF i$ 8086&
%F: -t is used "or single stepping through a program. -n the mode$ the &0&* generates an internal
interrupt a"ter execution o" each instruction.
/F: -t is used to set direction in string operation.
-F: -t is used to receive external maskable interrupts through -D%= pin. 8learing -F$ disable these
interrupts.
22.What i )!"'ati)$ /a''i"* )2t 0h"$ 8086 "1"/2t" th" i$t'2/ti)$ MO;S> &
,23#B 7 ,ove #tring Byte
EE/-FF EE#-FF
,ove & bit data "rom memory location addressed by #- segment in /# location to addressed by /-
in segment E#.
-" /F 5/irection Flag6 . 0$ #- is incremented by 1.
. 1$ #- is decremented by 1.
5.What i th" )!"'ati)$ /a''i"* )2t Wh"$ 8086 "1"/2t" th" i$t'2/ti)$ MO;SW &
,23#1 7 ,ove #tring 1ord.
%his instruction trans"ers a word "rom the source string 5addressed by #-6 to the destination string
5addressed by /-6 and update #- and /- to point to the next string element.
8.What a'" th" *i33"'"$/" -"t0""$ 8088 a$* 8086&
.$) 8088 8086
1 & bit microprocessor 1* bit microprocessor
'. '
1*
memory locations '
10
memory locations
B. #e)uential "acility 9ipelined architecture available
(. ;ow speed !igh speed
6.Stat" th" 32$/ti)$a# 2$it a(ai#a-#" i$ 8086&
B-:@ Bus -nter"ace :nit
E:@ Execution :nit
:.Stat" th" +)*" i$ 0hi/h 8086 )!"'at"&
,inimum mode
,aximum mode.
PART->
1.Explain the signal description o" &0&*.
'.Explain and draw the system bus timing diagram o" &0&*.
B.Explain the minimum mode con"iguration o" &0&* with neat diagram
B.Explain the maximum mode con"iguration o" &0&* with neat diagram
UNIT III -INTERFACIND CONCEPTS
1.What i th" !2'!)" 3)' th" 8288 PPI&
%he &'++A is a widely used$ programmable$ parallel ->2 device.-t can beprogrammed to trans"er data under various
conditions$ "rom simple ->2 to interrupt ->2.
2. Lit th" )!"'ati$% +)*" )3 8288A PPI&
G%wo &@bit ports 5A and B6
G%wo (@bit ports 58uand 8;6
G/ata bus bu""er
G8ontrol logic
3. S!"/i3, th" -it )3 a /)$t')# 0)'* 3)' th" 8288< 0hi/h *i33"'"$tiat" -"t0""$ th"I6O +)*" a$*
th" >SR +)*"&
B#= mode /H. 0$ and ->2 mode /+ . 1
5. W'it" th" i$!2t6)2t!2t 3"at2'" i$ M)*" 0 3)' th" 8288A PPI&
2utputs are latched
-nputs are not latched
9orts do not have handshake or interrupt capability
8W'it" *)0$ th" )2t!2t /)$t')# i%$a# 2"* i$ 8288A PPI&
G2BFoutput Bu""er Full
GA8<Acknowledge
G-D%= -nterrupt re)uest
G-D%E -nterrupt Enable
6. What i th" 2" )3 +)*" 2 i$ 8288A PPI&
%his mode is used primarily in applications such as data trans"er betweentwo computers or "loppy disk controller
inter"ace
:.Lit th" +aE)' /)+!)$"$t )3 82:9 .",-)a'* 6*i!#a, i$t"'3a/"&
G <eyboard section
G#can section
G/isplay section
G,9: inter"aceI.
8.What i th" !2'!)" 3)' /a$ "/ti)$ i$ B",-)a'* i$t"'3a/"&
%he scan section has a scan counter and "our scan lines. %hese scan linescan be decoded using a (@to@1* decoder to
generate 1* lines "or scanning.
9.What i USART&
:#A=% is an integrated circuit.-t is a programmable device Jits "unctionand speci"ications "or serial ->2 can be
determined by writing instructions in itsinternal registers .
10.D"3i$" >a2*&
%he rate at which the bits are transmitted is called Baud
11. D"3i$" !a'a##"#-t)-"'ia# /)$("'i)$&
-n serial transmission$ an &@bit parallel word should be converted in to astream o" eight serial bits. %his is known as
parallel@to@serial conversion
12.D"3i$" "'ia#-t)-!a'a##"# /)$("'i)$&
-n serial reception$ the ,9: receives a stream o" eight bits and it isconverted in to &@bit parallel word. %his is known as
serial @to@ parallel conversion.
13. D"3i$" i+!#"1 t'a$+ii)$&
-n simplex transmission$ data are transmitted in only one direction.Example: transmission "rom a microcomputer to a
printer.
15. What i t'a$+itt"' "/ti)$ i$ USART&
%he transmitter section accepts parallel data "rom the ,9: and convertsthem in to serial data. -t has two registers. A
bu""er register and an output register
18. W'it" a$ i$t'2/ti)$ 3)' "'ia# )2t!2t *ata&
,3- A$ &0! J#et /H in the accumulator . 1=A= J#et /* . 1#-,
16. Lit th" +aE)' /)+!)$"$t )3 8281A !')%'a++a-#" /)++2$i/ati)$ i$t"3a/"&

G=ead>1rite control logic
G%hree bu""er registers
G/ata register
G8ontrol registertransmission receiver
G/ata bus bu""er
G,odem control
1:.W'it" th" t"! $"/"a', t) i$itia#iA" a /)2$t"' i$ 0'it" )!"'ati)$&
G1rite a control word into the control register
G;oad the low@order address byte
G;oad the high order byte
18.Di(" th" (a'i)2 +)*" )3 8285 ti+"'&
,ode 0: interrupt or terminal count
,ode 1: =ate generator
,ode B:s)uare wave generator
,ode (: so"tware triggered strobe
,ode +:hardware triggered strobe
19. What i '"a* -a/. /)++a$* i$ 8285 ti+"'&
%he =ead@ Back 8ommand in &'+( allows the user to read the count andthe status o" the counter.
PART->
1.Explain the architecture o" &'++ 99- in detail.
'. Explain the architecture o" &'+I in detail.
B. Explain the architecture o" &'+1 in detail.
(. Explain the architecture o" &'HI in detail.
+. Explain the architecture o" &'+B in detail and explain the working o" modes with
timing diagram.
*. .Explain the architecture o" /,A controller in detail
UNIT I;- AD;ANCED PROCESSORS
1. What i th" *i33"'"$t /#)/. 3'"42"$/i" 2"* i$ 80286&
3arious versions o" &0'&* are available that run on 1'.+,!$ 10,! and
&,! clock "re)uencies.
2. D"3i$" 0a!!i$% i$&
%he portion o" a program is re)uired "or execution by the 89:$ it is "etched "rom the secondary
memory and placed in the physical memory. %his is called swapping inK o" the program.
3. What a'" th" *i33"'"$t )!"'ati$% +)*" 2"* i$ 80286&
%he &0'&* works in two operating modes
1. =eal addressing mode
'. 9rotected virtual address mode.
5. What a'" th" CPU /)$t"$t 2"* i$ 80286&
%he &0'&* 89: contains almost the same set o" registers$ as in &0&*
L Eight 1*@bit general purpose register
L Four 1*@bit segment registers
L #tatus and control register
L -nstruction pointer.
8. What i tat2 3#a% -it&
%he "lag register re"lects the results o" logical and arithmetic instructions. %he "lag register digits /0$
/'$ /($ /*$ /H and /11 are modi"ied according to the result o" the execution o" logical and
arithmetic instruction. %hese are called as status "lag bits.
6. What i a /)$t')# 3#a%&
%he bits /& and /I namely$ trap "lag 5%F6 and interrupt "lag 5-F6 bits$ are used "or controlling
machine operation and thus they are called control "lags.
:. What i i$t'2/ti)$ !i!"#i$i$%&
,aMor "unction o" the bus unit is to "etch instruction bytes "rom the memory. -n "act$ the instructions
are "etched in advance and stored in a )ueue to enable "aster execution o" the instructions. %his
concept is known as instruction pipelining.
8. What i 0a!!i$%&
%he procedure o" "etching the chosen program segments or data "rom the secondary storage into the
physical memory is called NswappingK.
PART->
1.1ith a neat diagram explain the architecture o" &0'&*C
'.Explain in detail about the modes o" operation o" &0'&*
B 1ith a neat diagram explain the architecture o" &0B&*C
(. 1ith a neat diagram explain the architecture o" 9entium processorsC
+.Explain the architecture o" &0(&* with a neat diagramC
UNIT ;- >UILDIND SCSTEMS
1.What iPCI&
%he 9eripheral 8omponent -nter"ace O98-O Bus was originally developed as a local bus expansion "or
the -#A>E-#A 598>A%6 bus. 98- architecture allows bus mastering o" multiple devices on the bus
simultaneously$ with the arbitration circuitry working to ensure that no device on the bus
5including the processor6 locks out any other device
2. What i US>&
:#B is :niversal #erial Bus and it a computer peripheral inter"ace.
:#B provides a serial bus standard "or connecting peripherals devices to 98 with simpli"ied
addition and removal.
3.What i -2&
A bus is a common pathway to connect various subsystems in a computer system. A bus consist o"
the connection media like wires connectors$ and a bus protocol. Buses can be serial$ or parallel$
synchronous or asynchronous.
5. What a'" th"F"at2'" )3 US>&
L#impli"ies the connection process and enables instantaneous addition and removals o" peripherals
L98 acts as host.once plugged 98 automatically detects peripherals and con"igures them.
L8onnects peripherals with ( wire connection.
L#upports B data rates (&0 ,bps 5:#B '65high#peed6 1' ,bps 5"ull speed6and 1.+ ,bps5low
speed6used to connect human inter"ace devices such as mouse$ keyboard etc.
8. What a'" th" US> U"&
L !uman -nter"ace /evices
7 <eyboards$ mice$ Moysticks$ game controllers
7 ;ow@speed$ interrupt data trans"er
L ,ice are polled every & ms$ respond with B' bits
L ,ass #torage /evices
PART->
1./escribe in detail o" 9eripheral component interconnect598-6 busC
'.Explain in detail about the :niversal #erial busC
B./iscuss about the Bus standards and bus concepts C