Tea 5764

* Philips Semiconductors
* Composed by: D. Janta, W. Brummelman

* Comm. No.: TEA5764
* Type: N53370
* Version: 2.7
Preliminary IC Specication V2.7 - TEA5764
CONFIDENTIAL
Accepted: IPM Dept. Date: 2004 Nov 09
Page: 1
NECTAR-R
TEA5764
FM-RADIO + RDS
Author: Wim-Jan Brummelman
Date: 2004 Nov 09
Reference Number: RNB-C/2631/2004XI-1545
Version: 2.7
Status: Approved
VERSION: CHANGES: DATE AUTHOR
1.1 - 6 feb 2003 WJ Brummelman
1.3 - 1 apr 2003 WJ Brummelman
1.4 see chapter 23 revision history 9 apr 2003 WJ Brummelman
2.0 Upgraded to V2.0, see chapter 23 revision history 4 jul 2003 WJ Brummelman
2.1 Updated SWPORT output, see chapter 23 revision history 10 jul 2003 WJ Brummelman
2.2 see chapter 23 revision history 28 jan 2004 WJ Brummelman
2.4 added Chip Scale Package pinning and die size information 04 feb 2004 WJ Brummelman
2.5 see chapter 24 revision history 03 jun 2004 WJ Brummelman
2.6 see chapter 24 revision history 04 jun 2004 WJ Brummelman
2.7 see chapter 24 revision history 09 nov 2004 WJ Brummelman
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 2
CONTENTS
1 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 ELECTRICAL PARAMETERS GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 FM / RDS OVERALL SYSTEM PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 FIGURE 1: BLOCKDIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 PINNING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1 Low Noise RF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.2 FM Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.5 PLL Tuning System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.6 Band Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.7 RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.8 Local / DX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.9 IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.10 FM Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.11 IF Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.12 Level Voltage Generator and Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.13 Softmute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8.14 Hard Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.15 Audio Frequency Mute - AFM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.16 MPX Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.17 Signal depending Mono/Stereo Blend (Stereo Noise Cancellation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.18 Software Progammable Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.19 Stand-By . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.20 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.21 RDS/RBDS Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.22 RDS Data and Clock Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.23 RDS/RBDS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.24 Audio Pause Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.25 Autosearch and preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.25.1 Auto Hi-Lo side injection stop switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.25.2 Muting during search or preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.26 RDS update / Aternative Frequency Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8.26.1 Muting during RDS update.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 INTERRUPT HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1.1 Interrupt clearing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1.4 Interrupt flags and behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.4.1 Multiple interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.4.2 Data available: DAVFLG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.4.3 RDS synchronisation: LSYNCFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.4.4 IF Frequency: IFFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.4.5 RSSI threshold: LEVFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1.4.6 Pause Detection: PDFLAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1.4.7 Frequency ready: FRRFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 3
9.1.4.8 Band limit: BLFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2 Interrupt Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 RDS DATA PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.1 DAV-A Processing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.2 DAV-B Processing mode / Fast PI search mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.3 DAV-C Reduced Processing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.4 Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4.1 Conditions for synchronisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.4.2 Data Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.5 RDS Flag behaviour during read action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.6 Error detection and reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.7 RDS test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.8 RDS data - Reading from the registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
11.1 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
12 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.1 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
14 AC / DC CHARACTERISICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
15 LIMITING VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
16 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
17 PACKAGE OUTLINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
18 OUTLINE-WFBGA34-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
19 SOLDERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.4 Manual soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.5 Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . . . . . . . . . . 61
20 DATA SHEET STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
21 DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
22 DISCLAIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
23 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
24 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 4
1 FEATURES
Chip Scale Package
High sensitivity due to integrated low noise RF input amplifier
FM mixer for conversion of the US/Europe (87.5MHz to 108MHz) and Japanese FM band (76 MHz to 90MHz) to IF
Preset tuning to receive Japanese TV audio up to 108MHz, raster 100kHz
RF Automatic Gain Control circuit
LC tuner oscillator operating with low cost fixed chip inductors
Fully integrated FM IF selectivity
Fully integrated FM demodulator, no external discriminator
Crystal reference frequency oscillator. The oscillator operates with a 32768Hz clock crystal.
PLL synthesizer tuning system
IF counter, 7 bit output via bus
Level detector, 4 bit level information output via the bus
Soft mute
Signal depending mono/stereo blend (SNC, stereo noise canceling)
Soft mute, SNC can be switched off via the bus
Adjustment free stereo decoder
Autonomous search tuning function
Stand-by mode
MPX output
One software programmable port
Fully integrated RDS/RBDS demodulator in accordance with EN50067
RDS/RBDS decoder with memory for two RDS data blocks provides block synchronization and error correction.
Block data and status information are available via the I
2
C-bus.
Audio Pause Detector
Interrupt flag
Suitable for automotive temperature range with supply voltages of 5Volt
2 GENERAL DESCRIPTION
The TEA5764 is a single chip electronically tuned FM stereo radio with RDS/RBDS demodulator and RDS/RBDS
decoder for low voltage application with fully integrated IF selectivity and demodulation.
The radio is completely adjustment free and does only require a minimum of small and low cost external components.
The radio can tune the European-, US- and Japan FM bands. The Radio does not meet all of the requirements from
EN55020 a trade off was done to make possible the previously stated features. The IC is available in HVQFN package
and in Chip Scale Package.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 5
3 ELECTRICAL PARAMETERS GENERAL
NOTE: The listed parameters are valid when a crystal is used which meets the requirements as stated in chapter 14
AC/DC Characteristics.
NR SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
G1 V
CC
analog supply voltage at pin 34 2.5 2.7 3.3 V
G2 I
CC
analog supply current pin 34 10 13.7 18 mA
G3 I
CCSB
stand-by supply current pin 34 0 1.0 5.0 A
G4 V
DD
digital supply voltage at pin 15 2.5 2.7 3.3 V
G5 I
DD
digital supply current pin 15
includes RDS current (page 52)
0.3 0.7 1.5 mA
G6 I
DDSB
digital stand-by current pin 15 10 18 25 A
G8 V
VREFDIG
Digital Reference Voltage for
Bus-interface
V
VREFDIG
<= V
DD
1.65 1.8 V
DD
V
G9 I
VREFDIG
digital pin reference current pin 9 Nominal, V
VREFDIG
=1.8V 0 0.5 1 A
G10 f
FMant
FM input frequency 76 108 MHz
T
amb
operating ambient temperature V
DD
, V
CC
=2.7V
V
VREFDIG
=1.8V
20 +85 C
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 6
4 FM / RDS OVERALL SYSTEM PARAMETERS
5 ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
RF
Sensitivity EMF value f
RF
= 76 to 108MHz
f=22.5kHz, f
mod
= 1kHz
(S+N/N)=26dB,
deemphasis = 75s, L=R
B
AF
= 300Hz to 15kHz
2 3.5 V
IP3
in
inband 3rd-order intercept point
related to V
36-37
(peak value)
f
1
=200kHz, f
2
=400kHz
f
tuned
= 76 to 108MHz
81 87 dBV
IP3
out
outband 3rd-order intercept point
related to V
36-37
(peak value)
f
1
=4MHz, f
2
=8MHz
f
tuned
= 76 to 108MHz
87 93 dBV
S
-200
low side 200kHz selectivity f=-200kHz
f
RF
= 76 to 108MHz
32 36 dB
S
+200
high side 200kHz selectivity
low side and high side selectivity
can be switched by changing the
mixer from high side to low side
LO injection
f=+200kHz
f
RF
= 76 to 108MHz
39 43 dB
V
outL
,V
outR
L-, R audio output voltage V
RF
= 1mV, L=R,
f=22.5kHz, f
mod
= 1kHz
deemphasis = 75s
60 75 90 mV
(S+N/N) maximum signal-to-noise ratio f
RF
= 76 to 108MHz
V
RF
= 1mV, L=R
f=22.5kHz, f
mod
= 1kHz
deemphasis = 75s
B
AF
= 300Hz to 15kHz
56 59 dB
sep
stereo channel separation V
RF
= 1mV, R=1,L=0 or
R=0, L=1,f
mod
=1kHz,
f
pilot
=6.75kHz,
f
L
=67.5kHz, f
R
=0 or,
f
R
=67.5kHz, f
L
=0
27 33 dB
THD total harmonic distortion
measured at pins VAFL, VAFR
V
RF
= 1mV, L=R, f=75kHz,
f
mod
= 1kHz, no pilot,
deemphasis = 75s
0.4 0.9 %
V
inRF
RDS Sensitivity EMF value f=22.5kHz, f
AF
= 1kHz,
L=R, f
RDS
=2kHz,
deemphasis = 50s,
Block Quality Rate >= 95%
SYM_1=0 and SYM_0=0
12
18
V
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
TEA5764HN HVQFN40 plastic micro leadframe package;40 leads; body 6 6 0.9 mm SOT618AB1
TEA5764UK WL-CSP Chip Scale Packaging / Flip-Chip; 34 bumps; die size 4 x 4 x 0.4 mm WFBGA34-2
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 7
6 FIGURE 1: BLOCKDIAGRAM
note: total of 23 external components including xtal and 12pF capacitor connected to pin 33
F
M

A
N
T
3
3
n
2
7
p
LEFT
RIGHT
C
L
O
C
K
D
A
T
A
MPXOUT
3
2
.
7
6
8
k
H
z
3
2
9
2
9
2
8
2
7
2
6
2
5
1
7
1
0
1
8
1
9
2
0
2
2
2
3
1
s
t

F
M
I
/
Q
-
M
I
X
E
R
:

2
N
1
I
F

F
I
L
T
E
R
L
I
M
I
T
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R
L
E
V
E
L
D
E
M
O
D
G
A
I
N
S
T
A
B
I
I
F

C
O
U
N
T
MPX DECODER
SDS
I
2
C

B
u
s
V
C
O
P
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l
o
t
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r
e
f
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A
d
j
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t
A
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5
7
6
4
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0
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X
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d
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v

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d
i
v

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t
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3
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T
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n
o
1
6
1
2
1
1
S
O
F
T
M
U
T
E
2
4
4
7
p
1
0
0
p
L
1
3
3
n
3
3
n
4
7
k
D
1
D
2
L
3
L
2
3
4
n
.
c
.
3
3
3
4
3
5
3
6
3
7
3
8
n
.
c
.
5
7
k
H
z

B
P

F
I
L
T
E
R
R
D
S
/
R
B
D
S
I
N
T
X
I
N
T
E
R
F
A
C
E
R
E
G
I
S
T
E
R
D
E
C
O
D
E
R
BUSENABLE
o
p
t
i
o
n
a
l

i
n
p
u
t

f
o
r
VREF DIG
n
.
c
.
i
n
t
c
o
n
1
SWPORT
8
V
D
D
1
2
3
3
n
7
6
5
V
C
C
3
3
n
3.7
33n
MPXIN
i
n
t
c
o
n
2
C
D
3
2
1
1
3
1
4
1
5
n
.
c
.
P
a
u
s
e
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e
t
e
c
t
o
r
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C
T
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G

S
Y
S
T
E
M
+
1
0
n
3
3
n
1
2
1
0
0
k
1
0
k
1
0
n
4
0
n
.
c
.
n
.
c
.
3
9
12pF
X
1
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 8
Table 1 List of components
SYMBOL PARAMETER TYPE MANUFACTURER
D1,D2 varicap for VCO tuning BB202 Philips
L1 RF band lter coil 120nH, 0603CS series or equivalent
Qmin = 20, tolerance: +- 5%
Coilcraft, Murata
L2,L3 VCO coil 33nH, 0603CS series or equivalent
Qmin = 40, tolerance: +- 2%
Coilcraft,Murata
X1 32.768KHz Crystal see section 14 AC/DC characteristics
R 10k, 47k, 100k +- 10% max
C 12p, 27p, 47p, 100p, 10n(2x),
33n(8x)
+- 10% max
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 9
7 PINNING
SYMBOL PIN WL-CSP
position
DESCRIPTION
LOOPSW 1 A1 Switch output of synthesizer PLL loop lter
CPOUT 2 B2 charge pump output of synthesizer PLL
LO1 3 A2 Local oscillator coil connection
LO2 4 A3 Local oscillator coil connection
CD1 5 A4 VCO supply decoupling capacitor
RDSLP 6 B4 RDS loop lter
SWPORT 7 A5 software programmable port
BUSENABLE 8 A6 Bus enable
VREFDIG 9 B6 Digital reference for bus signals
CLOCK 10 A7 Bus clock line input
DATA 11 B7 Bus data line input/output
NC1 12 - not connected
DGND 13 C7 digital ground
DGND 14 D6 digital ground
VDD 15 D7 Digital supply voltage
CD2 16 E7 VDD decoupling capacitor
INTCON2 18 E6 internally connected
DGND 19 F7 digital ground
INTX 20 G7 Interrupt pin
INTCON1 22 F6 internally connected
TMUTE 23 G6 time constant for soft mute
VAFR 24 G5 Right audio output
VAFL 25 F4 Left audio output
MPXOUT 26 G4 FM demodulator MPX output
MPXIN 27 G3 MPX decoder and RDS decoder MPX input
DGND 28 G2 digital ground, this pin has an internal pull-down resistor of 10 k to
ground.
AGND 30 F2 Analog ground
FREQIN 32 G1 input for 32.768kHz reference frequency
XTAL 33 F1 crystal input crystal oscillator
VCC 34 E1 Analog supply voltage
CD3 35 D2 VCC decoupling capacitor
RFIN1 36 D1 RF input1
RFIN2 37 C1 RF input2
RFGND 38 C2 RF ground
CAGC 39 B1 time constant RF AGC
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 10
Fig.2 HVQFN40 Pin configuration - Topview
C
P
O
U
T
RFIN2
RFGND
RFIN1
A
G
N
D
XTAL
CAGC
CD3
R
D
S
L
P
B
U
S
E
N
A
B
L
E
DATA
C
L
O
C
K
DGND
NC1
INTX
I
N
T
C
O
N
1
1 2 3 4 5
TEA5764HN
30
6 7 8 9 10
32
31
11
12
13
14
15
16
17
18
19
20
21 22 23 24
25 26 27 28 29
33
34
36
35
38
37
39
40
V
A
F
R
T
M
U
T
E
V
A
F
L
M
P
X
I
N
M
P
X
O
U
T
D
G
N
D
NC2
N
C
3
FREFIN
VCC
N
C
4
V
R
E
F
D
I
G
CD2
L
O
1
L
O
2
C
D
1
S
W
P
O
R
T
VDD
DGND
INTCON2
L
O
O
P
S
W
NC5
NC6
DGND
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 11
Fig.3 WLP-CSP pin layout bottomview, the die has a laser marking on the backside. The lasermarking marks pin
A1, see also chapter 18.
4000 m
4
0
0
0
m
500 m
500 m
1 2 3 4 5 6 7
G
F
E
D
C
B
A
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 12
8 FUNCTIONAL DESCRIPTION
8.1 Low Noise RF Amplier
The LNA input impedance together with the LC RF input circuit defines an FM band filter. The gain of the LNA is
controlled by the RF AGC circuit.
8.2 FM Mixer
FM quadrature mixer converts FM RF (76 to 108 MHz) to IF.
8.3 VCO
The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequency
range is 150MHz to 217MHz.
8.4 Crystal Oscillator
The crystal oscillator can operate with a 32.768kHz clock crystal, with a high performance as specified in chapter 14. The
osillator can be overruled via the FREFIN pin. When the FREFIN pin is used the oscillator is clocked externally with a
32.768kHz, signal. Selection between a reference clock or a reference crystal can be done via the bus. When a crystal
is connected the FREFIN pin must be left open and when the FREFIN pin is used a crystel may not be connected. It is
not possible to connect a crystal and apply a frequency via the FREFIN pin in the same application.
The crystal oscillator generates the reference frequency for
the reference frequency divider for synthesizer PLL
the timing for the IF counter
the timing for the Pause Detector
the free running frequency adjust of the stereo decoder VCO
the centre frequency for adjustment of the IF filters
clock frequency of the RDS/RBDS decoder
8.5 PLL Tuning System
The PLL synthesizer tuning systemis suitable to operate with a 32.768kHz reference frequency generated by the crystal
oscillator or a reference clock of 32.768kHz fed into the IC. To tune the radio to the wanted frequency the PLL word must
be calculated first and then programmed to the register. The PLL word is 14 bits long, see table 12. Calculation of this
14 bit word can be done as follows:
with: N
DEC
= Decimal value of PLL word
F
RF
= the wanted tuning frequency [Hz]
F
IF
= the Intermediate Frequency [Hz]: 225kHz
F
REFS
= the reference frequency [Hz] : 32.768 kHz
(4 x (F
RF
+ F
IF
))
N
DEC
=
F
REFS
(4 x (F
RF
- F
IF
))
N
DEC
=
F
REFS
Equation 1 for Hi-Side Injection: Equation 2 for Lo-Side Injection:
(4 x (100.1e6 + 225e3))
N
DEC
=
32768
Example for receiving a channel @ 100.1 MHz:
12246.704, round down to the lowest integer value = 12246, the PLL word becomes PLL
HEX
= 2FD6
= 12246.704
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 13
The result found using equation 1 or equation 2 must always be rounded to the lowest integer value.
So via the bus this value can be written to register FRQSET and the IC will then start an autonomous search beginning
at this frequency or go to a preset channel at this frequency. When the application is built according to the blockdiagram
of figure 1 and with the preferred components, the PLL will settle to the new frequency within 5ms.
The PLL is triggered by writing one of the following bytes: FRQSETMSB, FRQSETLSB, TNCTRL1, TNCTRL2,
TESTBITS, TESTMODE.
Accurate validation of the PLL locking on the new frequency can take 2ms - 10ms. When a lock is detected the LD bit,
table 20, is set.
8.6 Band Limits
The IC can be switched to the Japanese FM-band or the US/Europe FM-band. With BLIM set to 0 the band goes from
87.5Mhz to 108MHz, BLIM set to 1 gives the Japanese band 76 MHz to 90 MHz.
8.7 RF AGC
The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacent
channels. Default the RFAGC is on.
8.8 Local / DX
With the LDX bit set the LNA gain is reduced with 6dB to prevent distorsion when a transmitter is very near. With the LDX
bit zero the LNA gain is normal to receive long distance (DX) stations.
8.9 IF Filter
Fully integrated IF filter.
8.10 FM Demodulator
The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF-signal.
8.11 IF Counter
The received signal is mixed to a 225kHz Intermediate frequency. The result of the mixing is counted. A good IF count
result indicates that the radio is tuned to a valid channel and not to an image or a channel with much interference .The
IF counter outputs a 7bit count result via the bus . The IF counter is continuously active and can be read at any time via
the bus. It also activates a flag when the IF count result is outside the IF count valid result window. See also section
9.1.4.4.
Before a tuning cycle is initiated the IF count period can be set to 2ms or to 15.6ms with bit IFCTC. When the IF count
period is set to 2ms, initiating the tuning algorithm with a preset (SM = 0) will always give an RDS update as is shown in
section . In case the IF count time is set to 15.6ms the tuning flowchart of section is used. Once tuned, the IF count period
is always 15.6ms.
8.12 Level Voltage Generator and Analog to Digital Converter
The level voltage reflects the fieldstrength received by the antenna. The level voltage is analogue to digital converted
with 4 bit and output via the bus. The level ADC is continously active and can be read at any time via the bus. It also
activates a flag as the Level voltages falls under a predefined selectable threshold. With the bit LHSWlarge hysteresys
steps or small hyteresys steps can be chosen, according to table 23. See also section 9.1.4.5.
When the ADClevel is set to 3 its minimumvalue the search algorithmwill only stop at channels having a RF level higher
than/or equal to ADC level 3. After completing the search algorithm and being tuned to a station, due to the hysteresis
the effective limit will be set to 0. This means that the continuous ADC level check will never set the LEVFLAG.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 14
8.13 Softmute
The lowpass filtered level voltage drives the softmute attenuator at low RF input levels, the audio output is faded and
hence also the noise, see also figure 14 and 16 and compare the lines with reference nr 1 and 2. The softmute function
can be toggled via the bus, bit SMUTE.
8.14 Hard Mute
With the MU bit, of the TUNCTRL2 byte, the audio outputs VAFL and VAFR can be hard-muted, this means they are put
in tri-state. The same can be done by setting the bits LHM(Left Hard Mute) or RHM(Right Hard Mute) in byte TESTBITS,
which mute only one output at a time (or both when both set) and force the IC to mono. Also with the IC in standby-mode
the audio outputs are hard-muted.
8.15 Audio Frequency Mute - AFM
With the AFM bit, of the TUNCTRL register, the audio signal can be muted. In the softmute attenuator the audio signal
is blocked and thus pins VAFL and VAFR will be at their DC biasing point having no signal. The audio is automatically
muted during a preset as shown in the flowchart of Fig. 6. When the audio must be muted during search mode, this must
be done by setting the AFM bit before the search and resetting it afterwards.
When the AFM bit is set also the RDS data is stopped.
8.16 MPX Decoder
The PLL stereo decoder is adjustment free. The Stereo decoder can be switched to Mono via bus.
8.17 Signal depending Mono/Stereo Blend (Stereo Noise Cancellation)
With decreasing RF input level the MPX decoder blends from Stereo to Mono to limit the output noise. The continuous
mono-to-stereo blend can also be programmed by bus to an RF level depending switched mono-to stereo transition. SNC
can be switched off via bus with the SNC bit.
8.18 Software Progammable Port
One software programmable port (cmos output) can be addressed via bus.
With bit SWPM = 1 the softwareport (pin7) the output for the FRRFLAG, with bit SWPM = 0 the software port outputs bit
SWP of the registers, in testmode the software port outputs signals according to table 24. Testmode is selected setting
bit TM of byte TESTMODE. The sofware port is not disabled by the PUPD bits, see section 8.19.
8.19 Stand-By
With the PUPD (Power Up / Power Down) bits the radio can be put in stand-by mode. The RDS part can be turned off
seperately or both the RDS and the FM part can be turned off. The IC is still accesible via the bus, but takes only a low
power from the supply, in stand-by the audio outputs are hard-muted.
8.20 Power On Reset
After start-up of VCC and VDD a power-on-reset circuit will generate a reset pulse and the registers will be set to their
default values as shown in chapter 12. The power-on-reset is effectively generated by VDD.
Note: After a power-on-reset the IC is in standby mode and the PUPD bits are 0. After a power-on-reset the registers are
reset to their default value, except for bytes 12
R
to19
R
and flags DAVFLG, LSYNCFLG and PDFLAG. To reset these the
radio must be turned on by setting PUPD[0]. After setting PUPD[0] = 1, it will take 0.9ms to startup the IC and set these
registers to their default value.
The power supplies can be switched on in any order.
When the supply voltage VCC and VDD are made 0V, then all I/O s, the audio outputs and the reference clock input are
high-ohmic.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 15
8.21 RDS/RBDS Demodulator
Fully integrated RDS/RBDS demodulator, uses the reference frequency (32.678Hz) of the PLL synthesizer tuning
system. The RDS demodulator recovers and regenerates the continuously transmitted RDS or RBDS data streamof the
multiplex signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) for further processing by the integrated
RDS decoder.
8.22 RDS Data and Clock Direct
The RDS demodulator retrieves the RDS data and clock signals, this data can be put directly onto the pins V
AFL
and V
AFR
by setting the RDSCDA bit to HIGH.
8.23 RDS/RBDS Decoder
The RDS decoder provides block synchronisation, error correction and flywheel function for reliable extraction of RDS or
RBDS block data. Different modes of operation can be selected to fit different application requirements. Availability of
new data is signalled by bit DAVFLG and output pin INTX, which generates an interrupt. Up to two blocks of data and
status information are available via the I
2
C-bus in a single transmission.
The behaviour of the DAVFLG is described in section .
8.24 Audio Pause Detector
The Audio Pause detector watches the audio modulation for pauses by looking at low levels. The modulation threshold
can be adjusted in 4 steps of 4dB by the control bits PL0 and PL1. The minimum time for detecting a pause can be
adjusted by the control bits PT0 and PT1 as in table 39. When there is a pause this is indicated by a flag, the PDFLAG
is set to 1 and a hardware interrupt is generated. See also section 9.1.4.6.
8.25 Autosearch and preset
In search mode the IC can search channels automatically.
Before starting a search or a preset the INTMSK register must be reset and only the FRRMSK must be set. This way the
uP will only be interrupted when the search/preset algorithm is ready.
Search mode is initiated setting the SMbit to 1. The SMbit is in the FRQSETMSB byte. When SUD is 0 then it searches
down, when SUD is 1 it searches up. The tuner starts searching at the frequency set in the FRQSET bytes. With the SSL
(Search Stop Level) bits the fieldstrength of channels to be found can be set. The tuner will stop on a channel with a
fieldstrength equal to or higher than this reference level and then check the IF frequency, when both are valid it stops.
(Note that this depends on the AHLSI bit as described in figure 5.) If the level-check or the IF-count fails, it keeps on
searching. If the level-check or the IF-count fails, it keeps on searching. When no channels are found the IC stops
searching when it has reached the band-limit and the the BLFLAG goes high. A search always stops with the FRRFLAG
being set and a hardware interrupt. Figure 5 describes this procedure.
The search algorithm can stop at a frequency which will give an offset of the IF frequency of maximum 12kHz, while
applying a preset can limit the offset of the IF frequency to maximum 8kHz. It is recommended to do a preset after a
search when the found frequency has an offset higher than 8kHz for the best tuning.
After this interrupt the IC will not update the tuner-registers for a period of 15ms. The state of the IC can be checked by
reading the bytes of: INTFLAG, FRQCHKMSB, FRQCHKLSB and TUNCTRL1/2. Table 2 shows the possible states after
an autosearch or a preset.
A preset is done by setting SM to 0 and writing a frequency to byte FRQSETMSB. The tuner jumps to the selected
frequency and sets the FRRFLAG when it is ready. After this interrupt the IC will keep not update the tuner-registers for
a period of 15ms. The state of the IC can be checked by reading registers: INTFLAG, FRQCHKMSB, FRQCHKLSB and
TUNCTRL1/2. Table 2 shows the possible states after an autosearch or preset.
8.25.1 AUTO HI-LO SIDE INJECTION STOP SWITCH.
When a channel is searched or a preset is done, reception can sometimes improve when injection is done at the other
side of the wanted channel.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 16
The IC has bit HLSI, this bit toggles the injection of the local oscillator from Hi-Side HLSI=1to Lo-Side with HLSI = 0.
When HLSI is toggled also a new PLL setting must be sent to the IC.
When the AHLSI bit is set, the search/preset algorithmwill stop after a channel has a valid RSSI level check but fails the
IF count. The uP can now respond by toggling the HLSI switch and sending a new PLL value to the tuner.
8.25.2 MUTING DURING SEARCH OR PRESET.
During a preset the tuner is always muted, this is done by the algorithm itself. A search is default not muted unless the
AFM is set or the AHLSI bit is set. When the AHLSI bit is set and the tuner stopped during a preset or a search because
of a wrong IF count, the tuner keeps muted; this way the uP can switch the Hi-Lo setting quietly and wait for the new
result. The AFM bit mutes the tuner always, independent of a search or a preset. It can be used to mute a search, by
setting the AFM bit before a search is initiated and resetting it when the tuner is ready. Note: Only set FRRMSK when
initiating a search or preset.
All these mute actions are done by blocking the audio signal inside the softmute attenuator, the audio output will keep
its DC level and stay low-ohmic i.e. 50 (a hard mute with the MU bit will cause a plop).
Table 2 Tuner Truth Table*
Note: This table is valid untill 30.6ms after the tuning cycle has completed. It shows the outcome of the flag register when
a read is done after INTX has gone low, on condition that no other mask bits are set than shown in the table.
IFFLAG BLFLAG FRRFLAG
Comment
0 0 0 If INTX has gone low and only IFMSK, FRRMSK and BLMSK were set then this
cannot occur.
0 0 1 Channel found during search/preset FRRMSK set.
0 1 0 Not a valid state.
0 1 1 A valid channel found and the bandlimit has been reached during a search, BLMSK
or FRRMSK set.
1 0 1 A preset or search has been done, but the wanted channel has a valid RSSI level
but fails the IF count. When AHLSI was set HLSI must be toggled and a new PLL
value must be programmed, FRRMSK set.
1 1 1 Bandlimit is reached during search, no valid channel found, BLMSK or FRRMSK
set.
Wanted channel Image on Hi-Side Image on Lo-Side
Switch LO from Hi-Side to Lo-Side
Fig.4 Switch from Hi-Side injection of LO to Lo-Side injection using the HLSI bit..
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 17
Fig.5 Flowchart autosearch or preset (IF statement down = True).
wait for PLL to settle
Start
Searchmode
IF OK
AHLSI
decrement current_pll
by 100 kHz
increment current_pll
by 100 kHz
Searchup
Level OK
During a preset mute is always active.
Search mode is default not muted
unless AHLSI is set.
BLFLAG = 1
FRRFLAG = 1
BandLimit
BLFLAG = 0
FRRFLAG = 1
BLFLAG = 0
FRRFLAG = 1
Unmute
set PLL frequency
reset Flags
muted
Set LEVFLAG
Unmute
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 18
8.26 RDS update / Aternative Frequency Jump
A channel which transmits RDS data can have alternative channels which have the same information. These alternative
channel frequencies are in the RDS data, so the uP can read the alternative frequencys and store them in a memory.
The tuner can do an RDS update. This is much like a preset, but with a 4ms IF count time. The tuner will jump to the
alternative frequency and check the level and the IF count using a 4ms count time. When RSSI level check is above the
specified level and the IF count result is within the limits then the tuner will stay at the alternative frequency and stay
muted, the uP can now decide what to do. If the Alternative Frequency is not valid it will jump back to the frequency it
came from. The algorithmwill finish with the FRRFLAGbeing set and generate an interrupt. After this interrupt the IC will
not measure the IF count for a period of 15ms. 15ms after completing a RDS jump a measurement of the IF count will
start and hence the IF count result and the IFFLAG will be updated 30.6ms after completing the algorithm. The Level
measurement will start immediately after the tuning algorithm, so the LEVFLAGwill be updated 500us after the algorithm.
The state of the IC can be checked by reading registers: INTFLAG, FRQCHK and TUNCHK. Table 3 shows the possible
states after an autosearch, figure 6 the flowchart.
8.26.1 MUTING DURING RDS UPDATE.
An RDS update (AF jump) is always muted. There are two possibilities for leaving the algorithm.
The tuner jumps to an alternative frequency which is not valid (according to the specified SSL limit and fixed IF counter
limits) and jumps back, then it will automatically unmute.
Or the tuner jumps to a valid alternative frequency and stays there. Now it does not unmute. The uP can unmute or it
keeps the tuner muted and can check for the presence of RDS data. The valid way to unmute is to do a preset to the
current frequency (at a preset an ifcount time of 15.6ms is used, which gives a more accurate if count result than the
result obtained by the AF jump, where 2ms is used).
Table 3 RDS update Truth Table*
Note: This table is valid untill 30.6ms after an RDS update has completed. It shows the outcome of the flag register when
a read is done after INTX has gone low, on condition that no other mask bits are set than shown in the table.
IFFLAG BLFLAG FRRFLAG
Comment
cannot occur.
0 0 1 Alternative Frequency Jump succesfull, radio is tuned to the alternative frequency
and keeps muted.
1 0 1 AF jump has been done, but the wanted channel fails the IF count, the PLL will be
set back to the old value.
cannot occur.
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* Version: 2.7
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Date: 2004 Nov 09
Page: 19
Fig.6 Flowchart RDS update.
wait for PLL to settle
Start
Level OK?
Unmute
Activate mute
Set pll to AFfreq.
BLFLAG = 0
FRRFLAG = 1
keep muted
Store old PLL setting
(pll is old freq)
(pll is AF freq)
IF OK?
set IF count time
to 2ms
Clear LEVFLAG
Clear IFFLAG
Wait for IF counter
Reset old PLL setting
Wait for PLL to settle
BLFLAG = 0
FRRFLAG = 1
Set LEVFLAG
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9 INTERRUPT HANDLING
9.1 Interrupt Register
The first two bytes of the I
2
C register contain the interrupt masks and the interrupt flags.
Table 4 INTFLAG Byte0
R
A flag is set when it is 1.
Table 5 INTMSK Byte0
W
/ Byte1
R
The interrupt flag register contains the flags set according to the behaviour outlined in section 9.1.4. When these are set
they can also cause the INTX to go active (HWinterrupt line) depending on the status of the corresponding mask bit in
table 5. A 1 in the mask register enables the HW interrupt for that flag.
Hence it is conceivable that, with all the mask bits cleared, the SWcould operate in a polling mode by continuous read
operation of the interrupt flag register to look for bits being set.
Interrupt mask bits are always cleared after reading the first two bytes of the interrupt register. This is to control multiple
HWinterrupts. See figure 7. The LSYNCMSKhas a different function and is not cleared after reading the interrupt register
bytes, see also section 9.1.4.3.
9.1.1 Interrupt clearing
The interrupt flag and mask bits are always cleared after:
they have been read via the bus
a power on reset
9.1.2 Timing
The timing sequence for the general operation interrupts is shown in Figure 7 and shows a read access of the interrupt
bytes INTFLAG and INTMSK and a subsequent (though not necessarily immediate) write to the mask register. It also
indicates two key timing points A and B.
If an interrupt event occurs while the register is being accessed (after point A) it must be held until after the mask register
is cleared at the end of the read operation (point B).
Point A is after the R/Wbit has been decoded and point B is where the acknowledge has been received fromthe master
(uP etc.) after the first two bytes have been sent.
The low time for the INTX line (T
FMINT
) has a maximum value specified in chapter 14. However it can be shorter if the
read of the INTREG registers occurs within the T
FMINT
.
9.1.3 Reset
A reset can be performed (at any time) by a simple read of the interrupt bytes, byte0
R
and byte0
W
, which automatically
clears the Interrupt flags and masks.
Bit No
7 6 5 4 3 2 1 0
Name DAVFLG TESTBIT LSYNCFLG IFFLAG LEVFLAG PDFLAG FRRFLAG BLFLAG
Bit No
7 6 5 4 3 2 1 0
Name DAVMSK - LSYNCMSK IFMSK LEVMSK PDMSK FRRMSK BLMSK
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Data
Interrupt Event
Interrupt Flag bit
Interrupt Mask bit
INTX
A B
2
Interrupt events that occur outside of
the region A-B set their respective flag
bits in the normal way i.e. immediately
and can thus trigger a HW interrupt if
the mask bits are set.
All interrupt mask bits are cleared
at the end of the interrupt flag and
mask bytes.
Interrupt events that occur between A and B set their
respective flags after the mask bits are cleared. Which
means that in this picture an interrupt event occurred in
period A-B, so after A-B the Flag goes high.
INTX is set HIGH (inactive) at the end of
reading the interrupt mask bytes.
SW writes to the mask byte and enables the
required mask bits. Any flags currently set will
then trigger a HW interrupt.
Fig.7 I
2
C Interrupt sequence, read and write operation.
S 0
R
data
Device
address
R
A A
Data A
INTFLAG
1
R
data
INTMSK
A
S 0
W
data
Device
address
W
A A
A
INTMSK
1
W
data
FRQSETMSB
A 2
W
data
FRQSETLSB
P
Read access Write access
B
1
1. The blocking of interrupts is marked by the region A - B1/B2 depending on the
actual read cycle.
2. B1 is when only the INTFLAG register is read and a stop condition is received
(i.e. only INTFLAG is read so only this will be cleared)
3. B2 is when both registers are read and hence cleared and this is terminated by
either an ack or stop bit.
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9.1.4 Interrupt flags and behaviour
9.1.4.1 Multiple interrupt events
If the interrupt mask register bit is set then the setting of an interrupt flag for that bit causes a HW interrupt (INTX goes
low). If the event occurs again, before the flag is cleared, then this does not trigger any further HW interrupts until that
specific flag is cleared. However two different events can occur in sequence and generate a sequence of HWinterrupts.
Only when read, followed by a write of the INTMSK byte has been done, a second interrupt can be generated, as the
first interrupt blocks the input of the INTX oneshot generator.
If subsequent interrupts occur within the INTX low period then these do not cause the INTX period to extend beyond its
specified maximum period. See also section 9.2.
9.1.4.2 Data available: DAVFLG
The DAVFLG is set when a new block of data is received according to the diagrams shown in chapter 10 where the
different DAV modes are described. Once synchronised, this continues for all subsequent received blocks (dependent
on DAV mode) and in the following situations:
* During sync search, in any DAV mode, two valid blocks in the correct sequence received with BBC<BBL
(synchronised).
* During synchronization search in DAVB mode if a valid A(C)-block has been detected. This mode can be used for fast
search tuning (detection and comparison of the PI code contained in the A(C)-block).
* If the pre-processor is synchronized and in mode DAVA and DAVB a new block has been processed. This mode is the
standard data processing mode, if the decoder is synchronized.
* If the pre-processor is synchronized and in DAVC mode two new blocks have been processed.
* If the decoder is synchronised and for any DAV mode, with LSYNCMSK=0, loss of synchronisation is detected (flywheel
loss of synchronisation, resulting in a restart of synchronisation search).
The DAVFLG is reset by a read of RDSLBLSB (byte15
R
) or RDSPBLSB (byte17
R
). An interrupt is given each time when
a new block of data is decoded and when the DAVMSK is set, for details look in chapter 10.
9.1.4.3 RDS synchronisation: LSYNCFL
The SYNC bit, table 25, shows the status of the RDS decoder. If it is set then the decoder is synhronised, if it is 0 it is not.
The action of the ASIC depends on the status of the LSYNCMSK bit in table 5. If this is set then the loss of
synchronisation causes the LSYNCFL to go HIGH when synchronisation is lost and a hardware interrupt. The RDS part
of the ASIC is set to IDLE and waits for the uP to initiate a new synchronisation search by setting the NWSY bit as
described in table 25.
If the LSYNCMSK bit is 0 and synchronisation is lost the ASIC automatically starts a new synchronisation search. It will
not generate a hardware interrupt. The uP can wait untill the RDS decoder is synchronised again, this will be indicated
by the DAVFLAG and the SYNC status bit (this requires the DAVMSK being set).
The LSYNCFL is reset by a read of the INTMSK byte1
R
.
The LSYNCMSK is not reset by a read of the INTMSK byte, it must be set or reset by the uP. Resetting it automatically
would change the status of the ASIC and cause an automatical synschronisation search as described above.
How the synchronisation is defined is explained in brief in chapter 10 and in [2].
9.1.4.4 IF Frequency: IFFLAG
During Automatic frequency search, preset or AF update, the FM part of the ASIC performs a check on the received IF
frequency as a measure of the level of interference in the channel received. If an incorrect IF frequency is received then
this indicates the presence of strong interferers or tuning to an image and the IFFLAG bit in the INTFLAG register is set.
Also a preset to a channel with no signal will result in a wrong IF count value and hence setting of the IFFLAG.
When a search, preset or AF update is finished the FRRFLAG will be set to indicate this and generate an interrupt. The
uP can now read the outcome of the registers which will contain the IF count value and the IFFLAGstatus of the channel
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it is tuned to. In case of an AF update the IF count value of the alternative frequency will be in the registers, also when it
jumps back, because it will then not start a new IF count. Note: 15.6 ms after the tuning algorithm has completed the IF
counter will start a new count. So 30.6ms after a failed AF update the IF count result will be equal again to that of the
channel from where the jump was initiated.
15ms after the FRRFLAG has been set the IF counter will start to run continuously on the tuned frequency and if the
conditions for correct frequency are not met then this sets the IFFLAGbit in the interrupt register. When the IFMSK is set
this will also cause an interrupt.
The IFFLAG bit is cleared by a read of byte1
R
, or by starting the tuning algorithm.
9.1.4.5 RSSI threshold: LEVFLAG
The level voltage reflects the fieldstrength received by the antenna. The level voltage is analogue to digital converted
with 4 bit and output via the bus, this 4 bit level value can be compared to a threshold level set by the SSL bits in table
16 or the LH bits in table 23. The levelADC (which converts the analogue value to digital) can be triggered to convert in
two ways.
During a tuning step, a search, a preset or an AF update the LEVFLAG is triggered by these algorithms and compares
the level with the threshold set by the SSL bits. The LEVFLAG bit is set if the RSSI level drops below the threshold level
set by the SSL bits in table 16, the HW interrupt is only generated if the corresponding mask bit is set.
After a search, a preset or an AF update, the threshold for comparison is switched to the hysteresis level. The hysteresis
level is set by the combination of SSL bits and the LHSWbit table 21, which results in a hysteresis as shown in table 23.
Then the levelADC starts to run automatically and compares the level each 500s with the hysteresis level. The
LEVFLAG bit is set if the RSSI level drops below the threshold level set by the SSL bits in combination with the LHSW
bit table 23, the HWinterrupt is only generated if the corresponding mask bit is set. With the LHSWbit a small or a large
hysteresis can be selected, which results in the levels of the left RSSI hysteresis threshold column for LHSW= 0 and in
the right RSSI hysteresis threshold column see table 23. Note: When a search or preset is done with the ADC level set
to 3 then when the algorithm has finished, the threshold level is set to 0. Hence the LEVFLAG will never be set.
The LEVFLAG bit is cleared by a read of the INTMSK byte1
R
, or by starting the tuning algorithm
9.1.4.6 Pause Detection: PDFLAG
The pause detector compares the amplitude of the audio signal and starts counting when this drops below the reference
level, when the counter reaches the specified count time a pause is detected and the PDFLAG will be set. If
PDMSK=1then setting the PDFLAG will also give an interrupt. The PDFLAG operates independent of the PDMSK.
The PDFLAG bit is cleared by a read of byte1
R
on condition that the read action takes place more than 500usec after
receiving the pause interrupt on the INTX line.
The PDFLAG only works when RDS is turned on PUPD[1] = 1 and RDS is not idle by a loss of synchronisation.
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Refer to Figure 7. When the peak audio level of the (L+R) drops below the threshold (t1) set by the PL bits in table 39.
It then counts the duration of the pause and if the pause lasts longer than the value set by the PT bits, then the PDFLAG
bit is set and this in turn generates a HW interrupt (if PDMSK=1).
The circuit should ignore short transients where the audio level momentarily rises above the threshold (at t2).
The PSCOn signal is going directly to the software port, the PDFLAG is set by the integrator and going to the bus. The
interrupt line is triggered by the PDFLAG.
t
pause
t
pause
t
audio
Audio present
No Audio present
E.g. Suppose PT = 20ms, t
pause
=16ms and t
audio
= 1.5ms. The pause detector will count according (2):
2*t
pause
- 8*t
audio
= 20ms => 2*16ms - 8*1.5ms = 20ms.
In this case the pause detector has measured 1*16ms 'pause', 8*1.5ms 'no pause' and 1*16ms pause. Therefore, on average
the pause detector has measured 16ms-12ms+16ms = 20ms pause time and hence a pause will be detected.
Audio signal
PSCO
+reference level "PL [mV]
0
Pause
No pause
To detect a pause the amplitude of the audio signal is compared with the reference level selected by the PL-bits. The result
signal pscoof this comparison is sampled with a frequency of 2341Hz, resulting in the signal PSCOn . A pause is detected
if:
{ SUM(0 to N-1) [PSCOn =0] - 8*SUM(0 to N-1) [PSCOn = 1] } > PT x 2341 (1)
t
pause
- 8* t
audio
> PT (2)
where N equals the number of samples taken over time and PT represents the pause time selected by the busbits PT. On
detection of a pause the integrator will be reset. The integrator value cannot become smaller than zero. Therefore, if in the
formula above the second SUM becomes larger than the first SUM, the integrator output will remain zero.
PSCOn
PT x 2341
Integrator
output
0
- reference level "PL
The reference level is defined in kHz,
but internally this is transformed to mV.
E.g. 22.5kHz = 75 mV
1kHz = 3.3mV
Audio
PDFLAG
t1 t2
Note: The actual PSCO
signal behaves as
shown above, here we
assume that all samples
are taken at peaks of the
audio signal, which
results in PSCOn
Fig.8 Operation and timing of Pause Detection according to levels set in table 39.
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Date: 2004 Nov 09
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9.1.4.7 Frequency ready: FRRFLAG
The Frequency Ready flag bit is set when the automatic tuning has finished a search, a preset or an RDS AF update.
the description of this bit is in table 2 and table 3. The FRRFLAG is cleared by a read of byte1
R
.
9.1.4.8 Band limit: BLFLAG
The Band Limit bit BLFLAG is set when the automatic tuning has detected the end of the tuning band or when the PLL
cannot lock on a certain frequency, the description of this bit is in table 2 and table 3 . This bit is cleared by a read of
byte1
R
.
9.2 Interrupt Line
The interrupt line driver is a MOS transistor with a nominal sink-current of 680 uA, it is pulled high by an 18k resistor
connected to VREFDIG. The interrupt line can be connected to one other similar device with an interrupt output and an
18k pull-up resistor, providing a wired OR function. This allows any of the drivers to pull the line low by sinking the
current as specified in chapter 14. So when a flag is set and not masked it generates an interrupt:
Fig.9 Interrupt line behaviour.
<10ms 10ms
<10ms
10ms
VCC
Flag
INTX
Read INTMSK
Note1: read INTMSK clears Flag, INTMSK and INTX
Note2: write INTMSK enables INTX
Note3: when Flag is set next interrupts are blocked untill Read/Write INTMSK
read clears INTX
Write INTMSK
Flag is set immediately after the
reset, because event is still there.
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10 RDS DATA PROCESSING
The RDS demodulator and decoder perform the following operations:
Demodulation of the RDS/RDBS data stream from the MPX signal
Symbol decoding
Obtain block and group synchronisation
Error detection and correction
Store last and previous data block received with associated ID and error status.
Set the DAVFLAG when new data is received
Set the SYNC status bit according to the current synchronisation state.
Set the LSYNCFL flag when synchronisation is lost.
The RDS decoder can be set in different modes, each meant to look for specific information. The modes DAV-A, DAV-B
and DAV-C are described in the next paragraphs.
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10.1 DAV-A Processing mode
The DAV-A processing mode is the standard processing mode used. In this mode each time when a data block has been
decoded it is transferred to the bus-registers. It generates interrupts on the INTX line after every new block of RDS data
that has been processed and also the DAVFLAG is set. This is shown in figure 10. The DAVFLAG is reset by a read of
the bus-registers.
If a data block is decoded and a new one arrives, INTX will go low again, the DAVFLAG will be set and the Last Block
will be shifted to the Previous Block and the last decoded block will be put in the Last Block. This means that all RDS
data is still available in the BL and BP registers.
When the bus-registers are not read the DAVFLAG will not be reset. If a data block is decoded and a new one arrives,
INTX will go low and the Last Block will be shifted to the Previous Block and the last decoded block will be put in the Last
Block. This means that all RDS data is still available in the BL and BP registers, but must be read. This is indicated by
the DOVF bit, which is set.
If again the bus-registers are not read data will be lost, except when this read is done within 20ms after the INTX line has
gone low, so 2ms before the arrival of a new block. If this read is done at least 2ms before the arrival of a new block, then
BL and BP are read and the data in the decoder buffer is then instantanieously shifted to the BL register. All data is now
read and the DOVF bit will be reset.
The diagram assumes that block synchronisation has been achieved and that no other interrupt flags are being set.
A
1
B
1
C
1
D
1
A
2
B
2
INTX
read intflg+RDS on INTX
t
Read
21.9ms
BL Register
BP Register x
B
1
C
1
B
1
C
1
Data Overflow bit
B
1
If there is no read cycle, B1 is placed in
the BP register and the new block C1 is
now in the BL register. The DOVF bit is
set to indicate two blocks available.
DAV-A/B: Normal
DOVF set when 2 new blocks
received in BL/BP
DOVF is cleared when the
BL is read. To be of use
DOVF has to be read be-
fore BL and BP registers
Decoder
Registers
A
2
Instant copy of decoder buffer to BL
register and BL register to BP register
after reading RDSR4. The block in BL
is concidered as a new block.
T
INT_RD
<~ 10ms
A
1
Being decoded
In the decoder buffer
B
1
A
1
C
1
B
1
D
1
C
1
A
2
D
1
A
2
B
2
C
2
A
2
>2ms
end read intmsk
In order not to lose D1
a read must have been
performed before A2
has been decoded.
DAVFLG DAVFLG set on
DAVN=0, cleared on
read BL-reg
B
2
T
INT_RD
Read BL
Read BL Read BL
D
1
C
1
A
2
D
1
D
1
A
2
A
1
A
2
A
2
B
2
To prevent DOVF to
be set again, an
extra read of BL
must be performed
before A2 has been
decoded
Bus
Registers
Fig.10 DAV-A timing diagram
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10.2 DAV-B Processing mode / Fast PI search mode
This mode is used when, for example, the receiver has been re-tuned to a new station and a fast search of the PI code,
always contained in the A or C block, is required. The diagram shown in figure Fig.11, assumes that the RDS decoder
is unsynchronised initially and is performing a synchronisation search.
During synchronisation search the decoder does not set the DAVFLG until a valid A/C -block is detected. If then a valid
B-block is immediately detected, then the decoder is now synchronised and the SYNC bit is set to 1. In fact, if any 2 good
blocks in a valid order are found the RDS decoder will synchronise and give an interrupt.
If for some reason a valid B block was not received then the next valid A/C-block would be decoded and the DAVFLAG
set. The BP and BL registers would record the A block history.
When the decoder is synchronised each decoded block will set the DAVFLAG (assuming it was reset by a read-action)
and generate an interrupt.
B
1
C'
1
D
1
A
2
B
2
DAV B mode: With Bad blocks detected during sync search
INTX
21.9ms
BL Register
BP Register
Good A or C' block detected
BusAccess - Read
Sync status bit
Unsynchronised
Synchronised
Only valid blocks with no errors
are counted as good blocks
Error correction applied
according to SYM bits
Bad Good Bad Bad
X
X X
C'
1
C'
1
Good
Good
B
2
C'
1
C
2
C
2
DAVFLG
X
C'
1
X B
2
Note: BBG > 2
read intmsk
Read BL register
Fig.11 DAV-B timing diagram
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10.3 DAV-C Reduced Processing mode
The DAV-C processing mode is very similar to DAV-A mode with the main exception that a data flag is only set after two
new blocks are received. Hence the update rate is reduced by half.
A
1
B
1
C
1
D
1
A
2
B
2
DAVFLG
INTX
Read access
(Case 1)
t
INTX
T
INT_RD
t
Read
21.9ms
BL Register
BP Register
A
1
D
0
A
2
Data Overflow
bit
Read access
(Case 2)
t
Read
DAVFLG
(Case 2)
Case2: Late read of BL, BP register
Case 1: Normal DAV-C mode
Dashed line shows what would happen if no read occured at (a). DOVF bit set
until the next read of BP register, however,D1,A2 would be lost.
(a)
INTX cleared @ end read INTMSK
DAVFLG not cleared as no read performed
C
0
D
0
D
1
D
1
No read on INTX so
B1 will be lost
DAVFLG reset when
1
st
new block would
have been copied to
BL register
B1 copied to BLreg shortly before
C1 decoded
BLreg copied to BPreg
and C1 to BLreg
t
INTX
= 10 ms
DAVFLG cleared @ end read BPreg
and forced to zero till en read RDSR4
C
1
A
1
C
1
Instant copy of C
1
from
decoder buffer to BL
and BL to BP just
before D
1
decoded
due to read action.
2 new blocks
have arrived in
BL/BP register
2 new blocks have arrived in BL/BP (C
1,
D
1
) and a new block (A
2
)
has entered the decoder buffer. Hence, DOVF is set again. To
prevent this, an extra read must be performed after reading (a).
DAVFLG set when 2
nd
new block
in decoder buffer
Instant copy A
2
from decoder
buffer to BL and
BL to BP
Being
decoded
Fig.12 DAV-C timing diagram
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10.4 Synchronisation
10.4.1 CONDITIONS FOR SYNCHRONISATION.
When the RDS decoder is turned on it must be synchronised to extract valid data from the MPX signal. To do so the
decoder automatically initiates a search for synchronisation. The conditions to meet synchronisation and the status of
this synchronisation can be set and checked with the following bits.
BBL - Bad Blocks Lose - these bits can be set via the bus and have a value between 0 - 63.
GBL - Good Blocks Lose - these bits can be set via the bus and have a value between 0 - 63.
BBG - Bad Blocks Gain - these bits can be set via the bus and have a value between 0 - 32.
GBC - Good Block Count - these bits can be read via the bus and have a value between 0 - 63.
BBL - Bad Block Count - bits can be read via the bus and have a value between 0 - 63
When the decoder is not synchronised it will initiate a synchronisation search. This involves calculation of the syndrome
(see reference [2] for details) for each block of 26 received bits on a bit-by-bit basis. When a correct syndrome (and hence
block ID) is received the decoder clocks the next 26 bits into the internal registers and performs a second syndrome
check. Synchronisation is found when a certain number of blocks have been decoded and two goods blocks have been
found, this number of blocks is defined by the BBG bits. If the first block needed for synchronisation has been found and
the expected second block (after 26 bits) is an unvalid block, then the decoder module internal bad_blocks_counter is
incremented and the next expected block is calculated; exception: if RBDS mode is selected and the first block is E, then
the next expected block is always block A, until synchronisation is found or the maximum bad_blocks_counter value is
reached. If the the decoder module internal bad_blocks_counter reaches the value of the BBG<4:0>, then immediately
start of new synchronisation search (bit-by-bit) is started to find a new first block.
The synchronisation is monitored by use of two flywheel counters, GBC and BBC. These are 6-bit counters that can be
preset by the GBL and BBL bits to values between 0 and 63. Each time a block is decoded and recognised as a bad
block the Bad Block Counter value, BBC, is incremented by 1. When the BBC value is equal to the BBL value,
synchronisation is lost. The SYNC bit will become 0 and the LSYNCFL is set to signal the loss of synchronisation. (Now
the ASIC will automatically initiate a new synchronisation search).
Each time when a good block is decoded the GBC value is incremented. When the GBC value is equal to the GBL value
both counters, BBC and GBC, are set to 0 and a new count starts. The GBC counter is only incremented when the
decoder is synchronised.
10.4.2 DATA OVERFLOW
During synchronisation after RDS data is read from the registers, new available blocks are shifted to the registers as
described in sections 10.1- 10.3. When the registers are not read in time, the decoder cannot shift any new available
block to the registers and hence a data overflow will occur, this is indicated by the DOVF bit which is set to 1. The DOVF
bit is reset by a read of the registers or if NWSY = 1 which results in the start of a new synchronisation search.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 31
10.5 RDS Flag behaviour during read action.
Each time when a RDS data block is decoded the DAVN signal will go low to signal the presence of a new data block. Also the DAVN signal triggers the interrupt output
INTX. In principle the Processor must now start reading and must have read all RDS data, so byte12
R
to byte19
R
before the arrival of a new RDS data block. In the
application it can be that there is a too large delay between the arrival of a new block and reading this block. This can have various causes such as a Processor which
has to start up fromsleep mode or when polling is used instead of interrupt based read actions. The picture below describes the behaviour of the DAVFLGand the DAVN
signal in case off polling, which effectively means that reading can occur at any moment. Note: DAVN sets the INTX-oneshot generator when DAVMSK=1. Unlike INTX
DAVN is not cleared by a read of the Mask register.
A B C D A B C RDS data
DAVN
DAVFLG
BusRead byte: 0
R
15
R
17
R
19
R
W0
W
Read of byte15R in DAV-A and DAV-B mode clears DAVFLG. In DAV-C mode two consecutive RDS data
blocks are read and hence DAVFLG is reset after reading byte17R instead of byte15R (dotted line).
Read of byte19R clears DAVN
RDS flag behaviour during read actions and reading across a block boundary.
reset of DAVFLG
Blocking DAVFLG: At the end of reading byte15R / 17R (DAV-A,B/C) the DAVFLG signal is forced to zero . Only after reading
byte19RDAVFLG is released again.
When synchronous reading is done, using ASIC generated interrupts this problem does not occur.
To prevent undefined situations byte 12R- 19R should always be read in one read action immediately after eachother.
Note: DAVN INTX
10ms
Write byte0W - INTREG
Normally reading byte19R would reset
DAVN, but now it is reset after 10ms, the
max low time of the DAVN.
0
R
15
R
17
R
19
R
W0
W
0
R
15
R
17
R
19
R
W0
W
0
R
15
R
17
R
19
R
W0
W
0
R
15
R
17
R
19
R
W0
W
0
R
15
R
17
R
19
R
W0
W
Fig.13 RDS flag behaviour
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 32
10.6 Error detection and reporting
The FM/RDS ASIC must report information on the number of errors corrected in the last and previously decoded blocks.
This is reported in the ELB and ELP fields as shown in table 27.
During synchronisation search the error correction is disabled for detection of the first block and is enabled for processing
of the second block according to the mode set by the SYM bits as described in Table 37.
10.7 RDS test modes
In test mode the raw RDS clock and RDS data can be recovered directly from pins VAFL and VAFR when bit RDSCDA
= 1.
10.8 RDS data - Reading from the registers.
To read RDS data the Processor must read byte12
R
to byte19
R
. All 8 bytes must be read to reset the status bytes
byte12
R
and byte13
R
, i.e. effectively the status bits can be updated by the decoder after reading the last bit of byte19
R
.
The DOVL bit is cleared after reading the last bit of byte19
R
and the status of the SYNC bit does not depend on reading
the register, the SYNC bit tells if the decoder is synchronised or not. When starting a read action from byte12
R
, the
decoder blocks update from the RDS bytes untill byte19R has been read. RDS byte12
R
- 19
R
must be read in one read
action.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 33
11 CONTROL INTERFACE
The full I
2
C bus specification can be found in [1].
11.1 I
2
C Bus
I
2
C BUS Write mode
I
2
C BUS Read mode
Notes
1. S = START condition.
2. A = acknowledge
3. P = STOP condition.
The I
2
C Bus specification is based on version 2.1 January 2000 expanded by the following definitions.
The chip has two I
2
C addresses:
FM-radio : 0010000[RWn] starts at byte0
R
or byte0
W
.
RDS part: 0010001[RWn] starts at byte12
R
or byte7
W
.
Structure of the I
2
C Bus: Slave transceiver, Subaddresses not used.
The input maximumLOWlevel and the input minimumHIGH levels are specified to 0.3
*
VREFDIG resp. 0.7
*
VREFDIG.
Data Transfer to the IC:
The data transfer has to be in this order. The LSB=0 of the address indicates a WRITE operation to the IC, indicated by
the RWn bit of the I
2
C address.
Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of the byte.
The data becomes valid bitwise at the appropriate falling edge of the clock. A stop condition after any byte can shorten
transmission times. When writing to the transceiver by using the stop condition before completion of the whole transfer:
- The remaining bytes will contain the old information
- If the transfer of a byte is not completed, the new bits will be used, but a new tuning cycle will not be started.
So to speed up RDS traffic it is possible to read all the RDS data and then only write back byte INTMSK to set the
appropriate mask(s) again.
The tables below show the sequence of I
2
C data bytes for read and write operations for both FM and FM+RDS acces.
For simplicity the address, start, stop and acknowledge bits are not shown. The FM and RDS part have different I
2
C
addresses as stated.
When the IC is adressed with the FM-radio address, also in one read action byte12
R
- byte27
R
can be read. A read does
not have to stop at byte11R.
When writing also all bytes, byte0W - byte10W can be written with one write action.
So effectively using the RDS-part address only skips some bytes, which reduces bus-access.
Table 6 FM - Read mode data transfer
S
(1)
CHIP ADDRESS (write) A
(2)
DATA BYTE(S) A
(2)
P
(3)
S
(1)
CHIP ADDRESS (read) A
(2)
DATA BYTE 1
byte0R byte1R byte2R byte3R byte4R byte5R byte6R byte7R byte8R byte9R byte10R byte11R
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 34
Table 7 RDS - Read mode data transfer
Table 8 FM - Write mode data transfer
Table 9 RDS - Write mode data transfer
With the Standby Bit the IC can be switched in a low current stand-by mode. The bus is then still active. Is the Bus
Interface deactivated, by making pin BUSENABLE low, without programmed stand-by mode, the IC keeps its normal
operation, but is isolated from the bus lines.
It is possible to operate the IC with BUSENABLE hard wired to VREFDIG and have the businterface always active.
Power-on reset : The mute is set, all other bits are set default according to the tables in chapter 12. To initialize the IC
all bytes have to be transfered.
byte12R byte13R byte14R byte15R byte16R byte17R byte18R byte19R byte20R byte21R byte22R byte23R
byte24R byte25R byte26R byte27R
byte0W byte1W byte2W byte3W byte4W byte5W byte6W
byte7W byte8W byte9W byte10W
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 35
12 REGISTERS
12.1 Register Map
I
2
C-Byte Nr.
BYTE NAME
R/W ACCESS
RESET
0R INTFLAG R 00
1R/0W INTMSK R/W 00
1W/2R FRQSETMSB R/W 80
2W/3R FRQSETLSB R/W 00
3W/4R TNCTRL1 R/W 08
4W/5R TNCTRL2 R/W D2
6R FRQCHKMSB R -
7R FRQCHKLSB R -
8R IFCHK R -
9R LEVCHK R -
5W/10R TESTBITS R/W 00
6W/11R TESTMODE R/W 00
12R RDSSTAT1 R -
13R RDSSTAT2 R -
14R RDSLBMSB R -
15R RDSLBLSB R -
16R RDSPBMSB R -
17R RDSPBLSB R -
18R RDSBBC R -
19R RDSGBC R -
7W/20R RDSCTRL1 R/W 00
8W/21R RDSCTRL2 R/W 10
9W/22R PAUSEDET R/W 00
10W/23R RDSBBL R/W 00
24R MANID1 R 00
25R MANID2 R 2B
26R CHIPID1 R 57
27R CHIPID2 R 64
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 36
12.2 Register description
Table 10 INTFLAG - byte0R
Table 11 INTMSK - byte1R / byte0W
Table 12 FRQSETMSB - byte2R / byte1W
bit Bitname Def R/W
Functional description
7 DAVFLG 0 R DAVFLG = 1 RDS data is available
6 TESTBIT 0 R Internal Use
5 LSYNCFL 0 R LSYNCFL = 1 synchronisation is lost
4 IFFLAG 0 R IFFLAG = 1 IF count is not correct
3 LEVFLAG 0 R Outside the tuning period the RSSI level is continuously checked using the following RSSI
level: LEVFLAG = 1 RSSI level has dropped below (V
SSL[1:0]
- V
hys
) table 23.
During a tuning period (preset or search): LEVFLAG = 1 RSSI level has dropped below
V
SSL[1:0]
table 16.
2 PDFLAG 0 R PDFLAG = 1 a pause is detected
1 FRRFLAG 0 R FRRFLAG = 1 the tuner state machine is ready
0 BLFLAG 0 R BLFLAG = 1 during a search the bandlimit has been reached or time out
bit Bitname Def R/W
7 DAVMSK 0 R/W masks bit DAVFLG
6 - 0 R/W -
5 LSYMSK 0 R/W masks bit LSYNCFL
4 IFMSK 0 R/W masks bit IFFLAG
3 LEVMSK 0 R/W masks bit LEVFLAG
2 PDMSK 0 R/W masks bit PDFLAG and enables the Pause detection circuit
1 FRMSK 0 R/W masks bit FRRFLAG
0 BLMSK 0 R/W masks bit BLFLAG
IIC Bitname
Def
R/W
7 SUD 1 R/W 1 = search up, 0 = search down
6 SM 0 R/W 1 = search mode, 0 = preset mode
5 FR_13 0 R/W Frequency set bits, set the frequency of the PLL according to the formula in section 8.5.
4 FR_12 0 R/W
3 FR_11 0 R/W
2 FR_10 0 R/W
1 FR_09 0 R/W
0 FR_08 0 R/W
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 37
Table 13 FRQSETLSB - byte3R / byte2W
Table 14 TNCTRL1 - byte4R / byte3W
Table 15 TNCTRL2 - byte5R / byte4W
Table 16 Truth tables PUPD + SSL
bit Bitname Def R/W
7 FR_07 0 R/W Frequency set bits, set the frequency of the PLL according to the formula in section 8.5.
6 FR_06 0 R/W
5 FR_05 0 R/W
4 FR_04 0 R/W
3 FR_03 0 R/W
2 FR_02 0 R/W
1 FR_01 0 R/W
0 FR_00 0 R/W
bit Bitname Def R/W
7 PUPD_1 0 R/W Power up Power Down MSB - see PUPD truth table
6 PUPD_0 0 R/W Power up Power Down LSB - see PUPD truth table
5 BLIM 0 R/W 1 = Japan FM band 76 MHz to 90 MHz, 0 = US/Europe FM band 87.5MHz to 108 MHz
4 SWPM 0 R/W 1 = Software port is output of FRRFLAG, 0 = SWP
3 IFCTC 1 R/W 1 = IF count time = 15.02ms, 0 =IF count time = 2.02ms
2 AFM 0 R/W 1 = L-, R-audio muted, 0 = Audio not muted
1 SMUTE 0 R/W 1 = Soft mute on, 0 = off
0 SNC 0 R/W 1 = Stereo noise cancellation on, 0 = off
bit Bitname
Def
R/W
7 MU 1 R/W 1 = L-, R- Audio hard muted, 0 = no hard mute
6 SSL_1 1 R/W Search stop level MSB - see SSL truth table
5 SSL_0 0 R/W Search stop level LSB - see SSL truth table
4 HLSI 1 R/W 1 = high side injection, 0 = low side injection
3 MST 0 R/W 1 = forced mono, 0 = stereo ON
2 SWP 0 R/W 1 = SWPORT = High, 0 = SWPORT = Low
1 DTC 1 R/W 1 = deemphasis time constant = 50s, 0 = deemphasis time constant = 75s
0 AHLSI 0 R/W see section 8.25.1 for the functionality of this bit
PUPD truth table SSL truth table
PUPD_1 PUPD_0 status SSL_1 SSL_0 Search stop level
0 0 FM/RDS OFF 0 0 ADC3
0 1 FM ON / RDS OFF 0 1 ADC5
1 0 Not Used 1 0 ADC7
1 1 FM / RDS ON 1 1 ADC10
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 38
Table 17 FRQCHKMSB - byte6R
Table 18 FRQCHKLSB - byte7R
Table 19 IFCHK - byteR8
Table 20 LEVCHK - byteR8 + byte9R
bit Bitname Def R/W
7
6
5 PLL_13 - R Frequency output
4 PLL_12 - R
3 PLL_11 - R
2 PLL_10 - R
1 PLL_09 - R
0 PLL_08 - R
bit Bitname Def R/W
7 PLL_07 - R Frequency output
6 PLL_06 - R
5 PLL_05 - R
4 PLL_04 - R
3 PLL_03 - R
2 PLL_02 - R
1 PLL_01 - R
0 PLL_00 - R
bit Bitname
Def
R/W
7 IF_6 - R IF count MSB
6 IF_5 - R IF count bit
1 IF_0 - R IF count LSB
0
bit Bitname
Def
R/W
7 LEV_3 - R Level Count MSB
6 LEV_2 - R Level Count bit
5 LEV_1 - R Level Count bit
4 LEV_0 - R Level Count LSB
3 LD - R Lock Detect 1 = PLL is locked, 0 = PLL is not locked
2 STEREO - R 1 = pilot detected, 0 = no pilot
note: this does not switch the radio to mono or stereo, this depends on the RF input level as shown
under mono stereo blend or mono stereo switched
1
0
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 39
Table 21 TESTBITS - byte10R / byte5W
Table 22 TESTMODE - byte11R / byte6W
Table 23 LH - RSSI Level Hysteresis
bit Bitname
Def
R/W
7 LHM 0 R/W 1 = Left audio output is hard muted, 0 = not muted
6 RHM 0 R/W 1 = Reft audio output is hard muted, 0 = not muted
5 RDSCDA 0 R/W 1 = VAFL pin 25 is RDS clock and VAFR pin 24 is RDS data, 0 = normal operation
4 LHSW 0 R/W 1 = Level hysteresis is large, 0 = level; hysteresis is small
3 TRIGFR 0 R/W 1 = Reference Frequency selected pin 19, 0 = XTAL as reference pin 33
2 LDX 0 R/W 1 = Local DX on -6dB gain of LNA, 0 = Local DX off LNA has normal gain
1 RFAGC 0 R/W 0 = RFAGC on , 1 = RFAGC off
0 INTCTRL 0 R/W when INTCTRL is set to 1 this generates and interrupt on pin INTX
bit Bitname Def R/W
7 0 R/W
6 0 R/W
5 0 R/W
4 TM 0 R/W 1 =IC in testmode and software port outputs according to table 24, TM = 0 normal operation.
3 TB_3 0 R/W Test bits table 24 describes selection of signals outputted to the SWPORT when SWPM = 0
When TM = 1, TB_[3:0] = 0, so effectively this is an and function.
2 TB_2 0 R/W
1 TB_1 0 R/W
0 TB_0 0 R/W
RSSI ADC
Search Stop
Level
RSSI Hysteresis
Threshold LHSW =0
RSSI Hysteresis
Threshold LHSW =1
3 0 0
5 2 1
7 4 3
10 7 5
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 40
Table 24 Testbits (SWPM = 0)
TB_3
TB_2 TB_1 TB_0 SWPORT output signal
0 0 0 0 bit SWP of byte4W, depending on bits SWPM and SWP
0 0 0 1 oscillator output 32.768 kHz, when TM =1
0 0 1 0 Lock Detect bit LD
0 0 1 1 Stereo bit STEREO
0 1 0 0 Programmable Divider, when TM =1
0 1 0 1 PSCOn see section 9.1.4.6
0 1 1 0 57 kHz clock
0 1 1 1 tri-state
1 0 0 0 output of RDS comparator
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 41
Table 25 RDSSTAT1 - byte12R
Table 26 RDSTAT2 - byte13R
Table 27 Truth tables ELB + EPB
Table 28 Last Block ID addressing + Previous Block ID addressing
bit Bitname Def R/W
7
6 BLID_2 - R Block ID of Last block, see block ID truth table
5 BLID_1 - R Block ID of Last block
4 BLID_0 - R Block ID of Last block
3
2
1 ELB_1 - R nr. of Errors for last processed block
0 ELB_0 - R nr. of Errors for last processed block
bit Bitname Def R/W
7 BPID_2 - R Block ID of Previous block, see block ID truth table
6 BPID_1 - R Block ID of Previous block
5 BPID_0 - R Block ID of Previous block
4 EPB_1 - R nr. of Errors for previous processed block
3 EPB_0 - R nr. of Errors for previous processed block
2 SYNC - R SYNC = 1 RDS bitstream is synchronised, 0 = not synchronised
1 RSTD - R 1 =Power On Reset Detected
0 DOVF - R 1 = Data overow occured during read operation, 0 =normal operation
ELB truth table EPB truth table
ELB_1 ELB_0 Nr. of corrected bits. EPB_1
EPB_0
Nr. of corrected bits.
0 0 No errors 0 0 No errors
0 1 Max 2 bits 0 1 Max 2 bits
1 0 Max 5 bits 1 0 Max 5 bits
1 1 Uncorrectable 1 1 Uncorrectable
BLID truth table BPID truth table
BLID_2 BLID_1 BLID_0 Block BPID_2 BPID_1 BPID_0 Block
0 0 0 A 0 0 0 A
0 0 1 B 0 0 1 B
0 1 0 C 0 1 0 C
0 1 1 D 0 1 1 D
1 0 0 C 1 0 0 C
1 0 1 E 1 0 1 E
1 1 0 Inval. BL.E (RDBS) 1 1 0 Inval. BL.E (RDBS)
1 1 1 Invalid block 1 1 1 Invalid block
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 42
Table 29 RDSRLBMSB - byte14R
Table 30 RDSLBLSB - byte15R
Table 31 RDSPBMSB - byte16R
Table 32 RDSPBLSB - byte17R
bit Bitname
Def
R/W
7 BL_15 - R Last RDS Data Byte - MSB
6 BL_14 - R -
5 BL_13 - R -
4 BL_12 - R -
3 BL_11 - R -
2 BL_10 - R -
1 BL_9 - R -
0 BL_8 - R -
bit Bitname
Def
R/W
7 BL_7 - R -
6 BL_6 - R -
5 BL_5 - R -
4 BL_4 - R -
3 BL_3 - R -
2 BL_2 - R -
1 BL_1 - R -
0 BL_0 - R Last RDS Data Byte - LSB
bit Bitname Def R/W
7 BP_15 - R Previous RDS Data Byte - MSB
6 BP_14 - R -
5 BP_13 - R -
4 BP_12 - R -
3 BP_11 - R -
2 BP_10 - R -
1 BP_9 - R -
bit Bitname Def R/W
7 BP_7 - R -
6 BP_6 - R -
5 BP_5 - R -
4 BP_4 - R -
3 BP_3 - R -
2 BP_2 - R -
1 BP_1 - R -
0 BP_0 - R Previous RDS Data Byte - LSB
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 43
Table 33 RDSBBC - byte18R
Table 34 RDSGBC - byte19R
Table 35 RDSCTRL1 - byte20R / byte7W
Table 36 RDSCTRL2 - byte21R / byte8W
bit Bitname Def R/W
7 BBC_5 - R Bad Block Count MSB
6 BBC_4 - R -
5 BBC_3 - R -
4 BBC_2 - R -
3 BBC_1 - R -
2 BBC_0 - R Bad Block Count LSB
1 GBC_5 - R Good Block Count MSB
0 GBC_4 - R -
bit Bitname Def R/W
7 GBC_3 - R -
6 GBC_2 - R -
5 GBC_1 - R -
4 GBC_0 - R Good Block Count LSB
3
2
1
0
bit Bitname Def R/W
7 NWSY 0 R/W 1 = start new synchronisation, 0 = normal processing
6 SYM_1 0 R/W Error correction, see SYM truth table
5 SYM_0 0 R/W Error correction, see SYM truth table
4 RDBS 0 R/W 1 = RBDS processing mode, 0 = RDS processing mode
3 DAC_1 0 R/W RDS data output mode, see DAC truth table
2 DAC_0 0 R/W RDS data output mode, see DAC truth table
1 - 0 R/W -
0 - 0 R/W -
bit Bitname Def R/W
7 - 0 R/W -
6 - 0 R/W -
5 - 0 R/W -
4 BBG_4 1 R/W Bad Blocks Gain MSB
3 BBG_3 0 R/W Bad Blocks Gain bit
0 BBG_0 0 R/W Bad Blocks Gain LSB
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 44
Table 37 Truth tables SYM + DAC
Table 38 PAUSEDET - byte22R / byte9W
Table 39 Truth tables Pause Time + Pause Level
Table 40 RDSBBL - byte23R / byte10W
SYM Error corection truth table DAC RDS data output truth table
SYM_1 SYM_0 status DAC_1
DAC_0 Rds data output table
0 0 No correction 0 0 DAVA
0 1 Max 2 bits 0 1 DAVB
1 0 Max 5 bits 1 0 DAVC
1 1 No correction 1 1 Not used
bit Bitname Def R/W
7 PT_1 0 R/W Pause Time MSB, see PT truth table
6 PT_0 0 R/W Pause Time LSB, see PT truth table
5 PL_1 0 R/W Pause Level MSB, see PL truth table
4 PL_0 0 R/W Pause Level MSB, see PL truth table
3 GBL_5 0 R/W Number of Good Blocks Lose MSB
2 GBL_4 0 R/W -
1 GBL_3 0 R/W -
0 GBL_2 0 R/W -
PT truth table PL truth table
PT_1 PT_0 pause time PT [ms] PL_1 PL_0 Pause Level [kHz]
L=R
0 0 20 0 0 1
0 1 40 0 1 1.6
1 0 80 1 0 2.5
1 1 160 1 1 4.0
bit Bitname Def R/W
7 GBL_1 0 R/W -
6 GBL_0 0 R/W Number of Good Blocks Lose LSB
5 BBL_5 0 R/W Number of Bad Blocks Lose MSB
4 BBL_4 0 R/W -
3 BBL_3 0 R/W -
2 BBL_2 0 R/W -
1 BBL_1 0 R/W -
0 BBL_0 0 R/W Number of Bad Blocks Lose LSB
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 45
Table 41 MANID1 - byte24R
Table 42 MANID2 - byte25R
Table 43 CHIPID1 - byte26R
Table 44 CHIPID2 - byte27R
bit Bitname Def R/W
7 VERSION 0 R Version code
N1D = 0000
N2A = 0001
N2D = 0100
N2E = 0101
6 VERSION 0 R
5 VERSION 0 R
4 VERSION 0 R
3 MAN ID 0 R Manufacturer ID code
2 MAN ID 0 R -
1 MAN ID 0 R -
bit Bitname Def R/W
6 MAN ID 0 R -
5 MAN ID 1 R -
4 MAN ID 0 R -
3 MAN ID 1 R -
2 MAN ID 0 R -
0 IDAV 1 R 1 =manufacturer ID available, 0 = CHIP has no ID
bit Bitname Def R/W
7 CHIP ID 0 R Chip identication Code
6 CHIP ID 1 R -
5 CHIP ID 0 R -
4 CHIP ID 1 R -
3 CHIP ID 0 R -
2 CHIP ID 1 R -
1 CHIP ID 1 R -
bit Bitname Def R/W
6 CHIP ID 1 R -
5 CHIP ID 1 R -
4 CHIP ID 0 R -
3 CHIP ID 0 R -
2 CHIP ID 1 R -
1 CHIP ID 0 R -
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 46
13 DC CHARACTERISTICS
V
CC
= V
DD
= 2.7 V; V
VREFDIG
= 1.8 V; T
amb
= 25 C; unless otherwise specied the min. and max values include spread
due to: voltage from 2.5V to 3.3V; temperature from -20
o
C to 85
o
C;
Supply voltages
G1 V
CC
analog supply voltage 2.5 2.7 3.3 V
G4 V
DD
digital supply voltage 2.5 2.7 3.3 V
G8 V
REFDIG
digital supply voltage 1.65 1.8 V
DD
V
Supply currents
G2 I
CC
analog supply current operating
V
CC
= 2.5 V - 3.3V 10 13.7 18 mA
G3 standby mode
V
CC
= 2.5 V - 3.3V 0 1 5 A
G5 I
DD
digital supply current operating
V
DD
= 2.5 V - 3.3V mA
0.3 0.7 1.5
G6 standby mode
V
DD
= 2.5 V - 3.3V
A
10 18 25
G9 I
REFDIG
digital reference
supply current
operating
V
VREFDIG
= 1.65 V - V
DD
V 0 0.5 1 A
DC operating points
DC1 V
LOOPSW
unloaded DC voltage V
CD3
-0.2 V
CD3 V
DC2 V
CPOUT
0.1 V
CD3
0.1 V
DC3 V
LO1
V
CD3
-0.1 V
CD3 V
DC4 V
LO2
V
CD3
-0.1 V
CD3 V
DC5 V
RDSLP
1.15 V
DC8 V
TMUTE
measured w.r.t. CD3; V
RF
= 0 V 0.6 0.7 0.8 mV
DC10 V
VAFL
f
RF
= 98 MHz; V
RF
= 1 mV 720 850 940 mV
DC11 V
VAFR
f
RF
= 98 MHz; V
RF
= 1 mV 720 850 940 mV
DC12 V
MPXOUT
f
RF
= 98 MHz; V
RF
= 1 mV 680 815 950 mV
DC13 V
MPXIN
f
RF
= 98 MHz; V
RF
= 1 mV 780 mV
DC14
DC15
V
FREQIN
TRIGFR = 1 1.3 1.5 1.7 V
TRIGFR = 0 0 0.05 0.1 V
DC16
DC17
V
XTAL
w.r.t. CD3
TRIGFR = 1 0.9 1.17 1.3 V
TRIGFR = 0 0.8 1 1.2 V
DC18 V
RFIN1
420 530 680 mV
DC19 V
RFIN2
420 530 680 mV
DC20 V
CAGC
V
RF
= 0 V 1 1.57 2 V
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 47
14 AC / DC CHARACTERISICS
V
CC
= V
DD
= 2.7 V; V
VREFDIG
= 1.8 V; T
amb
= 25 C; all AC values are given in RMS; unless otherwise specied the min.
and max values include spread due to: voltage from 2.5V to 3.3V; temperature from -20
o
C to 85
o
C;
Voltage controlled oscillator
V1 f
osc
oscillator frequency 150 217 MHz
Reference frequency input, pin32
FR1 V
FREFIN(osc)
oscillator input voltage
(pin 32)
externally clocked 0 V
CC
V
FR2 R
FREFIN
input resistance
(pin 32)
externally clocked
with 32.768KHz
500 K
FR3 C
FREFIN
input capacitance
(pin 32)
externally clocked
with 32.768KHz
5 6 7 pF
Crystal oscillator 32.768KHz, pin33
FR4 f
r
series resonance
frequency at 25C
the parasitic capacitance on
the PCB <= 2 pF
32.768 kHz
FR5 f/f
r
frequency deviation 20 +20 ppm
FR6 C
s
shunt capacitance 3.5 pF
FR7 C
m
motional capacitance 1.5 3.0 fF
FR8 R
s
series resistance 75 K
Reference frequency 32.768KHz, pin32
FR10
f
r
frequency @ 25C 32.768 kHz
FR11
f/f
r
frequency deviation @ 25C 20 +20 ppm
FR12
f/f
r
frequency deviation -20C - +75C 150 +150 ppm
FR13
Duty Cycle square wave 30 70 %
FR14
Input high level square wave 1.15 1.95 V
FR15
Input low level square wave 0 0.55 V
FR16
Jitter Integrated over the band
300Hz - 15kHz
1 Hz
Synthesizer
PROGRAMMABLE DIVIDER
S1 D
prog
programmable divider
ratio
FRQSET
[15:8]
= XX11 1111
and
FRQSET
[7:0]
= 1111 1110
8191
S2 D
prog
ratio
FRQSET
[15:8]
= XX00 1000
and
FRQSET
[7:0]
= 0000 0000
2048
S3 D
step
step size
1
CHARGE PUMP: PIN 2(CPOUT)
S5 I
sink
charge pump sink peak
current
0.2V < V
1
<V
4
-0.2V
f
VCO
> f
REF
divratio
250 500 1000 nA
S6 - I
source
charge pump source
peak current
0.2V < V
1
<V
4
-0.2V
f
VCO
<f
REF
divratio
250 500 1000 nA
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 48
IF counter
I1 N
IF
IF counter length 7 bit
I2 V
RF
Sensitivity 12 18 V
I3 N
IFcount
IF count result for search
stop
20V < Vrf < 1V 31 3C HEX
I4 T IF counter period IFCTC = 1
IFCTC = 0
f
xtal
= 32768Hz
15625
1953
s
s
I5 RES
IFCOUNT
IF counter resolution f
xtal
= 32768Hz, 4096 Hz
LOGIC PINS , pin 10, 11, 13, 14, 8 - Clock, Data, Busenable
L1 R
i
input resistance 10 M
L2 Logic High Level input switching level up 0.7*V
9
- V
9
+0.3 V
L3 Logic Low Level input switching level down -0.3 - 0.3*V
9
V
Software programmable port; pin 7
L10 V
out(max)
maximum output voltage V
9
-0.2 V
9
V
L11 V
out(min)
minimum output voltage 0 0.2 0.4 V
L12 I
sink/source
SWPORT minimum
current pin 7
500 A
L13 I
leak
SWPORT maximum
leakage current pin 7
0< V
7
< V
VREFDIG
V -1.0 1.0 A
INTX, pin 20
L15 V
out(max)
maximum output voltage 1.65 V < V
VREFDIG
< 1.95V
Rpull-up of second device
connected to INTX 18K +- 20%.
or
maximum load current 200A
V
9
-0.2 V
9
+0.2 V
L16 V
out(min)
minimum output voltage 0.130 0.215 0.4 V
L17 I
sink
pull-down current
interrupt output
500 680 1200 A
L18 R
pull-up
pull-up resistor 14.4k 18k 21.6k
L19 INTX low period One shot pulse time when the low period is not
shortened by a read action
5 9.98 10 ms
FM SIGNAL CHANNEL
FM RF INPUT
RF1 R
i
input resistance (pin 36
and 37 to RFGND)
75 100 125
RF2 C
i
input capacitance
(pin 36 and 37 to
RFGND)
2.5 4 6 pF
RF3 V
RF
Sensitivity EMF value f
RF
= 76 to 108MHz
f=22.5kHz, f
mod
= 1kHz
(S+N/N)=26dB
deemphasis = 75s
B
AF
= 300Hz to 15kHz
1 2 3.5 V
RF4 IP3
in
inband 3rd-order
intercept point related to
V
36-37
f
1
=200kHz, f
2
=400kHz
f
tuned
= 76 to 108MHz
RFagc = off
81 87 dBV
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 49
RF5 IP3
out
outband 3rd-order
intercept point related to
V
36-37
f
1
=4MHz, f
2
=8MHz
f
tuned
= 76 to 108MHz
RFagc = off
87 93 dBV
INBAND AGC
RF6 V
RF
RF input voltage for start
of AGC
f
RF
= 98MHz
V
TMUTE
/V
RF
< 4mV/dBV
55 61 67 dBV
WIDEBAND AGC
RF7 V
RF1
RF input voltage for start
of AGC
f
RF1
= 93MHz, f
RF2
= 98MHz
V
RF2
= 50dBV,
V
TMUTE
/V
RF1
< 4mV/dBV
radio tuned to 98MHz
66 72 78 dBV
IF FILTER
IF1 f
IF
IF lter center frequency 215 225 235 kHz
IF2 BW
IF
IF lter bandwidth 85 94 102 kHz
IF3 S
+200
high side 200kHz
selectivity
f=+200kHz
f
tuned
= 76 to 108MHz
low and high side selectivity
can be measured by
changing the mixer fromhigh
side to low side LO injection
39 43 dB
IF4 S
-200
low side 200kHz
selectivity
f=-200kHz
f
tuned
= 76 to 108MHz
32 36 dB
IF5 S
+-100
high/ low side100kHz
selectivity
f=+-100kHz
f
tuned
= 76 to 108MHz
8 12 dB
IF6
image
image rejection f
tuned
= 76 to 108MHz,
V
RF
= 50dBV
24 30 dB
FM IF LEVEL DETECTOR AND MUTE VOLTAGE
LE1 V
level
level output DC voltage V
RF
= 0 V 1.55 1.65 1.8 V
LE2 V
level
level output DC voltage V
RF
= 3 V 1.6 1.7 1.85 V
LE3 S
level
slope of level voltage
(V
level
/ V
RF
)
V
RF
= 10V to 500 V 150 165 180
LE4 V
RF
level ADC start byte9
R
= 0001 0000 2 3 5 V
LE5 V
RF
level ADC step size 2 3 5 dB
LE6 R
o
output resistance
(pin 23)
280 400 520 K
FM Demodulator
D1 V
MPXOUT
demodulator output
voltage
V
RF
=1mV, L=R, f=22.5kHz,
f
mod
= 1kHz
deemphasis = 75s
B
AF
= 300Hz to 15kHz
60 75 90 mV
D2 R
MPXOUT
demodulator output
resistance
500
D3 Isink
MPXOUT
demodulator output sink
current
30 - - A
mV
20 dB
---------------
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 50
D4 (S+N/N) maximum
signal-to-noise ratio
V
RF
=1mV, L=R, f=22.5kHz
f
mod
= 1kHz
deemphasis = 75s
B
AF
= 300Hz to 15kHz
57 60 dB
D5 THD total harmonic distortion V
RF
=1mV, L=R, f=75kHz
f
mod
= 1kHz
deemphasis = 75s
B
AF
= 300Hz to 15kHz
0.4 0.9 %
D6 THD total harmonic distortion
overdrive
V
RF
=1mV, L=R, f=100kHz
f
mod
= 1kHz, deemphasis =
75s, B
AF
= 300Hz to 15kHz
1 %
D7 V
MPXFM
/V
MPXFM
AM suppression L=R, f=22.5kHz, f
mod
=
1kHz
V
RF
= 100V -> V
RF
= 10mV
m=0.3, deemphasis = 75ms
BAF= 300Hz to 15kHz
-40 dB
Soft Mute
SM1 Soft mute start
level
Mute attenuation = 3dB SMUTE = 1, relative to V
AFL
@ V
RF
= 1 mV, f=22.5kHz,
f
mod
= 1kHz
3 5 10 uV
SM2
mute
mute attenuation V
RF
= 1V, L=R, f=22.5kHz
f
mod
= 1kHz,
deemphasis = 75s
B
AF
= 300Hz to 15kHz
SMUTE = 1
10 20 30 dB
MPX Decoder
M1 V
AFL
,V
AFR,
L-, R-AF output voltage V
RF
= 1mV, L=R, f=22.5kHz
f
mod
75s
60 75 90 mV
M2 R
AFL,
R
AFR
left, right audio output
resistance
MU = LHM = RHM =0
RDSCDA = 0, AFM = 0 or
AFM =1
50 100
M3 R
AFL,
R
AFR
resistance when muted
MU = LHM = RHM = 1
RDSCDA = 0
500 k
M4 Isink
AFL,
Isink
AFR
sink current
170 A
M5 V
maxmpxin
input overdrive margin THD = 3%relative to f
AF
=
1kHz, V
AF
= 250mV
4 dB
M6 V
AF
=V
AFL
/V
AFR
L-, R-AF output voltage
difference
V
RF
= 1mV, L=R, f=75kHz
including 9% pilot,
f
mod
= 1kHz,
deemphasis = 75s
-1 1 dB
M7
sep
stereo channel
separation
V
RF
= 1mV, f=75kHz
including 9% pilot, R=1, L=0
or R=0, L=1, f
mod
= 1kHz
MST = 0, SNC = 1
27 dB
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 51
M8 AF
BWH
Higher Audio bandwidth
-3dB point
V
RF
= 1mV, f=22.5kHz, L=R,
preemphasis = 75s,
deemphasis = 75s, with C
between 27 - 26 = 33n +- 5%
13 15 17 kHz
M9 AF
BWL
Lower Audio bandwidth
-3dB point
V
RF
= 1mV, f=22.5kHz, L=R,
preemphasis = 75s,
deemphasis = 75s, with C
between 27 - 26 = 33n +- 5%
20 25 30 Hz
M10 (S+N/N) maximum
mono
V
RF
= 1mV, f=22.5kHz, L=R,
f
mod
75 s , B
AF
= 300Hz to 15kHz
+ A-weighting lter
56 59 dB
M11 (S+N/N) maximum
stereo
V
RF
= 1mV, f=22.5 kHz,
L=R, f
mod
= 1kHz, pilot = 6.75
kHz, deemphasis = 75 s,
B
AF
= 300Hz to 15kHz +
A-weighting lter
52 55 dB
M12 THD total harmonic distortion
MONO
V
RF
= 1mV, f=75kHz , L=R
f
mod
= 1kHz, no pilot,
deemphasis = 75s
0.4 0.9 %
M13 THD total harmonic distortion
STEREO
V
RF
=1mV, L=1 R=0,
f=75kHz including 9% pilot,
f
mod
75s, B
AF
= 300Hz to 15kHz
0.9 2.5 %
M14
19
Pilot suppression
measured at pins VAFL,
VAFR
related to f=75kHz including
9% pilot, f
mod
= 1kHz
deemphasis = 75s
40 50 dB
M15 f
pilot1
stereo pilot frequency
deviation
V
RF
= 1mV
STEREO = 1
3.6 5.8 kHz
M16 f
pilot2
stereo pilot frequency
deviation
V
RF
= 1mV
STEREO = 0
1.0 3 kHz
M17 f
pilot1
/f
pilot2
pilot switch hysteresis V
RF
= 1mV 2 6 dB
M18 T
deem
deemphasis time
constant
V
RF
= 1mV
DTC = 1
DTC = 0
38
57
50
75
62
93
s
s
Mono stereo blend
M20 Mono/stereo
blend start level
With increasing input
levels the radio switches
gradually from mono to
stereo.
stereo channel separation
=1dB, SNC = 1.
2 4 20 V
M21
sep
stereo channel
separation
V
RF
= 30V, f=75kHz
or R=0, L=1,f
mod
= 1kHz
MST = 0 ,SNC = 1
4 10 16 dB
Mono stereo switched
M23
sep
switching from mono to
stereo with increasing RF
input level
V
RF
= 30V, f=75kHz
or R=0, L=1, f
mod
= 1kHz
MST = 0 , SNC = 0
27 33 dB
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 52
M24
sep
switching from stereo to
mono with decreasing RF
input level
V
RF
= 10V, f=75kHz
or R=0, L=1, f
mod
= 1kHz
MST = 0 , SNC = 0
1 dB
M25 Mono/stereo
switching level
The mono stereo switching
level is the RF input level for
switching from mono-to
stereo.
f=75kHz, including 9%pilot,
f
mod
= 1kHz, SNC = 0
17 22 32 V
M26 Mono/stereo
hysteresis
f=75kHz, including 9%pilot,
f
mod
= 1kHz, SNC = 0
3 3.5 4 dB
Bus driven Mute funtions
Tuning mute
MU1
mute
VAFL,VAFR ,muting
depth
AFM = 1 -60 dB
MU2
mute(L)
VAFL muting depth AFM = 1, LHM = 1 -80 dB
MU3
mute(R)
VAFR muting depth AFM = 1, RHM = 1 -80 dB
RDS demodulator / decoder
R1 I
RDS
I
DD
current when RDS is running 0.3 0.7 1.5 mA
R2 V
inRF
RDS Sensitivity EMF
value
f=22.5kHz, f
AF
= 1kHz, L=R,
f
RDS
=1.2kHz, deemphasis =
50s,
Block Quality Rate >= 85%,
SYM_1=0 and SYM_0=0,
average over 2000 blocks
20 30 V
R3 V
inRF
RDS Sensitivity EMF
value
f=22.5kHz, f
AF
= 1kHz, L=R,
f
RDS
=2kHz, deemphasis =
50s,
Block Quality Rate >= 95%,
SYM_1=0 and SYM_0=0,
average over 2000 blocks
12 18 V
R4 fc
(RDS
) RDS lter center frequency 56.5 57 57.5 kHz
R5 B
-3dB
RDS lter Bandwidth 2.5 3 3.5 kHz
Pause Detector
P1 f
pause
Pause detection threshold f
mod
=1kHz, L=R,
PL_0=0, PL_1=0
0.7 1.0 1.4 kHz
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 53
0 dB
-10
-20
-30
-40
-50
-60
-70
-80
TEA5764HN-N2D, VCC=2.7V, 25 deg
Remark: AFoutR, A_weighting, BPF 300Hz-15kHz
0.1 V 1 V 10 V 100 V 1 mV 10 mV 100 mV 1 V
4.0 %
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Input Level
Date: Monday, 18 October 2004, 15:26
Owner: 4m
Signal
Signal Inc RF: FM: 22.5 kHz AF: 1000 Hz
Key data:
dB = 0 71 mV at 3 V RF
dB = -3 1.0 V
dB = 26 1.4 V
RF Frequency: 98 MHz
Measurements/Decade: 12
Noise
Noise Inc RF:
Key data:
dB = -3 1.0 V
dB = 26 1.4 V
THD
THD Inc RF: FM: 75 kHz AF: 1000 Hz
Key data:
dB = -3 1.0 V
dB = 26 1.4 V
Fig.14 Mono Characteristics
(1) Mono signal, Softmute off
(2) Noise in mono mode,Softmute off
(3) Total harmonic distortion f = 75 kHz
1
2
3
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 54
0 dB
-10
-20
-30
-40
-50
-60
-70
-80
TEA5764HN-N2D, VCC=2.7 V , 25 deg
Remark: AFoutR, A_weighting, BPF 300Hz-15kHz , SNC on
0.1 V 1 V 10 V 100 V 1 mV 10 mV 100 mV 1 V
4.0 %
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Input Level
T
H
D

+

N
Owner: 4s
Right (R=1, L=0)
Right (R=1, L=0) Inc RF: FM: Stereo: R at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHz
Key data:
dB = 0 228 mV at 470 V RF
dB = -3 21.3 V
dB = 26 1.2 V
Stereo Noise
Stereo Noise Inc RF: FM: Stereo: L at 0 kHz AF: 1000 Hz Pilot at 6.75 kHz
Key data:
dB = 0 228 mV at 470 V RF
dB = -3 21.3 V
dB = 26 1.2 V
Right (R=0, L=1)
Right (R=0, L=1) Inc RF: FM: Stereo: L at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHz
Key data:
dB = 0 228 mV at 470 V RF
dB = -3 21.3 V
dB = 26 1.2 V
THD (stereo)
THD (stereo) Inc RF: FM: Stereo: R at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHz
Key data:
dB = 0 228 mV at 470 V RF
dB = -3 21.3 V
dB = 26 1.2 V
Fig.15 Stereo Characteristics
(1) V
AFL
signal, Softmute off
(2) V
AFR
signal, Softmute off
(3) Noise in stereo mode,Softmute off
1
2
3
4
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 55
0 dB
-10
-20
-30
-40
-50
-60
-70
-80
TEA5764HN-N2D, VCC=2.7V, 25 deg
Remark: AFoutR, A_weighting, BPF 300Hz-15kHz, Soft mute on
0.1 V 1 V 10 V 100 V 1 mV 10 mV 100 mV 1 V
4.0 %
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Input Level
Owner: 4m
Signal
Signal Inc RF: FM: 22.5 kHz AF: 1000 Hz
Key data:
dB = 0 69 mV at 15 V RF
dB = -3 3.5 V
dB = 26 1.4 V
Noise
Noise Inc RF:
Key data:
dB = 0 69 mV at 15 V RF
dB = -3 3.5 V
dB = 26 1.4 V
THD
THD Inc RF: FM: 100 kHz AF: 1000 Hz
Key data:
dB = 0 69 mV at 15 V RF
dB = -3 3.5 V
dB = 26 1.4 V
Fig.16 Sofmute and Overdrive Characteristics
(1) Mono signal, softmute on
(2) Noise in mono mode, softmute on
1
2
3
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 56
0.1
1
10
100
1000
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Fig.17 Level ADC conversion
Level ADC output
V
RF
[V]
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 57
15 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Notes
1. Machine Model l (R = 0 , C = 200 pF).
2. Human body model (R = 1.5 k, C = 100 pF).
3. Charged Device Model (JEDEC Standard JESD22-C101
[4]
).
16 THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
2
VCO tuned circuit output 1 0.3 (+8) V
V
3
VCO tuned circuit output 2 0.3 (+8) V
V
15
digital supply voltage 0.3 (+5.5) V
V
34
analog supply voltage 0.3 (+8) V
T
stg
storage temperature 55 +150 C
T
amb
operating ambient temperature 40 +85 C
V
es
electrostatic handling ESD note 1 200 +200 V
note 2 2000 +2000 V
note 3 500 +500 V
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
HVQFN40 thermal resistance from junction to ambient in free air 80 K/W
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 58
17 PACKAGE OUTLINE
terminal 1
index area
0.5 1
A
1
E
h
b UNIT y e
0.2
c
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
6.1
5.9
D
h
4.25
3.95
y
1
6.1
5.9
4.25
3.95
e
1
4.5
e
2
4.5
0.30
0.18
0.05
0.00
0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT618-1 MO-220 - - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT618-1
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm
A
(1)
max.
A
A
1
c
detail X
y y
1 C e
L
E
h
D
h
e
e
1
b
11 20
40
31
30
21
10
1
X
D
E
C
B A
e
2
01-08-08
02-10-22
terminal 1
index area
1/2 e
1/2 e
A C
C
B v M
w M
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
E
(1)
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 59
18 OUTLINE-WFBGA34-2
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 60
19 SOLDERING
19.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for
surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflowsoldering is often
used.
19.2 Reow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times
(preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should
preferable be kept below 230 C.
19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with
a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth
laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction
of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
The footprint must incorporate solder thieves at the downstream end.
For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the
printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues
in most applications.
19.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron
applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between
270 and 320 C.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 61
19.5 Suitability of surface mount IC packages for wave and reow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE
SOLDERING METHOD
WAVE REFLOW
(1)
BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable
(2)
suitable
PLCC
(3)
, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
(3)(4)
suitable
SSOP, TSSOP, VSO not recommended
(5)
suitable
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 62
20 DATA SHEET STATUS
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DATA SHEET STATUS
PRODUCT
STATUS
DEFINITIONS
(1)
Objective specication Development This data sheet contains the design target or goal specications for
product development. Specication may change in any manner without
notice.
Preliminary specication Qualication This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specication Production This data sheet contains nal specications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 63
21 DEFINITIONS
Short-formspecification The data in a short-formspecification is extracted froma full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics
sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified
use without further testing or modification.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 64
22 DISCLAIMERS
Life support applications These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Philips Semiconductors for any damages resulting from such application.
Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or
performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or
warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise
specified.
23 REFERENCES
[1] The I
2
C-Bus Specification Version 2.1 January 2000
[2] Specification of the radio data system (RDS) for VHF/FM sound broadcasting range from 87.5 to 108MHz, BS
EN50067:1998
[3] Datasheet, TEF6892H Car radio integrated signal processor, 2002 Sep 13.
[4] JEDEC Standard JESD22-C101
[5] Datasheet, SAA6588 RDS/RBDS pre-processor, 2002 Jan 14.
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 65
24 REVISION HISTORY
From V2.4 (04 feb 2004) to V2.5 (03 jun 2004)
Chapter 3
- Updated electrical parameters general changed condtions all are set to 2.7V
- updated limits
Chapter 4
- updated specpoint for IP3 and changed conditions
- new limits for (S+N/N)
- moved min limit for RDS sensitivity spec
Chapter 5
- added name for WL-CSP package
Chapter 6
- changed value of decoupling capacitor, connected to CD3, back to 33nF
Chapter 7
- added column with positions for WL-CSP
- changed name TIFCENTER to DGND in figure 3
Chapter 8
- updated sections: 8.6, 8,7, 8.11, 8.19, 8.20, 8.25, 8.26
- updated table 2 Tuner truth table and table 3 RDS update truth table
- updated figure 5 flowchart autosearch or preset
- updated figure 6 flowchart RDS update
Chapter 9
- updated figure 7 I
2
C interrupt sequence
- updated section 9.1.4.2 DAVFLG
- updated section 9.1.4.3 LSYNCFL
- updated section 9.1.4.4 IFFLAG
- updated section 9.1.4.5 LEVFLAG
- updated section 9.1.4.6 PDFLAG
- section 9.2 updated description of interrupt line behaviour and figure 9
Chapter 10
- complete update including all pictures, reflecting the behaviour of the TEA5764N2
Chapter 11
- put correct address for starting point when using the RDS I2C address
- removed influence of BUSENABLE on standby current
Chapter 12
- table 14 changed upper limit of Japan band
- table 24 renamed to testbits and updated functionality
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 66
Chapter 13
- added DC characteristics
Chapter 14
- new numbering
- adjusted limits of: I3, L2, L3, L17, RF4, RF5, D3, M2, M3, M20, R2, R3
- updated conditions for: L17, RF4, RF5, SM1, M1, M5, M21, M23,R2, R3
- added: M8, M9, M11, M13
Chapter 15
- added specpoint for Charge Device Model
From V2.5 (03 jun 2004) to V2.6 (04 jun 2004)
Chapter 6
- Updated blockdiagram connection of CAGC from GND to CD3 (pin 39)
- updated table 1 removed 2 capacitors
From V2.6 (04 jun 2004) to V2.7 (09 nov 2004)
- Page 1 changed status from Objective to Preliminary
Chapter 3
- specpoint G1 changed voltage range from 2.4 - 5.0 V to 2.5 - 3.3 V
- specpoint G3 changed limits
Chapter 6
- blockdiagram added 12pF in series with pin 33
- table 1 added 12pF to list of components
Chapter 8
- section 8.5 added statement which bytes trigger the PLL
- section 8.7 changed default setting of AGC
- section 8.12 added comment about ADC level 3
- section 8.13 updated reference to figures 15 and 17
- section 8.20 changed dependency of POR from VCC to VDD and added statement about order of switching on power
supplies
- section 8.25 added comment about preset after search
Chapter 9
- section 9.1.4.6 updated functionality of pause detector and updated figure 8
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 67
Chapter 10
- updated figure 10; red is changed
- updated figure 12; red is changed
Chapter 11
- section 11.1 changed table 9 removed byte0W
Chapter 12
- table 21 changed functionality of RFAGC
- table 24 changed text of setting 0000 and changed ouput of setting 0101
Chapter 13
- changed conditions for which the figures in chapter 13 are valid
Chapter 14
- changed conditions for which the figures in chapter 14 are valid
- specpoint G3 changed limits
- specpoint G2, G3, G4, G5 changed conditions set to 2.5 - 3.3 V
- specpoint DC6 and DC7 removed
- specpoint DC8 changed output of TMUTE voltage, now w.r.t. CD3
- specpoint DC16 and DC17 changed limits
- specpoint FR4 added condition
- specpoint FR15 changed upper limit set to 0.55V
A
1
B
1
C
1
D
1
A
2
B
2
INTX
read intflg+RDS on INTX
t
Read
21.9ms
BL Register
BP Register x
B
1
C
1
B
1
C
1
Data Overflow bit
B
1
If there is no read cycle, B1 is placed in
the BP register and the new block C1 is
now in the BL register. The DOVF bit is
set to indicate two blocks available.
DAV-A/B: Normal
DOVF set when 2 new blocks
received in BL/BP
DOVF is cleared when the
BL is read. To be of use
DOVF has to be read be-
fore BL and BP registers
Decoder
Registers
A
2
Instant copy of decoder buffer to BL
register and BL register to BP register
after reading RDSR4. The block in BL
is concidered as a new block.
T
INT_RD
<~ 10ms
A
1
Being decoded
In the decoder buffer
B
1
A
1
C
1
B
1
D
1
C
1
A
2
D
1 A
2
B
2
C
2
A
2
>2ms
end read intmsk
In order not to lose D1
a read must have been
performed before A2
has been decoded.
DAVFLG DAVFLG set on
DAVN=0, cleared on
read BL-reg
B
2
T
INT_RD
Read BL Read BL Read BL
D
1
C
1
A
2
D
1
D
1
A
2
A
1
A
2
A
2
B
2
To prevent DOVF to
be set again, an
extra read of BL
must be performed
before A2 has been
decoded
Bus
Registers
A
1
B
1
C
1
D
1
A
2
B
2
DAVFLG
INTX
Read access
(Case 1)
t
INTX
T
INT_RD
t
Read
21.9ms
BL Register
BP Register
A
1
D
0
A
2
Data Overflow
bit
Read access
(Case 2)
t
Read
DAVFLG
(Case 2)
Case2: Late read of BL, BP register
Case 1: Normal DAV-C mode
Dashed line shows what would happen if no read occured at (a). DOVF bit set
until the next read of BP register, however,D1,A2 would be lost.
(a)
INTX cleared @ end read INTMSK
DAVFLG not cleared as no read performed
C
0
D
0
D
1
D
1
No read on INTX so
B1 will be lost
DAVFLG reset when
1
st
new block would
have been copied to
BL register
B1 copied to BLreg shortly before
C1 decoded
BLreg copied to BPreg
and C1 to BLreg
t
INTX
= 10 ms
DAVFLG cleared @ end read BPreg
and forced to zero till en read RDSR4
C
1
A
1 C
1
Instant copy of C
1
from
decoder buffer to BL
and BL to BP just
before D
1
decoded
due to read action.
2 new blocks
have arrived in
BL/BP register
2 new blocks have arrived in BL/BP (C
1,
D
1
) and a new block (A
2
)
has entered the decoder buffer. Hence, DOVF is set again. To
prevent this, an extra read must be performed after reading (a).
DAVFLG set when 2
nd
new block
in decoder buffer
Instant copy A
2
from decoder
buffer to BL and
BL to BP
Being
decoded
* Type: N53370
* Version: 2.7
CONFIDENTIAL
Date: 2004 Nov 09
Page: 68
- specpoint L12 changed text maximum to minimum
- specpoint L13 changed conditions from 5V to V
VREFDIG
V
- specpoint M2 removed preemphasis from conditions
- specpoint M11 removed text no pilot from conditions
- specpoint M12 added no pilot to conditions
- specpoint M13 changed upper limit, set to 2.5% added including 9 pilot to conditions
- specpoint M20 added limits
- specpoint M21 changed from 40uV to 30uV
- specpoint M23 added typical value 33dB
- specpoint M24 changed from 20uV to 10uV
- specpoint R2 updated limits and removed preemphasis from conditions
- specpoint R3 removed preemphasis from conditions
- page 53 updated figure 14 Mono Characteristics
- page 54 updated figure 15 Stereo Characteristics
- page 55 updated figure 16 Softmute and Overdrive Characteristics
- page 56 added figure 17 Level ADC conversion

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* Composed by: D. Janta, W. Brummelman

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