Thermal aware layout design

An independent study report submitted in partial fulfillment of the

degree of
Master of Technology
(VLSI-CE
by
Malli!ar"ungouda S# $atil
(%oll no& '()'*)+,-
under the guidance of
.r# Shubha"it %oy Choudhary
Center for VLSI and Embedded Systems Technology (CVEST/
International Institute of Information Technology/ 0yderabad#
Table of Contents
Abstract######################################################################################################################################################1
Introduction################################################################################################################################################+
0etero-2unction 3ipolar Transistors######################################################################################################-
Thermal a4are design################################################################################################################################-
.esign time solutions############################################################################################################################,
%un time solutions#################################################################################################################################,
$o4er dissipation in a VLSI chip##########################################################################################################,
Layout methods to reduce hotspots in ICs#################################################################################################5
Model description and problem formulation#########################################################################################5
Empty %o4 Insertion (E%I for 4ide hotspots######################################################################################5
Cell diffusion for concentrated hotspots##############################################################################################))
6on-uniform emitter finger spacing for multi-finger po4er 03Ts#####################################################)7
8sing a Through-9afer Via (T9V for multi-finger po4er 03Ts####################################################)*
E:periment and %esults###########################################################################################################################)1
Layout methods to remo;e 4ide and concentrated hotspots###############################################################)1
Layout method using non-uniform finger spacing for 03Ts##############################################################)5
Layout method using T9V for 03Ts#################################################################################################'(
Conclusion###############################################################################################################################################')
%eferences################################################################################################################################################')
List of figures
IIIT logo#####################################################################################################################################################)
<ig# )& Illustration of 4ide and concentrated hotspots###############################################################################5
<ig# '(a& Empty ro4 insertion bet4een ad"acent ro4s/ original layout##################################################)(
<ig# '(b& Empty ro4 insertion bet4een ad"acent ro4s/ after E%I###########################################################)(
<ig# 7(b& Cells in the hotspot diffuse in the surrounding area/ after 0S.##############################################)'
<ig# 7(a& Cells in the hotspot diffuse in the surrounding area/ original layout#######################################)'
<ig# *(a& Micrographs of the surface ;ie4 of the fabricated '(-finger po4er Si=e 03Ts/ uniform
finger spacing###########################################################################################################################################)7
<ig# *(b& Micrographs of the surface ;ie4 of the fabricated '(-finger po4er Si=e 03Ts/ non-uniform
finger spacing###########################################################################################################################################)7
<ig# 1(b& Layout of =aAs 03Ts/ using a T9V#######################################################################################)*
<ig# 1(a& Layout of =aAs 03Ts/ original layout####################################################################################)*
<ig# +& Schematic of .LL-based fre>uency multiplier#############################################################################)1
<ig# -& Layout of .LL-based fre>uency multiplier##################################################################################)+
<ig# ,& $o4er brea!-up of the layout under operation#############################################################################)+
<ig# 5& .LL layout 4ith E%I to remo;e 4ide hotspot#############################################################################)-
<ig# )(& .LL layout 4ith 0S. method to mo;e concentrated hotspots##################################################),
<ig# ))& .LL layout 4ithout 4ide or concentrated hotspots####################################################################),
<ig# )'& Input characteristics for 03Ts 4ith uniform and non-uniform finger spacing##########################)5
<ig# )7& Thermal profile across the multi-emitter fingers for 03Ts 4ith uniform and non-uniform finger
spacing#####################################################################################################################################################)5
<ig# )*& ?utput characteristics using routine and ne4 layout methods for po4er 03Ts########################'(
Abstract
9ith the continuing scaling of CM?S technology/ on-chip temperature and thermal-induced ;ariations
ha;e become a ma"or design concern# To effecti;ely limit the high temperature in a chip e>uipped 4ith
a cost-effecti;e cooling system/ thermal specific approaches/ besides lo4 po4er techni>ues/ are
necessary at the chip design le;el# The high temperature in hotspots and large thermal gradients are
caused by the high local po4er density and the nonuniform po4er dissipation across the chip#
9ith the ob"ecti;e of reducing po4er density in hotspots/ 4e study t4o placement techni>ues that
spread cells in hotspots o;er a larger area# Increasing the area occupied by the hotspot directly reduces
its po4er density/ leading to a reduction in pea! temperature and thermal gradient# To minimi@e the
introduced o;erhead in delay and dynamic po4er/ 4e maintain the relati;e positions of the coupling
cells in the ne4 layout#
9e ha;e made a study on the layout of multi-finger po4er 0etero-2unction 3ipolar Transistors(03T
4ith the ob"ecti;e of impro;ing its thermal stability# Si=e and =aAs are t4o most commonly used
03Ts and 4e ha;e studied ne4 layout methods for both of them#
Introduction
The dramatic increase in the degree of integration in CM?S technology has allo4ed the design of more
and more po4erful systems/ ranging from large mainframe ser;ers constituting bac!bones of the
Internet to portable hand-held de;ices/ 4hich enable people to be connected at anytime from any4here#
The increasing performance of ;ery large scale integration (VLSI circuits is accompanied by the
increasing po4er and po4er density/ 4hich e:hibit themsel;es in the form of heat and present a cooling
challenge# The cost of cooling solutions is a nonlinear function of po4er and/ to a large e:tent/ limits
the ma:imum amount of po4er that can be dissipated in a chip# To effecti;ely limit the high
temperature in a chip e>uipped 4ith a cost-effecti;e cooling system/ thermal specific approaches/
besides lo4 po4er techni>ues/ are necessary at the chip design le;el#
The rapid increasing "unction temperature can affect se;eral aspects of circuit design as many CM?S
circuit parameters are temperature dependent# The carrier mobility of a transistor decreases 4ith
increasing temperature/ 4hich lo4ers the dri;e current and leads to increased delays# The unit
resistance of a 4ire segment increases 4ith temperature ma!ing the delay on global 4ires/ especially
cloc! distribution net4or!s/ ;ery sensiti;e to high temperature and temperature gradient#
The une;enly distributed heat caused by large spatial ;ariations in po4er consumption at different
locations ma!es performance analysis difficult# Thermally induced de;ice mismatch is a ma"or concern
in high speed and high precision integrated circuit design/ such as cloc! distribution net4or!s/
arithmetic logic units/ data con;erters/ and amplifiers# Containing temperature and thermal gradient is
also critical in designing of mi:ed signal and analog integrated circuits#
Subthreshold lea!age has an e:ponential dependence on temperature# It has been sho4n that for e;ery
7( AC increase in temperature/ the amount of lea!age is more than double# The induced lea!age/ in
turn/ increases the total po4er consumption and causes further temperature rise# If the cooling system is
inade>uate to remo;e the generated heat fast enough/ the positi;e feedbac! loop bet4een temperature
and lea!age can e;entually cause thermal runa4ay and burn do4n the chip#
Temperature is also a ;ital factor in microelectronic systemBs reliability# 0igher "unction temperature
reduces mean time to failure for the de;ices/ 4hich has a direct impact on the o;erall system reliability#
It is reported that a small increase in operating temperature ()( ACC)1 AC can decrease the lifespan of
de;ices by t4o times# Many physical effects that cause reliability degradation are thermally acti;ated
processes# 6egati;e biased temperature instability and hot carrier in"ection effects/ 4hich are strongly
dependent on temperature/ degrade the performance of transistors in an irre;ersible manner o;er time#
These effects reduce a circuitBs lifetime and cause timing ;iolations e;entually# ?ther failure
mechanisms/ such as electromigration/ stress migration/ and dielectric brea!do4n/ are accelerated by
high temperature and temperature gradients causing permanent de;ice failures# According to IT%S/ the
"unction temperature of a semi- conductor de;ice must be !ept at ,1 AC or lo4er to ensure long-term
reliability#
0otspots are caused by high local po4er density/ 4hich results in faster temperature rise in hotspots
than full chip heating# $o4er density is defined as the po4er consumption per unit area# Various lo4-
po4er techni>ues can be applied to reduce the po4er consumption in hotspots# 0o4e;er/ po4er
consumption is dependent on circuit functionality and the room for reduction is not al4ays large# In
addition/ lo4-po4er techni>ues need to ha;e large timing granularity to be effecti;e for temperature
reduction# The time constant of on-chip heat conduction is in milliseconds/ 4hich is much larger than
the cloc! period in nanoseconds# Conse>uently/ any lo4-po4er techni>ues 4ith a short duration 4ould
ha;e a negligible effect on a circuitBs thermal profile#
At circuit design time/ the high local po4er density can be reduced through limiting thermal correlation
bet4een cells# 9hen cells 4ith large po4er consumption are placed close to each other/ the local po4er
density becomes so high that the region becomes a hotspot# Many physical design solutions ha;e been
proposed in the past/ including thermal-a4are partitioning/ floorplanning/ and placement# <rom the
definition of po4er density/ 4e can see that one direct 4ay of reducing po4er density is to increase the
hotspotBs area# It is desirable to reduce cell density mostly in hotspots instead of the 4hole circuit 4hile
maintaining (or e;en slightly increasing cell density in cooler regions#
Hetero-Junction Bipolar Transistors
%ecently/ because of the rapid gro4th of 4ireless communication mar!et/ hetero-"unction bipolar
transistor (03T technology is 4idely used for po4er amplifier($ A application due to their e:cellent
%< po4er performance# The 03T de;ices include t4o types that are silicon-germanium 03T (Si=e
03T technology and =allium Arsenide (=aAs 03T technology# In order to obtain high out put po4er
the $A designer often use multi-emitter-finger structure of 03T# .ue to thermal coupling bet4een these
emitter fingers/ a non-uniform "unction temperature across the multi-fingers is ine;itably resulted/ 4ith
the hotspot in the de;ice center# 3ecause of the positi;e temperature coefficient of emitter current/ the
center fingers conduct more current and conse>uently generate more heat/ 4hich gi;es rise to a local
hot spot and e;entually lead to the current gain collapse# These effect deteriorate the thermal stability
and the %< performance of the de;ices# Then impro;ement of the thermal stability of the multi-finger
po4er 03T is important for the $A design of Si=e 03T or =aAs 03T#
Si=e hetero-"unction bipolar transistor are ;ery attracti;e to high po4er applications due to the high
current handling capability and superior thermal dissipation capability compared to =aAs-based 03Ts#
Especially/ 4ith the continuing reduction in de;ice si@es and enhanced performance/ the increases in
current density and the subse>uent thermal effects should be concerned are more concerning#
Thermal aware design
Although the ele;ated temperature is caused by the increasing po4er consumption in a chip/ effecti;e
po4er management methods may not be ;ery useful for thermal management# $o4er dissipation is/ in
general/ spatially nonuniform across a chip/ and thus temperature in local hotspots can increase much
faster than full chip heating# Moreo;er/ po4er management performs a minsum optimi@ation/ 4hich
monitors full chip po4er consumption and attempts to lo4er the total energy consumed o;er an entire
application run# In contrast/ thermal management is a minma: optimi@ation problem/ 4here pea!
temperature at specific locali@ed hotspots is of concern# In addition/ heat distribution 4ithin a circuit
e;ol;es o;er timescales of hundreds of microseconds 4hile po4er dissipation changes e;ery cloc!
cycle/ 4hich is in nanoseconds# Conse>uently/ lo4-po4er techni>ues that reduce po4er dissipation at a
;ery short timing granularity do not ha;e an effect on reducing temperature# To perform thermal
management 4ithin a circuit/ techni>ues e:plicitly targeting the spatio-temporal thermal beha;ior are
needed# Thermal management can be di;ided into design time and run time techni>ues based on the
timing of acti;ation#
Design time solutions
.esign time thermal management in;ol;es the spatial arrangement of circuit structures in such a 4ay
that the ma:imum local po4er density is reduced#
The ad;antage of design time techni>ues is that they are applied during the physical implementation
stage and the incurred performance o;erhead can usually be optimi@ed# ?n the other hand/ the solution
is static and does not adapt to changes in thermal beha;iors such as the shifting of locations of hotspots
at runtime#
Run time solutions
%untime thermal management is also called .ynamic Thermal Management (.TM as they are
performed dynamically 4hen applications are running# .TM monitors chip temperature through
thermal sensors and triggers response mechanisms# %eacti;e .TM acti;ates responsi;e mechanisms
once the pea! temperature or thermal gradient e:ceeds predefined thresholds/ 4hile the timing of
acti;ation in proacti;e .TM is based on predictions of future temperatures# %esponse mechanisms
include dynamic po4er reduction techni>ues such as .ynamic Voltage and <re>uency Scaling (.V<S/
po4er gating and cloc! gating/ and architectural adaptation methods such as cloc! throttling/ limiting
the issue 4idth in multiple issue processors/ and tas! migration in multicore systems#
The ad;antage of runtime thermal management is that it can adapt to dynamic thermal beha;iors and is
suitable for applications 4here the 4or!load on bloc!s ;aries o;ertime as in the case of a
microprocessor# The disad;antage is that these techni>ues are usually comple: to implement and the
performance o;erhead due to the triggering of .TM can be significant#
ower dissipation in a !L"I chip
The ma"or source of heat generated in a VLSI circuit is the po4er dissipation of de;ices on the
substrate# The total po4er dissipation in a static CM?S gate can be 4ritten as/
$
total
D$
dynamic
E$
short-circuit
E$
lea!age
4here $
dynamic
denotes the po4er consumed 4hen charging and discharging the load capacitance during
signal transition/ $
short-circuit
represents the po4er dissipation 4hen the pullup and pulldo4n net4or!s are
simultaneously conducting/ and $
lea!age
is the static po4er caused by the static current dra4n from the
po4er supply#
La#out methods to reduce hotspots in ICs
$odel description and problem formulation
=i;en a ro4-based IC layout/ L/ 4ith area A
L
D(9FnF0/ 4ith n being the number of ro4s and 9 and
0 being the 4idth and height of a ro4/ and the corresponding thermal mesh made up of 6FM thermal
cells# Let A be the cross sectional area of a thermal cell and . be the critical delay of the circuit# Let G
be the hotspot region/ 4ith G L/ and si@e (6
G
FM
G
thermal cells/ allocate additional 4hitespace in
order to minimi@e the po4er density of the hotspot region such that/
)# the introduced area o;erhead is lo4er than a user defined threshold/
A
L
HDA
Lnom
()EI
area
/
'# the delay o;erhead on the critical path is smaller than a user defined threshold/
.
p
HD.
pnom
()EI
timing
#
<ig# ) sho4s t4o different types of hotspots# The layout placement methods proposed belo4 are the
solutions for each type of hotspot#
<ig# )& Illustration of 4ide and concentrated hotspots#
Empty Row Insertion (ERI) for wide hotspots
8nder this scheme/ the granularity of the area slac! insertion is a layout ro4# Conceptually/ it 4or!s as
follo4s& in the area of a gi;en hotspot/ 4e insert an empty ro4 bet4een e;ery ad"acent ro4# The
method is illustrated in <ig# '/ 4here dar!er rectangles indicate cells in the hotspot region and the
lighter rectangles indicate cells in the cool region# <ig# '(a sho4s the original layout 4ith a 4ide
hotspot region and <ig# '(b sho4s the layout after the E%I method is applied# As sho4n in <ig# '(b/
an empty ro4 is inserted bet4een each ro4 in the hotspot region 4hile the cool region remains the
same as the original layout# This ro4 of 4hitespace 4ill be filled 4ith filler cells that do not consume
po4er such that 4e only increase the area of the hotspot region#
(a (b
<ig# '& Empty ro4 insertion bet4een ad"acent ro4s# (a ?riginal layout# (b After E%I
The algorithm for E%I is/
)# I6$8T& %o4-based IC layout#
'# I6$8T& Thermal map#
7# I6$8T& Area and timing constraint#
*# Locali@e the 4ide hotspot region G#
1# List all the ro4s belonging to the hotspot region/ ro4
i
G#
+# Initiali@e the empty ro4s/ n
e
D(AFI
area
J9#
-# Insert ro4s from the middle of the hotspot#
,# 9hile timing constraint is ;iolated/
K.
p
L.
p nom
()EI
timing
M /
do
)# re;ert layout/
'# decrease the number of empty ro4s/ n
e/
7# insert n
e
ro4s in the middle of the hotspot/
*# update 4iring and po4er information/
1# update timing information#
end 4hile
5# =enerate ne4 thermal map#
)(# ?8T$8T& ?ptimi@ed layout#
9e first initiali@e the number of empty ro4s to the ma:imum a;ailable/ 4hich means that the area
o;erhead meets e:actly the area constraint# The empty ro4s are then inserted in a bisectional fashion
starting from the hotspot center# <or e:ample/ half of n
e
empty ro4s 4ill be inserted to the upper half of
the hotspot# The increase in area might introduce too much e:tra 4irelength causing delay constraint
;iolation although the reduction in po4er density is the largest# In such a case/ 4e re;ert to the original
layout and decrease the number of ro4s to insert/ 4hich subse>uently shrin!s the area and reduces the
timing o;erhead# The procedure is repeated until the timing constraint is not ;iolated# At the end of
each iteration/ timing analysis is performed to update circuit delay and po4er consumption is re-
e;aluated to update any changes caused by the increase in 4irelength# In this 4ay/ 4e achie;e po4er
density reduction through empty ro4 insertion 4ithout ;iolating the area or timing constraint#
Cell diffusion for concentrated hotspots
<or a concentrated hotspot/ it 4ould be more desirable to ha;e a larger reduction in po4er density in
the area of the hotspot than in the cooler regions# 9e increase the area of the hotspot in-site of its
original location/ 4hich means that the cell cluster constituting a hotspot 4ill gro4 in dimension as
illustrated in <ig# 7# Cells in the hotspot belonging to the same ro4 are mo;ed together and the original
ro4 ordering is preser;ed#
The ne4 location of each cell is calculated as a function of the total number of ro4s to mo;e and the
cellBs ro4 inde: 4ithin the hotspot# <or e:ample/ in <ig# 7(a/ cell A on the top most ro4 (ro4
A
D( in
the hotspot is mo;ed t4o ro4s up4ard# Cell 3/ 4hich has a ro4 inde: of ) (ro4
3
D) in the hotspot/ is
mo;ed one ro4 up4ard# The same procedure is applied to cells on the lo4er half of the hotspot# In the
end/ hotspot cells originally located on consecuti;e ro4s are no4 placed 4ith one cold ro4 in bet4een#
<or e:ample/ cell A and cell 3 are no4 ;ertically separated by one ro4# Conse>uently/ the hotspot
gro4s in area and diffuses into neighboring area such that po4er density is reduced in 4ell-defined
layout regions#
The algorithm for 0ot Spot .iffusion (0S. is/
)# I6$8T& %o4-based IC layout#
'# I6$8T& Thermal map#
7# I6$8T& Area and timing constraint#
*# Locali@e the hotspot region/ G#
1# List all the gates belonging to the hotspot region/ g
i
G#
+# List hot cells in the same ro4/ subro4"Dro4
"
NG#
-# Calculate the displacement for each cell/ dstDn
d
-ro4
gi
#
,# Mo;e n
d
subro4s to the neighboring cold area#
5# 9hile timing constraint is ;iolated/
K.
p
L.
p nom
()EI
timing
M /
do
)# re;ert layout/
'# decrease the number of subro4s to diffuse/ n
d
/
7# calculate displacement for each cell/ dstDn
d
-ro4
gi
/
*# mo;e n
d
ro4s to the neighboring area/
1# update 4iring and po4er information/
+# update timing information#
end 4hile
)(# =enerate ne4 thermal map#
))# ?8T$8T& ?ptimi@ed layout#
(a (b
<ig# 7& Cells in the hotspot diffuse in the surrounding area# (a ?riginal layout# (b After 0S.#
As in the empty ro4 insertion method/ 4e first try the ma:imum number of subro4s to diffuse/ 4hich
means cells belonging to the hotspot (part of a placement ro4 4ill be ;ertically mo;ed to neighboring
regions in the specified directions# If the timing constraint is ;iolated/ 4e re;ert the layout and decrease
the number of subro4s to diffuse until the timing constraint is met#
%on-uniform emitter finger spacing for multi-finger power HBTs
9e consider a Si=e multi-finger po4er 03T ha;ing '( emitter fingers# <or the traditional po4er Si=e
03Ts 4ith uniform finger spacing/ the self-heating effect and thermal coupling effects among emitter
fingers result in a higher temperature at the central fingers# 3ecause of the positi;e temperature
coefficient of emitter current/ the central fingers conduct more current and conse>uently generate more
heat/ 4hich e;entually gi;es rise to a local hotspot and possibly permanent de;ice damage# %esults
ha;e sho4n that the thermal stability can be impro;ed by using non-uniform finger spacing#
<ig# * sho4s the micrographs of the surface ;ie4 of the fabricated '(-finger po4er Si=e 03Ts 4ith
uniform and non-uniform finger spacing# The emiiter strips for both the strips are ha;ing an area of
7:+(Om
'
#3oth the 03Ts ha;e the same structure in each finger and same total spacing#

(a (b
<ig# *& Micrographs of the surface ;ie4 of the fabricated '(-finger po4er Si=e 03Ts# (a 8niform
finger spacing# (b 6on-uniform finger spacing#
<or a '(-finger 03T/ there are )5 finger spacings measured from the central of each emitter finger#
Considering the symmetry/ there are )( spacing ;alues to be designed# Assuming the spacing ;alues to
be P
)
/ P
'
/####P
)(
4here P
)(
denotes the central spacing# The table belo4 sho4s the spacing ;alues for
the t4o types of 03Ts/
P
)
P
'
P
7
P
*
P
1
P
+
P
-
P
,
P
5
P
)(
uniform
finger
spacing
'( '( '( '( '( '( '( '( '( '(
non-
uniform
finger
spacing
)+ )+ ), ), '( '( '' '' '* '*
%esults ha;e sho4n that the Si=e 03T 4ith non-uniform finger spacing has better thermal stability/
uniform temperature profile/ higher thermal resistance and higher po4er le;el for thermal regression#
&sing a Through-'afer !ia (T'!) for multi-finger power HBTs
9e consider a =aAs po4er 03T 4ith , fingers# The routine layout consists of four
'(fingers:'Om(emitter-4idth:*(Om(emitter-length# The emitter fingers ha;e uniform spacing
bet4een them# The interconnect metal of the eight emitter fingers are outside the acti;e thermal emitter
area#
<ig# 1 sho4s the routine layout and the impro;ed layout# The ne4 layout consists of an additional
Through-9afer Via (T9V# The T9V 4as inserted in the center of the po4er transistor 4here the
thermal coupling is the most# There is no acti;e emitter finger located in the center of the thermal
couple# So/ the thermal electric feedbac! 4ould be suppressed effecti;ely# Simultaneously/ the heat
coupling to the center can be collected and conducted to the substrate of the de;ice by the T9V# Also/
the emitter finger 4as connected by a 4ide metal layer that 4as e:actly on the acti;e thermal emitter
area# Since the acti;e emitter fingers are closely coupled to each other by the metal layer/ the difference
of the temperature bet4een the fingers can be reduced and the heat 4ould flo4 to the T9V easily# The
thic!er metal layer thus impro;es the ability of heat conduction#
The ne4 layout is simple and the designer need not change the finger length of the 03T cell from the
foundry library or to pay much attention to calculate the non-uniform space of the fingers#
(a (b
<ig# 1& Layout of =aAs 03Ts# (a ?riginal layout# (b 8sing a T9V#
The ne4 layout has impro;ed an impro;ed thermal stability# The thermal resistance of the ne4 layout is
less/ 4hich means it has a higher I
collapse
and higher po4er density at 4hich the de;ice can remain
thermally stable# The ne4 layout also has a better %< gain#
The ne4 layout is ;ery simple and easy to be adopted by a po4er amplifier circuit designer to impro;e
the thermal stability of a po4er 03T#
*+periment and Results
La#out methods to remo,e wide and concentrated hotspots
9e applied the methods discussed abo;e to remo;e 4ide and concentrated hotspots to our M#Tech# *
th
semester pro"ect& QA ) =0@ .elay Loc!ed Loop (.LL based fre>uency multiplier in ),( nm CM?SR#
The figures belo4 sho4 the schematic and layout of the entire circuit#
<ig# +& Schematic of .LL-based fre>uency multiplier#
<ig# -& Layout of .LL-based fre>uency multiplier#
The layout/ under operation consumes a po4er of '#7, m9# The figure belo4 sho4s the po4er
brea!up/ i#e#/ the po4er consumed by the indi;idual bloc!s in the layout#
<ig# ,& $o4er brea!-up of the layout under operation#
<rom the abo;e figure/ 4e see that most po4er is consumed by VC.L bloc!# This results in a 4ide
hotspot# This 4ide hotspot can be remo;ed by inserting empty ro4s in the VC.L layout/ thus
increasing the area and reducing the po4er density# The figure belo4 sho4s the ne4 layout#
<ig# 5& .LL layout 4ith E%I to remo;e 4ide hotspot#
<rom <ig# , abo;e/ 4e also see that the $<. and C$JL< bloc!s also consume significant po4er and
4hen placed close to VC.L bloc!/ may result in concentrated hotspots in the regions 4here the bloc!s
meet# These concentrated hotspots can be remo;ed by placing less po4er consuming bloc!s li!e 6?T
and T= in bet4een the po4er hungry bloc!s as sho4n in the figure belo4#
8sing the abo;e methods/ 4e arri;e at the layout sho4n in <ig# )) 4hich has no 4ide or concentrated
hotspots#
<ig# )(& .LL layout 4ith 0S. method to mo;e concentrated hotspots#
<ig# ))& .LL layout 4ithout 4ide or concentrated hotspots#
La#out method using non-uniform finger spacing for HBTs
<ig# )' sho4s the input characteristics for 03Ts 4ith uniform and non-uniform finger spacing# <or the
03T 4ith uniform spacing/ thermal collapse occurs at I
C
D))* mA and $
.C
D5)' m9# <or the 03T 4ith
non-uniform spacing/ thermal collapse occurs at I
C
D)*( mA and $
.C
D))'( m9# Thus/ the 03T 4ith
non-uniform finger spacing has higher current carrying capability before thermal collapse#
<ig# )'& Input characteristics for 03Ts 4ith uniform and non-uniform finger spacing#
<ig# )7 sho4s the thermal profile for both the 03Ts# <rom the figure/ 4e see that there is high
temperature in the central fingers for the 03T 4ith uniform spacing# The pea! temperature in 03T
4ith uniform spacing is *(1#-1 S 4hile the pea! temperature in 03T 4ith non-uniform spacing is
75(#)' S# The ma:imum temperature difference in 03T 4ith uniform spacing is 7+#1* S 4hile the
ma:imum temperature difference in 03T 4ith non-uniform spacing is ')#15 S#
<ig# )7& Thermal profile across the multi-emitter fingers for 03Ts 4ith uniform and non-uniform finger
spacing#
The ne4 layout method also has an impro;ement in thermal profile by )7#+5T and an impro;ement in
current carrying capability by ''#,T#
La#out method using T'! for HBTs
<ig# )* belo4 sho4s the output characteristics for the routine layout and ne4 layout of po4er 03Ts#
<rom the figure/ 4e see that the ne4 layout has an impro;ement in .C performance# In the old layout
method/ the current collapse occurs at a po4er density of (#-+ m9Om
-'
/ in the ne4 layout method/ the
current collapse occurs at a po4er density of )#)* m9Om
-'
# There is a larger margin for stable
operation in the ne4 layout method#
<ig# )*& ?utput characteristics using routine and ne4 layout methods for po4er 03Ts#
Conclusion
0igh local po4er densities/ 4hich cause temperature rise in hotspots/ can be reduced through
increasing the area in hotspots# The problem of hotspots can be sol;ed by increasing the area/ thereby
decreasing the po4er density# The relati;e position bet4een coupling cells is preser;ed to limit the
introduced delay due to the increase in 4irelength# As a part of this independent study/ 4e studied t4o
layout placement techni>ues to minimi@e 4ide hotspots and concentrated hotspots# The methods 4ere
applied to the layout of .LL#
9e studied ne4 layout methods for 03Ts 4ith multiple fingers# 9e used the techni>ue of non-uniform
finger spacing on Si=e 03T 4ith '( fingers# The ne4 layout has higher thermal stability and current
carrying capability as compared to the routine layout# 0igh temperature at the center of the emitter
fingers can also be minimi@ed by using a Through-9afer Via (T9V# This techni>ue 4as used on a
=aAs 03T 4ith , fingers# The ne4 layout has higher current carrying capability and thermal stability#
<rom this independent study/ 4e finally conclude that problems due to thermal effects in Integrated
Chips(ICs can be sol;ed by intelligent application of layout techni>ues#
References
)# QAlgorithms for VLSI physical design automationR by 6a;eed Sher4ani#
'# Layout-.ri;en $ost-$lacement Techni>ues for Temperature %eduction and Thermal =radient
Minimi@ation 9ei Liu U Calimera/ A# U Macii/ A# U Macii/ E# U 6annarelli/ A# U $oncino/ M#
Computer-Aided .esign of Integrated Circuits and Systems/ IEEE Transactions on
7# Layout design of multi-finger po4er Si=e 03Ts for thermal stability impro;ement 2in .ongyue
U Vhang 9anrong U Shen $ei U Pie 0ongyun U Win 2i:in U 9ang Wang U Vhang 9ei U 0e Li"ian U
Sha Wongping U Li 2ia U =an 2unning 6anoelectronics Conference/ '((,# I6EC '((,# 'nd IEEE
International
*# A ne4 layout method to impro;e the thermal stability of Multi-finger po4er 03T Chen/ W# U
Shen/ 0# U Liu/ P# ASIC/ '((5# ASIC?6 X(5# IEEE ,th International Conference on .igital
?b"ect Identifier& )(#))(5JASIC?6#'((5#171)*7(
1# Electrical and thermal layout design considerations for integrated po4er electronics modules
2onah Vhou Chen U Wing <eng $ang U 3oroye;ich/ .# U Scott/ E#$# U Thole/ S#A# Industry
Applications Conference/ '(('# 7-th IAS Annual Meeting# Conference %ecord of the