Current Steering Logic for

mixed-signal applications
M. Kayal & M. Pastre
Swiss Federal Institute of Technology (EPFL)
Electronics Laboratory
1015 Lausanne- Switzerland

1
 Outline
Outline
Ø Introduction
Ø Current Steering Logic (CSL)
Ø CSL Inverter Analysis
Ø Application : Autozero Op. Amp.
Ø Experimental results
Ø CSL CAD tools
Ø Conclusions

2
 Digital
Digital Switching
Switching Noise
Noise

Epoxi Die attache pad

L Chip die Bond wire
Veff Leadframe
i(t) Vdd

Heat sink
Inductive loop

CL VVCL
CL

Veff = Vdd-L di(t)/dt

i(t)=
i(t)=C.
C.d(V
d(VCL )/dt = C. Vdd /dt
CL )/dt = C. Vdd /dt
3
 Mixed-signal
Mixed-signal

Digital circuit Analog circuit

• Noisy part • Sensitive part
→ Power supply
→ Substrate coupling → High impedance
→...

Ø Shielding techniques.
Ø Increasing the matching and symmetry of analog part (differential designs).
Ø Decreasing
4
the switching noise in the digital part
 Static
Static Logic
Logic
Advantages
Static inverter
ü Simple design
Vdd
ü High packing density
ü Wide noise margins
A A
ü High operating frequencies
ü No static power dissipation.

Drawbacks
v High Digital Switching Noise
5
 Folded
Folded Source
Source Coupled
Coupled Logic
Logic
Advantages :
Folded Source Coupled Logic
(FSCL) ü Low Digital Switching Noise
Vdd
ü Differential strategy
Vo
I2 I2
Vo
ü Robustness of logic levels
βD βD
ü Small Logic Swing.
Vin
βL βL
Vin Drawbacks :
I1
v Complex design
v Several transistors per gate
v Low noise margins
6 v Static power dissipation.
 Current
Current Steering
Steering Logic
Logic
Advantages
Current Steering Logic ü Reduced Logic Swing
(CSL) ü Simple layout and routing
Vdd
ü High Density
I
Vout
ü Few transistors per gate
Vin
βL βD
ü Tolerant of technological fluctuations.
Drawbacks
v Larger Current Spikes than FSCL
v Low noise margins
v Static power dissipation
7
 Current
Current Steering
Steering Logic
Logic
CMOS inverter Current Steering Logic
(CSL)
Vdd
Vdd

I
Vin Vout Vout

Vin
βL βD

ØTarget
Ø Target Application
Application :: Mixed-Mode
Mixed-Mode Design
Design
Ø
Ø Key
Key aspect
aspect for
for evaluation
evaluation :: Digital
Digital Switching
Switching Noise
Noise
8
 Experimental
Experimental Noise
Noise Comparison
Comparison

38 CMOS static inverters

5V In1
Stat. Stat. Stat.
56K D1 Inv. Inv. Inv.
T1 Axis of
0V symmetry 5V
56K
56K
T1
100nF 0V T2 T2
0V D2 56K CSL CSL CSL
In2 100nF inv. inv. inv.
38 CSL inverters
0V

Schematic Diagram Chip

9
 Measurements
Measurements of
of Switching
Switching Noise
Noise
1.5E-1 1.5E-2

1.0E-1 1.0E-2
CMOS Static Noise [V]

CSL Noise [V]

5.0E-2 5.0E-3

0.0E+0 0.0E+0

-5.0E-2 -5.0E-3

-1.0E-1 -1.0E-2
0.E+0 2.E-6 4.E-6 6.E-6 8.E-6 1.E-5
Time [s]

= 20 µA
Ø Ibias
Ø VDD = 2.5 V
10
 CSL
CSL Static
Static Characteristics
Characteristics
Region II Region III Region IV
Vdd
VOH
I VI = V O

Ouput Voltage [V]

Region I

ILOGIC VOUT
IDIODE
D
VT0N
MD VIN ML VP

Gv - parameter of design VOL

β 0.0
L
VT0N V1 V2 VOH
Gv = L Input Voltage [V]
βD Region ML MD
I OFF ON - Saturation
β = µ Cox W/L II
III
ON - Saturation
ON - Saturation
ON - Saturation
OFF
IV ON - Triode OFF

11
 CSL
CSL Static
Static Characteristics
Characteristics
2.0
Ø Output high logic level VOH

VOH, VOL, VTH [V]

D 2.n.I.Gv 1.5
VOH - V =
βL
T0n VTH
1.0
Ø Logic threshold voltage
0.5
 VOH − V  D
VTH = V + 
L
 T0n VOL
 1+ Gv 
T0n 0.0
2 3 4 5 6
Gv
Ø Ouput low logic level
VOL = (VOH − VTL0n ) (1− 1 -Gv−1 )
Simulated,
Simulated, Measured
Measuredand
andCalculated
Calculated

The smaller is Gv the smaller can be the power supply voltage

12
 Noise
Noise Margin
Margin
1.0
Ø Low logic level noise margin NM L

( )
NML = VOH − VTD0n ⋅ (A − B)+ VTL0n 0.8

NMH, NML [V]

A= 1 ⋅ 2 1
0.6 NMH
Gv n ⋅ Gv+ 1 0.4
1
( )
B = ⋅ 1 − 1 − Gv−1
n
0.2

0.0
Ø High logic level noise margin 2 3 4 5 6
 ( )  Gv
+ 2
NMH=(VOH−VT0n)⋅ 1−
D  1 n 1 
⋅
 2⋅ n +1 Gv Simulated,
Simulated, Measured
Measuredand
andCalculated
Calculated

The higher is the Gv the larger is NMH, for a constant NM L.

13
 Dynamic
Dynamic Results
Results
Ø High to Low propagation time 2.5E-9
2 n CL

Inverter delay [s]

βD 2.0E-9
tpHL = −
2 ⋅ n⋅ I
{A − B}
⋅ Gv − 1 1.5E-9
βD
Simulated
Simulated
Ø Low to High propagation time 1.0E-9

5.0E-10 Measured
Measured
( )
CL CL
tp LH = ⋅ VTD0n − VOL + ⋅ ln(C)
I 2 ⋅ n⋅ I 0.0E+0
βD ⋅
βD 2 3 4 5 6
  Gv
B = arctg
1 1 
A = arctg  
 ( )− 
Gv
2
1   Gv − 1

1− 1  u IIbias
u = 20 uA
bias = 20 uA
 
C= 1 + Gv 
1 u VDD
u VDD==2.5
2.5VV
1+ 
14  1 + Gv 
 Second
Second Order
Order Analysis-
Analysis-Mismatching
Mismatching

Variance of NMH u Example of application

• I=20.10-6 A,
σ (δNMH ) = σ δV
2 2 D
+ σ δV
2 L
+
2
T0N T0 N
• (W/L)D=2.5µm/3µm,
 1 n ⋅ gmP β P   2  δβ P  
2 δβ D
 • (W/L)L=2.5µm/1µm,
 ⋅ ⋅ ⋅ σ
    + σ   +
2 βP βL    β P   βD   • (W/L)P=8µm/1µm
Device σ(δVT) [mV] σ(δβ/β) [%]
2
 1 (1 + n) n ⋅ gm    δβ 
 ⋅  σ 2  P  + σ 2  δβ L  
2

 ⋅ β
⋅ P
⋅ P
∼11 ∼1
 2 2⋅ n+1 βP β L    β P   βL   MD

ML ∼21 ∼2
 gmP β P   (1 + n)  1 n ⋅ gmP  
2 2 2
∼11 ∼1
σ δV
2
( P
T 0P )
⋅ ⋅
β
 ⋅ 
⋅ +
+ ⋅
 β




MR
 PI D   2 n 1 2 
σ(δNMH) = 0.066V
P

15
The final noise margin should be positive.
 Second
Second Order
Order Analysis-Thermal
Analysis-Thermal Effects
Effects
∆T⋅ BEX 2⋅ n⋅I
∆VOH= − ⋅ −TCV∆T
2+BEX
2⋅ Tref  W  T 
KP ⋅  ⋅  
 Ld  Tref

∆VOL = (∆VOH + TCV∆T) (1− 1− Gv−1 )

 (1+ n)2 
(
∆NMH= ∆VOH+TCV∆T ⋅ 1− )
2⋅ n+1
⋅ Gv−1 
 

T VOH VOL
16
 Mixed-Mode
Mixed-Mode Circuit
Circuit Choice
Choice

ØThe
ØThe chosen
chosen circuit
circuit was
was an
an autozero
autozero Op.Amp.
Op.Amp.
Ø
Ø Method
Method ofof compensation
compensation isis based
based on
on the
the offset
offset
current
current cancelling.
cancelling.
Ø
ØA A ping-pong
ping-pong scheme
scheme has
has been
been implemented
implemented to
to
improve
improve temperature
temperature drift
drift of
of autozero
autozero amplifier.
amplifier.

17
 Current
Current Offset
Offset Cancelling
Cancelling
vDD
Cc
M Ip IL
Uoff gm A
Ioff IDAC Vout

vSS

IILL =
= IIoff
off
 +
+ Ip
Ip -- II
DAC
DAC
=
= 0
0
18
 Self
Self Adjusting
Adjusting Amplifier
Amplifier
vDD
+
Ip +
Uoff OA
- Vout
COMP
M -
IDAC
DAC SAR
CLOCK

ggmm U
Uoff,max
off,max
=
= I
IDAC,max
DAC,max
/2
/2 =
= I
Ipp
19
 Theoretical
Theoretical Minimum
Minimum Offset
Offset
Vout
Vsat+ Uoff,max Max. offset
-Uoff,max Vin Uoff,min Min. offset
Uoff,max N DAC resolution
IDAC,max
Vsat- Uoff,min=
gm. 2N+1
Transfert curve
20
 SELF ADJUSTING SEQUENCES
Vout[V] 1 ∆t N=1-3 ∆VOUT= 2.Vsat
2.8 V 3 4 5
N=4-6 ∆VOUT = Uoff.Au
2 6
0V
4 8 12 16 20 24 28 32
IDAC [nA] ∆VOUT.Cc
∆t =
t[ms]
100
1 IL
2
50 3 4 5 6
0
4 8 12 16 20 24 28 32
t[ms]
Uoff IL ∆t
21
 Ping-Pong
Ping-Pong Principle
Principle
IDAC1 IP1
Vin- A1
A2 A2

+
A1 DAC1
A1 OA1
-
A4 A2 COMP SAR1 Vout
+
A5
A4 -
A3
- A5 SAR2
A1 OA2
+

Vin+ A1
A3 A3
A1 DAC2 IP2
IDAC2
22
 Op. Amp. Swapping
- -
-
OA1 OA1 OA1
+ +
+

- - -
OA2 OA2 OA2
+ + +

1- OA1 is under compensation

2- OA1 same condition as OA2
3- OA2 is under compensation
23
 Microphotograph
Microphotograph of
of the
the ASIC
ASIC
1 mm
DAC1
AO1
Digital block: 0.5 mm
COMP SW SAR1 & SAR2
AO2 P-P Timing

DAC2

24
ATMEL-
ATMEL- 0.7µm
0.7µm Technology
Technology
 CSL & Static implementation

Ø Same logic blocks realized in CSL and CMOS Std static

§ CSL § Static CMOS

Area = 0.5 mm2 Area =0.54 mm2
 CSL-Noise
CSL-Noise Measurement
Measurement
Vout[dBm]

OA
- -82(CSL)
Vout-32(Static)

0 1 2 3 4 [KHz]
26
 CAD
CAD tools
tools
ØAnalytical
Ø Analytical Approach:
Approach:
ü1ststorder design.
ü1 order design. ØSymbolic
Ø Symbolic Layout
Layout Editor:
Editor:
ØSimulation
Ø SimulationApproach:
Approach: üLayout
ü Layout generation.
generation.
üdesign
ü design adjustment.
adjustment.

CellEdit
CellEdit
CSL_ASLIB
CSL_ASLIB
27
 CAD
CAD Tool
Tool for
for CSL
CSL Libraries
Libraries Design
Design

CSL_ASLIB
Input Output
Simulator engine
User’s specifications
•Maximum frequency
•Load capacitance Procedural Cell Design
•Minimal noise margin
•Supply voltage Spice like
Parsing engine file
Data for Spice and
Base HDL format
Technology parameters
for EKV_MOS Model
Data base management

28
 Gates
Gates Optimization
Optimization Algorithm
Algorithm
User’s specifications

F o , NMHo , C load , VDD

Procedural cell Design

Io, Gv

Transistor sizing
Gv ← Gv ± 0.1
DC simulation

No
300< NMH < 350mV

Yes

Transient simulation Io ← Io*F o / Freq

F o -5% ≤ Freq ≤ F o+5% No

Yes
W(M L)←W(M L)+Wmin
Io_optimum ← Io

Yes
Io < Io_optimum

No
Io_optimum
Optimal transistor sizes

29 Writing in Data Base

 CellEdit
CellEdit :: Layout
Layout Generator
Generator Tool
Tool

Input Output

CSL Transistor size Layout

AS_LIB parameters (W/L) (CIF file)
CellEdit
Technology Simulation
parameters parameters

30
 CellEdit
CellEdit -- Design
Design Flow
Flow
Technology
Technology Editor
Editor

User Symbolic
Symbolic Editor
Editor Layout
Layout Editor
Editor
Compactor

Cell
Symbolic

Layout

Library
Library Editor
Editor
31
 CAD tools-interface

CSL
AS_LIB

CellEdit

32
 CSL
CSL Logic
Logic Gates
Gates Examples
Examples
VDD VDD
VDD
VDD Vbias cn Sn Vbias
Vbias
Vbias
bn cn-1
A
out
out
cn-1
an
A B an an bn
B an bn cn-1 bn

Nand Nor One bit full adder

Ø Layout
Ø Layout of
of basic
basic CMOS
CMOS static
static gates
gates isis smaller
smaller than
than the
the CSL
CSL
Ø When
Ø When the
the number
number of
of inputs
inputs and
and the
the complexity
complexity of
of gates
gates increase,
increase,
CSL
CSL area
area becomes
becomes comparable
comparable
33
 Power
Power Consumption
Consumption Consideration
Consideration
Power Consumption [µW]
300
Flip-Flop JK

Static
200
CSL

100 Inverter

0
25 50 75 100
Frequency [MHz]

Ø At
Ø At high
high frequencies
frequencies CSL
CSL JK
JK flip
flip flop
flop dissipates
dissipates less
less power
power than
than
CMOS
CMOS static
static logic
logic while
while using
using approximately
approximately the
the same
same area
area
34
 Conclusions
Conclusions
♦The reduction of switching noise in mixed-
mode circuits can be obtained using CSL.
♦The automatic design flow for the CSL
demonstrate that this approach is ready for
industrial applications.
♦Logic architectures for power consumption
management is the next challenge.

35