IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO.

6, JUNE 2003 911

A Single-Stage Variable-Gain Amplifier With

70-dB Dynamic Range for CDMA2000
Transmit Applications
Sudhir Aggarwal, Senior Member, IEEE, Abolfazl (Saeed) Khosrowbeygi, Member, IEEE, and
Anton Daanen, Member, IEEE

Abstract—A variable-gain amplifier (VGA) circuit is presented
with a gain range of more than 70 dB in a single stage. Vertical
stacking of multipliers in a single-stage VGA results in a consider-
able saving of power, which is a prime requirement in cellular sys-
tems. The gain-in-dB is a linear function of the control voltage and
has excellent stability over temperature. The amplifier is a part of
a code-division multiple access cellular transmit integrated circuit,
and provides good linearity and noise characteristics over a wide
range of IF frequencies. The circuit is fabricated in a 30-GHz
BiCMOS technology and consumes 8 mA at 2.7 V.
Index Terms—Code-division multiple access (CDMA), gain con-
trol, variable-gain amplifier (VGA).
I. INTRODUCTION
I N CELLULAR wireless communication applications, the
received and transmitted signals can have a wide range of
amplitude depending on the instantaneous signal path and other
obstructions, and hence, the transmitter and receiver must be de-
signed to handle this. In code-division multiple access (CDMA)
systems [1]–[3], the mobile transmitter is required to provide at
least 80 dB of the dynamic gain range. Normally, this is split be-
tween the intermediate frequency (IF) and radio frequency (RF)
stages, with typically 60 dB at IF and another 20 dB in the RF
stage. The variable-gain amplifier (VGA) must also meet strin-
gent linearity and receive-band noise requirements consistent
with the various air interfaces, while operating on battery supply
voltages as low as 2.7 V with minimal current consumption.
There are practical limitations in realizing a wide dynamic
range from a single stage because of device nonlinearity and par-
asitics associated with a large excursion of operating point. In
order to cover such a wide dynamic gain range, existing VGAs
use multiple stages of amplification or attenuation [4]–[6]. Mul-
tiple stages require more supply current, and the noise and lin-
earity degrade at the output of each stage as more stages are
cascaded.
In this paper, an IF VGA circuit is presented that is specif-
ically intended for cellular transmit IC applications [7]. In
Section II, the specification requirements of a mobile station
transmit VGA are discussed. Section III describes the circuit
Manuscript received December 4, 2001; revised February 24, 2003.
S. Aggarwal is with Philips Semiconductors, San Jose, CA 95131 USA
(sudhir.aggarwal@philips.com).
A. Khosrobeygi was with Philips Semiconductors, San Jose CA 95131 USA.
He is now with RF Micro Technology, Cupertino, CA 95014 USA.
A. Daanen is with Philips Semiconductors, San Jose, CA 95131 USA.
Digital Object Identifier 10.1109/JSSC.2003.811868
0018-9200/03$17.00 © 2003 IEEE
and implementation details with the simulated results. In Sec-
tion IV, experimental results obtained from the measurements
made on a transmit IC are presented. This is followed in
Section V by the conclusions drawn from this work .
II. VGA REQUIREMENTS
Our objective has been to design a VGA for the transmit sec-
tion of a CDMA mobile station operating in both the CELL
(TX 824–849 MHz) and PCS (TX 1850–1910 MHz) frequency
bands. A block diagram of the signal path for a typical transmit
IC is shown in Fig. 1(a). The base-band current input is up-
converted to an IF signal by the modulator driven by a
very high-frequency oscillator. For the gain control, it is fol-
lowed by an IF VGA. The IF VGA has an external LC tank as
its load, which is used to reduce the noise in the receive band.
The external tank is tuned according to the different IF frequen-
cies used in the CELL and PCS bands. The output of the IF
VGA is again converted to a quadrature ( and ) signal by the
phase shifter for upconversion by an RF mixer. For the RF up-
conversion, a single side-band (SSB) mixer is used which is an
image-reject type and, thus, results in saving a filter. The signal
up to this stage is a differential current. At the output, the signal
required is a single-ended voltage, therefore, the final stage is a
single-ended power amplifier (PA) driver. The RF stages have
about 20–30 dB of gain control. The CDMA mobile station is
required to meet the overall system specification imposed by
CDMA2000 [1] as well as the earlier IS-95 standard [2]. There-
fore, to meet these overall requirements, the IF VGA specifica-
tions were fixed as follows.
1) The gain range at IF frequencies (100–500 MHz) was
chosen to be 70 dB. In the transmit IC, where this VGA
has been used, the preceding modulator stage and the
following up-mixer stage were current mode [7]. There-
fore, the VGA was also chosen to be current mode with
a typical signal input of 1.5-mA peak current. In order to
save current consumption, the maximum output was also
fixed to be 1.5 mA peak. Therefore, this VGA actually
provides a current attenuation range of 0 to 70 dB.
2) For CDMA systems in the CELL band, the receive band
has an offset of 45 MHz with respect to the transmit
band. The transmitter is required to maintain a noise floor
below the receive-band noise limits. For the VGA, we de-
fine the output signal-to-noise ratio (SNR) between the
single-tone output current signal (in dBA) at IF frequency

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 912
Fig. 1. (a) Block diagram for a typical dual-band transmit IC used in CDMA cellular applications. (b) Block schematic diagram of the proposed VGA.
and the root-mean-square (rms) noise current per root
hertz dBA Hz at 45-MHz offset. Keeping in mind
the noise degradation in stages following the VGA, this
output SNR at 45-MHz offset was set to be 152 dBc. With
this SNR, the IF surface acoustic wave (SAW) filter which
is normally used in the IF path is not required. This SNR
degrades at the lower control voltages, but as long as the
noise floor is maintained, this does not matter.
3) In order to avoid interference with adjacent channels,
CDMA2000 standards impose certain limits on the
linearity of the transmitted signal. Normally, it is spec-
ified in term of adjacent-channel power ratio (ACPR),
but for this design, we translate this requirement into
a third-order intermodulation (IM3) specification, as it
can be easily simulated with a two-tone analysis. For the
VGA, the IM3 requirement was fixed at 42 dBc over
the entire control range.
4) The gain-control characteristics should not vary sig-
nificantly with the supply voltage and the temperature.
Further, there should be only minimal variation over the
process tolerances. A common requirement is for less
than 1 dB variation with respect to all of the above
mentioned factors.
5) Additional design constraints are imposed by the require-
ments of the minimum current consumption and min-
imum usable voltage for longer battery life. Therefore,
these limits were fixed to be 2.7 V with current consump-
tion of 8 mA.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003
6) For the automatic gain control (AGC) loop to function
properly, the gain should vary at least monotonically with
the control voltage. If the gain control is linear in dB, a
simplified system level AGC design is possible for the
mobile handset, and this was made a target for the design.
III. DESIGN IMPLEMENTATION
For the IF VGA, a block schematic diagram is shown in
Fig. 1(b). The circuit can be considered in two parts, one
part dealing with the preprocessing of the control voltage and
the other part providing the actual gain control. Each part is
described in detail below.
A. Main VGA
The circuit schematic of the proposed VGA core is shown in
Fig. 2. It consists of stacked multiplier cells with a common cur-
rent source. The complete gain stage operates in current mode,
with both input and output signals as signal current instead of
voltage. The input signal in the form of the ac differential cur-
rent is fed at the common-emitter node of the lower multiplier
cell as shown in Fig. 2. The circuit has a tank circuit tuned at the
required IF frequency as its load. The output signal is taken via
ac coupling capacitors at a low impedance into the succeeding
mixer stages. The tank circuit maximizes headroom at the col-
lectors and redirects the ac signal current into the next stage.
Thus, the vertical stacking of two multiplier stages still allows
for a minimum of 2.7-V operation. As the bias current is reused
 AGGARWAL et al.: SINGLE-STAGE VGA FOR CDMA2000 TRANSMIT APPLICATIONS
Fig. 2. Circuit schematic of the main VGA to provide linear-in-dB gain.
in the upper pair, this results in considerable saving in current
consumption.
The control voltage is applied to the bases of the transistors,
as shown in Fig. 2. There is a dc level shift between the control
voltage applied to the upper multiplier and the
voltage to the lower multiplier cells for proper
operation. For the lower multiplier cell, it can be shown that the
output current coming out of it is related to the input current as
follows:
(1)
where is the current gain of the lower multiplier cell. Equa-
tion (1) can be rewritten in the log form using
as
(2)
A plot of the current gain with a control input voltage
, without any temperature compensation and lin-
earization as in (2), is shown in Fig. 3. The raw control voltage
coming from an AGC circuit is a single-ended voltage
which is converted into a differential input of appropriate level
by a voltage-to-current – converter circuit, which will
be described in Section III-B. It is important to observe from
Fig. 3 that even for a small dynamic range, the current gain
curve is not linear and it varies with the temperature.
When the two multiplier cells are stacked as shown in Fig. 2,
we get one more stage of attenuation, and hence, the gain-con-
trol range is doubled in dB scale. This does not require any addi-
tional dc bias current, thus saving supply current compared with
two stages of VGA. Practically, each stage of the multiplier can
provide about 35 dB of linear control range. The practical limit
of about 35 dB is fixed by the linearization circuit which makes
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913
Fig. 3. Simulated gain characteristics of the basic single-stage VGA if a
differential voltage is applied directly to control input terminals. Observe the
nonlinearity and the spread due to the temperature over a small dynamic range.
the control voltage or rise sharply with
the control voltage . With the two stages stacked upon each
other as in Fig. 2, we can obtain about 70 dB of gain range while
still meeting linearity and noise constraints. The linearity of this
topology is mainly determined by the degree of modulation of
bias current by the maximum signal current. The noise of the
topology is mainly determined by the noise of the bias current
source and the noise accompanying control voltages.
B. Control Block
This block contains the circuitry to transform the raw control
voltage in such a way that the resultant control signal provides
a linear-in-dB response and gives a stable gain over the supply
voltage and temperature. The control voltage coming from the
AGC control function is normally a single-ended dc voltage
with a typical range of 0.1–2.3 V. Hence, it is initially converted
into a differential current signal; a simplified circuit schematic
of the – converter is shown in Fig. 4(a). The converted cur-
rent equal to flows equally into transistors Q1
and Q2, developing a voltage across the base–emitter junction of
these transistors. This output voltage coming from the – cir-
cuit is temperature dependent. In order to stabilize the gain with
respect to temperature[8], a compensation is applied to the con-
trol input using a proportional-to-absolute-temperature (PTAT)
current source in a translinear circuit, as shown in Fig. 4(a). For
this circuit, it can be shown easily that the output control voltage
is related to the input control voltage as follows:
(3)
where
current PTAT;
constant current;
reference voltage;
differential output resistance;
input resistance.
From (3), it can be seen that the output control voltage is pro-
portional to temperature, due to current. By making use
 914
Fig. 4. (a) Circuit schematic for the V –I converter and associated temperature
compensation. (b) Curvature linearization circuit to generate control voltage for
linear-in-dB gain.
of constant current and PTAT current in this translinear multi-
plier, we can get the required relationship of the control voltages
so as to make the gain control independent of temperature.
After obtaining the control voltage with temperature compen-
sation, we need to make the gain control linear-in-dB. This is
done by means of a “curvature linearization circuit” [9], which
applies a correction, that is, the inverse of the main VGA circuit
gain.
The simplified schematic for the linearization circuit is shown
in Fig. 4(b). In this circuit, transistors M6 and M7 form a current
mirror and, thus, the current in transistor Q6 is forced to be con-
stant by fixing the current . The current is chosen to
be a fraction of current. As the current in Q6 is fixed, its
emitter terminal follows the applied voltage . The emitter of
Q6 is also a common point for Q7 and Q8. Therefore, the rest
of current is steered between Q7 and Q8. The current in
Q8 has an exponential relationship with the applied input differ-
ential voltage . Therefore, the applied input voltage
develops an output voltage across the bases
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003
Fig. 5. Control signal waveforms with respect to the input control voltage V
at the output of (a) the temperature compensation circuit and (b) the curvature
linearization circuit from simulation.
of transistors Q7 and Q8. It can be shown that the relationship
between the output voltage and the input voltage for this circuit
is given as
(4)
The control signals at the output of the – converter after
temperature compensation and at the output of the linearization
circuit are shown in Fig. 5(a) and (b), respectively.
It can be seen from (2) that the gain will be linear-in-dB with
respect to control voltage if the right-hand-side function of
control input is made proportional to . This is ac-
complished by (3) and (4) when these are implemented for the
control voltage. Also, observe that the gain is temperature inde-
pendent as the effect of in (4) and in (3) compensate
each other. Thus, by implementing (2), (3), and (4), we can get
linear-in-dB gain control which is temperature independent.
C. Simulation Results
A complete VGA stage has been designed using the
above-described circuit principles for use in a transmit IC. The
circuit has been simulated using device models of a BiCMOS
technology having n-p-n transistors with of 30 GHz [10].
For the bipolar devices, a Mextram model has been used which
is well known for its accuracy.
The simulated gain defined as
with respect to the control voltage is shown in Fig. 6(a)
for three temperatures ( 40 C, 40 C, and 120 C) and three
supply voltages (2.7, 3.0, and 3.3 V). The nine curves corre-
sponding to the different supply voltages and the temperatures
 AGGARWAL et al.: SINGLE-STAGE VGA FOR CDMA2000 TRANSMIT APPLICATIONS
Fig. 6. (a) Plot of the simulated current gain in dB of the VGA with the control
voltage V (in increments of 100 mV) which is linear. The markers (nine curves)
are for three different supply voltages (2.7, 3.0, and 3.3 V) and temperatures
0
( 40 C, 40 C, and 120 C). (b) Plot of the simulated signal level and IM3
with the control voltage at different supply voltages and temperatures.
are one above another and very close to each other. As per (1),
the maximum gain of this circuit should be unity when the load
is not considered. However, the maximum current gain shown
is more than unity because of the impedance transformation
(loaded factor ) by the tank circuit, which is not ac-
counted for in the gain equation.
It can be seen from the figures that the spread in the gain over
the temperature and the supply voltage is less than a decibel.
This is a significant improvement compared with previously re-
ported values [4]–[6].
The simulated IM3 from a two-tone test with respect to the
control voltage is shown in Fig. 6(b) for the three temperature
values ( 40 C, 40 C, and 120 C) and the three supply volt-
ages (2.7, 3.0, and 3.3 V). It can be seen from the figure that the
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915
Fig. 7. Plot of the VGA tank output as measured with RF probe with respect
to the control voltage. A gain range of 68 dB can be seen (between 0.1–2.3 V).
The gain variation with the supply voltage is negligible within the experimental
errors as predicted by the simulations.
IM3 improves with the signal level. For the maximum signal,
the IM3 is more than 70 dB below the signal level. This value
of the IM3 is a strong function of the bias current modulation
by the signal. The required IM3 can be obtained by making the
bias current in the main branch of the amplifier more than the
maximum signal. The IM3 reduces with the control voltage for
this topology because the bias current in the multiplier branches
reduces compared with the input signal as it is steered to supply
by the control voltage.
IV. EXPERIMENTAL RESULTS
The VGA was implemented as part of a transmit IC which has
an modulator, VGA, an upconverter mixer, and PA drivers.
The output signal of the modulator is fed to the input of
the VGA. The output of the VGA goes to the input of the next
mixer stage as shown in Fig. 1(a).
In the complete chip, the VGA output is available at the tank
load as a voltage, which is external to the chip. Therefore, an
attempt has been made to get an idea of the VGA performance
by making direct measurement using an RF probe at the IF tank
load terminal.
To confirm the linear-in-dB gain, we used a single tone in
quadrature at the chip inputs. We measured the IF VGA tank
output power by putting a RF probe on it. The observed varia-
tion of the VGA output power at the different supply voltages
is shown in Fig. 7. This gain variation correlates well with the
simulated gain range of the IF VGA alone. Also, the effect of
the supply voltage on the gain range variation is negligible and
matches the simulation results.
In real applications, the transmit IC is tested with CDMA sig-
nals and linearity is measured indirectly by the ACPR. The side
lobes outside the signal bandwidth of 1.23 MHz are caused by
the IM3 and, therefore, the adjacent channel power is an indi-
cator of the linearity. The measurements reported here have been
made at an IF frequency of 263.6 MHz as used in a CDMA PCS
band transmitter. The values of the IF tank components are tuned
 916
Fig. 8. CDMA signal (single-ended) observed by RF probe at the tank terminal
of the VGA for different control voltages. Note the marker (MKR) readings.
to get the peak at the right IF frequency to account for the board
parasitic capacitances.
The CDMA output signal for different control voltages at the
tank load terminal is shown in Fig. 8. For CDMA signals, we
have measured the ACPR of better than 62 dBc (in a 30-kHz
resolution bandwidth at an offset of 1.25 MHz) at the maximum
VGA output. The gain control range can also be inferred from
the marker readings on this figure. Also, the absence of side
lobes, especially at low control voltages, indicates a good lin-
earity.
Because the VGA has been fabricated as a part of the com-
plete transmit IC, it is possible to make accurate RF measure-
ments only at the chip output RF ports. As an example, a plot of
the observed CDMA power and the ACPR at the final RF ports
with respect to the control voltage is shown in Fig. 9. The chip
output has contributions from all the blocks including the VGA.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 6, JUNE 2003
Fig. 9. Plot of the measured ACPR and RF output power at the chip RF output
port in PCS band with respect to the control voltage.
TABLE I
SUMMARY OF THE IF VGA PERFORMANCE PARAMETERS
As per design, a total gain range of 88 dB can be seen from this
figure with a good ACPR in the most useful middle region. The
mixer block limits the ACPR at low control voltages, while at
the top end the PA driver limits it. This is confirmed by the mea-
sured and simulated data. Thus, the IM3 of the IF VGA is not a
limiting factor, as shown by simulations.
The noise at the output of the VGA was measured indirectly
by measuring noise at the output of the complete chip. The noise
floor at the chip output was measured to be 132 dBm/Hz in the
PCS band at the maximum power output. From the simulation, it
is observed that this value of noise floor at the output is possible
if the SNR at the VGA output is more than 152 dBc.
The simulations of the VGA circuit have shown that, with
the appropriate tank circuit components, an IF frequency greater
than 500 MHz is possible. The important performance parame-
ters of the VGA are summarized in Table I. The measured per-
formance parameters are in good agreement with the simulated
values, as we have used the Mextram bipolar model which pro-
vides the most accurate results. Therefore, we consider the other
simulation results also reliable. The contributions of the VGA in
the overall performance of the chip has been observed to be very
good at the dual-band PCS/CELL IF frequencies. All the mea-
surements made at the chip output have corroborated the VGA
simulation results. The chip microphotograph of the complete
transmit IC chip is shown in Fig. 10, with the VGA circuit por-
tion of the chip marked.
 AGGARWAL et al.: SINGLE-STAGE VGA FOR CDMA2000 TRANSMIT APPLICATIONS
Fig. 10. Microphotograph of the complete transmit IC chip. The VGA block
is marked.
V. CONCLUSION
A single-stage VGA has been designed and implemented in a
BiCMOS technology as part of a transmit IC for cellular appli-
cations. It is shown that an excellent linear-in-dB gain control
with good temperature compensation can be realized. The VGA
circuit is shown to provide a wide gain range of about 70 dB in
a single stage. The stacked architecture of the VGA results in
considerable current saving and provides the noise and linearity
to meet the requirements of the current and forthcoming CDMA
systems.
ACKNOWLEDGMENT
The authors would like to thank Prof. B. Redman-White for
his suggestions and assistance in preparation of the paper and
the reviewers for their constructive comments, which resulted
in numerous improvements in the manuscript. They would also
like to thank the Philips management for encouraging this work.
REFERENCES
[1] Recommended Minimum Performance Standards for CDMA2000
Spread Spectrum Mobile Station, 3GPP2 Doc. C.S0011-A.
[2] Recommended Minimum Performance Standards for Dual-Mode
Wide-band Spread Spectrum Cellular Mobile Station, IS-98A.
[3] Recommended Minimum Performance Standards for 1.8 to 2.0 GHz
Code Division Multiple Access (CDMA) Personal Stations, ANSI
J-Standard 018.
[4] O. Shoji, G. Takemura, and H. Tanimoto, “A low-power low-noise ac-
curate linear-in-dB variable gain amplifier with 500-MHz bandwidth,”
IEEE J. Solid-State Circuits, vol. 35, pp. 1942–1948, Dec. 2000.
[5] G. S. Sahota and C. J. Persico, “High dynamic range variable-gain am-
plifier for CDMA wireless applications,” in IEEE Int. Solid-State Cir-
cuits Conf. Dig. Tech. Papers, Feb. 1997, pp. 374–375.
[6] D. Coffing, E. Main, and M. Randol, “A variable-gain amplifier
with 50-dB control range for 900-MHz applications,” in Proc.
Bipolar/BiCMOS Circuits and Technology Meeting, Oct. 2001, pp.
155–158.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY WARANGAL. Downloaded on November 2, 2008 at 07:28 from IEEE Xplore. Restrictions apply.
917
[7] S. Aggarwal, A. Daanen, M. Locher, A. Landesman, M. Judson, F. Gar-
rigues, M. Bracey, H. Xu, O. Charlon, and M. Gao, “A highly inte-
grated dual-band triple-mode transmit IC for CDMA2000 applications,”
in Proc. Bipolar/BiCMOS Circuits and Technology Meeting, 2002, pp.
57–61.
[8] D. Seremeta and R. G. Eschauzier, “Converter circuit and variable gain
amplifier with temperature compensation,” U.S. Patent 6 028 478, Feb.
22, 2000.
[9] R. G. Eschauzier, “Current Steering Variable Gain Amplifier with Lin-
earizer,” U.S. Patent 5 999 053, Dec. 7, 1999.
[10] A. Pruijmboom, D. Szmyd, R. Brock, R. Wall, N. Morris, K. Fong,
and F. Jovenin, “QUBIC3: A 0.5 m BiCMOS production technology,
with f = 30 GHz, f = 60 GHz and high-quality passive
components for wireless telecommunication applications,” in Proc.
Bipolar/BiCMOS Circuits and Technology Meeting, 1998, pp. 120–123.
Sudhir Aggarwal (S’84–M’89–SM’03) was born in
Ballabgarh, India, in 1960. He received the B.S. de-
gree in electronics and communication engineering
from the Regional Engineering College (REC), Ku-
rukshetra, India, in 1981, with top rank, and the Ph.D.
degree in electrical engineering from the Indian Insti-
tute of Technology (IIT), Delhi, India, in 1988.
From 1981 to 1989, he was with the Centre for Ap-
plied Research in Electronics, IIT Delhi, working on
various industrial and defense sponsored projects in
the area of MOS analog integrated circuits for signal
processing applications. From 1991 to 1995, he was with STMicroelectronics,
Grenoble, France, and Noida, India, where he developed statistical circuit/de-
vice models and optimization tools for analog circuits in BiCMOS technology.
He is currently with Philips Semiconductors, San Jose, CA, as a Senior Principal
Engineer. His current research interests include RF ICs for wireless communi-
cation, in particular for CDMA and WLAN systems.
Abolfazl (Saeed) Khosrowbeygi (M’96) was
born in Tehran, Iran, in 1958. He received the
B.Sc. degree in electrical engineering from Sharif
University of Technology, Tehran, the M.Sc., E.E.
in microwaves and modern optics, Postgraduate
Diploma in microwave engineering, and Ph.D.
degrees in microwaves and communications from
University College London, London, U.K.
From 1976 to 1979, he worked on developing
analog and digital hardware for wireless commu-
nication with the Sharif University of Technology.
In 1980, he joined the Iran Telecommunication Research Center, Tehran,
where he worked on different wireless and wired communication projects and
developed a number of wireless communication systems from high frequency
to microwave frequencies. From 1988 to 1994, he was with University College
London, where he worked on developing a wide range of microwave and RF
systems, including radio altimeters, automated systems for measuring electrical
and magnetic properties of materials at microwave and millimeter-wave
frequencies, and microwave and optical communications. In 1994, he joined
Philips Semiconductor, Sunnyvale, CA, where he developed RFICs for TDMA
and CDMA standards. In 2000, he founded Adaptive RF, a fab-less company,
developing chipsets for wireless LANs. Since 2001, he has been a Consultant
for developing wireless products with RF Micro Technology, Greensboro, NC.
Anton Daanen (M’90) was born in St. Agatha,
The Netherlands, on August 23, 1961. He received
the M.Sc. degree from the Technical University
Eindhoven, Eindhoven, The Netherlands, in 1987.
He joined Philips Semiconductors in 1987,
working on mixed-signal IC design for ISDN. In
1990, he moved to Philips Semiconductors, Zürich,
Switzerland, to work on DECT baseband processors,
focusing on the mixed-signal parts. In 2000, he
moved to Philips Semiconductors, Sunnyvale, CA,
doing RF IC design for CDMA applications. He is
currently working on WLAN.