ELE591 - VHDL for Synthesis

Issue 1.0: 1
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December 2010
The purpose of this laboratory experiment is to familiarise you with the principles of VHDL
for synthesis targeted at programmable logic devices. You will observe how various VHDL
descriptions result in Register Transfer Level RTL! implementations and how these can be
implemented within specific logic devices. The principles of bac"#annotation will also be
explored and how this can be used to examine performance limitations of specific hardware
resource mappings.
This lab assumes you are already familiar with $ilinx %&' and (odel&im) given that 'L'**+
is a prere,uisite for this module. %f necessary) consult the 'L'**+ lab guide) which is
included in the -oursewor" section of the 'L'+./ module webpage. (ost of the VHDL files
needed for this lab are also available from the same location.
Exercise 10
im0 To compare the results of different architectural descriptions for the same entity
Ste!s0
-reate a pro1ect named 2exercise/3. 4dd the file ex/a.vhd as a 2VHDL module3
&elect the &partan* as the target device
-ompile and synthesise the VHDL description and examine the design report file)
paying particular attention to the resource utilisation summary and timing path
analysis!. 4lso examine the RTL design.
Repeat with the files ex/b.vhd and ex/c.vhd and compare the results.
Exercise 20
im0 To illustrate the use of 2don5t care3 values in synthesis
Ste!s0
-reate a pro1ect named 2exercise63. 4dd the file docare.vhd as a 2VHDL module3
-ompile and synthesise the design targeting the &partan* device
4dd the file dontcare.vhd as a 2VHDL module3 and repeat the synthesis.
-ompare the report files.
Exercise "0
im0 To illustrate logic resource re,uirements for conditional versus mutually exclusive input
conditions
Ste!s0
-reate a pro1ect named 2exercise*3. 4dd the file cond.vhd as a 2VHDL module3
-ompile and synthesise the design targeting the &partan* device
4dd the file exclusiv.vhd as a 2VHDL module3 and repeat the synthesis.
-ompare the report files. 4lso compare the timings at the design logic level and at the
place and route level.
Exercise #0
im0 To review resource and timing re,uirements of a complex reset function
Ste!s0
'L'+./ VHDL for &ynthesis 7age / of * /
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December 68/8
-reate a pro1ect named 2exercise93. 4dd the file cntpt.vhd as a 2VHDL module3
-ompile) synthesise and simulate the design targeting the &partan* device
Review the report file paying particular attention to the reset e,uation.
:ow examine the file cntpt6.vhd which employs a synchronous complex reset.
4ttempt to simulate the designs and comment on the reset timing in both cases.
Exercise 50
im0 To compare -7LD and ;7<4 implementations of a ;%;= design
Ste!s0
-reate a pro1ect named 2exercise+3. 4dd the file fifo.vhd as a 2VHDL module3
-ompile and synthesise the design targeting the &partan* device
Recompile the design for a -oolrunner6.
-ompare the report files and the resulting RTL layouts.
7lace and route both designs
-ompare the design files paying particular attention to the maximum operating
fre,uency and the amount of resources used. >hich timing parameter is the limiting
factor on the operating fre,uency in each case?
Exercise $0
im0 To illustrate the effects of implicit memory
Ste!s0
-reate a pro1ect named 2exercise@3. 4dd the file memcont.vhd as a 2VHDL module3
-ompile and synthesise the design targeting the &partan* device.
'xamine the report file.
4dd the file memcont6.vhd as a 2VHDL module3. %n this file the signal assignments
for oe) we and addr are removed from under the reset condition.
-ompile and synthesise the design targeting the &partan* device.
-ompare the report file with that of the original design. Verify that implicit memory
resulted in the creation of a combinatorial latch.
Exercise %0
im0 To illustrate the advantage of 2one hot3 encoding of large state#machines implemented
in ;7<4 architectures
Ste!s0
-reate a pro1ect named 2exerciseA3. 4dd the file onehot.vhd as a 2VHDL module3
-ompile and synthesise the design targeting the &partan* device
7lace and route the design and record the number of logic cells re,uired) the setup
time) cloc"#to#output delay and maximum operating fre,uency.
:ow employ the file notonehot.vhd. This uses the synthesis tool to assign values to
the various enumerated states.
-ompile and synthesise the updated design targeting the &partan* device.
7lace and route the design and record the number of logic cells re,uired) the setup
time) cloc"#to#output delay and maximum operating fre,uency.
-ompare the results with the original design.
'L'+./ VHDL for &ynthesis 7age 6 of * /
st
December 68/8
This series of experiments should be written up as an %:D%V%DB4L formal lab report. The
report will be limited to a maximum of C pages of main text i.e. omitting title page etc!. The
hand#in date is the /Ath December) unless you are informed otherwise.
'L'+./ VHDL for &ynthesis 7age * of * /
st
December 68/8