Electric Power Systems Research 116 (2014) 1223

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Electric Power Systems Research
j our nal home page: www. el sevi er . com/ l ocat e/ epsr
Boost inverter-based HVDC transmission system with inherent
blocking capability of AC side contribution during DC side faults
A. Elserougi
a,
, A.M. Massoud
a,b
, A.S. Abdel-Khalik
a
, S. Ahmed
c
a
Department of Electrical Engineering, Alexandria University, Egypt
b
Department of Electrical Engineering, Qatar University, Qatar
c
ECEN Department, Texas A&MUniversity at Qatar, Qatar
a r t i c l e i n f o
Article history:
Received 26 May 2013
Received in revised form28 April 2014
Accepted 5 May 2014
Keywords:
Boost inverter-based HVDC system
DC side faults
DC fault blocking capability
Discharge current
HVDC Converters
Grid current contribution
a b s t r a c t
Semiconductor advancements in the past three decades have positioned the voltage source converter-
based HVDC (VSC-HVDC) solution as a practical and popular alternative to its line-commutated converter
high voltage DC (LCC-HVDC) counterpart. The VSC-HVDC systems offer higher exibility and system
controllability features. One of the important challenges requiring careful investigation in such systems
is the protection against DC side faults. Unfortunately, the VSC is inherently defenseless against such
faults (DC link short circuit or DC cable short circuit). This paper proposes an HVDC system topology,
namely, the boost inverter-based HVDC system (BI-HVDC), which provides complete blocking capability
between the AC grid and the DC side fault. This blocking capability limits the DC fault current level to the
DC capacitor discharge current. Ratings and characteristics of the proposed system compared to other
existing topologies are highlighted in this work. A simulation study is conducted to check the performance
of the proposed system during normal as well as abnormal operating conditions. A comparison between
the performance of the conventional 2-level VSC-HVDC and the proposed system during DC side faults is
also presented. The simulation results elucidate a signicant decrease in the DC fault current due to the
blocking capability of the BI-HVDC system during DC side faults.
2014 Elsevier B.V. All rights reserved.
1. Introduction
HVDC plays a signicant role in connecting unsynchronized
power system networks as well as systems with undersea cables
[1,2]. AVSC-HVDCtransmissionsystemprovides better operational
exibilityandreliability. Fault current limiting is vital toprotect the
power-electronic converter which represents the most sensitive
component in the system. Characteristically, a VSC is defenseless
against DC side faults (DC-link short circuit or DC-cable short cir-
cuit) as the freewheeling diodes act as a rectier bridge and feed
the DC fault [3]. As a result, the DC fault current in VSC-HVDC sys-
tems emanates fromthe contributions of both, AC grids as well as
the discharging current of the DC link capacitor. The discharging
current has a large rst peak decaying with time [4]; therefore the
employed DC circuit breakers should be able to withstand the high
fault current when the DC side is subjected to a fault. Due to the

Corresponding author at: Department of Electrical Engineering, Alexandria Uni-

versity, Egypt. Tel.: +20 1221268725; fax: +20 3 5921853.
E-mail addresses: ahmed.abbas@spiretronic.com, abbas zone@yahoo.com
(A. Elserougi).
high vulnerability of VSC semiconductor devices to DC side faults,
VSC-HVDC applications are restricted to point-to-point transmis-
sion applications.
Various papers in literature address the DC side fault issue in
VSC-HVDC congurations [38]. In [3], ground fault theoretical
analysis and location in VSC-based DC network cables are pre-
sented. A new transient energy protective scheme for HVDC lines
is proposed in [4]. A new protection algorithm for DC line faults
in multi-terminal high voltage DC (MTDC) systems is proposed
in [5]. An overview of existing methods for VSC system protec-
tion was provided in [6], these methods are divided into two main
approaches as follows [6]:

DC protection with AC devices (AC circuit breakers, or fuses);

DC protection with DC devices (IGBT-based circuit breakers, or

installing of protective components inside the VSC to detect and
isolate DC faults).
A new converter station with blocking capability of AC side
contribution during DC side faults is proposed in [7]. This pro-
posed topology is based on hybrid multilevel VSCs with AC side
http://dx.doi.org/10.1016/j.epsr.2014.05.002
0378-7796/ 2014 Elsevier B.V. All rights reserved.
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 13
cascade H-bridge cells. This system can successfully eliminate the
AC grid contribution due to a DC fault at steady state but it experi-
ences notable current overshoots during the transient period. The
Alternate-Arm Multilevel Converter conguration is presented in
[8] with a demonstration of its ability to deal with DC side faults.
The modular multilevel converter (MMC) [912] has emerged
as a good candidate for HVDC applications in recent years. One of
its types, namely, the full-bridge MMC (FBMMC) is able to block
the grid current contribution into DC side faults. Generally, the
main drawbacks of the MMC are circulating currents, requirements
of a large number of DC-capacitors (sub-modules capacitors), and
voltage balancing requirements [11].
Other recent research is directed toward the solid state DC cir-
cuit breaker [13] to overcome the DC side problem in VSC-HVDC
systems. The clear advantage is that the switching time can be as
low as a few micro-seconds, compared to the few milli-seconds
typical of a mechanical switch with separating metal contacts.
The main drawbacks are cost and relatively high losses due to
the fact that the resistance in conducting mode is in the order
of a few m; considerably higher when compared to a few
for a mechanical switch [13]. The full forward conduction losses
of the solid state devices are 0.10.4% [13] of the transmitted
power. The application of semiconductor switches is thus typically
limited to applications where a high power quality is of crucial
importance and minimum breaking time is needed. In addition, a
singlesemiconductor deviceis not abletowithstandthefull voltage
and current rating, but series and parallel arrangements of several
switches are used to achieve HVDC circuit breaker ratings.
In this paper, a new HVDC transmission system based on the
boost inverter (BI) topology is proposed. The topology provides (i)
independent control of activeandreactivepower inbothdirections,
(ii) sinusoidal output voltage, which eliminates the common mode
voltage problemand the required AC side lters, and (iii) DC-fault
blocking capability which is an inherent feature in the BI. Blocking
the contributionof the ACgrids tothe DCside faults canbe achieved
by inhibiting the IGBTs gate pulses at the time of fault occurrence.
The paper is organized in seven sections. Following the intro-
duction, Section 2 gives a detailed description of the architecture,
principle of operation, and control of the proposed system. Sec-
tion 3 shows the blocking capability of the boost inverter-based
HVDCtransmission(BI-HVDC) system, andintroduces amathemat-
ical analysis of the proposed HVDC system during DC side faults.
Section 4 shows the characteristics of the proposed BI-HVDC sys-
tems. Section 5 gives a detailed comparison between the proposed
BI-HVDC and other existing topologies. Section 6 presents a simu-
lated case study to check the performance of the proposed system
during normal conditions. A comparison between the performance
of the conventional 2-level VSC-HVDC and proposed BI-HVDC for
DC side faults is held as well in Section 6. Finally, Section 7 provides
the main conclusions of this work.
2. Boost inverter-based HVDC system(BI-HVDC)
2.1. Architecture and principles of operation
A single-stage three-phase BI is proposed in [14] with reference
to its possible use in distributed power generation. It provides not
only DC-to-AC three-phase conversion but also voltage boosting
capability. The system consists of three DC-to-DC bi-directional
boost converters sharing the same common point as shown in
Fig. 1. These converters produce a DC-biased sine wave output via
controlling the duty cycle (D) of each DC-to-DC converter. The AC
component of each converter output is 120

out of phase. There is

a common point for the capacitors, which is connected to the nega-
tive terminal of the DC link. The AC side is connected to the inverter
Fig. 1. Three-phase BI topology.
terminals whichis electricallyisolatedfromthecapacitors common
point.
For this topology, the reference of each output is composed of
AC and DC components as given by (1). The DC component should
be the same for all phases and greater than or equal to the sum
of the AC component peak and the DC input voltage (V
dc
) to avoid
operating at zero duty cycle, i.e. to avoid clipping the output volt-
age at the DC input voltage level. The AC side terminals are tapped
between the capacitors connected to the upper IGBTs. For equal DC
components, the three line voltages are sinusoidal. Eq. (2) shows
the converter output line voltages with eradicated DC components.
v
AOref
(t) V
dco
+V
aco
sin(t +)
v
BOref
(t) V
dco
+V
aco
sin
_
t +
2
3
_
v
COref
(t) V
dco
+V
aco
sin
_
t + +
2
3
_
(1)
v
AB
(t) = v
AOref
(t) V
BOref
(t) =

3V
aco
sin
_
t + +

6
_
v
BC
(t) = v
BOref
(t) V
COref
(t) =

3V
aco
sin
_
t +

2
_
v
CA
(t) = v
COref
(t) V
AOref
(t) =

3V
aco
sin
_
t + +
5
6
_
(2)
Based on Fig. 2, expressions (3)(5) describe the DC gain, mod-
ulation index, and instantaneous gain respectively.
G
dc
=
V
dco
V
dc
(3)
M =
V
aco

V
aco
=
V
aco
V
dco
V
dc
=
V
aco
V
dc
_
1
G
dc
1
_
(4)
g
ac
(t) =
v
AO
(t)
V
dc
=
V
dco
+V
aco
sin(t +)
V
dc
(5)
where,

V
aco
is the highest possible magnitude of the converter out-
put voltage. Substituting from(3) and (4) into (5), an expression for
the instantaneous AC gain is given in (6). The maximum value of
Fig. 2. Output voltage parameters.
14 A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223
(a) (b) (c) (d)
0.98 0.985 0.99 0.995 1
100
150
200
250
300
350
400
time, s
V
A
O

r
e
f

,

k
V
0.98 0.985 0.99 0.995 1
0.4
0.5
0.6
0.7
0.8
time, s
D
1
D
max
0.98 0.985 0.99 0.995 1
-1500
-1000
-500
0
500
1000
1500
2000
2500
time, s
i
L
1
,

A
I at D
max
I
Lmax
0.98 0.985 0.99 0.995 1
100
150
200
250
300
350
400
time, s
V
A
O

,

k
V
Capacitor
voltage peak
Fig. 3. Variationof duty cycle, inductor current, capacitor voltage withthe variationof reference voltage (a) reference voltage, (b) duty cycle of the converter, (c) corresponding
inductor current, (d) corresponding capacitor voltage.
instantaneous AC gain is given by (7). This expression is an impor-
tant design factor when considering switch rating selection.
g
ac
(t) = G
dc
+(MG
dc
M) sin(t +) (6)
g
ac
= G
dc
(M+1) M (7)
2.2. Selection of BI-HVDC parameters
Selection of BI parameters (inductors, capacitors, and switch-
ing frequency) is an important design consideration. Inductors are
designed to ensure continuous conduction while maintaining a
desired current ripple content. Capacitors are selected to limit the
output voltage ripples. Finally, the switching frequency is selected
based on the required converter rating and semiconductor device
type [15]. As in other high power applications, low switching fre-
quency is a design constraint in HVDC systems.
For an HVDC system with a DC-link voltage (V
dc
) of 100kV, an
output AC voltage reference (V
aco
) of 100kV, an output DC com-
ponent (V
dco
) of 250kV, a 1.5kHz switching frequency, 100mH
inductors, 10F capacitors, and an AC load of 200 per-phase.
The per-phase variation of the boost converter duty cycle, inductor
current, and capacitor voltage with the variation of the converter
output voltage reference is shown in Fig. 3. Based on Fig. 3, the duty
cycle is continuously changing to generate the desired variation in
the output voltage. With the variation of duty cycle, the inductor
current andits ripple magnitude are changing. The inductor current
reaches its peak (I
Lmax
) at the instant of the maximum duty cycle
(D
max
). It is clear that the highest current ripple magnitude (I)
occurs at the instant of D
max
which is expected from the DCDC
boost converter principles.
The inductor can be selected to meet the required design speci-
cations. At the instant of the inductor current peak (i.e. maximum
duty cycle), its value is given by (8) assuming negligible losses;
I
L max
=
v
c

I
gph
V
dc
(8)
where, v
c
is the peak of the capacitor voltage, and

I
gph
is the peak
of the grid current.
From DCDC boost converter principles, the expression for
peak-to-peak inductor current ripple at the instant of maximum
dutycycle is givenby(9); where L is the boost converter inductance,
f
sw
is the switching frequency, and D
max
is given by (10).
I|
Dmax
=
(V
dc
)D
max
Lf
sw
(9)
D
max
= 1
V
dc
v
c
(10)
Thus, a suitable inductor can be selected for a desired switching
frequency (f
sw
) and desired level of inductor current ripples. Practi-
cally, inductor current ripple is chosen lower than (I
Lmax
) to ensure
operating in continuous current mode.
Based on Fig. 3, the capacitor voltage and its ripple magnitude
are changing with the variation of duty cycle. Since the capaci-
tor voltage reaches its peak ( v
c
) at the instant of maximum duty
cycle (D
max
), the highest capacitor voltage ripple (v
C
) occurs at
this instant as well; i.e. the output voltage ripple is given by (11),
where C is the boost converter output capacitance.
v
C
=
D
max

I
gph
Cf
sw
(11)
For a desired switching frequency and desired level of output
voltage ripples, a suitable capacitance (C) can be selected.
2.3. Control system
Each boost DCDC converter is controlled to ensure robust per-
formance at different operating points. Sliding mode control of the
single-phase BI is proposed in [15]. Another control strategy for
the single-phase BI has been proposed in [16], in which each DC-
to-DC boost converter is controlled by a double-loop regulation
scheme using proportional-integral controllers (PI). The control
scheme consists of an inductor current control inner loop and an
output voltage control outer loop in order to cope with the vari-
able operating point conditions and to achieve a high robustness
to both input voltage and output current disturbances. In [17],
a proportional-resonant (PR) controller is employed instead of a
proportional-integral (PI) controller in the double loop-regulation
scheme. The PR controller has the ability to minimize the draw-
backs of the PI alternative, and enables tracking a sinusoidal
reference with zero steady-state error and high disturbance rejec-
tion capability [17].
The double-loop regulation scheme for the proposed three-
phase grid-connected BI is shown in Fig. 4. The outer loops
controllers are the conventional PQ closed loop controllers which
determine the AC voltage reference of the inverter. The boost
inverter controllers are based on double loop control (controlling
inductor current, and capacitor voltage) which is familiar in DCDC
converters controllers.
Based on Fig. 4, the grid voltages and currents are measured to
estimate grid active power, grid reactive power, grid voltage peak,
and grid voltage orientation (t). The inverter can operate under
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 15
Fig. 4. Grid-connected three-phase BI (a) topology and (b) control system.
DC voltage control or active power control via a selector. If DC volt-
age control mode is selected, the DC-link voltage is measured and
compared with the reference DC voltage (V
*
dc
), then the voltage
error is fed to a proportional integral (PI1) controller to generate
the suitable phase difference () between the inverter and grid vol-
tages. Similarly, if active power control mode is selected, the active
power reference is compared withgrid active power, and the active
power error is fed to a PI controller (PI2) to generate the suitable
(). On the other hand, the reactive power reference is compared
with grid reactive power, and the reactive power error is fed to
PI controller (PI3) to generate the suitable voltage difference (V)
betweeninverter andgridvoltages. This voltage difference is added
to grid peak voltage to obtain the suitable AC voltage magnitude
at the inverter output (V
aco
). Then, based on Eq. (1), the reference
output voltage of each DCDC boost converter can be simply gen-
erated (V
AO ref
, V
BO ref
, and V
CO ref
). The capacitor voltages (V
AO
, V
BO
,
and V
CO
) are controlled to track these voltage references using PI
controllers (PI4, PI6, and PI8) which generate the reference capac-
itor currents (i*
1
, i*
2
, and i*
3
). Based on these current references
and the measured grid current (i
g1
, i
g2
, and i
g3
), the inductor cur-
rent references (i
L1
, i
L2
, and i
L3
) can be estimated using Kirchhoffs
current law. Finally, the inductor currents are also controlled by PI
controllers (PI5, PI7, and PI9) which generate the inductor voltage
references (V*
L1
, V*
L2
, and V*
L3
), then based on Kirchhoffs voltage
law, these reference voltages can be used to estimate the suitable
instantaneous duty cycles for each DC-to-DC converter (D
1
, D
2
, and
D
3
). The duty cycle signals are compared with carrier waveforms to
generate gate pulses for the semiconductor devices (S
a
, S
a
, S
b
, S
b
,
S
c
, and S
c
). The frequency of these carrier waves is adjusted based
on the desired switching frequency. The use of shifted carriers is
preferred in order to reduce the inverter DC current ripples.
3. Mathematical analysis during DC side faults
3.1. DC fault blocking capability of BI-HVDC system
The BI-HVDC conguration inherently provides blocking capa-
bility of AC side contribution during DC side faults by inhibiting
its IGBTs gate pulses when DC side faults are detected. With all
IGBTs open, all freewheeling diodes are blocking the AC grid cur-
rent contributionto the DC side fault (all diodes are reverse biased),
as depicted fromFig. 5. The inverter output capacitors are seen as a
three-phasestar-connectedbalancedloadconnectedtotheACgrid.
Generally, the inverter output capacitors have small capacitance;
hence, grid current is limited after fault isolation to the capacitor
currents; i.e. the BI circuit topology provides a complete blocking
capability between the AC network and DC side fault which pre-
vents active power transfer betweenbothsides. The control system
should be modied to inhibit the IGBTs gate pulses after detecting
the DC side faults. This can be simply achieved by measuring the DC
link voltage of the BI. When the measured DC link voltage is lower
than a threshold level, the gate pulses are disabled.
3.2. Grid current under DC fault condition
The equivalent circuit on the AC side after inhibiting the gate
pulses of semiconductor devices is shown in Fig. 5. The capacitors
are seen by the grid as a star connected three-phase balanced load.
The grid current magnitude is given by (12), where r
T
and X
T
are
the resistance and leakage reactance of the interfacing impedance.
|I
g
ph
| =
|V
g
ph
|
_
r
2
T
+(X
T
X
c
)
2
(12)
Fig. 5. DC fault blocking capability of BI.
16 A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223
Hence, the active and reactive powers supplied by the AC grid
during the fault are given by (13) and (14) respectively.
P = 3|I
g
ph
|
2
r
T
(13)
Q = 3|I
g
ph
|
2
(X
T
X
c
) (14)
It is worthy to note that these power components account for
power inthe interfacingimpedances andthe inverter output capac-
itors. Although they have nonzero values, the generic assumed
blocking capability between the AC and DC sides is not violated.
3.3. DC fault current (capacitor discharge current)
The equivalent circuit of the DCside inthe BI-HVDCsystemafter
inhibiting the gate pulses is shown on the left side of Fig. 5. The DC
link capacitor is discharged into the DC fault (natural response)
without any contribution from the AC side. Applying Kirchhoffs
voltage lawon the DC side shown in Fig. 5 yields (15);
d
2
i(t)
dt
2
+
r
L
c
di(t)
dt
+
1
L
c
C
dc
i(t) = 0 (15)
where, r and L
c
are the resistance and inductance of the DC cable
from the inverter terminals to the fault, respectively. Taking the
Laplace transformof both sides of Eq. (15), the DC fault current in
the s-domain is as in (16);
I(s) =
sI
o
+(V
o
/L
c
)
(s
2
+(r/L
c
)s +(1/L
c
C
dc
))
(16)
where, I
o
and V
o
are the pre-fault DC link current and voltage
respectively. Accordingtothe systemparameters (r, L
c
, andC
dc
), the
natural response of the systemduring a fault may be over-damped
for (r >2
_
L
c
/C
dc
), critically-dampedfor (r = 2
_
L
c
/C
dc
) or under-
damped for (r <2
_
L
c
/C
dc
). Fig. 6 shows the dynamics of the DC
capacitor discharge current for different cases assuming I
o
=500A,
V
o
=400kV, cable length of 75km, C
dc
=1mF, r =133.33m/km,
and different values of L
c
(0, 0.1, 1, and 2mH/km). The total
resistance, r, will be 10 in all cases, while for the inductance
values (0, 0.1, 1, and 2mH/km), the 2
_
L
c
/C
dc
) term will be 0,
5.48, 17.3, and 24.5 respectively, i.e. over-damped condition is
conrmed in rst and second cases, while under-damped per-
formance is realized in third and fourth cases. In this paper,
the resistance of HVDC cables used in the simulation study is
more signicant than inductance, hence, over-damped response is
expected.
0 0.02 0.04 0.06 0.08 0.1
-10
0
10
20
30
40
time, s
D
i
s
c
h
a
r
g
e

c
u
r
r
e
n
t
,

k
A
L
c
=0
L
c
=0.1mH/km
L
c
=1mH/km
L
c
=2mH/km
C=1F, r=133.33m /km
Initial current
Fig. 6. Dynamics of DC capacitor discharge current.
4. Characteristics of the proposed BI-HVDC system
In this section, the selection of voltage and current ratings of
the employed semiconductor devices in the proposed BI-HVDC are
introduced.
4.1. Voltage rating of semiconductor devices
In the proposed BI-HVDC, six semiconductor devices are needed
with the voltage rating calculated as follows: for a peak grid phase
voltage of V
max
and a 1:1 transformer ratio, the peak of the AC com-
ponent of each DCDC buck-boost converter will be around V
max
.
The DC component of each converter is selected greater than or
equal to the summation of its AC component peak value and DC-
link voltage, i.e. the highest instantaneous voltage of the converter
output capacitor ( v
c
) will be around 2V
max
+V
dc
. Consequently, the
voltage rating of each device will be (2V
max
+V
dc
). Using the boost
converter input-output voltage relation, the DC-link voltage can be
given by (17).
V
dc
= (1 D
max
) v
c
=
2V
max(1Dmax)
D
max
(17)
Based on (17), the voltage rating of each semiconductor switch
will be given by (18),
voltage rating = (2V
max
+V
dc
) =
2V
max
D
max
(18)
It is obvious that the voltage rating of semiconductor devices
required in this topology is high compared to other existing topolo-
gies. Nevertheless, increasing the switchvoltage rating inreturnfor
the BI blocking capability of AC side contribution during DC side
faults may warrant interest.
In order to meet the required voltage rating, a large number of
series-connected IGBTs will be used. The main disadvantage of this
solution is the need for voltage balancing for the series connected
IGBTs due to mismatch in their characteristics. Instead of stack-
ing the IGBTs, the multi-module BI-HVDC conguration shown in
Fig. 7 can be used as an alternative. In the multi-module version
of the proposed boost inverter, the AC side is connected to the
multi-module three-phase boost inverter (n modules) through a
three-phase multi-open winding isolating transformer. Each mod-
ule consists of three single-phase boost inverters and its DC side
is connected to one of the DC-link capacitors (C
dc
). The DC-link
capacitors are connected together, as in Fig. 7, and the volt-
age of each capacitor is kept constant at (V
dc
/n) by employing
suitable voltage balancing technique. According to the available
voltage rating of semiconductor devices, the suitable number of
modules can be estimated. The voltage rating of semiconductor
device in this case is (2V
max
+V
dc
)/n. The multi-module concept
with its controllers has been presented in [18] but for buck-boost
conguration.
As another solution is decreasing the DC link voltage, which
helps inreducingthevoltageratingof thesemiconductor devices by
thedifferencebetweenoldandnewDCvoltagelevels. Themaindis-
advantage of lowering the DC link voltage for the same transferred
power is the increase in DC current consequently the transmis-
sion losses. This is limited by the current rating of the HVDC
system components. It is worthy to note that the transmission
loss problem is not relevant in the HVDC back-to-back congu-
ration since there is no need for the DC transmission cable in this
conguration.
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 17
Fig. 7. Multi-module three-phase BI-HVDC.
4.2. Current rating of semiconductor devices
In the proposed systemthe current rating of the semiconductor
devices is selected based on the inductor peak current which is
given by (19).
I
L max
=
_

I
gph
1 D
max
_
(19)
Based on (19), the current rating of semiconductor devices is
selected from(20);
current rating = i
L max
+0.5I|D
max
(20)
where, I|
Dmax
is the peak-to-peak inductor current ripple at max-
imum duty cycle, which is dependent on the boost converter
inductance and the switching frequency as in (9).
4.3. Optimummaximumduty cycle
Multiplying (18) and (19), the total VA rating of each semicon-
ductor switch is given by (21), assuming that the inductor is large
enough in order to obtain negligible current ripple.
VArating =
2
D
max(1Dmax)
V
max

I
gph
(21)
By differentiating the VA rating given by (21) with respect
to D
max
, the optimum maximum duty cycle, D
max-optimum
,
can be obtained as in (22); yielding an optimum duty cycle
D
max-optimum
=0.5
(VArating)
(D
max
)
=
2(1 2D
max
)
(D
max(1Dmax)
)
2
V
max

I
gph
= 0 (22)
Substituting (22) into (17), the optimumDC link voltage can be
obtained as in (23).
V
dcoptimum
= 2V
max
(23)
4.4. Efciency of the proposed systemcompared to other existing
topologies
4.4.1. Conduction losses
In this section the efciency of the proposed BI-HVDC is com-
pared with the most common HVDC converters such as the 2-level
VSC, half-bridge MMC (HBMMC), and full-bridge MMC (FBMMC).
Generally, the conduction losses of any semiconductor device are
given by (24);
P
c
= I
ave
V
on
+I
2
rms
R
on
(24)
where, I
ave
and I
rms
are the average and root mean square cur-
rent of the semiconductor device, V
on
is the on-state voltage
of semiconductor device, and R
on
is the on-state resistance of
semiconductor device. To study the efciency of the proposed
converter and compare it with other existing HVDC convert-
ers, an IGBT with data shown in Table 1 is used as a building
block for all required switches in the different types of HVDC
converters.
For an HVDC system with DC-link voltage of 400kV, peak grid
voltage, V
max
, of 200kV, peak AC output current, I
max
, of 2kA, load
power factor of 0.95 lag, and a 1:1 transformer ratio; each type
of HVDC converter will need a certain number of IGBTs connected
in series/parallel combinations to build one switch. The required
IGBTs for each switch in each topology are given in Table 2 in
addition to the corresponding equivalent on-state resistance and
voltage per equivalent switch.
Models of the four topologies have been tested assuming the
above mentioned data. The current of each equivalent switch and
diodearemeasuredandtheir correspondingaverageandroot mean
square values are obtained to calculate the conduction losses. The
estimated conduction losses as a percentage of total transferred
active power for the 2-level VSC, 3-level HBMMC, 3-level FBMMC,
and proposed converter are summarized in Table 3. It is clear that
the proposed converter has slightly higher conduction losses com-
pared to other congurations.
Table 1
Parameters of available IGBT.
Voltage rating 4kV
Current rating 1kA
RonT (for IGBT) 1m
RonD (for freewheeling diode) 2m
VonT (for IGBT) 1.2V
VonD (for freewheeling diode) 1V
18 A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223
Table 2
Parameters of equivalent HV switch for different types of HVDC converters based on the available IGBT.
Type Available IGBT 4kV, 1kA Vmax =200kV, Imax =2kA, 0.95 power factor lag
2-level VSC 3-level HBMMC 3-level FBMMC Proposed Converter at
(Dmax =0.5)
V
dc
400kV 400kV 400kV 400kV
No of needed switches 6 24 48 6
Voltage rating of each switch 400kV 200kV 200kV 800kV
Current rating of each switch 2kA 2kA 2kA 4kA
No of series connected IGBTs to withstand the voltage level 400kV/4kV=100 200kV/4kV=50 200kV/4kV=50 800kV/4kV=200
No of parallel IGBTs strings to withstand the current level 2kA/1kA=2 2kA/1kA=2 2kA/1kA=2 4kA/1kA=4
Total No. of IGBTs per switch 200=1002 100=502 100=502 800=2004
RonT per SW 50m 25m 25m 50m
RonD per SW 100m 50m 50m 100m
VonT per SW 120V 60V 60V 240V
VonD per SW 100V 50V 50V 200V
Table 3
Estimated converters losses when delivering 600MVA, at 0.95 lagging power factor.
Converter type 2-level VSC 3-level HBMMC 3-level FBMMC Proposed converter
Conduction losses (Based on
the data shown in Table 2)
0.143% 0.14% 0.302% 0.391%
Switching losses 0.4% at fs =1kHz 0.16% at fs =400Hz 0.7% at fs =1kHz
The main advantage of this type of converters that it can
operate with reduced switching frequency
4.4.2. Switching losses
Switching losses are mainly dependent onthe appliedswitching
frequency, the voltage level, and the current level. The switching
losses per switch, P
sw
, can be approximately given by (25),
P
sw
=
_
m

k=1
0.5(I
x
k
V
x
k
t
on
+I
y
k
V
y
k
t
off
)
_
f
o
(25)
where,

mis number of switch current pulses per fundamental cycle.

t
on
is the switch turn-on time.

t
off
is the switch turn-off time.

V
x
k
, andI
x
k
aretheoff-stateswitchvoltageandtheon-statesteady
stateswitchcurrent respectivelyat thebeginningof current pulse
number (k) where k =1, 2, . . ., m.

I
y
k
, and V
y
k
are the on-state switch current and the off-state
steady state switch voltage respectively at the end of current
pulse number (k) where k =1, 2, . . ., m.

f
o
is the fundamental frequency of the AC output voltage.
The simulation model of the proposed system can be used to
record the voltages and currents of each switch. For given turn-on
and turn-off times, Eq. (25) can be used to get the switching losses
per switch, and hence total switching losses can be estimated.
In the HVDC systemwith the same data used in calculating con-
duction losses, turn-on time of 1s, and turn-off time of 1s; the
estimated switching losses for the proposed topology and the other
HVDC converters are given in Table 3. It is clear that, the proposed
converter will have the lowest efciency.
4.4.3. Inductors losses
Copper losses in the inductors are another type of losses in the
proposed converter as well as modular multilevel converters. It can
be simply calculated by multiplying the square of rms value of the
inductor current and the inductor internal resistance.
Since the inductors are carrying high currents, their internal
resistances will be low (i.e. negligible internal resistances). As a
result, the inductor losses will be insignicant compared to other
types of losses.
5. Comparison between BI-HVDC and other existing
topologies
Table 4 shows a comparison between ratings and character-
istics of the most common HVDC converters such as the 2-level
VSC, m-level half-bridge MMC (HBMMC), m-level full-bridge MMC
(FBMMC), and the proposed converter (assuming a unity load
power factor, a unity modulation index, and a unity transformer
turns ratio).
Referring to Table 4, although the total VA rating of the semi-
conductor devices of the proposed converter is relatively high, and
its efciency is the lowest efciency among the other HVDC con-
verters, it offers, in addition to blocking the contribution of the AC
grids to the DC side faults, other desirable benets such as provid-
ing a pure sinusoidal output which eliminates the common mode
voltages, and reduces the dv/dt of the output voltage which avoids
local overstressingof thetransformer insulation. Theproposedcon-
verter andfull-bridgeMMC haveverysimilar semiconductor device
total VArating and both are able to block DC fault current. The main
advantages of the proposed converter over the FBMMC are: lower
dv/dt, and no need for voltage balancing.
6. Simulation and discussion
The block diagram for the simulated HVDC system is shown in
Fig. 8. In this system, inverter 1 operates in active-reactive power
control mode while DC voltage control mode is applied to inverter
2. For simplicity, AC system 2 and its inverter are modeled as a
constant DC source of 400kV. Two different simulation models
have been built. The rst uses the conventional 2-level VSC con-
guration (for Inverter 1) and the second uses the proposed BI
conguration. The main target is to investigate the performance
of the proposed conguration during normal operating conditions
and compare between the dynamic performances of each type dur-
ingDCfault conditions toillustrate the effectiveness of the BI-HVDC
during DC side faults.
The parameters of an HVDC system are given in Table 5. Based
on the desired switching frequency, inductor current ripple, and
capacitor voltage ripple, the boost converter inductance and capac-
itance are selectedas follows: for 200MVA ratedpower, and180kV
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 19
Table 4
Comparison between various types of HVDC converters.
Point of view Type
2-level VSC m-level HBMMC m-level FBMMC Proposed converter
(at Dmax =0.5)
Ratings of converters components
Switches
Number of switches 6 12(m1) 24(m1) 6
Voltage rating per switch 2Vmax 2Vmax/(m1) 2Vmax/(m1) 4Vmax
Current rating per switch Imax 0.75Imax

=(Imax) 0.75Imax

=(Imax) 2Imax
DC-link capacitors
Number of DC-link capacitors 1 6(m1) (one/sub-module) 6(m1) (one/sub-module) 1
Voltage rating 2Vmax 2Vmax/(m1) 2Vmax/(m1) 2Vmax
Filter capacitors
Number of capacitors 3 3 3 3
Voltage rating Vmax Vmax Vmax 4Vmax
Filter inductors
Number of inductors 3 3 3 3
Current rating Imax Imax Imax 2Imax
Characteristics
Arminductors No need Sixarminductors areneededtolimit circulatingandfault currents No need
DC blocking capabilities No No Yes Yes
Common mode voltages Yes Yes Yes No
dv/dt for output voltage Highest Low Low Lowest
Requirements for voltages balancing technique No Yes Yes No
Efciency Highest Lowest
Fig. 8. Description of simulated practice case study.
peak grid voltage, the corresponding peak grid current will be
approximately 750A. From (8), the inductor peak current at rated
conditions will be approximately 1500A assuming that the capac-
itor peak voltage is 800kV (i.e. D
max

=0.5), for inductor current

ripple of I =1300A (as shown in Fig. 9). Based on (9), an induct-
ance of 0.15H should be selected for a 1kHz switching frequency.
A larger inductance may be selected to lower current ripple mag-
nitude. On the other hand, based on (11), for an output voltage
ripple of 20%of capacitor peakvoltage (i.e. v
C
= 0.2 v
c
) anda 1kHz
switching frequency, a 5F will be sufcient.
Table 5
Parameters of HVDC systemmodel.
Rated power 200MVA
Grid voltage (rms) 220kV line-to-line
Three-phase transformer 220kV/220kV
Switching frequency 1kHz
Transformer and grid impedance 6.67+j26.67
Rated DC voltage, current 400kV, 0.5kA
DC link capacitor 1000F
DC cable length, DC resistance 150km, 133.33m/km
BI-HVDC parameters
Output capacitors 5F/phase
Input inductors 150mH/phase
DC offset (V
dco
) 600kV
Controllers data
PI1 (DC voltage controller) Kp =210
4
, K
i
=1.810
3
PI2 (active power controller) Kp =110
7
, K
i
=1.510
6
PI3 (reactive power controller) Kp =110
6
, K
i
=1.510
2
PI4, PI6, PI8 Kp =0.1, K
i
=1
PI5, PI7, PI9 Kp =2, K
i
=5
6.1. BI-HVDC simulation results
Active and reactive power control are applied to inverter 1
during normal operating conditions with AC system voltage of
V
ga
=180kV0

(peak). To test the performance of the proposed

topology, a number of scenarios are studied below.
6.1.1. Scenario1 (sudden change in reference power)
The active power reference is increased from 100MW to
200MWat t =1.5s, while reactive power is maintained constant at
zero VAR. The corresponding results are shown in Fig. 10. It should
be notedthat the positive signof reference active power means that
the grid is sourcing power and vice versa. The simulation results
demonstrate the acceptable performance of the proposed system.
Fig. 10a shows that the closedloopcontroller is able totrack the ref-
erence values effectively. Fig. 10b, c shows the corresponding grid
voltage and current. Although, Fig. 10d shows that the inverter out-
put voltages are slightly distorted at this lowswitching frequency,
the grid currents in Fig. 10c are pure sinusoidal due to the lter-
ing action of the interfacing reactance. Fig. 10e shows the capacitor
Fig. 9. Inductor current and its ripple magnitude in the simulated case study.
20 A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223
(c) (b) (a)
1.5 2 2.5 3
0
100
200
time, s
G
r
i
d

p
o
w
e
r
s

(
M
W
,

M
V
A
R
)
active
reactive
1.5 2 2.5 3
-200
-100
0
100
200
time, s
G
r
i
d

v
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
t
V
g
(kV)
0.1 i
g
(A)
2.4 2.42 2.44 2.46 2.48 2.5
-200
-100
0
100
200
time, s
G
r
i
d

v
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
t
V
g
(kV) 0.1 i
g
(A)
(f)
(e) (d)
2.46 2.47 2.48 2.49 2.5
-200
-100
0
100
200
time, s
I
n
v
e
r
t
e
r

v
o
l
t
a
g
e
,

k
V
2.46 2.47 2.48 2.49 2.5
0
200
400
600
800
time, s
C
a
p
a
c
i
t
o
r

v
o
l
t
a
g
e
,

k
V
1.5 2 2.5 3
-500
0
500
time, s
D
C

v
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
t
V
dc
(kV)
I
dc
(A)
Fig. 10. Simulation results (rst scenario in BI-HVDC conguration).
voltage of phase-A; it is clear that it has two components (DC and
AC components). Fig. 10f shows the DC side quantities; the DC
current is negative because it ows in opposition to the dened
direction in Fig. 8. Fig. 10f shows that when the DC current mag-
nitude increases, the DC-link voltage at inverter 1 increases. This
can be simply proven by applying Kirchhoffs voltage lawon the DC
side, i.e. (V
dc
=400kVI
dc
R
cable
), for negative I
dc
, the V
dc
will increase
with the increasing of I
dc
.
6.1.2. Scenario2 (power reversal)
To test the bi-directional independent control of both active and
reactive powers using the proposed topology, the active power is
reversedfrom100MWto100MWat t =1.5s whilereactivepower
is maintained constant at zero VAR. The corresponding results are
shown in Fig. 11. Fig. 11a shows the variation of actual active and
reactive power. It is clear that the power is reversed successfully.
Fig. 11b shows the corresponding grid current. Fig. 11c shows grid
current, for t <1.5s, in-phase with the grid voltage (i.e. positive grid
active power sourcing). Fig. 11d shows grid current, for t >1.5s,
out of phase with respect to grid voltage (i.e. negative grid active
power sinking). Fig. 10e shows that when the active power is
reversed, the DC-link voltage at inverter 1 decreases. This is gov-
erned by (V
dc
=400kV-I
dc
R
cable
); for positive I
dc
, V
dc
will be lower
than 400kV and vice versa. The variation of DC current (I
dc
) with
varying active power reference is shown in Fig. 11f. It is clear that
the DC current is reversed successfully.
6.1.3. Scenario3 (DC side fault)
In this scenario, the performance of the proposed converter is
tested during DC side faults. The converter was operating with an
active power reference of 200MW and zero MVAR before apply-
ing a DC side fault at the mid-point of the DC cable at t =2.5s.
When the DC fault is detected, the IGBT gate pulses are blocked.
The corresponding results are shown in Fig. 12. Fig. 12a shows the
variation of grid active and reactive power before and after apply-
ing the DC side fault. It is clear that the active power is limited
to zero after the fault, but the reactive power increases from 0 to
approximately 100MVAR due to the equivalent impedance seen
by the grid after inhibiting gate pulses; which is mainly capacitive
reactance as illustrated in Section 3.
Fig. 12b shows the variation of grid current. It is clear that
the current was in-phase with the grid voltage before initiation
(c) (b) (a)
(f) (e) (d)
1.5 2 2.5 3
-100
-50
0
50
100
time, s
G
r
i
d

p
o
w
e
r
s

(
M
W
,

M
V
A
R
)
reactive
active
1.5 2 2.5 3
-500
0
500
time, s
G
r
i
d

c
u
r
r
e
n
t
,

A
1.3 1.32 1.34 1.36 1.38
-200
-100
0
100
200
time, s
G
r
i
d

v
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
tV
g
(kV) 0.1 i
g
(A)
2.4 2.42 2.44 2.46 2.48 2.5
-200
-100
0
100
200
time, s
G
r
i
d

v
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
tV
g
(kV) 0.1 i
g
(A)
1.5 2 2.5 3
200
250
300
350
400
450
time, s
D
C

v
o
l
t
a
g
e
,

k
V
1.5 2 2.5 3
-500
0
500
time, s
D
C

c
u
r
r
e
n
t
,

A
Fig. 11. Simulation results (second scenario in BI-HVDC conguration).
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 21
(c) (b) (a)
(f) (e) (d)
2 2.2 2.4 2.6 2.8 3
-100
0
100
200
300
time, s
G
r
i
d

P
o
w
e
r
s
P(MW)
Q (MVAR)
2.5 2.55 2.6 2.65
-200
-100
0
100
200
time, s
G
r
i
d

V
o
l
t
a
g
e

a
n
d

c
u
r
r
e
n
t
V
g
(kV) 0.1 i
g
(A)
pf=1
pf=0 (lead)
2.45 2.5 2.55 2.6 2.65
-400
-200
0
200
400
time, s
I
n
v
e
r
t
e
r

v
o
l
t
a
g
e
,

k
V
2.45 2.5 2.55 2.6 2.65
0
200
400
600
time, s
D
C

V
o
l
t
a
g
e
,

k
V
2.4 2.5 2.6 2.7 2.8 2.9
-40
-30
-20
-10
0
10
time, s
D
C

c
u
r
r
e
n
t

(
I
d
c
)
,

k
A
-40kA
-450 A
Zero
2.4 2.5 2.6 2.7 2.8 2.9
-500
0
500
1000
time, s
C
a
p
a
c
i
t
o
r

v
o
l
t
a
g
e
,

k
V
Fig. 12. Simulation results (Third scenario in BI-HVDC conguration DC-side fault).
of the fault, and then it leads the voltage and decreases in mag-
nitude after inhibiting the IGBTs gate pulses (during the fault,
the grid current ows to the inverter output capacitors, which
are seen as a star-connected balanced three-phase load with high
capacitive impedance). The per-phase equivalent circuit of the AC
side after blocking the fault consists of the grid voltage (180kV
peak), interfacing impedance (6.67+j26.67), and boost converter
capacitance (X
c
=1/C=637). Based on (12), the newgrid current
magnitude is approximately 280A (i.e. the grid current changes
from7400A to approximately 280-90

A).
Fig. 12c shows that the grid voltage appears across the BI ter-
minals after applying the fault due to the blocking capability when
the IGBT gate pulses are inhibited. Fig. 12d shows that the DC link
voltage of inverter 1 decreased to zero after fault initiation. Fig. 12e
shows the DC fault current contribution. The peak capacitor dis-
charge current reaches 40kA, andthendecays to a zero steady state
value due to the blocking capability of this converter. As a result,
the DC circuit breaker associated with the BI topology will be sim-
ple and can disconnect at zero current crossings to clear the fault.
Finally, Fig. 12f shows the variation of boost converter capacitor
voltage, it is clear the capacitor voltage is positive for a long dura-
tion which reverse biases all diodes and blocks the AC grid current
contribution in DC-side fault.
6.2. VSC-HVDC simulation results (DC side fault)
To compare between the performance of the conventional 2-
level VSC and the proposed conguration during a DC side fault, the
same test fault is applied and the results are as shown in Fig. 13.
Fig. 13a shows the variationof gridactive andreactive power before
and after applying the DC side fault. It is clear that the active and
reactive powers increased after applying the DC fault due to the
rectication action of the freewheeling diodes in the VSC congu-
ration. In the proposed conguration the diodes are reverse biased
and the grid active power is limited to zero. Fig. 13b shows grid cur-
rent increasing to approximately 5kA due to the DC fault. Fig. 13c
shows the variation of per-phase inverter output voltage. It is clear
that the inverter voltage magnitude decreased signicantly due to
thelargeuncontrolledcurrent drawnfromthegridintotheDCfault.
Fig. 13d shows that the DC link voltage decreased to approximately
60kV (not to zero as in the proposed BI conguration). Finally,
Fig. 13e shows the DCfault current contribution. The peak capacitor
discharge current reaches 40kAas in the proposed BI conguration
because the initial discharge current is not affectedbythe converter
conguration but mainly depends on the DC-link capacitance and
DC cable parameters which are the same in both cases. After the
initial discharge, current decays with time and reaches to 5.8kA at
2 2.2 2.4 2.6 2.8 3
0
500
1000
1500
time, s
G
r
i
d

P
o
w
e
r
s
P(MW)
Q(MVAR)
2.45 2.5 2.55 2.6 2.65
-10
-5
0
5
10
time, s
G
r
i
d

c
u
r
r
e
n
t
,

k
A
2.45 2.5 2.55 2.6 2.65
-400
-200
0
200
400
time, s
I
n
v
e
r
t
e
r

v
o
l
t
a
g
e
,

k
V
(c) (b) (a)
(e) (d)
2.45 2.5 2.55 2.6 2.65
0
200
400
600
time, s
D
C

V
o
l
t
a
g
e
,

k
V
2.4 2.5 2.6 2.7 2.8 2.9
-40
-30
-20
-10
0
10
time, s
D
C

C
u
r
r
e
n
t

(
I
d
c
)
,

k
A
-450A
-40kA
-5.8kA
Fig. 13. Simulation results for DC-side fault in 2-level VSC-HVDC conguration.
22 A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223
(c) (b) (a)
1 2 3 4 5
200
250
300
350
400
450
time, s
D
C

V
o
l
t
a
g
e
,

k
V
2 3 4 5
0
50
100
150
200
250
time, s
A
c
t
i
v
e

p
o
w
e
r
,

M
W
2 3 4 5
-50
0
50
time, s
R
e
a
c
t
i
v
e

p
o
w
e
r
.

M
V
A
R
Fig. 14. Test of DC voltage controller, (a) DC-link voltage in kV, (b) injected grid active power in MW, and (c) injected grid reactive power in MVAR.
(b) (a)
1.36 1.37 1.38 1.39 1.4
-200
0
200
time, s
I
n
v
e
r
t
e
r

v
o
l
t
a
g
e
s
,

k
V
1.36 1.37 1.38 1.39 1.4
-1000
0
1000
time, s
G
r
i
d

c
u
r
r
e
n
t
s
,

A
Fig. 15. Effect of the output capacitors mismatch on the quality of the output AC voltages.
steady state (not to zero as in the proposed conguration); i.e. the
DC circuit breaker associated with the VSC topology will be more
complicated compared to the BI breaker.
6.3. Test of DC voltage controller in BI-HVDC
In this section, the DC voltage controller for the proposed topol-
ogy is tested. In this case, the converter was transferring 80MW
from the grid to the DC side (loading from the other converter),
then at t =2s the power is increased to 160MW. The correspond-
ing DC-link voltage, injected grid active power, and grid reactive
power at the converter at which the DC voltage control is applied
is shown in Fig. 14. It is clear that, the DC voltage is well regulated
and the grid is injecting the required amount of active power to
replenish the DC-link and maintain constant DC-link voltage.
6.4. Effect of the output capacitance variation on the inverter
output voltages
In this section, the effect of capacitors mismatch on the quality
of the three-phase inverter output voltages is tested. In this case,
the output capacitances are dened by 4.5F, 5F, and 5.5F to
emulate the mismatch between the capacitors. The per-phase out-
put voltages, and grid currents for this case are shown in Fig. 15
assuming same abovementioned converter parameters with con-
stant DC-link voltage of 400kV. The converter was transferring
200MWfromDC-side to its AC-side at unity power factor. It is clear
that, the voltage ripple ineachphase is different due tomismatchin
the capacitance, theses ripples are oscillating around same instan-
taneous average for all phases. These ripples will be damped and
will not appear on the grid current thanks to the ltration action of
the interfacing impedance as shown in Fig. 15, i.e. capacitors mis-
match has a negligible effect on the quality of the converter output
AC voltages.
7. Conclusion
This paper proposes a BI-HVDC system with blocking capabil-
ity of AC side contribution during DC side faults. The BI-HVDC
congurationprovides independent active andreactive power con-
trol in both directions. The main disadvantages of the proposed
topology are: (i) slightly lower efciency compared to existing
HVDC topologies due to higher conduction losses, and relatively
higher switching frequency. (ii) The requirement for semiconduc-
tor devices withrelativelyhigher voltage/current rating, andhigher
isolation requirements. The high voltage rating constraint can be
handled using the multi-module version of the proposed BI-HVDC
conguration where the series connection of IGBTs and their asso-
ciated problems can be avoided.
The main advantages of the proposed conguration can be sum-
marized as follows:

Complete blocking capability between the AC grid and DC

side faults via inhibiting the IGBT gate pulses which also pro-
tects the semiconductor devices against DC fault currents. This
feature is highly desirable especially in multi-terminal HVDC
systems.

Generation of sinusoidal output currents with no need for out-

put lters (interfacing reactance is sufcient). The generation of
direct sinusoidal output provides lowdv/dt stresses and no com-
mon mode voltage.
A simulation study of the proposed BI-HVDC system has also
been carried out during healthy conditions. The simulation results
demonstrate the acceptable performance of the proposedtopology.
A comparative simulation between the performance of BI-HVDC
and VSC-HVDC systems during a DC side fault has been carried out
as well. The simulation results showthe promising performance of
the BI-HVDC under DC side faults.
A. Elserougi et al. / Electric Power Systems Research 116 (2014) 1223 23
Acknowledgment
This publication was made possible by >NPRP grant (NPRP 4-
941-2-356) from the Qatar National Research Fund (a member
of Qatar Foundation). The statements made herein are solely the
responsibility of the authors.
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