Computer Arithmetic Slide 1 ( John C.

Knight 1997)
UVA
Department of Computer Science
COMPUTER A RITHMETIC
Computer Arithmetic Slide 2 ( John C. Knight 1997)
UVA
Department of Computer Science
NUMBER R EPRESENTATIONS
Positional Number System And Radix Point - Binary Is Radix 2
Integer And Fixed-Point Numbers
Sign-Magnitude:
- Store Magnitude With Separate Sign Indicator
- Normal Human Scheme
Radix Complement:
- Store Positive Number x In n Digits As |x|
- Store Negative Number x In n Digits As R
n
- |x|
- For R = 2 This Is Twos Complement
Diminished Radix Complement:
- Store Positive Number x In n Digits As |x|
- Store Negative Number x In n Digits As R
n
- 1 - |x|
- For R = 2 This Is Ones Complement
Computer Arithmetic Slide 3 ( John C. Knight 1997)
UVA
Department of Computer Science
TWOS C OMPLEMENT
n Binary Digits Can Represent 2
n
Bit Patterns
n Binary Digits Can Represent 2
(n-1)
Different Signed Numbers Including Zero
In n Bits, Representable Non-Negative Numbers Are 0 To 2
(n-1)
- 1
Represented As The Unsigned Integers 0 To 2
(n-1)
- 1
In n Bits, Representable Negative Numbers Are -1 To -2
(n-1)
Represented As The Unsigned Integers 2
n
- 1 To 2
(n-1)
Store -x As 2
n
- |x|
Leading Bit Is Sign, Fixed Binary PointNote Fraction Case
2s Complement - Invert Bits And Add 1 (Why Does This Work?)
Example With n = 4:
- Non-negative Numbers 0, 1, 2, 3, 4, 5, 6, 7
- Negative Numbers -1, -2, -3, -4, -5, -6, -7, -8
- Negative Numbers Stored As 15, 14, 13, 12, 11, 10, 9, 8
(Try This For Radix 10)
Computer Arithmetic Slide 4 ( John C. Knight 1997)
UVA
Department of Computer Science
ONES C OMPLEMENT (U SEFUL E XAMPLE, R ARELY U SED)
n Binary Digits Can Represent 2
n
Bit Patterns
Representable Non-Negative Numbers Are 0 To 2
(n-1)
- 1
Represented As The Unsigned Integers 0 To 2
(n-1)
- 1
Representable Negative Numbers Are -1 To -(2
(n-1)
-1)
Represented As The Unsigned Integers 2
n
- 2 To 2
(n-1))
Store -x As 2
n
- 1- |x|
Leading Bit Is Sign
Each Digit Is Its Own Complement
Form Ones Complement By Inverting Bits
(Why Does This Work?)
Example With n = 4:
- Non-negative Numbers 0, 1, 2, 3, 4, 5, 6, 7
- Negative Numbers -1, -2, -3, -4, -5, -6, -7
- Negative Numbers Stored As 14, 13, 12, 11, 10, 9, 8
(Try All This For Radix 10)
Computer Arithmetic Slide 5 ( John C. Knight 1997)
UVA
Department of Computer Science
TWOS C OMPLEMENT A DDITION
Assume n Bit Representation
Addition Algorithm:
- Form Simple n-Bit Binary Sum (Ripple-Carry Addition)
- Ignore Carry Out Of Adder!
- Signal Overflow If Unexpected Change Of Sign
- Overflow Possible Only If Both Operands Same Sign
Note No Special Attention To Negative Numbers
Does This Work? Yes! Why?
Four Sign Combinations To Consider:
- Both Operands Positive
- Both Operands Negative
- One Positive, One Negative, Result Positive
- One Positive, One Negative, Result Negative
Subtraction By Sign Change And Add (How Is Sign Changed?)
Computer Arithmetic Slide 6 ( John C. Knight 1997)
UVA
Department of Computer Science
ONES C OMPLEMENT A DDITION
Addition Algorithm:
- Form Simple Binary Sum
- Carry Bit Returned To Least-Signif-Digit Carry Input
- Signal Overflow If Unexpected Change Of Sign
Note No Special Attention To Negative Numbers
Again, This Actually Works
Four Cases:
- Both Operands Positive
- Both Operands Negative
- One Positive, One Negative, Result Positive.
- One Positive, One Negative, Result Negative.
Subtraction By Sign Change And Add
Computer Arithmetic Slide 7 ( John C. Knight 1997)
UVA
Department of Computer Science
OVERFLOW
Unsigned Representations
- Carry Out Of Most Significant Digit
Radix Complement Representations:
- Unexpected Sign Change
- Occurs Because Of Overflow From Adjacent Bit
Implemented As XOR Of Carries From Two Most Significant Bit Positions
Computer Arithmetic Slide 8 ( John C. Knight 1997)
UVA
Department of Computer Science
CARRY-LOOK-AHEAD A DDITION
Predict Carry Value Using Additional Circuitry
Two Basic Signals:
- Generate g
i
= x
i
y
i
- Propagate p
i
= x
i
+ y
i
Generate Indicates Carry If Both Inputs Are 1
Propagate Indicates Carry Through Of Input Carry
Both Signals Generated For Each Bit Of Adder (In Addition T o Full Adder)
- Example: See Hayes p228
All Carry Signals Predictable From Inputs
Expensive
Usual Approach Is To Apply To Subsets Of Bits (Hayes, Figures 4.5 , 4.6, 4.7)
See Complete Example Figure 4.9
Computer Arithmetic Slide 9 ( John C. Knight 1997)
UVA
Department of Computer Science
MULTIPLICATION
Shift Left To Multiply By Power Of Radix
Add In Series Of Partial Sums
Result Is Twice Length Of Operands
Adder Only Need Be Length Of Operands
Positive Operands:
- Works CorrectlyBut Be Careful Of Double Length
- Overflow Depends On Content And Radix Point Location
Negative Operands:
- Fails Every Time
- Problem Is That Partial Sums Are Half Required Width
- Adder Is Half Width But Result Is Formed From Full Width O perands
- Solution Is Sign Extension Of Negative Operands
- 2s Complement In n Bits Becomes 2s Complement In 2n Bits
Alternative Approach Is To Treat Numbers As Sign/Magnitude
Computer Arithmetic Slide 10 ( John C. Knight 1997 )
UVA
Department of Computer Science
BOOTHS A LGORITHM
Important Speedup Of Shift/Add Multiplication
Notice That:
- 2
n
+ 2
{n-1}
+ ... + 2
{n-k}
= 2
{n+1}
- 2
{n-k}
- (Prove This)
Hence, Any Sequence Of Shift/Adds Can Be Replaced By Two
Algorithm:
- Result Register Initially Zero
- Move Right To Left Across Multiplier
- Shift Multiplicand On Each Bit
- If 1 0 Encountered Then Add Shifted Multiplicand From Result
- If 0 1 Encountered Then Subtract Shifted Multiplicand To Resu lt
- Assume 0 To The Right Of Multiplier
For Positive Operands, Sign Zero So Last Operation Is Add Compl eting Pair
(Not Necessarily On Last Bit Position)
But, This Works For Negative Numbers Too!
Wow!
Computer Arithmetic Slide 11 ( John C. Knight 1997 )
UVA
Department of Computer Science
BOOTHS A LGORITHM - N EGATIVE O PERANDS
Assume An n+1 Bit, 2s Complement Representation
Negative Number X Stored As 2
(n+1)
- x Where x = |X|
But 2
(n+1)
- x = 2
n
+ y For Some y (Sign Bit Plus Remainder)
y Is A Positive Integer Less Than 2
n
Also, X = -2
n
+ y
NOTE:
- y Is Just Part Of The 2s Complement Form Of X
- y Does Not Have To Be Calculated
Multiplication Omits Last Step - Addition Of Multiplicand * 2
(n+1)
This Corrects For Use Of 2s Complement
Computer Arithmetic Slide 12 ( John C. Knight 1997 )
UVA
Department of Computer Science
VERY F AST MULTIPLICATION
Parallel Hardware Allows Basic Operations To Be Carri ed Out In Parallel
Single-bit Multiplication Done By Array Of ANDs
Result Computed By Addition Using Array Of Adders
See Hayes Pages 240-242
Computer Arithmetic Slide 13 ( John C. Knight 1997 )
UVA
Department of Computer Science
DIVISION
Binary Is Very Similar To Decimal
Divide By Repeated Subtraction Of Multiples Of Divisor
Subtract Divisor Shifted Left:
- Divisor Multiplied By Powers Of 2 By Shift
- But Comparison Required Before Subtract
- Sequence (Shift, Compare, Subtract) Is Too Slow
- Compare Is Full-Width Comparison
One Solution:
- The Restoration Method
- Always Do Subtract - Check Sign Of Result
- Add Back If Unnecessary
Second Solution:
- Non-restoring Method
- X - 2
{j-1}
D = X - 2
j
D + 2
{j-1}
D
- Check Result Of Step i
- If Negative, ADD On Step i + 1
- If Final Remainder Negative, Add Correction
Computer Arithmetic Slide 14 ( John C. Knight 1997 )
UVA
Department of Computer Science
ISSUES WITH F IXED-POINT A RITHMETIC
Limited Range Of Representation
Obscure Total FunctionsOperations Can Complete:
- By Producing Result
- Signaling An Exception
Used For Integers, Rarely For Fractions
Incomplete Fractional Representation
Multiple Representations For Negative Numbers
Computer Arithmetic Slide 15 ( John C. Knight 1997 )
UVA
Department of Computer Science
FLOATING P OINT
Store Number As A = [S, M] * B**E
- S - Sign Of Number
- M - Mantissa
- B - Base (Usually 2 But Not Always!)
- E - Exponent (Includes Exponent Sign)
- Sign Depends On Mantissa Format
Mantissa:
- Assumed Binary Point Somewhere, Usually LHS
- Often Sign/Magnitude Representation
- Sometimes 2s Complement, Rarely Anything Else
Exponent:
- Often Excess K For Some K
- E.g. Excess 127, i Stored As i + 127
Many Formats:
- Different Lengths, Representations, Bases
- But, Fortunately, There Is IEEE Standard 754
Computer Arithmetic Slide 16 ( John C. Knight 1997 )
UVA
Department of Computer Science
FLOATING P OINT
Many Representations Of The Same Number, So Normalize:
- Delete Extra Digits From Left Of Mantissa
- Shift Mantissa Left, Inject Zeros On Right
- Decrease Exponent To Compensate
Maximum Positive Value:
- Largest Positive Mantissa
- Largest Positive Exponent
Smallest Positive Value:
- Smallest Positive Mantissa
- Largest Negative Exponent
Most Negative Value:
- Largest Negative Mantissa
- Largest Positive Exponent
Least Negative Value:
- Smallest Negative Mantissa
- Largest Negative Exponent
Representable Spectrum Does Not Include Zero
Computer Arithmetic Slide 17 ( John C. Knight 1997 )
UVA
Department of Computer Science
IEEE S TANDARD 754
One-Bit Sign
Exponent:
- 8-bit, Excess-127 Binary Integer
- 0 < E < 255 Note End Cases Not Used
Mantissa:
- 23 Bits
- Absolute Value Of Number (Sign Separate)
- Normalized Representation
- Hidden BitValue 1
- Binary Point At Left Of Mantissa But Right Of Hidden Bit
Number Represented:
(-1)
s
x (1.M) x 2
(E-127)
Examples:
1.0 0 01111111 00000000000000000000000
-1.5 1 01111111 10000000000000000000000
100.5 1100100.1 (Fixed-point binary)
0 10000101 10010010000000000000000
Computer Arithmetic Slide 18 ( John C. Knight 1997 )
UVA
Department of Computer Science
IEEE S TANDARD 754 (C ONTINUED)
Special Cases:
- E = 255 and M <> 0 Not-a-Number
- E = 255 and M = 0 +/- Infinity
- E = 0 and 0.M <> 0 Denormalized (No Hidden Bit, Exp = -126)
- E = 0 and M = 0 F.P. Zero
Denormalized Used To Store Numbers:
- That Are Very Small
- Smaller (Closer To Zero) Than Smallest Normalized Num bers
- Give Up Precision By Shifting To The Right
Smallest Representable Number:
0 00000000 00000000000000000000001
+ 2
-126
2
-23
Computer Arithmetic Slide 19 ( John C. Knight 1997 )
UVA
Department of Computer Science
IBM S YSTEM/370 F LOATING P OINT F ORMATS
Exponent:
- 7-Bit Length
- Base 16
- Excess 64 Representation
Mantissas:
- 24 Or 56 Or 112 Bits
- Base 2
- Sign, Magnitude
Base-16 Exponent Implies Hex View Of Mantissa
Normalized If Leftmost Hex Digit (Leftmost Four Bits) Nonzero
Gain Dynamic Range
Lose Precision
Computer Arithmetic Slide 20 ( John C. Knight 1997 )
UVA
Department of Computer Science
FLOATING P OINT A RITHMETIC
Add:
- Check For Zero Operand(s)
- Align Mantissas (Increase Smaller Exponent)
- Add Mantissas
- Normalize
Subtract:
- Trivial - Reverse Sign Of Operand
Multiply:
- Check For Zero Operand(s)
- Add Exponents (Beware Of Excess Representations!)
- Multiply Mantissas
- Normalize
- Round
Examples:
- [0.25 * 10
2
] + [0.43 * 10
3
]
- [0.25 * 10
2
] * [0.43 * 10
3
]
Computer Arithmetic Slide 21 ( John C. Knight 1997 )
UVA
Department of Computer Science
ISSUES WITH F LOATING-POINT A RITHMETIC
Exponent Overflow:
- Positive Exponent Too Large
- Number Too Large
Exponent Underflow:
- Negative Exponent Too Negative
- Number Too Small
Mantissa Overflow:
- Overflow From Arithmetic
- Dealt With By Exponent Adjustment
Mantissa Underflow:
- Loss Of Digits During Alignment
- Numbers Too Different
Zero
Negative Overflow
Negative Underflow Positive Underflow
Positive Overflow
Positive Numbers Negative Numbers
Computer Arithmetic Slide 22 ( John C. Knight 1997 )
UVA
Department of Computer Science
DECIMAL A RITHMETIC
Zoned BCD:
- Character Code Of Digits, Like ASCII
Packed BCD:
- 4-bit Binary Number Per Digit
- Two Digits Per Byte
Excess 3:
- Store Digit i As i+3 In 4 Bits
Arithmetic:
- Binary Adder Does Not Work Immediately
- Need To Correct By Adding 6 Sometimes
- Some Machines, Especially Microprocessors, Have Special Ins tructions
Arithmetic Works For Excess 3:
- Always Generates Carry Correctly (Exceeds 15)
- Add 3 To Result If Carry Out
- Subtract 3 From Result If No Carry Out