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Proceedings I Ber Chip 2012
Proceedings I Ber Chip 2012
PROCEEDINGS
Roberto Murphy
INAOE, Mexico
Reydezel Torres
INAOE, Mexico
Table of Contents
Tatsuya Maruyama and Alberto Palacios Pawlovsky. A Study of Methods to
Improve an Immune Algorithm for Searching for the Pair of Inputs that Cause
the Maximum Number of Switching Gates in a Combinational Circuit ------------------------ 1
Laurentiu Acasandrei and Angel Barriga. Implementacin sobre FPGA de un
sistema de deteccin de caras basado en LEON3 ------------------------------------------------ 6
Jess Balosa, Francisco Jos Crespo and Angel Barriga. Sistema empotrado
de reconocimiento de voz sobre FPGA ------------------------------------------------------------ 10
Juan Nez, Mara J. Avedillo and Jos M. Quintana. Bifurcation Diagrams in
MOS-NDR Frequency Divider Circuits-------------------------------------------------------------- 14
Romulo Volpato, Tales Pimenta, Filipe Ramos, Michel Santana and Paulo
Crepaldi. Prediction of Energy Transfer in Implantable Devices ----------------------------- 18
David Cabral, Leonardo Zoccal, Paulo Crepaldi and Tales Pimenta. Schottky
Barrier Diodes SBD in Standard CMOS Process---------------------------------------------- 21
Joel Molina, Rafael Ortega, Wilfrido Calleja, Pedro Rosales, Carlos Zuniga
and Alfonso Torres. Performance of a MOHOS-type Memory by Using
Different Tunneling Oxide Thickness. --------------------------------------------------------------- 26
Elisa Calvo Gallego, Piedad Brox Jimnez and Santiago Snchez-Solano.
Un algoritmo en tiempo real para etiquetado de componentes conectados en
imgenes --------------------------------------------------------------------------------------------------- 30
Alexander Zemliak, Antonio Michua and Tatiana Markina. Behavior of
Lyapunov Function for Different Strategies of the Circuit Optimization
Problem ---------------------------------------------------------------------------------------------------- 36
Adriana Aparecida Dos Santos Izidoro, Eduardo Souza Dias, Fernando A
Cardoso and Tales Cleber Pimenta. Digital Multiplexer of an EEG Signal
Acquisition System -------------------------------------------------------------------------------------- 40
Diego Brengi, Salvador Tropea and Christian Huy. S3Proto-mini: Tarjeta de
Hardware Libre con FPGA de encapsulado BGA------------------------------------------------ 43
Fernando Urbano, Vladimir Trujillo and Jaime Velasco. Implementacin
Hardware de un Multiplicador Serial Basado en Bases Normales sobre
GF(2^163) ------------------------------------------------------------------------------------------------- 47
ii
iii
iv
Salvador Antonio Arroyo Daz, Alejandro Diaz Sanchez and Apolo Zeus
Escudero Uribe. Architecture for myolectric features extraction by H.O.S. of
four sMES channels ------------------------------------------------------------------------------------ 179
Salvador Antonio Arroyo Daz and Karina Rosas Paleta. Control de Robot
Mvil Basado en FPGA-------------------------------------------------------------------------------- 183
Victor H. Vega G. and Edmundo Gutierrez. Multiport Analysis of TwoDimensional Nanosystems in a Magnetic Field Based on the NEGF
Formalism ------------------------------------------------------------------------------------------------- 188
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I.
INTRODUCCIN
II.
i( x' , y' )
ii ( x , y )
(1)
x ' x, y ' y
A
C
B
ii1
ii3
ii2
ii4
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D2
D1
D3
DN
III.
CODISEO HARDWARE-SOFTWARE
W H W H
(2)
(3)
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IV.
RESULTADOS
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V.
AGRADECIMIENTOS
Este trabajo ha sido soportado parcialmente por el proyecto
financiado por la Unin Europea MOBY-DIC Project FP7IST-248858, por el Ministerio de Ciencia y Tecnologa bajo el
proyecto
TEC2008-04920
y
TEC2011-24319
con
cofinanciacin FEDER y por la Junta de Andaluca bajo el
proyecto P08-TIC-03674.
REFERENCIAS
[1]
[2]
[3]
[4]
[5]
[6]
[7]
a)
CONCLUSIONES
b)
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I.
II.
INTRODUCCIN
y ( n ) ai x ( n i )
(1)
i 1
e( n ) x ( n ) y ( n ) x ( n ) ai x ( n i )
i 1
(2)
RECONOCIMIENTO DE VOZ
(3)
donde
R (0)
R(1)
R
R( N 1)
10
R (1)
R (0)
R( N 2)
R ( N 1)
R( N 2)
R (0)
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R (1)
R (2)
R( N )
A. Codec de audio
La placa de desarrollo ML505 dispone de una FPGA de
Xilinx de la familia Virtex-5. Dicha placa contiene entradas y
salidas de audio controladas mediante el cdec AC97 de
Analog Device AD1981B [3]. Entre las caractersticas de este
cdec destacamos las siguientes:
FPGA
MicroBlaze
OPB
Controlador
AC97
Cdec AC97
plbv46_opb
bridge
AC97Reset n
El cdec dispone de mdulos de conversin analgicodigital (ADC) y digital-analgico (DCA). Los convertidores
ADC y DCA estn basados en convertidores -. El mdulo de
conversin digital-analgico se utiliza para generar la salida de
audio, es decir, para reproducir sonidos. Est compuesto por 4
convertidores -, dos de 16 bits y dos de 20 bits.
PLB
Bit Clk
Sync
SData_Out
SData_In
III.
11
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Seal de audio
Digitalizacin
Pre-nfasis
Ventana de Hamming
Autocorrelacin
Clculo de coeficientes LPC
Decisin
Figura 2. Flujo del proceso de identificacin
Funcin
Descripcin
WriteAC97Reg
(4)
0n N
(5)
rl (m)
[ x l (n) x l (n m)]
m 0,1,..., p
n0
(6)
N 1 m
V.
12
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VI.
CONCLUSIONES
REFERENCIAS
[1]
[2]
[3]
[4]
13
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from MOS transistors that can be used to design a frequency divider circuit which operation is based on the
same principle as the RTD.
II. THE MOS-NDR STRUCTURE
Figure 1a shows the structure of the MOS-NDR device we have used, which is based on the circuits described in [4]. It consists of one CMOS inverter, made
up by NMOS1 and PMOS1 and biased by VINV, and one
NMOS transistor (NMOS2) whose gate-to-source voltage is modulated by the output voltage of the CMOS inverter. Figure 1b shows the simulated current-voltage
characteristic of the MOS-NDR device for transistor
parameters
given
by
WPMOS,1 = 0.16m,
WNMOS,1 = 2m, and WNMOS,2 = 5.4m; channel
length for all of them is 0.12m. For this case, the peak
current (Ip) is 2.11mA for a peak voltage (Vp) of 0.25V.
Both, the PDR and the NDR zones of the IV characteristics are obtained through the current of the NMOS2
transistor.
I. INTRODUCTION
Non-autonomous, very simple frequency divider
circuit based on the period-adding bifurcation sequences which appear in an RTD chaos circuit have been reported in the past few years [1], [2], [3], and
experimental results have been obtained, showing that
the phase noise is comparable to that of conventional dividers. These circuits exploit the NDR region in the
RTD IV characteristic to obtain autonomous nonlinear
oscillators and, in general, extremely complex behaviors with applications in diverse fields. Additionally,
when an external periodic excitation signal is used, such
circuits exhibit an increased variety of bifurcations sequences.
iNDR(mA)
2 Ip
PMOS1
VNDR
INDR
Vp
VINV
- 0.2 - 0.1
NMOS2
vNDR(V)
-1
NMOS1
-2
(b)
(a)
(c)
This work has been partially supported by the Spanish Government
14
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The peak voltage and current of the IV characteristic in Figure 1b can be modified by setting up properly
the sizes of the transistor. In this way, Ip is increased
with the width of NMOS2. Assuming that all transistors
have the same gate length, the position of Vp is controlled by the ratio between the widths of NMOS1 and
PMOS1. In this way, higher values of Vp are obtained by
decreasing the ratio W NMOS 1 W PMOS 1 . Additionally, we can obtain higher peak current values by increasing VINV [5]. Compared to the RTD device, the IV
characteristic in the MOS-NDR device lacks the second
PDR zone and presents a typical -shape. Figure 1c depicts the I-V characteristic, measured by a HP-4145A
parameters analyzer, of a MOS-NDR which we have
designed and fabricated in a standard commercial
0.13m CMOS process.
pendence of time t in the expression for excitation signal E, and periodic with period T = 1 f . If we choose
EM and IM as scale parameters with physical dimensions of voltage and current, respectively, and rescale
v C = xE M , i L = yI M , t = LC , E DC = E M ,
E A = E M , and f = LC , then variables x, y, ,
and will be dimensionless. Redefining now as t, the
following set of normalized equations are obtained:
1
x = --- y g x
y = + sin 2t x
The dynamics of Eq. (2) has been extensively studied for different parameter values. By fixing
and , the frequency of the external periodic signal has been used as the control parameter, and numerical integration using an adaptive-step Runge-Kutta
algorithm has been carried out to build one-parameter
bifurcation diagrams in the x plane. These diagrams plot the normalized output voltage x sampled at
a fixed phase of the normalized input signal for each
normalized frequency , and solutions during the first
60 periods of the input signal have been discarded to
avoid transient behaviour. Figure 3 shows a typical bifurcation diagram for the circuit computed when the
normalized frequency is swept in the range (0.01,1.5)
with the following values for the remaining parameters:
= 2 , = 0.3 , and = 0.4 . In circuit parameter values, this could correspond, among other possible set of
values, to C = 4pF, L = 1H, EM = 1V, IM = 1mA; an
external periodic signal with EDC = 0.3V, EA = 0.4V,
and a frequency between 10MHz and 1.5GHz. The
MOS-NDR device is biased in the negative resistance
region and a swing is applied. In this bifurcation diagram two kinds of regions are identified: those with a
continuum of points for a given value of , where the
behaviour is quasi-periodic or chaotic, and regions with
a finite number of points, where a periodic solution with
a period which is a multiple of the driving signal is
found.
di L
1 ----- E vC
dt- = -L
(1)
iL
vC
iNDR
vL
C
iC
MOS-NDR
device
(2)
15
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0.45 0.53 (period-6 to period-7), we find a frequency locked window of period-13 (=6+7) in the region 0.508 0.514 . Farey sequences also appear
when finer regions are considered, as is also shown in
Figure 6, where a period as high as 19 (6+13) appears in
the region 0.503 0.505 . Finally, we have also
performed some simulations to confirm our previous
theoretical study. Figure 7 shows the obtained results
for the circuit parameters in Section III (C = 4pF,
L = 1H, EM = 1V, IM = 1mA, EDC = 0.3V, and
EA = 0.4V). Figure 7a shows a division by 3 of a external periodic signal of frequency 125MHz ( = 0.25),
and Figure 7b the division by 5 of a signal which frequency is 10MHz ( = 0.38).
IV. CONCLUSIONS
References
[1] Y. Kawano, Y. Ohno, S. Kishimoto, K. Maezawa, and T.
Mizutani, 50 GHz frequency divider using resonant tunnelling chaos circuit, IEE Electronics Letters, Vol. 38,
no. 7, pp. 305-306, 2002.
[2] Y. Kawano, Y. Ohno, S. Kishimoto, K. Maezawa, T. Mizutani, and K. Sano, 88GHz dynamic 2:1 frequency divider using resonant tunnelling chaos circuit, IEE Electronics Letters, Vol. 39, no. 21, pp. 1546-1548, 2003.
[3] J.M. Quintana and M.J. Avedillo, Analysis of frequency divider RTD circuits, IEEE Trans. on Circuits and Systems I:
Regular Papers, vol. 52, no. 10, 2005, pp. 2234-2247.
[4] C. Wu, and K.-N. Lai, Integrated -type differential negative resistance MOSFET device, IEEE J. Solid-State Circuits, Vol. SC-14, pp. 1094-1101, Dec. 1979.
[5] W.-L. Guo, CMOS-NDR transistor, 9th International
Conference on Solid-State and Integrated-Circuit Technology, (ICSICT), pp. 92-95, Oct. 2008.
[6] T. S. Parker and L. O. Chua, Practical Numerical Algorithms for Chaotic Systems. New York: Springer-Verlag,
1989.
[7] L.-Q. Pei, F. Guo, S.-X. Wu, and L. Chua, Experimental
confirmation of the period-adding route to chaos in a nonlinear circuit, IEEE Trans. on Circuits and Systems, Vol.
33, no. 4, pp. 438-442, April 1986.
[8] K. Kaneko, Collapse of Tori and Genesis of Chaos in Dissipative Systems. Singapore: World Scientific, 1986.
16
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Figure 4: Trajectories from the numerical results for diagram for = 0.32 , ( = 2 , = 0.3 , and = 0.4 ).(a) in the
Figure 5: Trajectories from the numerical results for diagram for = 0.64 , ( = 2 , = 0.3 , and = 0.4 ).(a) in the cylindrical space, (b) in the plane x y , and (c) Poincar map.
vC(V)
19
13
(a)
t (s)
vC(V)
(b)
t (s)
17
ISSN 977-2177-128009
Romulo Volpato
INATEL
Santa Rita do Sapucai, Brazil
II.
I.
INTRODUCTION
y p G p jC p
Rs
18
(1)
Gp
2
G p (C p ) 2
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(2)
Cs
G p 2 (C p ) 2
(3)
2C p
where:
Gp
1
Rp
(4)
Rt R2 R p
(5)
The measurement and simulation were conducted
considering the voltage of generation as 1 V, the parallel load
of tag as 1k and the generator resistance as 50 .
Thus:
V1 I1 ( Rs1 jL1
1
) I 2 jM
jC1
(6)
0 I1 jM I 2 ( Rs 2 ` jL2
1
)
jC2
(7)
V1M
1
1
[(M ) 2 ( Rs 2 ' jL2
)( Rs1 jL1
)]C2
jC2
jC1
(8)
Distance
25mm
20mm
15mm
10mm
5mm
Measurement
769mV
943mV
1038mV
1026mV
1007mV
Simulation
1001mV
1061mV
1063mV
1055mV
1052mV
M
0.287H
0.370 H
0.532 H
0.692 H
0.917 H
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IV.
Distance
10mm
15mm
20mm
25mm
Error
3.26%
4.39%
7.3%
3.61%
CONCLUSIONS
The presence of pig tissue between the reader and the tag
causes a voltage tag reduction and a consequently reduction of
power. This power reduction is, in the worst case of 14%.
Therefore, the voltage (or power) drop is known, it should be
taken into consideration during RFID systems design.
It also can be inferred the small influence of any tissue at
13.57 Mhz. It is very important to know the maximum voltage
in the tag, mainly for implantable devices, so that the designer
can take the proper precautions.
Fig. 6 Measurement set up between tag and reader for free space.
ACKNOWLEDGMENT
The authors acknowledge CAPES, CNPq and FAPEMIG
for their financial support.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Distance
10mm
15mm
20mm
25mm
Free space
1932mV
1869mV
1671mV
1247mV
[8]
Pork tissue
1869mV
1787mV
1549mV
1202mV
[9]
20
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SAR
I.
dT SAR
dt
c
INTRODUCTION
Base Unit
Skin
DC
Sensors
+
Aquisition
+
Signal
Conditioning
+
Processing
Transponder (tag)
Implanted Device
(2)
Antennas
Information
RF to DC
Rectification
RF
Cs
(1)
Kg
21
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Metal
Insulator
SDB are also used in rectifiers for high and low voltage
because of their high current density and low voltage drop.
For solar cell applications, any voltage drop will result in a
reduction in efficiency and therefore a low voltage drop diode
is essential [5].
N type Semiconductor
Figure 3. MIS capacitor.
qBN qM
High frequency
qVbi
EC
Metal
Low frequency
Inversion
EF
Depletion
Semiconductor
EV
M1
Vbi BN
kT N C
ln
q N D
Accumulation
R1
W=100m
L=100m
R2
(3)
22
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P+
N+
P+
Nwell
Substrate P
C
A
W D max 1 0 S
C min
C max
4 S F
2
qW D
kT N D
ln
q ni
III.
(4)
In order to implement the metal-semiconductor junction it
is necessary the following mask sequence. First, an NWELL
(layer #42, TSMC) and an ACTIVE (#43) are used to delimit
the area that will contain the multi-finger SBD and guard
ring. Then an NPLUS layer (#45) is used to indicate N+
regions that will be the SBD ohmic contacts (cathode). The
next step is the CONTATCT layer (#48) that will be filled
with METAL 1.
(5)
(6)
MASK FLOW
23
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IV.
P type wafer
Silicon Dioxide
CGEOM
CT
LS
N type silicon
(MASK #42)
RS
RD
Figure 10. Small-signal SBD equivalent circuit.
CGEOM
P+ diffusion
(MASK #43)
A s
L
(7)
N+ diffusion
(MASK #45)
Rd
dV
dI
(4)
and
Via oppening
(MASK #48)
1/ 2
qN D s
CT A
2Vbi V
(5)
Metal deposition
(MASK #49)
V.
MEASURED RESULTS
24
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VI.
CONCLUSIONS
ACKNOWLEDGMENT
4,0E-02
3,5E-02
Average15
REFERENCES
Avarage10
3,0E-02
Current (A)
Avarage5
[1]
2,5E-02
2,0E-02
[2]
1,5E-02
1,0E-02
[3]
5,0E-03
[4]
Bias (V)
0,0E+00
-1,0
0,0
1,0
2,0
3,0
4,0
[5]
1,0E-03
[6]
[7]
8,0E-04
6,0E-04
4,0E-04
2,0E-04
0,0E+00
0,10
0,20
0,30
0,40
0,50
25
ISSN 977-2177-128009
M
O
The active trapping layer based on HfO2 nanoparticles (npHfO2) embedded in a SiO2 matrix layer, deposited by spin-on glass,
is deposited on thin chemical oxide. After some thermal annealing
treatments, a final oxide is deposited by a sol-gel method in order to
block the generated charge toward the gate. This layer is called
blocking oxide. The high oxide acts as a charge storage which can
develop memory effects by modulating the density of trapped charge
according to the applied gate voltage. The thickness of the active
oxide layer is limited by the grain size of the np-HfO2 which is about
100 nm in diameter. It is expected that, by using a high quality
blocking oxide, the density of trapped charge present by the active
high layer can be retained and get wider hysteresis window because
of its ability for charge retention. Measurements of capacitancevoltage and current-voltage are performed in order to extract the
performance of these devices. Also, figures of merit like
program/erase time and retention time are obtained.
H
O
S
Metal Gate
Blocking oxide
Charge-trapping layer
Tunneling oxide
N-type (100) Si
Back contact
26
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2.2
1.8
1.6
1.4
IG (A)
thickness (nm)
2.0
1.2
1.0
0
12
16
20
24
28
32
36
time (min)
Fourier
Transform
Infrared
Spectroscopy
(FTIR)
measurements were performed to charge-trapping layer in order to
observe composition and chemical bonding. Figure 3 shows the
spectrum of samples and the related absorbance peaks. As can be
seen, the characteristic absorption peaks of thermal SiO2 associated
whit vibration modes of stretching LO (1252 cm-1), stretching TO
(1075 cm-1) and rocking (458 cm-1) are observed [5,6]. Besides, two
absorbance peaks which belong to Hf-O bonding (752 cm-1 and 515
cm-1) and some peaks of organic impurities, related to solution
preparation, of C=C and C=O bonding (1300 cm-1 and 1800 cm-1) are
also present [6]. The np-HfO2 embedded in a SiO2 matrix are present
in the charge-trapping layer.
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
I-V characteristics of
SOHOS-type memories
FN tunneling
mechanism
VBD=3V
-10
0.02
Si-O
rocking
C=C
C=O
-4
-2
10
Cox=165pF
140p
Si-O
stretching TO
Si-O
stretching LO
-6
160p
0.04
-8
180p
Charge-trapping layer
deposition at 7000rpm
cured 600C
0.06
absorbance (u.a.)
-1
VG (V)
Capacitance (F)
0.08
10
Hf-O
VFB=0.25V
120p
100p
80p
60p
gate area=13.44E-4cm
40p
fresh condition
writing VG=2V
20p
0.00
VFB=-0.4V
erase VG=-2V
0
-2.0
2000
1800
1600
1400
1200
1000
800
600
400
-1.5
-1.0
-0.5
0.0
0.5
1.0
VG (V)
-1
wavenumber (cm )
27
ISSN 977-2177-128009
0.60
(a)
0.55
writing
VG=2V
0.50
0.45
tunneling oxide
2nm
1.45 nm
1.2nm
0.40
VFB (V)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.1
10
100
1000
time (s)
0.60
erase
VG=-2V
(b)
0.55
0.50
tunneling oxide
2nm
1.45 nm
1.2nm
0.45
0.40
0.35
VFB (V)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.1
10
100
1000
time (s)
Fig. 6. (a) Writing time characteristics and (b) erase time characteristics of
MOHOS-type memories with different tunneling oxide thicknesses.
100
90
80
70
60
50
40
Charge retention
30
tunneling oxide
2nm
1.45nm
1.2nm
20
10
0
1
10
100
1000
10000
time (seg)
28
ISSN 977-2177-128009
0.60
(a)
writing
VG=2V
0.55
0.50
0.45
0.40
0.35
VFB (V)
Acknowledgements
tunneling oxide
2nm
1.45 nm
1.2nm
0.30
0.25
0.20
0.15
References
0.10
[1] Suzuki, E., Hiraishi, H., Ishi, K., and Hayashi, Y. A low voltage alterable
EEPROM
with
silicon-oxide-nitride-oxide-semiconductor
(SONOS)
structure IEEE Transactions on Electron Devices. ED-30, 122. 1983
[2] ITRS 2010 Update Overview. 2010
[3] Kingon, A. I. Maria, J. P. Streiffer, S. K. Alternative dielectrics to silicon
dioxide for memory and logic devices, Nature, vol. 406, no.6799, pp. 1032
1038, 2000.
[4] Sugizaki T., Kobayashi M., Ishidao, M., Minakata, H., Yamaguchi, M.,
Tamura, Y., Sugiyama, Y., Nakanishi, T., y Tanaka, H. Novel multibit
SONOS type flash memory using a high-k charge trapping layer VLSI Symp
Tech Dig, 27-28. 2003
[5] V. P. Tolostoy, I. V. Chernyshova, V. A. Skryshevsky. Handbook of
infrared spectroscopy of ultrathin films. Ed. Wiley & Sons. 1985
[6] N. B. Colthup, L. H. Daly. Introduction to infrared an raman
spectroscopy. Ed. Academic press. 1982
[7] R. Perera, A. Ikeda, R. Hattori, Y. Kuroki. Trap assisted leakage current
conduction in thin silicon oxynitride films grown by rapid thermal oxidation
combined microwave excited plasma nitridation. Elsevier. 2003
[8] D. K. Schroder, Semiconductor material and device characterization
3rd. Ed. Wiley-Interscience.2006
[9] Y.N. Tan, W.K. Chim, B. J. Cho, W. K. Choi Over-erase phenomenon in
SONOS-type flash memory and its minimization using a hafnium oxide charge
storage layer IEEE Trans. Electron Dev. Vol. 51, no. 7. 2004
[10] D. S. Golubovic, E. Vianello, A. Arreghini, F. Driussi, M. J. van
Duuren, N. Akil, L. Selmi and D. Esseni. Programme and retention
characteristics of SONOS memory arrayswith layered tunnel barrier
Semicond. Sci. Technol. 23. 2008
[11] M. Sze, and K. Kwok. Physics of semiconductor devices WileyInterscience 3rd. ed. 2007
0.05
0.00
-11
-10
10
10
-9
10
-8
-7
10
10
-6
10
-5
10
-4
-3
10
10
-2
10
-1
10
-1
10
10
0.60
0.55
erase
VG=2V
(b)
0.50
tunneling oxide
2nm
1.45 nm
1.2nm
0.45
0.40
VFB (V)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
Fig. 8. (a) Writing time characteristics and (b) erase time characteristics of
MOHOS-type memories with different tunneling oxide thicknesses after
integrating gate current density with programming time.
IV. Conclusions
A MOHOS-type Flash memory was proposed by deposition
of np-HfO2 embedded in a SiO2 matrix as a charge-trapping layer.
The electron trapping at np-HfO2 causes a flatband voltage shift
which is measured in order to extract the most important
performance characteristics of memory devices. The FN tunneling
mechanism is used as an efficient mechanism of electron injection to
charge-trapping layer. Also it was found that after erase operation not
all charge is released from the charge trapping layer due to deep trap
levels in np-HfO2. The tunneling oxide thickness is an important
parameter in devices performance. A thin oxide thickness increases
the writing/erase time but decreases the charge retention time.
Therefore, by considering a high retention time of about 80% for the
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I.
INTRODUCCIN
II.
Este trabajo ha sido financiado por los proyectos: MOBY-DIC FP7-IST248858 (www.mobydic-project.eu) de la Comunidad Econmica Europea,
TEC2008-04920 del Ministerio de Ciencia e Innovacin de Espaa y P08TIC-03674 de la Junta de Andaluca (con soporte FEDER).
30
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( )
31
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III.
A. Algoritmo genrico
Este tipo de algoritmos comienzan realizando un primer
barrido de la imagen, en el que se asignan etiquetas temporales
a los pxeles y se identifican las posibles equivalencias que
puedan producirse. La expresin matemtica que permite
describir la etiqueta temporal asignada al pxel (x,y) durante el
primer barrido es la siguiente:
(
{(
(
} (
)
)
[{ (
}]
)( )
}])
[{ ( ) ( )
}]
(4)
)
(
( (
))
(5)
)(
donde:
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A. Imgenes
Para evaluar la bondad y aplicabilidad del mtodo
propuesto se han realizado una serie de simulaciones con
varios grupos de imgenes reales utilizando las herramientas
del entorno Matlab. Las imgenes, tomadas de las bases de
datos de la USC-SIPI [21] y el Berkeley Computer Vision
Group [22], han sido seleccionadas intentando abarcar el
mayor rango posible en cuanto a temas, para comprobar la
aplicabilidad del mismo en distintos campos: medioambiente
(animales, paisajes), seguridad (personas), medicina (clulas),
etc.), y dificultad, con el fin de verificar la calidad del
etiquetado (para ello se han seleccionado imgenes de texturas
e imgenes areas).
ALGORITMO PROPUESTO
[{ ( (
([{ (
)(
)) (
}])
)
[{ ( ( )) (
)
)
}]
}]
(7)
B. Medidas realizadas
La calidad del algoritmo se midi mediante el clculo de
los siguientes valores:
C. Resultados obtenidos
Los resultados obtenidos, resumidos en la Tabla I, reflejan
que el porcentaje de imgenes en las cuales se cometi errores
en el etiquetado descendi de un 55-75% con el 'Algoritmo 1'
a un 6-10% con el algoritmo propuesto. Este dato, unido a que
el error medio que se comete es en el peor de los casos de 14
etiquetas en el algoritmo propuesto frente a 120 etiquetas en el
'Algoritmo 1', y a que el error relativo mximo cometido con
el algoritmo propuesto es de 1,07% (en imgenes de texturas),
permite afirmar que la calidad del algoritmo propuesto es
buena y mejor que la de un algoritmo tpico de este tipo.
Adems, hay que tener en cuenta que las imgenes con las que
33
ISSN 977-2177-128009
N(p)
Imgenes
Texturas
Areas
Miscelneas
Miscelaneas con un
preprocesamiento de
deteccin de bordes
Texturas
Areas
Miscelneas
Miscelaneas con un
preprocesamiento de
deteccin de bordes
VI.
Algoritmo 1
Algoritmo
propuesto
ErrorA
ErrorR
ErrorA
ErrorR
119,22
76,11
19,33
8,89
3.46
2.83
13,88
11,55
3,6
1,07
0,5
0,3
0,9
7,4
85,22
88
25,8
13,84
7,99
6.34
1,55
1,88
0,73
0,18
0,14
0,2
6,74
47,83
B. Implementacin
Se han realizado dos implementaciones sobre FPGA del
algoritmo propuesto, considerando, en ambos casos, la
conectividad en un entorno de 4 vecinos. Una de ellas permite
reducir el nmero de recursos usados en el dispositivo a costa
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BIBLIOGRAFA
[1]
[2]
[3]
[4]
[5]
C. Resultados de la implementacin
Tras sintetizar los diseos para una placa SPARTAN 3A
DSP (XC3SD1800A), se comprueba que la mayor imagen que
es posible sintetizar sin el uso de memoria externa
considerando una tabla de equivalencias mxima es de
330x240 en el caso del diseo de un ciclo y de 400x370 en el
caso del diseo de dos ciclos. No obstante, en la mayora de
los casos, el nmero de etiquetas asignadas en la primera
pasada no excede del 20% de las que se pueden asignar. Si se
considerase una tabla de equivalencias con el 30% del tamao
mximo, sera posible sintetizar imgenes con resoluciones de
hasta 500x460 y 670x600 respectivamente. En ambos casos, el
recurso que limita el tamao mximo de imagen con el cual es
posible trabajar son los bloques de memoria RAM de doble
puerto de 16 kb de datos, ya que los porcentajes de utilizacin
del resto de recursos son muy bajos (ej. slo se usan un 3% de
los ''Slice Flip Flops'' y ''4 inputs LUTs'' disponibles en la
placa). La frecuencia mxima de reloj obtenida es
aproximadamente de 32 MHz. Con estos datos, se estima que
con el primer diseo se puede trabajar en tiempo real con el
tamao de imagen mximo sintetizable (es decir, si nos
ajustamos a los estndares de vdeo existentes, es posible
trabajar con un estndar WCIF) siendo la RAM disponible el
recurso que impide trabajar con dimensiones mayores. El
segundo diseo, por el contrario, est limitado por la velocidad
a la cual es posible trabajar. Con l, se puede trabajar en
tiempo real con resoluciones de hasta 640x480 (VGA).
VII.
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
CONCLUSIONES
[18]
[19]
[20]
[21]
[22]
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Tatiana Markina
I.
INTRODUCTION
s +1
(1 u ) g
j
= X
+ ts H
( X ) = 0,
j = 1, 2 , . . . , M
(2)
where X RN , X = ( X, X) ,
(1)
36
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F ( X ,U ) = C ( X ) + ( X ,U )
(3)
( X ,U ) =
g 2j ( X )
(4)
j =1
dxi
= f i ( X ,U ) ,
dt
i = 1,2,...,N
V ( X , U ) = [F ( X , U
F ( X , U )
V ( X , U ) =
x i
i
F (X ,U ),
xi
i = 1,2 , ... , K
(7)
2
(8)
(5)
fi (X ,U ) =
)]r
(6)
(1 uiK ) { xs + ( X )} (6')
f i ( X ,U ) = uiK
F( X ,U ) +
i
i
ts
xi
i = K + 1, K + 2 , ... , N ,
Lyapunov function: W = V/ V .
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N Control
vector
1
2
3
4
5
6
7
8
Iterations
number
( 000)
( 001)
( 010)
( 011)
( 100)
( 101)
( 110)
( 111)
Total
design
time (sec)
10.61
198989
10.71
586750
5.87
272611
6.11
541099
2.64
118901
4.72
278663
3.35
198162
2.14
274751
0
0
0
0
0
0
0
0
Figure 2. Behavior of the functions W(t) and S(t) for all strategies of
structural basis during the design process.
other time interval. We can assume that the area under the
curve -W(t) may be the best way to predict the CPU time, as
important to the behavior of this function at a certain time
range, rather than a specific point. In this case, it makes
sense to introduce a new function defined by the integral of
the function W(t), which will serve as a criterion for
analyzing of dynamic properties for a Lyapunov function.
V (t )
dV 1
dV
V(t )
dt =
= ln
dt V
V
V(0)
V ( 0)
0
t
(9)
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x12 = y1,
x22 = y2 , x32 = y3 , x42 = y4 , x52 = y5 , x62 = y6 , x72 = y7 ,
x8 = V1 , x9 = V2 , x10 = V3 , x11 = V4 , x12 = V5 , x13 = V6 ,
x14 = V7 . The model of this network (2) includes seven
The vector X
V. CONCLUSION
The problem of the construction of minimal-time
algorithm of designing can be solved adequately on the basis
of the control theory. The designing process in this case is
formulated as the controllable dynamic system. The
Lyapunov function and its time derivative include the
sufficient information to select more perspective design
strategies. The special function S(t) has been proposed to
predict the better designing strategies with a minimal
designing time. These functions can be used as the principal
tool to the prediction of the optimal in time algorithm of
designing.
REFERENCES
[1]
N Control
vector
1
2
3
4
5
6
7
8
9
10
( 000 000 0)
( 001 010 1)
( 011 100 0)
( 101 010 1)
( 101 110 1)
( 101 111 1)
( 111 011 1)
( 111 110 0)
( 111 111 0)
( 111 111 1)
Iterations
number
2354289
110889
1075433
102510
107541
38751
43387
185085
147094
52651
Total
design
time (sec)
420.181
117.150
272.014
50.211
43.440
12.753
13.891
110.624
66.131
4.782
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MUX
Sync
Sync
INTRODUCTION
SAR
Sync
I.
SAR
SAR
Sync
D_out
Sync
D_in
Sync
Interface PC-Memory
Clk
Electrodes
Sync
PC
Sync
SAR
III.
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MUX
Electrode
Sync-Master
D - InOut
En
D - InOut
RUp
En
RUp
D
Master/Slave
Vector_In
IV.
Request_Data
Send_Data
Serial/Parellel
Sync
SYNCHRONIZATION
Clk_16x
Reset
Vector_Out
Clk_Sync
Start Bit
D
Samples
Start Bit
Verification
Data Sampling
Clk_16x
Clk_sync
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Request Data
Clk_Sync
Wait Start
D_Sync
Stop/Reset
Read_Write
Data
Vector_In
Vector_Out
ACKNOWLEDGMENT
This work was supported by CAPES, FAPEMIG and
CNPq.
D InOut
VI.
Send Data
Next are placed the data bits and last bit indicating stop bit
or reset signal to electrode, meaning that the electrode must
sample a new data. The transmitted bits form a frame_byte.
V.
Request Data
REFERENCES
SYNCHRONIZING SAMPLES
[1]
[2]
[3]
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I.
O BJETIVOS
DEL PROYECTO
43
DE SELECCIN
C RITERIOS
III-C.
III-A.
III-B.
I NTRODUCCIN
III.
Grid Array.
ISSN 977-2177-128009
IV.
C IRCUITO
DESARROLLADO
Circuito Impreso
Caractersticas generales
44
FABRICACIN
DE LOS PROTOTIPOS
ISSN 977-2177-128009
45
VII.
R ESULTADOS Y
CONCLUSIONES
ISSN 977-2177-128009
AGRADECIMIENTOS
46
R EFERENCIAS
[1] INTI Electrnica e Informtica et al., Proyecto FPGA Libre, http:
//fpgalibre.sourceforge.net/.
[2] S. E. Tropea, D. J. Brengi, and J. P. D. Borgna, FPGAlibre: Herramientas de software libre para diseo con FPGAs, in FPGA Based Systems.
Mar del Plata: Surlabs Project, II SPL, 2006, pp. 173180.
[3] I. Gonzlez, J. Gonzlez, and F. Gmez-Arribas, "hardware libre:
clasificacin y desarrollo de hardware reconfigurable en entornos
gnu/linux",
http://www.iearobotics.com/personal/juan/publicaciones/
art4/hardware-libre.pdf.
[4] Opencollector.org, "writings on open source hardware", http://www.
opencollector.org/Whyfree/.
[5] Aeroflex Gaisler. LEON processor & Grlib IP-core library. [Online].
Available: http://www.gaisler.com/
[6] J. Gaisler, An open-source VHDL IP library with plug&play configuration, in IFIP Congress Topical Sessions, R. Jacquart, Ed. Kluwer,
2004, pp. 711718.
[7] GNU project, http://www.gnu.org/, Jun. 2010.
[8] A. Muoz, E. Ostua, M. J. Bellido, A. Millan, J. Juan, and D. Guerrero,
Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution, in 2008 IEEE International
Symposium on Industrial Electronics (ISIE). IEEE, 2008, pp. 1727
1732.
[9] D. J. Brengi, S. E. Tropea, and J. P. D. Borgna, Tarjeta de diseo
abierto para desarrollo y educacin, in 2007 3rd Southern Conference
on Programmable Logic Designer Forum Proceedings, Mar del Plata,
2007, pp. 5760.
[10] J.-P. Charras, "Kicad: GPL PCB Suite", http://www.lis.inpg.fr/realise_
au_lis/kicad.
[11] Free Software Foundation, Inc., "The Free Software Definition", http:
//www.gnu.org/philosophy/free-sw.html.
[12] C. Huy and D. Brengi, Mdulo de alimentacin para placas
con dispositivos FPGA, in Congreso de Microelectrnica Aplicada,
uEA2010. San Justo, Buenos Aires: Universidad Nacional de La
Matanza, 2010, p. 21. [Online]. Available: http://utic.inti.gob.ar/
publicaciones/uEA2010/uea2010_submission_49.pdf
[13] D. Brengi, S. Tropea, M. P. Visentin, and C. Huy, Soldadura,
inspeccin y verificacin, en laboratorio, de un prototipo con chip
BGA, in II Congreso de Microelectrnica Aplicada, uEA2011: Libro
de memorias. La Plata, Buenos Aires: Universidad Nacional de
La Plata, 2011, pp. 95100. [Online]. Available: http://utic.inti.gob.ar/
publicaciones/uEA2011/bgaS3.pdf
[14] (2003, Oct.) Openwince GNU JTAG Tools. [Online]. Available:
http://openwince.sourceforge.net/jtag/
[15] Free Software Foundation, Inc., GNU General Public License, http:
//www.gnu.org/copyleft/gpl.html.
ISSN 977-2177-128009
Grupo de Bionanoelectrnica
Escuela EIEE, Universidad del Valle
Cali, Colombia
{vlatruo, jvelasco}@univalle.edu.co
I.
INTRODUCCION
II.
Multiplicador Serial
La multiplicacin secuencial es descrita por la ecuacin 1.
Se tiene que C =
m 1
c
i =0
ecuacin (1).
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ISSN 977-2177-128009
m 1 m 1
cs = ai + s b j + s (ij0 ) = ai + s b j + s ij = ai + s ij b j + s (1)
i, j
i, j
j =0 i =0
Se define un elemento
m1
m1
x s +t ,mt = ai + s +t i , t bs = ai + s i t , t bs = ai + s it bs (7)
i
=
0
i
=
0
i
=
0
xst , para 0 s y t m 1 , en
GF (2m ) como
m1
xst = ai+ s it bt + s ,
i =0
X t de X es
Por lo tanto
donde
(x
0t
(x
0t
(2)
(3)
m1
i =0
columna
TABLA I.
x
t =0
st
ENTRADAS: A, B
(4)
m1
A = ai i
i =0
m1
B = bi i
i =0
Para t = 0 hasta m 1
(8)
Fin Para.
Para todo 0 s m 1 .
0 i m 1 , donde AB = ci i .
i =0
Yt ,
Ds +2 = Ds +1 = Ds +1 + ys ,s +1
son
calculados
simultneamente para todo 0 s m 1 , por ejemplo
Xt
Xt
(2 )
D0 , D1 ,..., Dm1 0
X como sigue:
( )
GF 2m
ALGORITMO DE MULTIPLICACION
SALIDAS: C GF
= cs .
m1
i + s it
X t y X mt .
......
......
y la s + t-sima entrada de
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ISSN 977-2177-128009
(9)
Ds se
todos los
Ds + 2
ys1,s y yss ,
m+
m 1
(k 1) XORs [9].
2
III.
(11)
A.
calcular
m1
m1
i =0
ms
m 1
(k 1) XORs.
2
'
Cuando s = 0, entonces el nmero de entradas no cero de
i 0 , para 0 i m 1 , es uno porque 0 = 2 = 1.
Ds +1
}
m 1
Ds = yss + ys ,s+1 + y s ,s+2 + ... + ys ,s+i = y s ,s+i = cs (10)
1424
3
i =0
ai s y bi s de
C = ci i
A = ai i
multiplicacin
m1
Por ejemplo si
de
i =o
i =o
B = bi i , para 0 i 4, son
i =o
c0 = ( a3 + a 4 ) b2 + a1b0 + ( a1 + a 2 ) b3 + ( a 0 + a3 ) b1 + ( a 2 + a 4 ) b4
(13)
( )
GF 2 m para m = 5 . Las
Figuras 1 y 2 muestran el arreglo y la celda Ri del
m1
multiplicador diseado.
49
ISSN 977-2177-128009
163
1A02580C3AE101408D8A1829E72D1721968282A8B
3404B01875C202811B143053CE5A2E432D0505516
398C19165805858E6EA9764A669EC0A1B598E8370
68096030EB840502362860A79CB45C865A0A0AA2C
GF (25 )
para m = 5.
Figura 2.
Bloque de la celda
Ri
(b) Resultado de la simulacin para A*A2 = A3
B.
IV.
50
ISSN 977-2177-128009
rea (ALUTs-Registros)
600
500
400
300
ALUTs
200
Registros
100
AGRADECIMIENTOS
0
5
11
23
69
Campo Binario m GF(2^m)
163
REFERENCIAS
[1]
V.
CONCLUSIONES.
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I.
II.
E x E0 x exp ikx ,
(1)
INTRODUCTION
MATHEMATICAL FORMULATION
x m / 2
x
E0 x exp
(2)
(3)
E1 E1x iE1 y ,
E2 E2 x iE2 y ,
(4)
52
I
,
A
(7)
ISSN 977-2177-128009
2 j 1
n0
2
2 D
E1 E 2 E 3 E 4 ,
4 2 D
A E1 E 2 E 3 E 4
n 0
2
A B E1 E 2 E 3 E 4 ,
...,
(10)
2
n 4
(15)
A B 0 E j ,
2 j 1
n0 3 4
4 2 z
1
A
E j E k* ...
n0
2 j 1 k 2
n 3 4
A B 0 E j E k* , (16)
2 j 1 k 2
(9)
III.
is the
with
(12)
x, z K .
13
x 10
8
Radiation pressure [Pa]
0
90
2
60
1.5
1
30
I z ,
(13)
E40 J 2 1 exp i 0
0.5
Angle of polarization [DEG]
calculated are:
I z ,
(14)
E30 J 2 1 exp i 0
(8)
E E E ,
Two induced gratings, and
53
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Intensity [MW/m2]
Intensity [MW/m2]
IV.
1
0.5
0
20
10
-10
-20
-20
-10
10
ACKNOWLEDGMENT
20
1
0.5
0
20
CONCLUSION
REFERENCES
[1]
10
-10
-20
-20
-10
10
20
Gain
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
Beam power [Watts]
54
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I. I NTRODUCTION
Rapid system prototyping has evolved into a complex multidisciplinary area involving many layers of system design. Not
only hardware and software skills, but also appropriate system
specification and modeling are required to implement a working prototype which satisfies original design requirements.
Embedded systems are currently used in a large variety of
industries confirming their great importance. As system complexity increases, design tools and debugging techniques must
evolve to keep up with strict time to market and performance
needs [1]. This paper describes the rapid system prototyping
course taught at the University of South Florida, and the
computer logic design class at the University of New Mexico.
It is designed with the intention of providing the student
with theoretic concepts as well as practical system design
and implementation. From beginning to end the student is
encouraged to understand the topics in terms of their location
within the whole system to help clarify their specific functions
and interactions. Many evaluation boards are available from
different vendors and with different set of peripherals, some
of them even tailored to specific markets (what Xilinx refers
to as targeted platforms). We selected Xilinxs Spartan-3E
Starter Kit due to the wide variety of included peripherals such
as ROM, RAM, LCD, LEDs, VGA, and UART which give
the student and the professor great flexibility for the project
assignments and examples. FPGA-based design on Xilinxs
Spartan-3E Starter Kit, shown in Fig. 1, using Xilinx ISE
design tools provides the flexibility to present the student
with many capabilities in terms of design entry, simulation,
synthesis, and hardware programming (Fig. 2). The paper is
organized as follows. In section II, the class structure and
assignments are described in detail. Hardware and software
development tools are presented in section III. Section IV
describes some of the projects that have been implemented
by students in the past. Finally, conclusions and future work
are included in section V.
Fig. 1.
55
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Fig. 2.
Fig. 3.
56
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Fig. 4.
Fig. 5.
Fig. 6.
57
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Fig. 9.
Fig. 7.
Fig. 10.
Fig. 8.
V. C ONCLUSIONS
The rapid system prototyping class has been very successful at providing students with understanding of FPGA-based
system design. From open discussions with the students, class
structure and resources have been adapted over the years to
improve the interaction and learning experience. Recommendations to fellow students to take the class from previous
students confirm satisfaction and interest for the course.
A mix of theoretical knowledge of concepts and practical
implementation is fundamental to build a complete and clear
system perspective.
The most difficult part of the course is the evaluation. There
are many concepts involved from cross-disciplinary areas that
it is complicated to fairly judge student concepts assimilation.
58
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59
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II.
I.
Bajo
la regin de
(1)
Donde es el factor de la corriente en inversin dbil, es es
el factor de no idealidad,
es el voltaje de compuerta a
fuente y el voltaje trmico. Esta corriente se genera cuando
es menor al voltaje de umbral.
consumo,
Despejando
INTRODUCIN
(2)
"#$
%&
(3)
Donde '.
60
'$ ! '-
ISSN 977-2177-128009
(4)
(4a)
Simplificando
?+
: CD >
ln 4 5
: A> !
?,
: B>
(10)
Despejando
lo siguiente.
IJ
IJ
678
>
(11)
G+
G
"
G,
G
(12)
H: >
G,
B G
: >
CD
(5)
"?S
?+
R?
De la misma forma:
?S O"T$Q
?,
(13)
"
O"T$Q
?S
?S O"T$Q
(14)
$
O"T$Q
(15)
De lo anterior obtenemos:
IJ
B
OBU+Q
"
+
OBU+Q
(16)
KL O ! 1Q
(17)
IJ
1@ !
?,
1"
?+
: A> ! ?,
(6)
: B>
?+
: A> !
III.
(8)
?,
: B>F
(18)
Simulacin
: CD >
"
(7)
: CD >
B
OBU+Q
+
OBU+Q
(9)
61
ISSN 977-2177-128009
IV.
M2
M3
M4
1.2um
1.2um
1.2um
2.1um
15um
15um
15um
15um
LAYOUT
Tabla 1
62
ISSN 977-2177-128009
VI.
V.
MEDICIONES.
VII.
63
REFERENCIAS
[1]
[2]
[3]
Weihsing Liu, Wei-Lung Mao, Jyh Sheen, A Low-power and Lowvoltage Cube-law Circuit, IEEE Conference on Electron Devices and
Solid-State Circuits, Dec 2007. EDSSC 2007, Pags 829-832.
[4]
[5]
[6]
[7]
[8]
[9]
CONCLUSIONES
ISSN 977-2177-128009
nucleo
IP (Intelectual Property) para classificaca o de modulaca o
I. I NTRODUC AO
As tecnicas de radio cognitivo (RC) vem sendo bastante
pesquisadas devido sua capacidade de aumentar a eficacia dos
sistemas de comunicaca o. A classificaca o de modulaca o [1] e
um dos modulos da etapa de sensoriamento espectral em RC
que mais demanda esforco computacional.
Na tarefa de classificaca o de modulaca o, o objetivo e
determinar que tipos de sinais estao ocupando o espectro.
Para isso, em etapa previa, definem-se as N classes e o
classificador convencional ira sempre decidir por uma dentre
as N classes. A definica o das classes pode levar em conta o
tipo de modulaca o, forma de onda, largura de faixa, frequencia
da portadora, dentre outros aspectos [2].
O processo de classificaca o de modulaca o e constitudo por
dois blocos: um bloco de extraca o de parametros e um de
classificaca o. O primeiro bloco extrai a informaca o relevante
para a decisao, transformando os sinais recebidos (apos passar
pelo canal) em um conjunto chamado de parametros ou
64
ISSN 977-2177-128009
16QAM, SNR = dB
8PSK, SNR = dB
0
100
200
300
Indice das amostras
400
500
4
3
2
Magnitude / Fase (rad)
1
0
1
2
3
4
16QAM, SNR = 15 dB
8PSK, SNR = 15 dB
0
100
65
400
500
200
300
Indice das amostras
1
n
c(f (xi ), yi )
(1)
i=1
PROGRAM AVEL
Esta seca o apresenta o desenvolvimento de um IP
core consistindo de uma SVM para funcionar como um
ISSN 977-2177-128009
f (x) =
wi xi + b.
(2)
i=1
66
B
msb
B
lsb
B-1
msb
B-1
lsb
B-1
w
D
2
msb
2
lsb
1
msb
1
lsb
1
w
D
B
D
2
D
B
D-1
B-1
w
D-1
2
D-1
1
w
D-1
D-1
B
4
B-1
w
4
2
4
B
2
B
1
B-1
w
3
B-1
2
B-1
1
2
3
2
2
2
1
1
2
1
1
B
3
1
w
4
1
w
3
ctrl
Fig. 3.
ISSN 977-2177-128009
1
D
1
b
1
D-1
1
1
B-1
D
D-1
1
D
1
D-1
1
1
B-1
B-1
D-1
B-1
D
D-1
B-1
D-1
B-1
1
B
D
B-1
1
B-1
B
D-1
B
D
B
1
D-1
B
D-1
B
1
contagem
3
4
cy
c y-1
c1
max
classe
Fig. 4.
Memria
wB
B
2
B
1
B-1
2
B-1
1
w2
w2
w 2D/2-1
w2
2
2
2
1
w1
w1
D-1
w 1D/2+1
w1
1
2
1
1
2
D-1
x 2D/2+1
x2
x2
x2
1
D
1
D-1
x 1D/2+1
x1
D/2
x1
2
x1
B-1
B-1
D-1
x
x
B-1
w D/2
x2
D/2
D/2
D/2
i1
i2
ctrl
wB
wB
clk
Lgica de
Acesso
Memria
w1
w1
x2
x2
x1
x1
D/2
w D/2+1
wB
w D-1
w BD/2+1
D-1
wD
B-1
Fig. 5.
wB
67
Fig. 6.
C. Funcionamento
Para compreender esta arquitetura, e necessario lembrar que
para realizar a classificaca o multiclasses, os coeficientes dos
B classificadores binarios SVM deve ser inserido, bem como
um conjunto de teste, o qual precisa ser tratado antes de ser
aplicado aos classificadores binarios. Todas estas informaco es
chegam ate o bloco principal, representado pela Fig. 5, atraves
dos sinais i1 e i2. Estes sinais chegam ao bloco de forma serial
e a uma taxa definida por ckd.
O sinal ctl e responsavel por informar qual o destino das
informaco es contidas em i1 e i2. Quando o valor de ctl e zero,
indica ao bloco que as entradas i1 e i2 apresentam um novo
smbolo de teste e que devera ser direcionado para um dos
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68
V. R ESULTADOS
A arquitetura proposta foi inicialmente implementada e
testada no software Matlab e para auxiliar no desenvolvimento
e treino do classificador foi utilizado o software de mineraca o
de dados WEKA (Waikato Environment for Knowledge
Analysis) [15], o qual e uma ferramenta livre que reune
uma serie de classificadores e e bastante utilizada no meio
academico para comparaca o de desempenho em problemas de
classificaca o.
As modulaco es utilizadas foram BPSK, 4-PAM, 16-QAM e
8-PSK. Considerando rudo AWGN (Additive White Gaussian
Noise), de acordo com os trabalhos de classificaca o de
ISSN 977-2177-128009
U TILIZAC AO
SI NTESE DO CLASSIFICADOR CSS-SVM UTILIZANDO Q UARTUS II.
Recurso
Elementos L
ogico (Total)
Func
oes Combinacionais
Registradores L
ogicos Dedicados
Total Registradores
Total de bits de mem
oria
Multiplicadores Embarcados
Tempo p/ 200 classificac
oes
Consumo
1.824 (10%)
1.586 ( 8%)
704 ( 4%)
704
64.000 (27%)
24 (46%)
138 ms
69
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I. INTRODUCTION
Currently, the advancement of microelectronics leads to
the designing of increasingly complex digital systems. Most of
these systems are battery powered and focus on different
applications such as wireless, laptops, aerospace (satellite and
missile), aviation, automotive and medical. Being battery
powered it is desirable that these devices have long useful life,
making power dissipation to be an important parameter in the
design of these systems [1,2]. In this context, the synthesis of
synchronous finite state machines (FSM) has an important role
in the design of digital circuits powered by batteries.
Many digital circuits are described by an architecture
composed by a network of controllers with data paths and/or
processors [2]. The synchronous controllers of these devices are
often described as FSM. They can always be specified by a
State Transition Graph (STG). Generally, these circuits are
implemented in the VLSI (Very Large Scale Integration)
technology. Digital circuits are implemented with CMOS
components. In this technology the major part of the power
dissipation occurs during switching (dynamic power),
consisting mainly of two parts: the combinatorial part, related
to the excitation and output equations, and the sequential part,
related to the flip-flops (FFs).
In digital circuits, the sequential part is the largest
contributor to the power consumption. Recent studies indicate
that the clock of these circuits consume a large percentage of
the total power (15% to 45%) [1]. This consumption is related
to the buffers, clock distribution network and registers.
Techniques for reducing dynamic power can be applied at
different levels of digital design [1]. Currently, the dynamic
Playa del Carmen, Mexico, February 29-March 2, 2012
70
(1)
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71
C. Asynchronous control
An asynchronous control (AC) is a Mealy asynchronous
FSM that serves to activate and deactivate the N existing subFSMs and operates in generalized fundamental mode [24]. It is
described in the flexible extended burst-mode specification
(FXBM), which allows multiple input changes [19].
AC_FXBM is described from the N coded STGs where the
state transitions (divided arcs) that cross the sub-FSM are
declared. The AC specification is obtained just in these
transitions. When the division is performed in an unconditional
state transition, the FXBM specification uses only the involved
state variable. This variable, in FXBM, is seen as a sensitive
signal to the transition and has a monotonic behavior.
The example of Fig. 3 shows the division of an
unconditional state transition B G. Fig. 3a shows its
description in FXBM. When the division is performed in a
conditional cross-state transition, the FXBM specification uses
both the state variables and the input signals. The input signals
do not have a monotonic behaviour (allow glitches) and can be
sensitive to the level (symbol <signal>) and sensitive to the
transition [23]. The example of Fig. 7 shows the conditional
state E, with a cross-state transition E C. Fig. 3b shows its
description in FXBM. There are conditional states where the
transitions cross to another FSM, for example, the state D
(D E and D G), seen in Fig. 7. So, in this specification,
FXBM it is treated as unconditional.
D. Synthesis procedure
The method of synthesis used starts from the STG
specification that describe the monolithic FSM and is
implemented in the architecture presented in Fig.1. The steps
are related to partitioning and synthesis of the sub-FSMs [18]:
a) state minimization of the STG; b) partitioning in N subFSMs; c) state assignment of the N sub-FSMs on the one-hot
code; d) logic minimization of the N sub-FSMs. The last step is
related exclusively with the synthesis of the synchronous
communication control. Specify and synthesize through the
operation table the synchronous control (signals Zs) for STGs
minimized and encoded of the N sub-FSMs.
III. STUDY OF CASE
In order to show the efficiency of the proposed method, it
is presented a study of case where a detector of two sequences
is analyzed (0101 and 1010). Despite being small sequences,
this is an excellent example of the method application because
the same procedures can be used for larger sequences as well.
Fig. 4 shows the minimized Moore STG of the detector (step
1). Step 2 performs partitioning.
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01000
10000
E/11
F/00
00100
X
00001
X
G/00
H/10
Q4
Y Z
I/11
0 0
0
00 00
0 1
1 1
00
01
00010
X
00
01
11 11
10 00
00
01
1 0
0
10
10
4
11
3
11
10
10
00
72
ISSN 977-2177-128009
[2]
[3]
[4]
[5]
[6]
[7]
Figure 12. Logic circuit gC asynchronous control: a) Y; b) Z.
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
Figure 13. Results: asynchronous controls.
[18]
73
[19]
[20]
[21]
[22]
[23]
[24]
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I.
INTRODUCTION
74
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D a ta _ in
C o n tr o l
D a ta _ o u t
R i
II.
A o
F u n c t io n a l
B lo c k
R o
A i
III.
75
ISSN 977-2177-128009
/ x y
c
a
A
a
/ x
/ x y
/ x y
y
c / x
a / x y
C
a
/ x y
D
c / x
/ x y
/ x
76
ISSN 977-2177-128009
D a te
Mux 2x1
S E T
C
C LR
D a te
S ET
Q
C LR
C LK
CLK
(a )
(b )
D a te
SE T
C
CLR
(c )
IV.
V.
CASY OF STUDY
77
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8
X 1
Y 1
8
R e s
R i
G C D
R o
A o
A i
VI.
78
ISSN 977-2177-128009
[4]
[12] W. Hardt, et. al., Architecture Level Optimization for Asynchronous IPs,
Proc. 13th Annual IEEE Int. Conf. ASIC/SOC, pp.158-162, 2000.
VII. CONCLUSIONS
In this paper we show that synchronous and asynchronous
paradigms may be used together in the design of an
asynchronous system. The decomposition style is familiar to
synchronous paradigm and can be used in the high-performance
asynchronous design. We proposed an architecture that
communicates effectively with the external environment through
the protocol of two phases. We also propose an algorithm to
convert a STG of a synchronous FSM for XBM_STG. For
future work, develop a tool for the methodology proposed.
REFERENCES
[1]
[2]
[3]
79
ISSN 977-2177-128009
Resumo Neste trabalho uma ferramenta de dimensionamento de portas e de transistores baseada em Programaca o
Geometrica (PG) e apresentada, onde o atraso e calculado usando
o modelo de Elmore. A otimizaca o pode ser feita com o objetivo
de minimizar atraso e/ou a rea (potencia). Uma comparaca o entre
o dimensionamento de portas e de transistores e apresentada
para analisar o custo-benefcio entre o tempo de execuca o e
o atraso mnimo alcancado. Para qualificar nossa abordagem,
os circuitos de teste do ISCAS85 foram mapeados para uma
tecnologia de 45nm. Apos foram executados os dimensionamentos de portas e de transistores minimizando o atraso. O
dimensionamento de portas comparado aos tamanhos de celulas
encontradas numa biblioteca comercial reduziu o atraso em 21%,
em media, considerando os mesmos valores de a rea e potencia
do dimensionamento fornecido pela biblioteca de celulas. Apos
foi feito o dimensionamento de transistores que reduziu o atraso
em 40,4% e a potencia em 2,9%, em media, comparado com
o dimensionamento de portas. Porem, o dimensionamento de
transistores possui um tempo de execuca o maior, usando um
numero
de variaveis duas vezes maior que o dimensionamento
de portas. O dimensionamento de portas otimizando a rea foi
executado considerando como restrica o de atraso o mesmo
valor encontrado na minimizaca o de atraso, possibilitando uma
reduca o, em media, de 28,2% em a rea e 27,3% em consumo de
potencia.
I. I NTRODUC AO
Um aumento na performance do circuito pode ser alcancada
atraves do dimensionamento de transistores, visando a reduca o
do pior caso de atraso. Sendo que, um transistor maior tem
uma capacidade aumentada para carregar (descarregar) uma
carga, reduzindo o tempo requerido para mudar um sinal
de 0 (1) para 1 (0). Entretanto, um transistor maior impoe
uma capacitancia maior para ser carregada (descarregada) pela
porta que a esta alimentando. Portanto, escolher o correto
dimensionamento para o transistor nao e um problema trivial.
O dimensionamento de portas e um caso especial do dimensionamento de transistores onde os transistores de uma
mesma porta sao sujeitos a um mesmo fator de escala. E
mais restritivo que o dimensionamento de transistores, mas
o numero reduzido de variaveis leva a um tempo de execuca o
menor.
Ha um fator de escala o timo para cada porta, considerando
que aumentando o tamanho da porta e, consequentemente, dos
transistores, aumenta sua habilidade para carregar uma carga,
reduzindo o tempo requerido para a porta chavear seu sinal.
Contudo, aumentando o tamanho da porta:
80
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81
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P OSINOMIAL E P ROGRAMAC AO
III. F UNC AO
G EOM E TRICA (PG)
O termo Programa Geometrico foi introduzido em 1967 [1]
e e usado para definir um tipo de problema de otimizaca o
matematica onde a funca o objetivo deve ser uma funca o
posinomial.
Para entender o que e uma funca o posinomial, primeiro
e definido monomio, conforme mostra a expressao 1, onde
o coeficiente c pode ser qualquer numero positivo, e os
expoentes podem ser quaisquer numeros reais.
minimizar
Area
sujeito a Xmin Xi Xmax
(5)
max
Cin Cin
D Dmax
V. D ESENVOLVIMENTO DA F ERRAMENTA
Pode ser dito que o problema de dimensionamento de portas
e o problema de escolher os fatores de escala a fim de
encontrar o mnimo atraso sujeito a limites na a rea total e
outras restrico es ou encontrar a a rea mnima sujeita a limites
do atraso maximo.
A ferramenta de dimensionamento de portas e de transistores usando PG foi desenvolvida da seguinte forma:
1) As portas logicas sao modeladas usando o modelo RC
a nvel de chaveamento [3].
2) No dimensionamento de transistores, para cada transistor
e definida uma variavel que representa a largura do
transistor. Para o dimensionamento de portas, e usado
um fator de escala para cada porta logica que multiplica
a largura dos transistores que fazem parte da porta. Estas
sao as variaveis de otimizaca o do problema e elas afetam
a a rea, o consumo de potencia e a velocidade do circuito.
3) Os valores de capacitancia e resistencia sao obtidos
por simulaca o SPICE considerando transistores PMOS
e NMOS. As capacitancias do transistores sao proporcionais a largura do mesmo e a resistencia de conduca o
e aproximadamente inversamente proporcional a largura
do transistor.
4) O atraso e calculado pelo modelo de Elmore, conforme
ja citado. O atraso do circuito e o maximo atraso entre
todos os caminhos do circuito.
5) A a rea e a soma da largura Wi de cada transistor i que
compoe o circuito, onde n e o numero de transistores
do circuito:
n
an
1 a2
f (x) = (cx1a1 xa2 2 ...xann ) = c xa
1 x2 ...xn
B. Minimizar Area
(Potencia) Sujeito a um Atraso Maximo
Para este otimizaca o, e feita uma alteraca o, onde a funca o
objetivo torna-se a a rea e o atraso torna-se uma restrica o. A
formulaca o e a seguinte:
(1)
f (x) =
(2)
k=1
Atotal =
Wi
i=1
82
ISSN 977-2177-128009
(6)
Cini ) V dd2 f
P = (Cload +
(7)
i=1
83
ISSN 977-2177-128009
C432
C499
C1908
C880
apex1
apex2
apex3
apex5
Media
Potencia (W )
Dimens.
Dimens.
SC
PG
22,2
22,4
58,3
58,4
33,6
33,7
31,4
31,1
239,8
239,5
527,1
523,6
254,3
251,9
264,6
258,3
178,9
177,3
R
(%)
-0,9
-0,2
-0,3
1,1
0,1
0,7
0,9
2,4
0,5
Atraso (ps)
Dimens.
Dimens.
SC
PG
718
666
750
651
472
425
451
330
673
504
863
650
687
507
662
431
660
521
PARA
(SC)
Area
(m2 )
Dimens.
Dimens.
SC
PG
210,4
210,4
536,4
536,4
304,3
304,3
281,0
277,4
2304
2296
5180
5145
2441
2413
2512
2446
1721
1704
R
(%)
7,3
13,1
10,0
26,8
25,2
24,7
26,3
34,9
21,0
R
(%)
0,0
0,0
0,0
1,3
0,4
0,7
1,2
2,6
0,8
TABELA II
ENTRE O D IMENSIONAMENTO DE P ORTAS L OGICAS
R ESULTADOS DE COMPARAC AO
(DP) E O D IMENSIONAMENTO DE T RANSISTORES (DT)
DE AREA
C432
C499
C1908
C880
apex1
apex3
apex5
Media
Potencia (W )
DP
DT
R (%)
22,4
21,8
2,7
58,4
56,2
3,8
33,7
32,3
4,7
31,1
30,2
3,9
239,5 231,3
4,9
251,9 245,1
4,8
258,3 255,7
1,0
127,9 124,7
2,9
DP
666,1
651,5
425,0
330,2
503,7
506,5
431,0
502
Atraso (ps)
DT
R (%)
400,6
39,9
421,6
35,3
253,1
40,4
188,3
43,0
294,2
41,6
293,9
42,0
255,9
40,6
301,1
40,4
DP
210,4
536,4
304,3
277,4
2296
2413
2446
1212
PROPOSTO
Area
(m2 )
DT
R (%)
210,4
0,0
536,4
0,0
304,3
0,0
277,4
-1,3
2296
-0,35
2441
-1,2
2512
-2,7
1227
-0,8
TABELA III
N UMERO
TOTAL DE VARI AVEIS
USADAS PARA RESOLVER
DIFERENC
A (D IF.) ENTRE ESSES N UMEROS
C432
C499
C1908
C880
apex1
apex3
apex5
Media
#
Portas
184
403
259
232
1728
1939
1942
955
#
Transistores
666
1608
1008
900
6842
7476
8244
3821
# Variaveis
Auxiliares
344
755
455
399
3351
3771
3663
1820
EO
# Total de variables
DP
DT
Diff. (%)
528
1010
91,3
1158
2363
104,0
714
1463
104,9
631
1299
105,9
5079
10193
100,7
5710
11247
97,0
5605
11907
112,4
2775
5640
102,3
TABELA IV
C432
C499
C1908
C880
apex1
apex2
apex3
apex5
Media
Potencia (W )
Min.
Min.
Reduca o
Atraso
Area
(%)
22,4
22,4
0,00
58,4
58,4
0,00
33,7
33,7
0,00
31,1
20,2
34,9
239,5
137,3
42,7
523,6
270,3
48,4
251,9
135,8
46,1
258,3
138,5
46,4
177,3
102,1
27,3
84
Min.
Atraso
210,4
536,4
304,3
277,4
2295,6
5144,8
2413
2446,4
1704
Area
(m2 )
Min.
Reduca o
Area
(%)
210,4
0,00
536,4
0,00
304,3
0,00
171
38,4
1293,5
43,7
2647,3
48,5
1274,1
47,2
1269
48,1
963,3
28,2
ISSN 977-2177-128009
combinando os trabalhos [3] e [4]. O problema de dimensionamento de portas e de transistores e formulado de duas
maneiras:
1) Objetivando minimizar o atraso do circuito para um
valor maximo de a rea, ou
2) Minimizando a a rea sob uma restrica o de atraso. As
potencias dinamica e de fuga dependem linearmente da
a rea. Por isso, minimizando a a rea se esta diretamente
minimizando o consumo de potencia.
Foi realizada uma comparaca o entre o dimensionamento
de portas e o dimensionamento de transistores desenvolvidos
nesse trabalho que utilizam PG. Para os testes, foram utilizados
os circuitos sintetizados pela ferramenta RLT Compiler da
Cadence para uma biblioteca de celulas em 45nm. O dimensionamento de portas para a minimizaca o de atraso obteve
uma reduca o em 21% no atraso, em media, para os mesmos
valores de a rea e potencia do dimensionamento fornecido pelas
standard cells. O dimensionamento de transistores reduziu o
atraso em 40,4%, em media, comparado com os resultados
do dimensionamento de portas. Embora o dimensionamento
de transistores tenha alcancado melhores resultados comparado ao dimensionamento de portas, ele possui um tempo
de execuca o muito maior pois o numero de variaveis de
otimizaca o e cerca de 2 vezes maior, envolvendo, dessa forma,
uma relaca o de custo-benefcio entre a reduca o no atraso e o
tempo de execuca o.
Em uma segunda analise, os circuitos foram dimensionados buscando minimizar a a rea, onde o atraso foi restrito
ao valor obtido na minimizaca o de atraso. Atraves desta
segunda otimizaca o, pode-se obter uma reduca o em a rea de
28,2% e 27,3% em potencia comparado aos valores dados
pela minimizaca o de atraso. Dessa forma, utilizando as duas
abordagens de otimizaca o, uma apos a outra, e possvel obter
o atraso mnimo e a a rea mnima para o circuito.
Usando uma ferramenta de geraca o automatica de celulas,
como mostrado em [23], pode-se gerar celulas no tamanho
desejado e aproveitar os melhores resultados em atraso, a rea
e potencia, que sao crticas em tecnologias recentes.
Como um trabalho futuro, nos pretendemos expandir essas
analises para avaliar nosso metodo com outros metodos da literatura. Outra tarefa e inserir os tempos de subida e de descida
e as capacitancias dos fios no modelo. Nos tambem pretendemos executar experimentos analisando o atraso usando uma
ferramenta com mais precisao no calculos, pois o modelo de
atraso de Elmore da valores aproximados.
AGRADECIMENTOS
Este trabalho e parcialmente suportado pelo Conselho Nacional de Desenvolvimento Cientifico e Tecnologico - CNPq
- Brasil e da Coordenaca o de Aperfeicoamento de Pessoal de
Nvel Superior (CAPES).
R EFERENCES
[1] R. J. Duffin, E. L. Peterson, and C. Zener, Geometric programmingtheory and application, John Wiley & Sons, 1967.
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(1a)
Ip (t) dt
Qp =
(1b)
I0 =
Qp
F R
(1c)
I. I NTRODUCCI ON
Con lo que ocurrio con el satelite Telstar en 1962, debido
a una explosion nuclear de gran altitud, fue posible conocer
los efectos de la radiacion sobre los dispositivos electronicos.
Con el avance tecnologico y la disminucion de tamano de los
transistores, los CIs se vuelven mas suceptibles a los efectos de
la radiacion. las fuentes de radiacion pueden venir del espacio
(protuberancias solares, cinturon de Van Allen, viento solar o
rayos cosmicos) [1], o desde fuentes radioactivas o electromagneticas de la Tierra. Una vez que el circuito es expuesto
a una fuente de radiacion, este puede tener sus valores de
salidas alterados, alterando las caractersticas del circuito o
bien deshabilitandolo de forma permanente, dependiendo de
la cantidad de radiacion a la cual el circuito fue expuesto.
Estas son las principales razones por las cuales es importante
predecir el comportamiento de CI con fallas debido a este
fenomeno. Las Fallas Transitorias, que son uno de los tantos
tipos de fallas debidas a radiacion, son fallas que duran un
corto tiempo. Estas fallas pueden ser consideradas desde ruido
de baja magnitud hasta pulsos suficientemente grandes como
para danar un dispositivo electronico de forma permanente.
Estas tambien pueden causar efectos acumulativos que hacen
que el equipo falle gradualmente hasta su completa perdida.
Entre esta fallas estan los SETs, fenomenos causados por
partculas que impactan contra las uniones PN inversamente
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Figura 2.
Vth
VDS
W VGS
e nT
1 e T
L
(2a)
VDS 2
2
IDres =
n ox W
tox L
IDsat =
n ox W
(VGS Vth )2 (1 + VDS )
2tox L
(2b)
(2c)
|2F |)
(3)
A. Generador de SET
El VI SET.vi esta basado en (1). La figura 2 muestra el
bloque VI que lo representa. Las entradas de datos Io (A),
tF (s), y tR (s) son I0 , F y R respectivamente. La entrada
Eval. Time (s) es el maximo tiempo de generacion del SET.
Para desplazar el SET en el tiempo de usa la entrada Shifting:
si le numero de elementos del arreglo de salida Ip(t) (A) es
N = Ts /t y se necesita que el SET se ubique en el tiempo
lt , entonces lt [0, N 1], donde Ts es el valor de la entrada
Eval. Time (s) y t es el valor de la entrada dt (s) (debe
cumplirse que Ts
t). La salida Charge (C) muestra la
carga equivalente de este transitorio de corriente. El FP de
este VI se muestra en la figura 1.
SET.vi
Req =
87
3 VDS
5
1 VDS
4 IDSAT
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ISSN 977-2177-128009
(4)
rds
ID
n ox W
=
VGT (1 + VDS )
VGS
tox L
ID
=
VDS
n ox W
=
V 2
tox 2L GT
(5)
(b) Esquematico
(6)
Figura 4.
TABLA I
PAR AMETROS
T ECNOL OGICOS
PARA T RANSISTORES MOS DE 250nm [8].
Parametro
Tension Umbral a VGS = 0 (V)
Efecto Cuerpo (V0.5 )
Funcion Trabajo (V)
Dens. de Donadores (cm3 )
Dens. de Aceptadores (cm3 )
Ancho de Canal (V1 )
Velocidad de Saturacion (m/s)
Dens. de Port. en el Si (cm3 )
Forma Sub-Umbral
Smbolo
Vth0
F
ND
NA
vsat
ni
n
PMOS
-0.40
0.40
-0.30
1 1016
1 1014
-0.10
100000
1.5 1010
1.49
NMOS
0.43
0.40
0.30
1 1016
1 1014
0.06
100000
1.5 1010
1.49
(7)
C. Espejo de Corriente
Figura 5.
Tank PtByPt.vi
2 LC
(8)
D. Circuito Tanque
La herramienta Tank PtByPt.vi es un VI que realiza la
simulacion funcional de un Circuito Tanque. Esta basado en
una capacitancia e inductancia en paralelo. Su VI es mostrado
en la figura 5. Para sintonizar el Tanque se debe usar la
entradaVtune con un numero real entre 1 y 1.8V para ajustar
la capacitancia del Tanque C entre 500 y 1 pF; este valor es
definido a seguir:
Rs =
2f L
Q
Rp = Rs (1 + Q2 )
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ISSN 977-2177-128009
(9a)
(9b)
1
gm1
1
gm2
=0
gm =
n (Nvar )ox W
(I + Ip (t))
tox
L
(12)
donde n (Nvar ) es la mobilidad de los portadores que depende de Nvar = N I/(I + Ip (t)) y N = NA + ND es
el numero total de portadores en el silicio. Si la corriente
transitoria Ip (t) es cero, entonces se vuelve a (11) y el par
cruzado trabajara normalmente.
Para este VI, solo uno de los transistores del par cruzado
sera afectado por el SET, el transistor de transconductancia
gm2 . As, adicionalmente a los cambios causados en la corriente de drenador y la movilidad, son tambien afectadas las
tensiones de drenador los transistores del par cruzado. Este
efecto puede ser aproximado de la siguiente manera:
(10)
Vdf i =
gm1 + gm2
Vdi
2 (R
gm1
p1 + Rp2 )
(13)
Y R ESULTADOS
III. S IMULACI ON
En este caso, se simulara un circuito VCO de 250nm
afectado por un pulso SET con una carga de 37.125pC usando
las herramientas desarrolladas. Este pulso fue simulado usando
la ecuacion de corriente transitoria y de carga colectada (1) (en
este caso I0 =25mA, R =15ps y F =1.5ns). Las partculas
alfa que impactan contra los circuitos analogicos contribuyen
con poca carga (50fC aproximadamente), que es interpretado
como ruido rosado de corta duracion. Para observar los efectos
de estas fallas sobre estos circuitos es necesario simular pulsos
de gran duracion de gran carga superior a los 10pC.
Un VCO es un circuito analogico que genera una senal
periodica (usualmente senoidal), cuya frecuencia es controlada
por una tension de sintona (la cual es tpicamente menor que
la tension de polarizacion). El circuito es mostrado en la figura
7. Este circuito usa un arreglo de Par Cruzado de Transistores
(formado por los transistores M1 y M2) y de Circuitos Tanque.
Tambien se usa un transistor en modo de resistencia activa
(M3) y un circuito de Espejo de Corriente (formado por los
transistores M4, M5 y M6).
(b) Esquematico
Figura 6.
2k
W
I
L
(11)
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2
1.5
1
0.5
0
0
Figura 9.
5n
10n
15n
Time (s)
20n
25n
30n
Figura 8.
Laser.
La figura 9 muestra la simulacion hecha con las herramientas desarrolladas en LabVIEW. Esta simulacion es muy
parecida a la experiencia de laboratorio realizada por W. Chen
et al. en el Laboratorio de Microelectronica de la Universidad
de Bordeaux [4], la cual es mostrada en la figura 10a. Esta
comparacion es totalmente cualitativa debido a la no inclusion
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Figura 11.
R EFERENCIAS
[1] R. Velazco, P. Fouillat, and R. Reis, Radiation Effects on Embeded
Systems. Dordratch, the Netherlands: Springer, 2007.
[2] G. C. Messenger, Collection of charge on junction nodes from ion
tracks, IEEE Transactions of Nuclear Science, vol. NS-26, no. 6,
December 1982.
[3] R. Caverly, CMOS RFIC Design Principles. Norwood, Massachusetts
02062: Artech House, Inc., 2007.
[4] W. Chen, V. Pouget, H. Barnaby, J. Cressler, G. Niu, P. Fouillat,
Y. Deval, and D. Lewis, Investigation of single-event transients in
voltage-controlled oscillators, Nuclear Science, IEEE Transactions on,
vol. 50, no. 6, pp. 2081 2087, dec. 2003.
[5] J. Travis and J. Kring, LabVIEW for Everyone : Graphical Programming
Made Easy and Fun, 3rd ed. Prentice-Hall PTR, 2006.
[6] G. W. Johnson and R. Jennings, LabVIEW Graphical Programming,
4th ed. New York, USA: McGraw-Hill, 2006.
[7] W. E. Calienes Bartra, Ferramentas para a simulaca o de falhas transientes, Masters thesis, Universidade Federal do Rio Grande do Sul,
Diciembre 2011.
[8] J. M. Rabaey, A. Chandrakasan, and B. Nicolic, Digital Integrated
Circuits, a Design Perspective, 2nd ed. Upper Saddle River, New
Jersey 07458: Pearson Education, Inc., 2003.
[9] K. Kano, Semiconductor Devices. Upper Saddle River, New Jersey
07458: Prentice Hall, 1998.
[10] J. M. Rabaey, A. Chandrakasan, and B. Nicolic, Spice model
level 49 for 0.25 micron cmos process, Berkeley Wireless
Research Center, Berkeley University, 2003, disponible en:
http://bwrc.eecs.berkeley.edu/icbook/models.htm.
[11] C. G. Montoro and M. C. Scheider, Mosfet Modeling for Circuits
Analysis and Design. London, Great Britain: World Scientific, 2007.
[12] A. Cunha, M. Schneider, and C. Galup-Montoro, An mos transistor
model for analog circuit design, Solid-State Circuits, IEEE Journal of,
vol. 33, no. 10, pp. 1510 1519, oct 1998.
IV. C ONCLUSIONES
Fue simulado un VCO CMOS de 250nm inyectando un SET
para observar el comportamiento de este tipo de circuito ante
los pulsos transitorios y estos resultados fueron comparados
con los obtenidos en [4], encontrando grandes similitudes
cualitativas con la experiencia experimental.
La Firma de Decoloracion es una herramienta u til para
predecir lo que ocurrira con el circuito oscilador cuando es
afectado por un pulso transitorio. El analisis de esta caracterstica tambien predice el nivel de armonicos que afectan al
circuito y la carga crtica necesaria para considerar un SET
como falla que afectara al dispositivo.
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Departamento de Electrnica
Instituto Nacional de Astrofsica ptica y Electrnica
Sta. Ma. Tonantzintla, Puebla, Mxico
rventura@inaoep.mx
I.
INTRODUCCIN
,,
,,
(1)
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II.
(2)
y B :
donde los operadores A :
representan las sinapsis de "feedback" y "feedforward" ,
y las
respectivamente, que relacionan las salidas
de las clulas de la esfera de influencia con el
entradas
estado de la clula Ci,j. En el caso de la CNN estndar,
,
,
y bi,j
donde ai,j
,
1,
,
,
,
1
1
(3)
III.
,
,
t =
(t),
t ,u
1, ,
,
1, ,
(5)
ALGORITMO DE LA SCNN
(4)
V3=(0,1)
V2=(1,1)
p=(0.8,0.3)
donde F :
es una funcin lineal a tramos; y , t
0,1 es el vector de salidas de las clulas pertenecientes a la
0,1 es el vector de
esfera de influencia Si,j; u , t
V0=(0,0)
c0=f(V0)=0
c1=f(V1)=1
c2=f(V2)=0.8
c3=f(V3)=0.9
V1=(1,0)
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SIMULACIONES Y RESULTADOS DE LA
IMPLEMENTACIN
IV.
con los valores de cn se procede a interpolar para obtener el
resultado del punto p (figura2), esto se hace por medio de su
descomposicin convexa, en los siguientes pasos:
1.
2.
0.5
0
G (U ) = u5 u1 + u2 + u3 + u4 + u6 + u7 + u8 + u9
1
0
1
1
0.5
0
0
1
0
0.2
a)
b)
0
0
(6)
cumpliendo con:
(7)
5.
4.
1
1
0.3
0.5
0
3.
A. Matlab
La deteccin de bordes es un procesamiento bsico en el
anlisis de imgenes, el cual es ampliamente utilizado en
sistemas de visin. Este tipo de procesamiento es el que se
aplic para la comprobacin del algoritmo descrito en la
seccin anterior. La funcin boleana que resuelve para un
pixel dado, si es o no es borde es la siguiente [7]:
1
0
B. Xilinx
Se realizaron dos diseos de celdas simplicial en VHDL,
basados en la metodologa usada en las simulaciones de
Matlab. Las celdas S-CNN fueron simuladas, sintetizadas, e
implementadas a travs de las herramientas de Xilinx. Las
Figuras 4(a) y 4(b) muestran los diagramas RTL del primero y
segundo diseo respectivamente.
0
0
0
1
0.8
0.8
0.5
0.2
0.74
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TABLA II.
a)
C. Resultados de la Implementacin
En la Fig. 6 se muestra una imagen de la tarjeta Spartan3E XC3S500E con la implementacin del segundo diseo de
la celda, en la cual se est procesando el mismo ejemplo de la
Fig.4. Como resultado se obtiene el valor de 241 en binario
(11110001).
Figura 4. a) Diagrama RTL del primer diseo, b) Diagrama RTL del segundo
diseo.
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Bloques
Mquinas de estado
Multiplexores
Contadores 0 a 8
Contadores 0 a 10
Contadores 0 a 110
Mdulos
descomposicin
Memorias ROM
TABLA III.
Diseo 1
0
0
0
1
1
9
Diseo 2
3
1
1
1
1
1
V.
[3]
[4]
CONCLUSIONES
[5]
[6]
[7]
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J.Y.Mori
C.Sanchez-Ferreira, C.H.Llanos
I.
INTRODUCTION
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II.
RELATED WORK
Algorithm
Low-Pass Filter
Dilation
Erosion
Operations
The output pixel is the median value of
neighborhood.
The output pixel is the maximum value of the
neighborhood.
The output pixel is the minimum value of the
neighborhood.
Opening
Closing
Morphological
Smoothing
Morphological
Gradient
BACKGROUND
D. Convolution/Correlation
Convolution and correlation are well-known operations
in signal processing area (in this case the images can be
considered as two-dimensional signals), and they are widely
used for image filtering. The operations of convolution and
correlation are described by (3) and (4), where i(x, y) and k(x,
y) are the image and filter, respectively.
E. Binary Morphology
The binary morphology operations are similar to the
The operation of converting a color image to grayscale is
order filters (described in section III-C) and, in this case, the
a point operation and, therefore, the process has a complexity
main difference is that order filters only operate over grayof O (NM) (N and M are the image dimensions).
scale images. The binary morphology operations are made
over binary images (which has one bit per pixel). Such
B. Thresholding
images are obtained using the thresholding operation (see
Another point operation is the threshold, and this
section III.B). The most basic morphological operations are
algorithm compares the pixel value (already in grayscale)
the erosion and dilation, and both operate on a region of the
I = ( R + G + B ) / 3
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F. Edge Detection
An edge is the boundary between two regions with
different properties. From the differential and integral
calculus it is known that the derivative of a function
determines its rate of change. An edge generally means an
abrupt change in the intensity of the pixels, e.g. a high rate of
change. In this case, the calculation of the derivative of the
image provides points of maxima, which probably are the
edges of objects (in an image). Images are two-dimensional
functions and, therefore, horizontal and vertical partial
derivatives can be independently used. The gradient operator
shown in (9) and (10) is a suitable tool for achieving this.
( )
where the index j indicates the element of the mask and the
corresponding pixel in the image after the thresholding
process. The output is the value of a new pixel, which is also
binary. By performing both dilation and erosion in several
sequences (combinations) new operations such as opening,
closing, morphological smoothing and morphological
sharpening are achieved (see Table 1).
IV.
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mask. Equations (3) and (4) show that the convolution mask
is obtained by rotating the correlation mask by 180 degrees,
and vice versa. Therefore, the same architecture can be also
used for calculating both operations. Figure 5 shows the
implemented architecture, in which the inputs are the outputs
of the neighborhood loader block (in [16] a similar
architecture for implementing the convolution is described).
The Fig.5(b) shows two basic operations (multiplication
and addition) together in a pipelined structured for achieving
these operations. The multiplication block performs 9
multiplication operations in parallel (using one clock cycle).
The addition block operates over the multiplication results,
yielding also the output in a single clock cycle. Otherwise,
the architecture is scalable according to the predefined size
of the neighborhood and also the number of the internal
multipliers in the FPGA.
Desired
Neighborhood
Buffered pixels
Pixels not loaded
by the camera yet
(a)
Discarded
pixel
Input pixel
from camera
Available 3x3
Neighborhood
(b)
E. Convolution/Correlation Architecture
3x3 Neighborhood
K1
K4
K7
K2
X
K5
K3
X
X K8
K6
X
K9
X
X
X
Output
pixel
(a)
3x3
Neighborhood
Multiplication
Addition
clock
Convolution/
Correlation
result
(b)
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Absolute
Gy
Magnitude
Absolute
Comparer
clock
Gy
Absolute
Magnitude
(b)
V.
Memory
Bits
DSP9x
9
Freq.
(MHz)
Initial
delay
Dilation
24
420.17
26
93.65
34
420.17
7471
138680
32
49.14
8045
(a)
Gx
LC
Edge detection
(Fig.8a)
Edge Detection
(Fig.8b)
Chain for
comparison
Absolute
clock
Architecture
RESULTS
Camera
Image
acquisiton
architecture
Color
Conversion
Neighborhood
Loader
Median Filter
(Rank Order)
Neighborhood
Loader
Erosion
Neighborhood
Loader
Threshold
Maximum Value
(Rank Order)
Robinson
operators (9
convolutions)
Neighborhood
Loader
Dilation
Neighborhood
Loader
Erosion
Image display
architecture
FPGA
LCD
TABLE II.
SYNTHESIS RESULTS
Architecture
LC
Memory
Bits
DSP9x
9
Freq.
(MHz)
Initial
delay
Entire FPGA
33,216
483,840
70
440
N/A
Color Conversion
94
420.17
Thresholding
11
154.34
Neighborhood
Loader
1201
12256
224.32
1603
Rank Order
3710
165.48
Convolution/
Correlation
469
36
283.13
Erosion
22
420.17
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REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
(a),(b),(c),
(f),(e),(d),
(g),(h)
[7]
[8]
VI.
[9]
CONCLUSIONS
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
ACKNOWLEDGMENT
The authors would like to thanks CAPES Foundation for
the financial support of this work. A special thanks to Altera
Corp. by providing Quartus II Licenses and to DHW
Engenharia e Representao Ltda. for the partnership.
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I. INTRODUCIN
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s + 0 .3568 s + 0 .05917
G ( z) =
0 .02335 z + 0 .02073
z 13 z 2 1 .65 z + 0 .6999
Ecu. 3
y ( k ) = G ( q 1 )u ( k ) + H ( q 1 ) e ( k )
G (z) =
Ecu. 4
III.
IV.
89 .88 z + 82 .14
z 2 1 .111 z + 0 .4077
Ecu. 5
CONTROLADOR DIFUSO
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A. Esquema de control
Una vez determinado el modelo matemtico del sistema,
utilizando mtodos Eye Ball (Sistema de Caudal) o mtodos
paramtricos (Transmisin Hidrosttica) se elabora el
diagrama de bloque de la figura 6, para evaluar la respuesta
dinmica ante una entrada escaln. Los modelos matemticos,
descritos anteriormente, no presentan integrador, por lo tanto
la salida del regulador fuzzy indicar, para cada uno de los
procesos, la razn de cambio de la accin de control. El
limitador corresponde a la mxima accin de control que
puede alcanzar cada actuador. Las variables de entrada para el
controlador fuzzy son la seal del error y la razn de cambio
del error.
ERROR
NEGATIVO
RAZN DE
CAMBIO
POSITIVO
NEGATIVO
NEGATIVO
CERO
POSITIVO
CERO
NEGATIVO
CERO
POSITIVO
POSITIVO
NEGATIVO
CERO
POSITIVO
V.
ALGORITMOS GENTICOS
A. ndices de error.
El comportamiento del error dinmico en un sistema de
control es comnmente utilizado como criterio de diseo
durante la sintonizacin de controladores. Debido a su
comportamiento dinmico, este error es evaluado mediante un
criterio o ndice de comportamiento.
CERO
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TABLA II
PARMETROS DE CONFIGURACIN DEL ALGORITMO GENTICO
PARMETRO
Transmisin Hidrosttica
y[ n ] = 89 .88 u [ n 1] + 82 .14 u [ n 2 ] +
1.111y[n - 1] - 0.4077y[n - 2]
Nvar
Npop
150
Niter
80
Xrate
0.7
mutrate
0.1
Ecu. 11
VALOR
106
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Fig. 10. Conjuntos difusos para la T.H.. a) Seal de error. b) Seal razn de
cambio del error c) Salida del regulador
VI.
SISTEMA SCADA
107
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VII.
CONCLUSIONES
[4]
[5]
[6]
[7]
108
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I.
INTRODUO
R1
NI1
R2
R3
NI2
Ncleo 1
Ncleo 2
R4
NI4
R5
R7
Ncleo 8
Roteador
Interconexo
Roteador-Roteador
Ncleo 6
R8
NI8
Ncleo 7
R6
NI6
Ncleo 5
NI7
Interface de
Rede (NI)
Ncleo 3
NI5
Ncleo 4
Ncleo
NI3
R9
NI9
Ncleo 9
Interconexo
Roteador-NI
Situaes de
Falha
TRABALHOS RELACIONADOS
109
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aquelas que esto sempre atuando no hardware para proteglo, principalmente contra falhas transientes. Neste caso, o
diagnstico e a deteco ocorrem em tempo de execuo, e a
correo do dado pode ou no ser feita simultaneamente.
Alguns exemplos de tcnicas dinmicas so o cdigo de
Hamming, a paridade, a redundncia e o TMR. Porm, elas
exigem um alto custo de rea extra, afetando diretamente a
potncia. J as tcnicas estticas necessitam de deteco e
diagnstico prvio [4 - 6], para configurar as estruturas de
tolerncia a falhas. A rea necessria para tcnicas estticas
tambm significativa, porm os ganhos ocorrem quando o
hardware tolerante a falhas no precisa ser completamente
utilizado, evitando gastos desnecessrios.
Em [7], a combinao de cdigo de Hamming foi
utilizada para proteger os buffers, o roteador e as
interconexes. Os autores protegem o dado de apenas uma
nica falha em cada interconexo, focando em falhas
transientes no buffer e crosstalk. Casos com mltiplas falhas
no podem ser tratados por [7]. Resultados reportados
mostram uma penalidade na frequncia de 32% para uma
tecnologia de 180 nm, e mais de 50% em rea extra sem
incluir o aumento de fios nas interconexes. Em [8], para 130
nm, foi apresentada uma tcnica que utiliza cdigo de
Hamming em cada metade dos dados, e a retransmisso pode
ser utilizada quando Hamming no suficiente para a
correo dos dados com falha. Mesmo assim, a retransmisso
pode no ser suficiente para manter a confiabilidade dos
dados, quando existem mltiplas falhas. As principais
desvantagens deste mtodo so a quantidade extra de rea e o
consumo excessivo de potncia, pois a rea do roteador tornase mais de 3 vezes maior do que o roteador no protegido, e a
latncia tambm incrementada em quase 4 vezes. Em [9]
existe uma proposta similar a de [8], e a principal diferena
a substituio do cdigo de Hamming por paridade. Porm,
[9] tolera crosstalk e apenas uma nica falha permanente em
cada interconexo. Se, por exemplo, existem 2 falhas
permanentes em uma interconexo, sendo cada uma delas
localizada em uma das metades do fio, significa que o bit de
paridade sempre estar errado, e mesmo utilizando a
retransmisso no ser possvel ter um dado sem a presena
de erro. Em [10], a redundncia utilizada em alguns
componentes no roteador e nas interconexes para prover
confiabilidade. Um BIST foi includo na implementao para
prover o diagnstico da falhas. Porm, para uma interconexo
que corresponde em torno de 5% da rea total da rede, a
conectividade mostrou-se baixa, em torno de 30% para at
100 fios defeituosos, numa rede intra-chip 8x8.
Em [11] o cdigo de Hamming utilizado e as
interconexes so completamente duplicadas, permitindo que
at trs falhas sejam toleradas, e quatro falhas sejam
detectadas. Quando acontecem duas falhas em cada conjunto,
ento a implementao permite apenas detect-las, j que o
uso de Hamming permite correo apenas de falha nica para
cada conjunto de fios. Embora a tenso nos fios seja reduzida,
as interconexes foram completamente duplicadas,
aumentando a probabilidade de falhas.
Para solucionar a limitao da cobertura de falhas com as
tcnicas dinmicas, [12] utiliza uma tcnica esttica para
ESTRATGIAS DESENVOLVIDAS
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Dout7
Dout6
Dout5
DD
Canal de Entrada
Interconexo
(8 bits)
Dout7 / Dout3
Dout6 / Dout2
Dout4
Dout3
Dout2
DD
Din7
Din6
Din5
Din4
Dout5 / Dout1
Dout4 / Dout0
Din3
Din2
Dout1
Din1
Dout0
Din0
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ISSN 977-2177-128009
R2
A
R3
R1
C
R4
B
R2
B
R3
Espelhamento Vertical
R2
D
R3
C
A
R4
R1
R4
A
C
R3
Mapeamento Original
R1
R2
Area
lgica
(m2)
Frequncia
Mxima
(MHz)
Potncia @
Freq. Max.
(mW)
Potncia @
500MHz
(mW)
Original
10.954
885
1,68
1,42
RRADD sem
DD ativo
RRADD com
DD ativo
Hamming
14.104
870
1,70
1,43
14.104
588
2,41
2,07
12.614
510
2,16
2,12
B
R4
Roteador
Potncia para 1 mm
(mW@500MHz)
9,04
12,06
IV. RESULTADOS
Para os resultados de sntese, uma biblioteca standard cell
de 90 nm com tecnologia CMOS foi utilizada com a
ferramenta Power Compiler da Synopsys. Na tabela I os
resultados de rea extra, frequncia mxima de operao e
potncia so apresentados para largura de canal de 8 bits, e a
sigla RRADD significa Roteador com Roteamento
Adaptativo e Diviso de Dados. O que se pode perceber
que nossa proposta tem 28% de rea extra, enquanto
Hamming tem apenas 15%. Porm, o impacto no caminho
crtico de nossa proposta apresentou-se melhor, uma vez que
Hamming tem uma longa cadeia de portas XOR para
codificao e decodificao dos dados. Quando os resultados
de potncia so normalizados a 500 MHZ, pode-se ver que a
Entre
Roteadores
Torus
Entre Roteador
e Ncleo
Total
34
14
24
72
16
22
39
24
24
50
112
ISSN 977-2177-128009
MPEG4
17 (35%)
26 (54%)
2,2%
6,6%
135 us
84,3 us
232 us
130 us
VOPD
Potncia
(mW)
Energia
(J)
Tempo
Mdio
(s)
MPEG4
Potncia
(mW)
Energia
(J)
Nossa
Proposta
200,1
30,86
6,17
119,7
30,86
3,67
Hamming
232,0
37,98
8,81
133,3
37,98
5,06
D) Conectividade da Proposta
A figura 7 mostra a conectividade da rede de acordo com
o nmero de falhas, que varia de 0 at 100, distribudas em
qualquer fio da rede. Foram avaliados o melhor e o pior
cenrio de conectividade para um caso genrico,
considerando uma rede 4x3 e uma rede 8x8, e os resultados
foram comparados com a conectividade de [10]. O melhor
cenrio corresponde ao caso onde as falhas esto
completamente distribudas entre as interconexes, e o pior
caso de falha considerado quando as falhas atingem mais de
50% das interconexes. Para a rede 8x8 com 100 fios
defeituosos distribudos pela rede, o pior cenrio mostra uma
perda de 30% de conectividade para nossa proposta, enquanto
que [10] tem quase 70% de perda na conectividade.
V. CONCLUSO
Para prover tolerncia a falhas nas interconexes, foram
utilizadas as tcnicas de roteamento adaptativo e diviso de
dados, e ambas as tcnicas podem ser combinadas com o
remapeamento das tarefas para minimizar o impacto da falha
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ISSN 977-2177-128009
[8]
[9]
[10]
100
90
80
[11]
% Conectividade
70
60
50
40
[12]
30
20
10
[13]
0
0
10
20
30
40
50
60
70
80
90
100
# Falhas
[14]
REFERNCIAS
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Agrawal, Vishwani D.; "Testing for Faults, Loooking for Defects," Test
Workshop (LATW), 2011 12th Latin American, Keynote Talk, March
2011.
Cuviello, M.; Dey, S.; Xiaoliang Bai; Yi Zhao;, Fault Modeling and
Simulation for Crosstalk in System-on-Chip Interconnects,
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, San Jose, CA, pp. 297-303, 1999.
Dehon, A.; Naeimi, H.; Seven strategies for tolerating highly defective
fabrication, IEEE Design & Test of Computers,vol.22, no.4, pp. 306315, 2005.
Concatto, C.; Almeida, P.; Kastensmidt, F.; Cota, E.; Lubaszewski, M.;
Herve, M.; Improving yield of torus NoCs through fault-diagnosisand-repair of interconnect faults, 15th IEEE International On-Line
Testing Symposium (IOLTS), pp.61-66, 2009.
Herve, M.; Cota, E.; Kastensmidt, F.L.; Lubaszewski, M.; Diagnosis
of interconnect shorts in mesh NoCs, 3rd ACM/IEEE International
Symposium on Networks-on-Chip, 256-265, 2009.
Yang, H.; Papachristou, C.; A Method for Detecting Interconnect
DSM Defects in Systems on Chip, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol.25, no. 1, pp.197204, 2006.
Arthur Frantz; Fernanda Kastensmidt; Luigi Carro; Erika Cota;
Dependable Network-on-Chip Router Able to Simultaneously Tolerate
Soft Errors and Crosstalk, Proceedings International Test Conference
(ITC), vol. 1, pp. 1 9, 2006.
[15]
[16]
[17]
[18]
[19]
[20]
[21]
Lehtonen, T.; Liljeberg, P.; Plosila, J.;, "Online Reconfigurable SelfTimed Links for Fault Tolerant NoCs," VLSI Design, IEEE
International, 2007.
Braga, M.; Cota, E.; Kastensmidt, F.L.; Lubaszewski, M.; , "Efficiently
using data splitting and retransmission to tolerate faults in networks-onchip interconnects," Circuits and Systems (ISCAS), Proceedings of
2010 IEEE International Symposium on, vol., no., pp.4101-4104, May
30 2010-June 2 2010.
Kakoee, M.R.; Bertacco, V.; Benini, L.; , "ReliNoC: A reliable network
for priority-based on-chip communication," Design, Automation & Test
in Europe Conference & Exhibition (DATE), 2011 , vol., no., pp.1-6,
14-18 March 2011.
Ganguly, A.; Pande, P.P.; Belzer, B.;, "Crosstalk-Aware Channel
Coding Schemes for Energy Efficient and Reliable NOC
Interconnects," Very Large Scale Integration (VLSI) Systems, IEEE
Transactions on , vol.17, no.11, pp.1626-1639, Nov. 2009.
Palesi, M.; Kumar, S.; Catania, V.; , "Leveraging Partially Faulty Links
Usage for Enhancing Yield and Performance in Networks-on-Chip,"
Computer-Aided Design of Integrated Circuits and Systems, IEEE
Transactions on , vol.29, no.3, pp.426-440, March 2010.
Dutta Choudhury, A.; Palermo, G.; Silvano, C.; Zaccaria, V.; "Yield
Enhancement by Robust Application-specific Mapping on Network-onChips, Second International Workshop on Network on-Chip
Architectures (NoCArc'09), pp. 37-42, 2009.
Schonwald, T.; Zimmermann, J.; Bringmann, O.; Rosenstiel, W.;
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-onChip Architectures, 10th Euromicro Conference on Digital System
Design Architecture, Methods and Tools, pp. 527-534, 2007.
Koibuchi, M.; Matsutani, H.; Amano, H.; Mark Pinkston, T.; A
Lightweight Fault-Tolerant Mechanism for Network-on-Chip. 2nd
ACM/ IEEE International Symposium on Networks-on-Chip, pp. 13-22,
2008.
Tornero, R.; Sterrantino, V.; Palesi, M.; Ordua, J.M.; A multiobjective strategy for concurrent mapping and routing in networks on
chip, IEEE International Symposium on Parallel & Distributed
Processing, pp.1-8, 2009.
Changbo Long; Lei He; Distributed sleep transistor network for power
reduction, IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, pp. 937-946, 2004.
Shi, K.; Howard, D.; Sleep Transistor Design and Implementation Simple Concepts Yet Challenges To Be Optimum, International
Symposium on VLSI Design, Automation and Test, 2006.
Sakurai, T.;, "Approximation of wiring delay in MOSFET LSI," SolidState Circuits, IEEE Journal of , vol.18, no.4, pp. 418- 426, Aug 1983.
Vu-Duc Ngo; Huy-Nam Nguyen; Hae-Wook Choi; Analyzing the
Performance of Mesh and Fat-Tree topologies for Network on Chip
design, LNCS (Springer-Verlag), pp 300-310, 2005.
Bertozzi, D.; Benini, L.; Xpipes: a network-on-chip architecture for
gigascale systems-on-chip, IEEE Circuits and Systems Magazine,
vol.4, no.2, pp. 18- 31, 2004.
Antes do Remapeamento
Depois do Remapeamento
Tempo de
Computao (s)
80,6
Energia
(J)
2,37
Tipo de
Remapeamento
Horizontal
MPEG4 (caso 2)
84,6
2,49
Vertical
76,6
2,25
MPEG4 (caso 3)
146,4
4,53
Vertical
119,2
3,67
MPEG4 (caso 4)
125,2
3,86
Horizontal
113,3
3,49
MPEG4
133,3
5,06
(Original - Hamming)
133,3
5,06
VOPD (caso 5)
135,7
3,99
Horizontal
133,4
3,92
VOPD (caso 6)
206,5
6,37
Horizontal e Vertical
197,2
6,08
VOPD
232,0
8,81
(Original - Hamming)
232,0
MPEG4 (caso 1)
114
Tempo de
Computao (s)
76,6
Energia
(J)
2,25
8,81
ISSN 977-2177-128009
I.
INTRODUCTION
PROPOSED ARCHIITECTURE
115
TABLE I.
0 to 2.56 V
Up to 8 bits
3.3 V
AMS 0.35 m
Discrete Multi-ramp
ISSN 977-2177-128009
The switches "A" and "B" are also controlled by the phase
and , if the output voltage of comparator circuit is a logic
"1", otherwise, if the logic level on comparator output is "0",
the key "A" and "B" are controlled by and , respectively.
Thus, the operation of the circuit in a time instant k can be
summarized in Table II.
TABLE II.
Vo
QI
QR
QO
VCo
SEQUENCE OPERATION
N N P CR
VI = N
VR
N
CI
(1)
CR
Co
VCo min = VR
(2)
C IVI
C RVR
Qo ( k 1 )
Qo ( k 1 ) + Q I ( k ) + Q R ( k )
Qo ( k 1 ) QR (k )
Qo ( k 1 ) + Q I (k ) Q R ( k )
VCo ( k 1 )
VCo ( k 1 ) VR
CR
Co
VCo ( k 1 ) + VI
CI
C
+ VR R
Co
Co
VCo ( k 1 ) + VI
CI
C
VR R
Co
Co
VCP = VR
CR
Co
(3)
CR
C
+ VR I
Co
Co
(4)
Co 3C R
(5)
116
ISSN 977-2177-128009
0.9
0.8
VCo/VR
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VI/VR
VR
(6)
CR
V I max
It can be observed in (6) that reducing the input dynamic
range is equivalent to apply a gain to the input signal. In this
study, five capacitance values were chosen, allowing a digital
selection to the dynamic range of the converter. In Figure 3
are demonstrated the values of capacitors and the
corresponding maximum dynamic range of the converter for
each capacitance, for CR=200 fF.
CI =
III.
CIRCUIT DESGIN
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IV.
AMPLIFIER
W(m)
40
30
10
20
60
M1, M2
M3, M4, M5, M6
M7, M8
M9, M10
M11, M12
SIMULATION RESULTS
L(m)
0.7
2
2
2
2
W(m)
4
0.5
0.4
20
2
1
4
L(m)
0.35
0.35
0.35
0.35
0.35
0.35
0.35u
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119
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[2]
[3]
Figure 15. FFT plot for the converter with resolution of 5 bits
From the result of the FFT the signal-to-noise ratio and the
effective number of bits is obtained from the following
equation:
ENOB =
( SNR 1.76)
6.02
(7)
[4]
FINAL CONSIDERATIONS
In this work the design at transistor level of a switchedcapacitor integrating A/D converter with programmable input
range and resolution in the technology AMS 0.35 m was
proposed. A converter with programmable resolution greater
than 8 bits can be implemented, making the circuit of the
counter up/down realize higher counts of cycles.
Increasing the resolution reduces the value of the LSB,
requiring components with better accuracy. To reduce the time
of conversion clock frequencies above 1 MHz could be used.
The technique used for adjustment of the ADC input range
was to change the input capacitance, and the behavioral
simulations of different input ranges of the converter proved to
be satisfactory. The programmable capacitor used has a
minimum number of capacitances, and ensures the signal
[5]
[6]
[7]
[8]
[9]
[10] CHOI, H. C.; KIM, Y. J.; YOO, S. W.; HWANG S. Y. LEE, S.-H. A
Programmable 0.8 V10-bit 60-MS/s 19.2-mW 0.13- m CMOS ADC
Operating Down to 0.5V. IEEE Transactions on circuits and systems
Express Briefs, VOL 55, No. 4, 2008
120
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I.
INTRODUO
II.
, ,
, =
1
()
|| ||22,
2
|| ||22,
2
121
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122
ISSN 977-2177-128009
= +
IMPLEMENTAO E SIMULAO
123
ISSN 977-2177-128009
Mtodo utilizado
Figura 5.
V.
Metodologia de simulao.
RESULTADOS
10
15
20
NLM em software
8,91
24,17
40,56
113,61
NML em FPGA
8,89
24,68
41,42
113,71
C. Performance em tempo
Conforme sugerido por Buades [2], foi utilizado M=7, e
uma janela de pesquisa de 2121 pixels. Como as operaes
relativas ao clculo da distncia Euclidiana ponderada so
efetuadas em hardware paralelo.
So gastos 441 ciclos calculando pesos para filtrar um
pixel e todas as outras operaes so realizadas em pipeline.
Essa informao juntamente com perodo de relgio de
(9,45ns obtidos na simulao) permite inferir o tempo
despendido para filtrar uma imagem. Para uma imagem com
2 pixels so gastos 441 2 .
Na Tabela II, experimentos em um PC com um
processador Core I5 2.53GHz e 6GB de RAM demonstraram
que o NLM em software gasta aproximadamente 12 minutes
para filtrar uma imagem de 10241024 pixels, enquanto que
a verso em FPGA aqui proposta gasta 22 segundos
aproximadamente para filtrar a mesma imagem.
Comparado ao algoritmo original, o resultado do trabalho
proposto aproximadamente 170 vezes mais rpido,
conforme demonstrado na Tabela II e na Fig. 8.
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NLM em software
NLM em FPGA
Razo
512*512
198,32s
1,10s
180,3
740,12s
4,41s
167,8
1024*102
4
2592*194
4
Mtodo utilizado
3740,50s
21,2s
REFERNCIAS
[1]
176,4
[2]
[3]
[4]
[5]
[6]
[7]
VI.
[8]
CONCLUSO
[9]
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I. INTRODUCTION
Many biomedical applications such as pacemakers and
implantable prostheses depend on the operation of a battery.
Thus, implantable devices need some measuring circuit to
determine the battery charge consumed and/or estimate the
remaining charge. This information is critical to health
professionals, who must recommend the replacement of the
device, or postpone a delicate surgical procedure [1]. Thus, the
circuit that monitors the battery charge is fundamental,
requiring reliability, security, and very low power
consumption.
Some kinds of battery monitors circuits are available in the
literature [1] -[6]. In general, the majority of these circuits use
the traditional topology of charge integration, shown in Fig. 1,
which has continuous and undesirable energy consumption
over the lifetime of the battery. This topology integrates the
current of battery using a passive device as a resistor. In this
example, the value of the charge consumed is stored in digital
memory.
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TABLE I.
Variable
Expression
Drain current
I D = I F I R = I S (i f ir )
Specific Current
Source/drain to bulk
voltage
Pinch-of voltage
Drain-to-source
saturation voltage
Source
transconductance
Power spectral density
of thermal noise
(saturated transistor)
TRANSISTOR MODEL
'
I S = nCOX
t2 W
2 L
)]
VP VS ( D ) = t 1 + i f (r ) 2 + ln 1 + i f (r ) 1
VP
VG VT 0
n
(
( 1+ i
VDS , SAT t 1 + i f + 3
g ms( d ) =
2I S
f (r)
1 + if + 1
8
2
Sint = kBTg m
3
1 + if 1
RBAT =
VCsh1 VCsh 2
Iforce
(1)
DEVELOPED CIRCUITS
H ( s) =
Vout
Gm1
1
=
Vbat+ -Vbat- Gm2 1 + sCf / Gm2
(2)
127
ISSN 977-2177-128009
2
2
2
I 2 g
2
2 + 4 D1 2 m I ( VT ) + 2
2
N . gm1
D M 5
gm
D M 1
2
2
I2 g
2
+ 2 D12 m ( VT
+ 2
)
I
D M 7
gm1
2
2
= 2 ( VT
Vin
)+
+ ...
(7)
where the first term in square brackets refers to the sourcecoupled pair (M1 and M2), the second term in square brackets
refers to the series-parallel current mirror (M3, M4, M5 and
M6), while third term in square brackets refers to the current
mirror (M7 and M8) in Fig. 4.
To reduce silicon area, the filter capacitor, Cf in the Fig. 3,
was implemented as a gate capacitor biased in strong
inversion, which leads to an area around five times smaller
than that of a polysilicon capacitor on the same 0.35 m
process. Considering operation in strong inversion and the
expressions of table I, the relationship between the inversion
level and the gate capacitance CG can be written as
Fig. 3. Differential OTA-C filter used to amplify the signal from the
impedance monitoring.
CG C ' oxWL 1
n i f + 2
(8)
Fig. 4. OTA circuit that employs series and parallel associations of transistors
for current division.
Vn 2 flic ker =
4 nk BT ( f 2 f1 )
1+ if1 +1
Gm
2 nk BT ln ( f 2 / f1 ) N ot _ n
+
N *C 'ox
(WL )1
( 1+ i
f1
N ot _ n
2 2 N ot _ p
+ 1
+
N
(
WL
)
(
WL )3
(3)
Fig. 5. Source follower circuit.
(4)
Gm1
2
AVT
2
A2
, 2 =
2WL
2WL
(6)
VIN VT 0
+ Kt
n
(9)
where
I
I
K = 1 + B 2 + ln 1 + B 1
I S1
I S1
(5)
VOUT
(10)
128
ISSN 977-2177-128009
Fig. 6. Level-shift circuit, used to monitor the battery voltage. VBAT is the
battery voltage.
Fig. 7. Layout and micrograph of the battery monitor in the AMS 0.35 m
technology.
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TABLE II.
Variable
Value
Gm1
56 nA/V
Gm2
7 nA/V
1.6 V
Total area
~ 0.15 mm2
Current consuption/day
~ 6.5 nAh
V. CONCLUSION
We have presented a battery monitor circuit. Its main
advantages are the extremely low power consumption and the
simplicity of the method. The monitor functionality has been
experimentally verified for a prototype implemented in a 0.35
m CMOS technology.
ACKNOWLEDGMENT
The authors would like to acknowledge CNPq and CAPES,
Brazilian agencies for scientific development, and the Genius
Institute of Manaus, Brazil, for the general support of this
work.
REFERENCES
[1]
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In this work, a CAD tool has been developed that allows the
user to supply any type of potential profile, which can be used
as preliminary design tool and for research and educational
purposes as well.
The mathematical and numerical models are presented in
section II and III respectively. In section IV, simulations
assuming different potential profiles are shown and finally, in
section V, some conclusions are drawn.
I. I NTRODUCTION
Nowadays, with the aim to obtain a better device performance and higher density integration, the dimension reduction
to nanometer scales of the MOSFET is an inevitable trend. At
this scale, various quantum effects become dominant over the
device performance. For instance, gate-oxide tunneling and
channel energy quantization, are some quantum mechanical
effects that affect the MOSFET performance [1]. Due to
this reduction in size, the gate oxide thickness is scaled to
nanometer dimensions and the substrate is highly doped to
avoid short channel effects. As a direct consequence, there
is a high electric field in the silicon-oxide interface, which
results in gate oxide tunneling. Besides, the quantum well
potential formed in the inversion layer confines the inversion
channel under the interface. Therefore, Classical Mechanics
is not appropriate to describe the charge transport of a nanoscale MOSFET and Quantum Mechanics has to be taken into
account. In confined quantum systems, as in this case, the
coupled Schrodinger-Poisson equation system is used in order
to model the charge transport of nano-scale MOSFETs.
In the last two decades, several research groups have
proposed different numerical methods to solve the coupled
Schrodinger-Poisson equations [2]-[8]. However, these numeric solvers are able to use only a small variety of potential
profiles in the gate oxide-substrate interface, such as symmetric, square, asymmetric and parabolic profiles. It clearly results
that in order to tackle the new effects arising in nano-scale
interfaces, where multiple gate oxide stacks are used, a wider
variety of gate oxide potential barrier profiles are required.
]
[
2 d2
h
2 + V (z) = E
2m dz
d2
q
= (N d n(z))
dz 2
(1)
(2)
(3)
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ISSN 977-2177-128009
initial condition into the Poisson equation. Due to the redistribution of charges, the new potential is calculated by solving
the Poisson equation and once again the Schrodinger equation
is solved with this new potential in an iterative manner.
The electrostatic potential is related to the potential energy
in the Schrodinger equation by equation 4, where Ec is the
potential energy profile due to the band offset at the interface
oxide-substrate.
Fig. 1.
V (z) = q + Ec
and
j1 2j + j+1
q
= (N d n(zj ))
2
z
Jj =
Im
m
dz
2
h
[j1 + (Vj 2j E) + j+1 ] = 0
2m 2
(8)
(9)
| V (z)i+1 V (z)i |
J(z) =
(4)
[
]
qh
i,j+1 i,j1
Im
m i
2z
(10)
(5)
(11)
df (z)
f (zj+1 ) f (zj1 )
=
dz
2z
(6)
d2 f (z)
f (zj1 ) 2f (zj ) + f (zj+1 )
=
dz 2
2z
(7)
Vg |z=0 = 0
and
Vg |z=L = VG
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ISSN 977-2177-128009
(a)
(b)
(a)
Fig. 2. Square Profile. (a) Shows the bending of the potential when Vg = 0
and (b) shows the electron density.
(a)
(b)
Fig. 4. Parabolic Profile. (a) Shows the bending of the potential when Vg = 0
and (b) shows the electron density.
(a)
(b)
(b)
Fig. 3. Step Profile. (a) Shows the bending of the potential when Vg = 0
and (b) shows the electron density.
Fig. 5. Gaussian Profile. (a) Shows the bending of the potential when Vg = 0
and (b) shows the electron density.
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ISSN 977-2177-128009
(a)
(b)
Fig. 6. High-K Dielectric Profile. (a) Shows the bending of the potential
when Vg = 0 and (b) shows the electron density.
Fig. 8.
(a)
(b)
Fig. 7. Triangular Profile. (a) Shows the bending of the potential when
Vg = 0 and (b) shows the electron density.
R EFERENCES
[10] Chang L. Yang K., Yeo Y-C., Choi Y-K., King T-J., and Hu C.
Reduction of direct-tunneling gate leakage current in double-gate and
ultra-thin body MOSFETs.Electron Devices Meeting. IEDM Technical
Digest. International. pp.521-524, 2001.
[11] Zhao Y. and White M.H. Modeling of Direct Tunneling Current through
Interfacial Oxide and High-K Gate Stacks. Solid-States Electronics Vol.
48, issue 10-11, 2004.
[1] Trellakis A. Andlauer and Vogl P. Efficient Solution of the SchrodingerPoisson Equations in Semiconductor Device Simulation Lecture Notes in
Computer Science 3743, pp. 602-609, 2006.
[2] Tan I-H, Snider G.L., Chang L.D. and Hu E.L. A self-consistent solution of Schrodinger-Poisson equations using nonuniform mesh.Journal of
Applied Physics Vol. 68, No. 8, October, 1990.
[3] Lo S.H,Buchanan D.A.and Taur Y. Modeling and characterization, of
quantization, polysilicon, depletion, and direct tunneling effects in MOSFETs with ultrathin oxides.IBM Journal of Research and Development
Vol. 43, No. 3, May, 1999.
[4] Abramo A.,Cardin A., Selmi L. and Sangiorgi E. Two- Dimensional
Quantum Mechanical Simulation of Charge Distribution in Silicon MOSFETs.IEEE Trans. on Electron Devices Vol. 47, No. 10, October, 2000.
[5] Driskill S.Heterostructure Device Simulations using a Self-Consistent
Schrodinger-Poisson Formulation.REU Conference, 2004.
[6] Curatola G., Doornbos G., Loo J., Ponomarev Y. and Iannaccone G.
Detailed Modeling of Sub 100nm MOSFETs Based on Schrodinger DD
Per Subband and Experiments and Evaluation of the Performance Gap
to Ballistic Transport. IEEE Transactions on Electronic Devices, Vol. 52,
No. 8, 2005.
[7] Datta S.Quantum Transport: Atom to Transitor. Cambridge University
Press, 2005.
[8] Karner M., Gehring A.,Holzer S. Pourfath M.,Wagner M.,Goes W.,
Vasicek M., Baumgarter O., Kernstock C., Schnass G., Zeiler G., Grasser
T., Kosina H. and Selberherr S. A multi-purpose Schrodinger-Poisson
Solver for TCAD applications. Journal of Computational Electronics Vol.
6, pp. 179-182, 2007.
[9] Darbandy G., Ritzenthaler R., Lime F., Garduo I., Estrada M., Cedeira A.
and Iiguez B. Analytical modeling of direct tunneling current through gate
stacks for the determination of suitable high-k dielectrics for nanoscale
double-gate MOSFETs. IOP Semiconductor Science and Technology Vol.
26, 2011.
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I.
INTRODUO
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Onde:
temp: temperatura ou nmero de iteraes
faz_perturbao(): a funo que move uma
clula, ou seja, faz a perturbao
novo_custo = custo novo, obtido depois que as
alteraes foram feitas, sendo que o custo o
HPWL
custo_atual: custo anterior a perturbao
rand: nmero aleatrio entre 0 e 1
deltacost: custo novo custo antigo
aceitar(): aceitar a perturbao
rejeitar(): rejeitar a perturbao
(a)
e delta/ T
(1)
(b)
Fig. 1 (a) HPWL inicial=45825 e (b) final=5065
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V. INTERFACE
Um dos objetivos do trabalho foi desenvolver uma
interface com facilidades para a visualizao da
execuo do posicionamento gerado pelo SA[11] ,
como apresentado na figura 3.
pesoHPWL*hpwl_atual+ pesoOverflow*overflow_atual,
Fig. 3 - Interface do SA
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VI. RESULTADOS
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
# clulas
100
350
700
805
599
458
235
522
255
315
153
425
# linhas
100
400
535
638
579
685
123
352
300
600
245
354
HPWL inicial
47915
182595
236925
274955
258905
302030
56470
155320
130520
268185
110440
163135
HPWL final
5120 (-89,3%)
49195(-72,06%)
26150 (-88.96% )
27080 (-90.15% )
46540 (-82.02% )
139390 (-53.85% )
4850 (-91.41% )
26235 (-83.11% )
27145 (-79.20% )
92820 (-65.39% )
20660 (-81.29% )
76545 (-53.08% )
51
407
1273
1572
978
637
193
815
225
329
88
550
Overflow final
0
0
946 (-25.69% )
1323 (-15.84% )
574 (-41.31% )
155 (-75.67% )
0
373 (-54.23% )
0
0
0
0
VII. CONCLUSES
O SA desenvolvido neste projeto permite ao usurio ter
uma boa visualizao de como o algoritmo funciona e
dinmico, permitindo a alterao de valores durante a
execuo. Outra facilidade que o algoritmo pode ser
executado passo a passo e isso permite compreender melhor
alguns conceitos bsicos do posicionamento, como por
exemplo HPWL. O SA tambm mais acessvel, uma vez
que foi desenvolvido para ser rodado via web e pode ser
acessado na pgina http://www.inf.ufrgs.br/~tmferla/teste/
sa.html.
Overflow inicial
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139
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Wilfrido Moreno
I.
INTRODUCTION
The
design
and
fabrication
process
for
microelectromechanical systems (MEMS) are a fundamental
aspect of device performance. MEMS capacitors have been
proposed for many applications such as sensors, radiators,
antennas (RF systems), mirrors (optical systems), and
material testing, among others. However, there are some
aspects that are important to consider in the design of the
structure (identifying and determining the critical parts of the
design); the structural materials used in the fabrication
process (determining the thickness of the film, the
combination of the materials and the deposition technique),
etc. In addition, the performance of MEMS devices is
affected by the mechanical behavior, whose residual stress
gradient can be controlled with the appropriate release
process for the MEMS structures. However, recent novel
designs for MEMS devices have successfully exploited the
effect of residual stress gradients to improve the performance
of such devices, as for instance in achieving a high ramp in
the fabrication process, specially, in the lithography steps of
the sensors, so to achieve more movement [1]. This work
presents the design of MEMS capacitors and a novel
fabrication process technique using surface micromachining
technology, which is fully compatible with integrated circuit
processes.
This paper is organized as follows. Section II first presents
the design of a MEMS capacitor, then establishes and
analyzes the materials for high frequency devices based on
their RF performance, which is evaluated considering
material losses and electromagnetic properties. Section III
C=
0rWL
g
(1)
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ISSN 977-2177-128009
Material
Resistivity
[-m]
Youngs
Modulus
[GPa]
Melting
point
[C]
Poisson
ratio
Tensile
Stress
[MPa]
124170
240370
Gold
Au
0.02214
79-109
1064
0.42-0.44
Titanium
Ti
0.42
116-120
1668
0.32
0.0282
70-79
660.4
0.35
40-50
0.01678
110-128
1084
0.34
210
Aluminum Al
Copper
Cu
(2)
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III.
FABRICATION PROCESS
(a)
(b)
(c)
(d)
(e)
A. Release Technique
A new technique for the release of the MEMS structure
was determined, based on a series of experiments, based on
both chemical and dry etching processes [9-11].
This new technique consists of three steps: First, a
chemical treatment using C5H9NO [12] and methanol in two
steps. The aim of the first step is to eliminate the sacrificial
layer, while methanol is used to clean the waste and to keep
the structure wet. Second, a thermal process at 120C in a
conventional oven in a nitrogen (N2) environment for 15 min
is performed to dry the structures. Finally, a dry etching
process to eliminate photoresist residues that could cause
stiction between the electrodes is undertaken using the
following conditions: oxygen (O2), 500 mTorr and 200 Watt
during 10 min. The great advantage is avoiding the use of a
Critical Point Drying (CPD) process [13], which has several
limitations, such as surface tension effects, small sample size
and the use of CO2. The procedure herein outlined is highly
reliable and inexpensive, simple and easily done.
(f)
(g)
(h)
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ISSN 977-2177-128009
(a)
(i)
Figure 4. Fabrication Process. (a) Standard wafer cleaning followed by the
thermal growth of SiO2, (b) 0.5m thick Titanium deposited by sputtering,
(c) 1.5m thick aluminum deposited by sputtering, (d) Ground plane
patterned with Ti and Al by lithography, (e) Dimple formed by SU8-2002
pattering, (f) AZ-4260 sacrificial layer forming, (g) Definition of anchor by
pattering, (h) Ti-Al deposited by sputtering and (i) MEMS release process.
IV.
(b)
!
Figure 6. Profile in the X axe of the MEMS capacitor by the interferometry
technique.
ACKNOWLEDGMENT
The authors wish to acknowledge CONACyT, Mexico, for
the partial support of this work through Grant 83774-Y, and
FORDECyT project number 115976. Georgina Rosas also
thanks CONACyT for the scholarship to undertake doctoral
studies, number 102735 and for the support in carrying out
this research. Special recognition is due to the
Nanotechnology Research Center (NREC) at the University of
South Florida (USF) for their valuable support during the
fabrication of the device.
REFERENCES
[1]
143
Kuang-Shun Ou, Kuo Shen Chen, Tian-Shiang Yang and Sen-Yun Lee,
A Novel Semianaltical Approach for Finding Pull-In Voltages of
Micro Cantaliver Beams Subjetect to Electrostatic Loads and Residual
Stress Gradients, Journal of Microelectromechanical Systems, Vol. 20,
No. 2 april 2011.
ISSN 977-2177-128009
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
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ISSN 977-2177-128009
I.
INTRODUO
II.
FUNES DE HASH
145
ISSN 977-2177-128009
SHA-3
KECCAK
146
ISSN 977-2177-128009
especficas
para
Keccak-f[b](A) {
forall i in 0nr-1
A = Round[b](A, RC[i])
return A
}
Round[b](A,RC) {
step
C[x] = A[x,0] xor A[x,1] xor A[x,2] xor A[x,3] xor A[x,4],
forall x in 04
D[x] = C[x-1] xor rot(C[x+1],1),
forall x in 04
A[x,y] = A[x,y] xor D[x],
forall (x,y) in (04,04)
and steps
B[y,2*x+3*y] = rot(A[x,y], r[x,y]),
Absorbing phase
forall block Pi in P
S[x,y] = S[x,y] xor Pi[x+5*y],
S = Keccak-f[r+c](S)
Squeezing phase
Z = empty string
while output is requested
Z = Z || S[x,y],
S = Keccak-f[r+c](S)
return Z
step
A[x,y] = B[x,y] xor ((not B[x+1,y]) and B[x+2,y]), forall (x,y) in (04,04)
}
step
A[0,0] = A[0,0] xor RC
return A
B. Funo de Esponja
A funo Keccak[r,c] utiliza a construo em esponja,
que recebe um valor de entrada de tamanho varivel e gera
uma sada de tamanho arbitrrio [7]. A funo recebe dois
parmetros, onde: r o parmetro de bitrate e c o parmetro
de capacidade.
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V.
SMART CARDS
Recursos suportados
Tipos boolean, byte e short
Arrays unidimensionais
Pacotes Java
Classes,interface e exceptions
JAVA CARDS
Recursos no suportados
Theads
Tipos double, float e long
Arrays Multidimensionais
Char e Strings
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ISSN 977-2177-128009
Tamanho da
Funo (bytes)
1275
EEPROM
Utilizado (bytes)
2579
RAM Utilizada
(bytes)
703
Funo
MD5
SHA
Keccak
Tempo aproximado de
execuo (s)
0,194
0,196
37,392
Tamanho
hash (bits)
256
300
224
CONCLUSO
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ISSN 977-2177-128009
150
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German Alvarez-Botero
galvarez@inaoep.mx, rmurphy@inaoep.mx, reydezel@inaoep.mx
I. I NTRODUCTION
The requirements of modern communication systems put
stringent demands on semiconductor technologies for providing performance at a low cost [1]. BiCMOS technology based
on SiGe heterojunction bipolar transistors (HBTs) provides
an attractive solution to address these exigencies, due to the
inherent properties of the SiGe HBTs, such as low noise,
high linearity, and low power consumption. However, these
remarkable characteristics can be considerably degraded in the
microwave range due to the influence of the substrate parasitic
effects, which become more important as the operation frequency rises. For this reason, for advanced RF circuit design,
the impact of the substrate effects must be correctly accounted
for in the modeling of the HBTs.
For an adequate modeling of the substrate effects, it is
necessary developing physically based models according to
the device structure. For instance, in the present analysis it
is important considering the buried layer (n+) (referred to in
subsequent as the sub-collector), the depletion region of the
sub-collector-substrate junction, the resistive nature of the bulk
substrate (p), and the channel stopper (p). A cross-section
of the HBT under study showing this structure is presented in
Fig. 1.
Substrate contact
p+
Base contact
Emitter contact
SiGe:C layer
Collector contact
n+
p
n+
n-
Fig. 1.
Depletion region
Substrate
contact
p+
Re
n+
p
Cbe
Rb
Rbci ie
Cbcx
Cbci
Rbcx
nRsub
Ysub
Rbe
Rbi
Collector
contact
Rc
n+
Csub
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ISSN 977-2177-128009
II. E XPERIMENT
On-wafer two-port S-parameter measurements up to
40 GHz, using a vector network analyzer (VNA) and groundsignal-ground (GSG) coplanar RF probes with a pitch of
100 m, were performed to a common-emitter SiGe HBT,
fabricated on p-type Si substrate in a 0.13 m BiCMOS
technology. Using an off-wafer LRM (line-reflect-match) procedure, and an impedance-standard-substrate, the equipment
was previously calibrated up to the probe tips, establishing a
reference impedance of 50 .
Operating the transistor under cold-HBT condition, which
is defined as the condition when the emitter-base junction
and base-collector junction are zero biased, and therefore
both junctions are depleted, results in a simplified equivalent
circuit that allows an accurate characterization of the substrate
effects. Thus, the device under test (DUT) was biased at
VBE = VBC = 0 in order to obtain the S-parameters used
for developing the model proposed in this work. Afterwards,
the experimental data were de-embedded from pad parasitics
by applying a three-step procedure and the measurements
collected to open and a short dummy structures. [3].
Port 1
Port 1
Cbe
Port 2
(1)
(2)
Thus, plotting (1) and (2) versus , the values of Cbe and
Cbc can be obtained from the respective slopes, as illustrated
in Fig. 5.
Im (-Y12) (mS)
Im (Y11+Y12) (mS)
15
Experimental data
Linear regression
10
5
Slope:
Cbe = 37.85 pF
0
4
Slope:
Cbc = 11.97 pF
0
0
10
20
30
40
f (GHz)
Cbci
Rbi
Ysub
Cbcx
Base
Cbe
Collector
Emitter/Substrate
Cbc
Base
Collector
Ysub
Fig. 5.
Port 2
Emitter/Substrate
Fig. 3. Small-signal equivalent circuit model for a SiGe HBT biased at
VBE = VBC = 0.
Additionally, for a bipolar transistor fabricated on a highresistivity substrate, the value of the intrinsic base resistance is
much lower than Re(Zsub ), where Zsub = 1/Ysub . Therefore,
(3)
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ISSN 977-2177-128009
Substrate
contact
Emitter contact
Rbe
Rbi
Cbcx
Rbcx
p+
n+
p
Cbe
Rbci ie
Cbci
n+
n-
csub
rsub
Collector
contact
csub
csub
rsub
p-
rsub
Ysub
Base
contact
Experimental data
Distributed model
Lumped model
-1
-2
From [5][7], it is possible obtaining an analytical expression for Ysub , this is:
Ysub =
jcsub
tanh( jrsub csub )
rsub
50
Experimental data
Distributed model
40
30
20
1/2
-12
Im (Ysub)/ (S/rad 10 )
10
0
40
Im(Ysub)/ = csub
-40
0
(4)
2rsub csub
Re(Ysub ) =
(5)
rsub
Im(Ysub )/ = csub
(6)
-20
10
20
30
40
f (GHz)
Fig. 8. Comparison between experimental and simulated data for the S22 parameter using a distributed network for modeling the substrate parasitics in
a SiGe HBT.
V. C ONCLUSIONS
A distributed model for representing the substrate parasitic
effects in a SiGe HBT has been proposed and analyzed. Also
an analytical extraction method to determine its constitutive
parameters, extracted from S-parameters measurements has
been proposed. A very good simulation-experiment correlation
for the output electrical characteristics of the HBT up to
40 GHz has been obtained, which is primordial for accurate
circuit behavior prediction and circuit optimization.
The proposed model represents an important contribution in
the field of physics-based equivalent circuit modeling since it
helps to understand the substrate effects. Thus, the proposal
can be used for improving the integrated circuit design,
evaluating the process technology or optimizing the device
structure.
20
VI. ACKNOWLEDGEMENTS
10
20
30
40
f (GHz)
The authors acknowledge IMEC, Leuven, Belgium for supplying the test structures. They also acknowledge the partial
support of this project by CONACyT through Grant 83774Y, and the scholarship to undertake doctoral studies number
213292.
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R EFERENCES
[1] A. Joseph, J. Dunn, G. Freeman, D. Harame, D. Coolbaugh, R. Groves,
K. Stein, R. Volant, S. Subbanna, V. Marangos, S. Onge, E. Eshun,
P. Cooper, J. Johnson, J. Rieh, B. Jagannathan, V. Ramachandran,
D. Ahlgren, D. Wang, and X. Wang, Product applications and technology
directions with SiGe BiCMOS, IEEE Journal of Solid-State Circuits,
vol. 38, no. 9, pp. 14711478, Sep. 2003.
[2] S. Fregonese, D. Celi, T. Zimmer, C. Maneux, and P. Sulima, A Scalable
Substrate Network for Compact Modelling of Deep Trench Insulated
HBT, Solid-State Electronics, vol. 49, no. 10, pp. 16231631, Oct. 2005.
[3] R. Torres-Torres, R. Murphy-Arteaga, and J. A. Reynoso-Hernandez,
Analytical Model and Parameter Extraction to Account for the Pad
Parasitics in RF-CMOS, IEEE Transactions on Electron Devices, vol. 52,
no. 7, pp. 13351342, 2005.
[4] M. Reisch, High-Frequency Bipolar Transistors, 1st ed. Springer, 2003.
[5] E. Abou-Allam and T. Manku, A Small-Signal MOSFET Model for
Radio Frequency IC Applications, IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 16, no. 5, pp.
437447, 1997.
[6] , An Improved Transmission-Line Model for MOS Transistors,
IEEE Transactions on Circuits and Systems-II, vol. 46, no. 11, pp. 1380
1387, 1999.
[7] M. Vaidyanathan and D. L. Pulfrey, Extrapolated fmax of Heterojunction
Bipolar Transistors, IEEE Transactions on Electron Devices, vol. 46,
no. 2, pp. 301309, 1999.
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II.
EXPERIMENT
I.
INTRODUCTION
A Vector Network Analyzer (VNA) and ground-signalground coplanar Cascade probes of 100 m pitch were
155
ISSN 977-2177-128009
Im(Y11 ) C gs + C gd + C gb
Z1 =
Z2 =
Z3 =
Im(Y22 ) C gd + C jd
)2
(5)
(6)
1
1
1
1
jC gd C gb
+
+
C gd C jd C gb
Im
1
1
1
jC gd C jd
+
+
C gd C jd C gb
1
1
1
1
jC gbC jd
+
+
C gd C jd C gb
1
jC gs
1
1
1
1
1
Z
+
1 Z4
+ Z2
Y22
(2)
156
(7)
Z 4 = Rg
(1)
(4)
b)
Im(Y12 ) C gd
(3)
Re(Y22 ) 2 Rb C jd 2
III.
Re(Y11 ) 2 Rg C gs + C gd + C gb
a)
C gs C gd
1
C jd +
Im(Z 22 )
C
gs + C gd
Z3
(8)
(9)
(10)
= Im(Y ') = C js
ISSN 977-2177-128009
(11)
Experimental data
Linear regression
Im (Y22) (mS)
- Im (Y12) (mS)
f = 20 GHz
4
-15
(F)
10
12
-15
Slope: Cgd+Cjd=155.5 x 10
0
0.0
14
f = 4 GHz
2
1
0
0
Experimental data
Linear regression
0.5
1.0
1.5
10
(rad x 10 )
(F)
2.0
2.5
10
(rad x 10 )
-15
16
(F)
Im (Y11) (mS)
f = 4 GHz
Experimental data
Linear regression
Experimental data
Linear regression
12
f = 20 GHz
8
4
-15
(F)
0
0.0
0.5
1.0
1.5
2.0
2.5
10
12
14
10
(rad x 10 )
10
(rad x 10 )
5.4
-4
Experimental data
Linear regression
Re (Y22) ( x 10
Re (Y11) ( x 10
-4
4
7.2
f = 20 GHz
3.6
1.8
-26
F)
0.0
0
20
40
60
80
2
100
2
120
140
Experimental data
Linear regression
f = 4 GHz
2
1
F)
160
20
(rad x 10 )
20
(rad x 10 )
12
Im (Y') (mS)
-25
Experimental data
Linear regression
f = 20 GHz
f = 6 GHz
6
-15
(F)
0
0
10
12
14
10
(rad x 10 )
Fig. 3. Linear regression of experimental data for the parameter extraction of an RF-NMOS device, with Lm=80nm, Wf=3um and NF=64. Also, Vgs, Vds, Vbs are
equal to 0V.
TABLE I.
EXTRACTED PARAMETER VALUES
Parameter
Cgd
Cjd
Cgs
Cgb
Rg
Rb
Cjs
Extracted value
60.2
102.5
62.2
3.0
2.8
50.1
98.2
Unit
fF
fF
fF
fF
fF
a)
b)
Fig. 4. The equivalent circuit for Y22. The nodes are drain (D), source (S) and
substrate (B). Also, Vgs, Vds, Vbs are equal to 0V.
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ISSN 977-2177-128009
Phase(S22) (Deg.)
0
-2
-4
Experimental data
With Cjs and Cgb
0
-30
-60
-90
0
-0.4
-0.8
Experimental data
With Cjs and Cgb
-1.2
12
16
20
Frequency (GHz)
Fig. 7. Experimental and simulated data with/without Cjs and Cgb for the
magnitude and phase of S22. Also, Vgs, Vds, Vbs are equal to 0V.
-60
-90
0
12
16
20
Frequency (GHz)
-2.1
-2.4
-2.7
0
-15
12
-30
-45
Experimental data
With Cjs and Cgb
-60
14
16
18
20
Frequency (GHz)
Fig. 8. Experimental and simulated data of the proposed model and of the
model in [2] for S22. Also, Vgs, Vds, Vbs are equal to 0V.
90
0.0
60
30
Fig. 5. Experimental and simulated data with/without Cjs and Cgb for the
magnitude and phase of S11. Also, Vgs, Vds, Vbs are equal to 0V.
Phase(S12) (Deg.)
Experimental data
Proposed model
Model in [2]
-30
Phase(S11) (Deg.)
-1.8
0
0
0
12
16
20
Frequency (GHz)
Fig. 6. Experimental and simulated data with/without Cjs and Cgb for the
magnitude and phase of S12. Also, Vgs, Vds, Vbs are equal to 0V.
-0.8
Experimental data
Proposed model
Model in [2]
-1.2
-0.4
12
16
20
Frequency (GHz)
Fig. 9. Experimental and simulated data of the proposed model and of the
model in [2] for S11. Also, Vgs, Vds, Vbs are equal to 0V.
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IV.
REFERENCES
CONCLUSIONS
[1]
[2]
[3]
[4]
[5]
[6]
ACKNOWLEDGMENT
The authors acknowledge IMEC, Leuven, Belgium for
supplying the test structures. They also thank CONACyT,
Mxico, for the partial support of this project through Grant
83774-Y, and the scholarships awarded to undertake master
and doctoral studies, numbers 375862 and 213292,
respectively.
[7]
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Facultad de Instrumentacin Electrnica; 2 Department of Mathematics; 3Departament of Mathemtics and Statistics; 4Departamento
de Electrnica
1
Universidad Veracruzana; 2Ege University; 3 University of South Florida; 4Instituto Nacional de Astrofsica, ptica y Electrnica
1
Xalapa, Veracruz, Mxico; 2Izmir, Turkey; 3Tampa, FL, USA; 4Sta. Mara Tonantzintla, Puebla, Mxico
hvazquez@uv.mx
AbstractEn este artculo se muestra cmo se puede adaptar y
I.
INTRODUCCIN
TCNICAS DE TRAZADO
H ( f ( x), 1 , 2 ) = f ( x, 2 ) (1 1 ) f ( xi , 0)
(1)
(2)
HOMOTOPA MULTIPARAMTRICA
f ( x) = 0 donde f : n n
H ( f (x), 1 , 2 , , k ) = 0
donde H : n +1 n .
(3)
(4)
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ISSN 977-2177-128009
H ( f ( x), 1 , 2 ) = f ( x),
(5)
M ( 1 , 2 ) = 1 +
2
" A B B 1+ A
2
$
+
$ A B 1
A B 1
#
2.
) %'
) '&
(
(
(6)
() (
) (
)
+ ( c ) + ( c )
S = x1 c1 + x2 c2 +
2
n+1
n+2
(7)
C () = ( 1 cn+1 ) + ( 2 cn+2 ) r 2
(8)
(a)
(b)
Fig. 1 a) Funcin paramtrica; b) Tcnica de las hiperesferas.
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+ 2.863168 I s (exp(40v2 ) 1) 12
f 2 = 5.4v1 + 3.58I s (exp(40v1 ) 1)2 + 6.62 I s ( exp ( 40v2 ) 1)
+ v3 + 0.7 I s ( exp ( 40v3 ) 1) + 0.5I s ( exp ( 40v4 ) 1) 22
f3 = 6.103168I s ( exp ( 40v3 ) 1) 2.863168I s ( exp ( 40+v4 ) 1) 2
+ 4.36634v4 12
f 4 = v1 + 0.7 I s ( exp ( 40v1 ) 1) 2 + 0.5I s ( exp ( 40v2 ) 1)
+ 5.4v3 + 3.58I s ( exp ( 40v3 ) 1) + 6.62 I s ( exp ( 40v4 ) 1) 2 20
CONCLUSIN
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163
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Dissipao de potncia em
Redes de Transistores versus Clulas Padro
Gerson Scartezzini, Ricardo Reis
PPGC-PGMicro, Instituto de Informtica
Universidade Federal do Rio Grande do Sul UFRGS
Porto Alegre, Brazil
gerson.scartezzini@inf.ufrgs.br, reis@inf.ufrgs.br
I.
INTRODUO
METODOLOGIA
164
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(1)
IV.
DESENVOLVIMENTO E RESULTADOS
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A. Projeto e Dimensionamento
Para o desenvolvimento deste experimento, foi utilizado
um PDK (Process Design Kit) comercial de 0.35m da
empresa AMS (Austria Micro Systems). Mesmo no sendo
um nodo tecnolgico ideal para a anlise de potncia esttica,
sua utilizao j uma boa referncia para se comparar
circuitos desenvolvidos por diferentes metodologias.
A primeira etapa deste experimento foi desenvolver um
conjunto de 14 funes do tipo AOI (and, or, inverter) e 14 do
tipo OAI (or, and, inverter), em um total de 28 funes
lgicas. Para cada uma destas funes, foi descrito uma rede
de transistores utilizando a linguagem Spice.
A partir destas descries, tanto a rede de pull-up, como
pull-down, foram dimensionadas com o mesmo par de w
(wn=1m e wp=1.6*wn). De forma a manter o mesmo atraso
em todas as estruturas, utilizou-se o mtodo Logic Effort [12] ,
em cada uma das descries.
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TABELA 2. COMPARAO ENTRE FUNES IMPLEMENTDAS UTILIZANDO CLULAS PADRO E REDES DE TRANSISTORES.
Funo
#
F=(A*B)+C
F=(A*B)+C+D
F=(A*B)+(C*D*E)
F=(A*B)+(C*D)
F=(A*B)+(C*D)+E
F=(A*B)+(C*D)+(E*F*G)
F=(A*B*C)+(D*E*F)
F=(A*B*C)+(D*E*F)+(G*H)
F=(A*B*C)+(D*E*F)+G
F=(A*B*C)+D
F=(A*B*C)+(D*E)+F
F=(A*B*C)+D+E
F=(A*B)+(C*D)+(E*F)
F=(A*B*C)+(D*E*F)+(G*H*I)
F=(A+B)*C
F=(A+B)*C*D
F=(A+B)*(C+D+E)
F=(A+B)*(C+D)
F=(A+B)*(C+D)*E
F=(A+B)*(C+D)*(E+F+G)
F=(A+B+C)*(D+E+F)
F=(A+B+C)*(D+E+F)*(G+H)
F=(A+B+C)*(D+E+F)*G
F=(A+B+C)*D
F=(A+B+C)*(D+E)*F
F=(A+B+C)*D*E
F=(A+B)*(C+D)*(E+F)
F=(A+B+C)*(D+E+F)*(G+H+I)
V.
10
12
18
16
20
26
20
28
22
12
20
14
26
30
10
12
18
16
20
26
20
28
22
12
20
14
26
30
Implementao em
Clulas Padro
Potncia
Leakage
Atraso
dinmica
(nW)
mdio(ns)
mdia (W)
0,158
0,146
0,102
0,125
0,118
0,104
0,108
0,097
0,177
0,128
0,116
0,172
0,108
0,099
0,167
0,083
0,074
0,246
0,094
0,084
0,182
0,075
0,067
0,251
0,085
0,077
0,176
0,131
0,119
0,105
0,095
0,087
0,171
0,110
0,102
0,102
0,094
0,085
0,242
0,068
0,061
0,259
0,148
0,140
0,100
0,114
0,108
0,104
0,105
0,096
0,178
0,124
0,113
0,173
0,101
0,092
0,168
0,081
0,072
0,247
0,091
0,083
0,182
0,073
0,065
0,252
0,079
0,072
0,175
0,123
0,115
0,105
0,089
0,081
0,171
0,100
0,094
0,103
0,090
0,080
0,242
0,066
0,059
0,260
#
6
8
10
8
10
14
12
16
14
8
12
10
12
18
6
8
10
8
10
14
12
16
14
8
12
10
12
18
Implementao com
Redes de Transistores
Potncia
Atraso
Leakage
dinmica
mdio(ns)
(nW)
mdia (W)
0,126
0,135
0,037
0,103
0,112
0,041
0,080
0,085
0,040
0,093
0,105
0,038
0,087
0,096
0,039
0,064
0,073
0,042
0,066
0,079
0,042
0,060
0,070
0,043
0,065
0,076
0,040
0,109
0,113
0,042
0,074
0,085
0,040
0,089
0,099
0,040
0,073
0,081
0,039
0,053
0,063
0,044
0,124
0,136
0,036
0,097
0,109
0,040
0,080
0,093
0,040
0,094
0,107
0,039
0,081
0,093
0,041
0,064
0,076
0,042
0,072
0,083
0,042
0,057
0,069
0,043
0,063
0,076
0,042
0,099
0,111
0,040
0,072
0,084
0,041
0,081
0,096
0,041
0,069
0,080
0,042
0,056
0,067
0,044
Reduo mdia (%)
CONCLUSES
Reduo
de # (%)
Reduo
do atraso
mdio (%)
40,0
33,3
44,4
50,0
50,0
46,2
40,0
42,9
36,4
33,3
40,0
28,6
53,8
40,0
40,0
33,3
44,4
50,0
50,0
46,2
40,0
42,9
36,4
33,3
40,0
28,6
53,8
40,0
41,4
20,4
17,6
26,4
27,7
20,0
22,8
29,2
19,2
24,0
17,0
22,8
19,1
22,1
22,8
16,5
15,2
23,6
24,1
19,6
20,3
20,6
20,9
20,0
19,6
19,9
18,7
23,3
14,2
21,0
Reduo
Reduo
da da
potncia do Leakage
(%)
dinmica
mdia(%)
7,8
63,8
5,2
61,0
12,2
77,6
9,1
77,8
3,6
76,5
2,2
82,8
6,1
76,9
-4,3
82,8
1,6
77,1
5,0
60,3
1,6
76,8
3,6
60,9
4,3
83,8
-3,9
83,1
2,8
63,6
-0,6
61,0
3,2
77,4
5,4
77,6
-0,8
75,6
-5,5
82,8
0,2
77,0
-6,9
82,9
-6,2
76,3
3,4
62,1
-4,2
75,8
-2,0
60,5
0,2
82,7
-15,0
83,2
1,0
74,3
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VI.
TRABALHOS FUTUROS
Kim, N.S.; Austin, T.; Baauw, D.; Mudge, T.; Flautner, K.; Hu,
J.S.; Irwin, M.J.; Kandemir, M.; Narayanan, V. Leakage Current:
Moores Law Meets Static Power; In IEEE Computer Society; P. 6875; Vol. 36, 2003.
[2] Jeong T. T. and Ambler P. A.; Design Trade-Offs and Power
Reduction Techniques for High Performance Circuits and System, In
ICCSA 2006, pp. 531-536, vol. 3984.
[3] Reis, R. e Cols., Concepo de Circuitos Integrados, 2 edition..
Srie Livros Didticos do Instituto de Informtica, ed. Bookmann,
Porto Alegre, 2009, 258 Pginas. ISBN 9788577803477.
[4] Henzler, Stephan; Introduction to Low-Power Digital Integrated Circuit
Design - Power Management of Digital Circuits in Deep Sub-Micron
CMOS Technologies; In: Springer Series in Advanced
Microelectronics, 2007, Volume 25, 1-21, DOI: 10.1007/1-4020-5081X_1.
[5] Borkar, S.; , Design challenges of technology scaling, Micro, IEEE ,
vol.19, no.4, pp.23-29, Jul-Aug 1999.
[6] Reis, A; Reis, R; Auvergne D.; Robert M., Library Free Technology
Mapping, In: IFIP TC10 WG10.5 International Conference on Very
Large Scale Integration, Gramado, Brazil, August 26-30, 1997. pp. 303314, ISBN: 0 412 82370 5.
[7] Ziesemer, A.; Lazzari, C., Reis, R., Transistor Level Automatic Layout
Generator for non-Complementary CMOS Cells, In: IFIP/CEDA
VLSI-SoC2007, International Conference on Very Large Scale
Integration, Atlanta, USA, October 15-17, 2007. pp. 116-121, ISBN:
978-1-4244-1710-0.
[8] Reis, R.; , "Physical Design Automation at Transistor Level,"
NORCHIP, 2008. , vol., no., pp.241-245, 16-17 Nov. 2008 doi:
10.1109/NORCHP.2008.4738270
[9] J. A. Butts and G. S. Sohi. A static power model for architects, In
Proc. of the 33rd Annual Intl. Symp. on Microarchitecture, 2000.
[10] Gonzalez, R.; Gordon, B.M.; Horowitz, M.A.; , "Supply and threshold
voltage scaling for low power CMOS," Solid-State Circuits, IEEE
Journal of , vol.32, no.8, pp.1210-1216, Aug 1997. Doi:
10.1109/4.604077
[11] De-Shiuan Chiou; Shih-Hsin Chen; Shih-Chieh Chang; Chingwei Yeh; ,
"Timing driven power gating," Design Automation Conference, 2006
43rd ACM/IEEE , vol., no., pp.121-124, 0-0 0 doi:
10.1109/DAC.2006.229189
[12] Sutherland, I.; Sproull, B.; Harris, D. Logical Effort: designing fast
Cmos Circuits, San Francisco, CA, USA: Morgan Kaufmann
Publishers Inc., 1999.
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ALGORITMO RAPIDO
PARA LA BUSQUEDA
DE AUDIO POR CONTENIDO
1
Universidad Santo Tomas, Facultad de Ingeniera Electronica, Bogota, Colombia.
Universidad Santo Tomas, Facultad de Ingeniera de Telecomunicaciones, Bogota, Colombia
3
University of Sao Paulo Microelectronics Laboratory LME, Sao Paulo, Brazil
adriana.sanabria@ieee.org, jaimevitola, cesarpedraza@usantotomas.edu.co, jsepulveda@lme.usp.br
2
mas busquedas
en tiempo real.
de comparacion DTW (DynamicT imeW arping). La aplicacion especfica que se le ha dado a este algoritmo es
el reconocimiento de anuncios comerciales transmitidos por
una emisora de radiodifusion. En la seccion II se expone el
problema de la busqueda de audio por contenido. Luego en la
seccion III se propone un modelo de algoritmo rapido para la
extraccion firmas digitales, comparacion y busqueda en tiempo
real de anuncios comerciales. Posteriormente en la seccion
4 se muestran los resultados de los experimentos realizados
para verificar el funcionamiento del algoritmo y finalmente se
muestran las conclusiones.
.
I. I NTRODUCCI ON
Existe gran interes en el reconocimiento de pistas o piezas
de audio con diversos fines, por ejemplo monitorear emisoras
de radio, reconocer la legalidad de los contenidos publicados
en la Internet o identificar canciones. Para lograrlo han sido
planteadas e implementadas diferentes tecnicas que permiten
identificar una trama de audio entre las demas.
Para conseguir este reconocimiento existen dos mecanismos: agregar una firma digital que contenga informacion
como el ttulo y nombre del autor que se introduce en la
trama de audio sin afectar la percepcion que tiene el odo
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PARA LA BUSQUEDA
DE AUDIO POR CONTENIDO
Extracci
on de la firma
Archivo
de
audio
Se han planteado diferentes metodos para hallar los coeficientes de prediccion lineal como son:
1) Covarianza
2) Autocorrelacion
3) Enrejado
4) La formulacion inversa
5) La estimacion del espectro
6) La maxima probabilidad
7) El producto interno.
Para el caso particular de este algoritmo se implemento el
metodo de Autocorrelacion inventado por N. Levinson en 1947
y modificado por J. Durbin en 1959.
El cepstrum es una transformacion de la senal de audio
con dos principales propiedades: separa las componentes y las
cmbina linealmente [7]. Esta tecnica fue propuesta por Bogert,
Healy y Tukey (1963) y Noll(1967) El cepstrum real de una
senal x(n) se calcula como lo muestra la ecuacion 2.
Se
nal de
audio
Normalizaci
on
Normalizaci
on
Enventanamiento
Enventanamiento
LPC Cepstrum
LPC Cepstrum
Firma de audio
Firma de audio
DTW
Normalizaci
on
Derivada
C(n) = F 1 {log|F(x(n))|}
coincidencia?
Si
(2)
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ALGORITMO RAPIDO
PARA LA BUSQUEDA
DE AUDIO POR CONTENIDO
Serie temporal 1
g=
i(j1)
si
j, i = 0
si
i = 0, j > 0
M(i1)j
si j = 0, i > 0
M (i 1)(j 1))
si
i, j > 0
(4)
n,m
Serie temporal 2
Serie
de
tiempo
A
1,1
Serie de tiempo B
Mij = (Ai Bj )2 + g
Playa del Carmen, Mexico, February 29-March 2, 2012
(3)
IV. R ESULTADOS .
A. Experimentos.
Se realizaron dos tipos de experimentos para validar el
algoritmo. El primero consistio en verificar los tiempos de
respuesta para la busqueda de pistas de audio de 5, 10, 20 y
30 segundos en una trama de audio de 3600 segundos. Las
longitudes de las pistas fueron seleccionadas de acuerdo a
las duraciones tpicas de anuncios comerciales de la radio.
El segundo experimento consistio en verificar la efectividad
del algoritmo respecto a su confiabilidad en la diferenciacion
de distintos anuncios o posibles combinaciones de audio entre
s. Para esto, se realizo un banco de pruebas en el que se
generaron pistas de forma aleatoria y cada cierto tiempo se
insertaron pistas a buscar tambien de forma aleatoria.
B. Tiempos de respuesta.
Para obtener los tiempos de respuesta se lanzo el algoritmo
en un computador con un procesador core i7 con 4GB de
memoria. La tabla I muestra los valores de tiempo obtenidos
y aquellos con la tecnica de la correlacion [11]. Se observa
que los tiempos de respuesta son notablemente menores,
obteniendose valores de speedup de hasta 8 para el caso del
comercial de 30 segundos. De lo anterior se deduce que es
mas eficiente buscar pistas de audio de mayor longitud.
Pista con longitudes de 30, 20 y 10 segundos fueron
insertadas de forma aleatoria en la trama de audio de 3600
segundos. Las figuras 4, 5 y 4 muestran la probabilidad de
encontrar dicha pista calculada por el algoritmo en prueba.
Se observa una probabilidad cercana a uno en los puntos en
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ALGORITMO RAPIDO
PARA LA BUSQUEDA
DE AUDIO POR CONTENIDO
TR algoritmo
37.25
58.28
101.62
141.13
Speedup
5.2
6.57
7.51
8.08
0.95
Probabilidad
Pista 30s
0.9
0.85
0.8
0.75
0.7
0.65
0
500
1000
1500
2000
Tiempo [s]
2500
3000
3500
4000
500
1000
1500
2000
2500
Tiempo en que se inserta la pista [s]
3000
3500
Probabilidad
Pista 20s
500
1000
1500
2000
Tiempo [s]
2500
3000
3500
4000
Probabilidad
Pista 10s
500
1000
1500
2000
Tiempo [s]
2500
3000
3500
4000
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PARA LA BUSQUEDA
DE AUDIO POR CONTENIDO
[3] L. Shen, Y. Guan, Y. Wu, and Y. Zhao, Fast audio fingerprint search
strategy for song identification, Networking and Digital Society, International Conference, pp. 259262, 2009.
[4] G. Clarence, Robust computer voice recognition using improved , New
Trends in Information and Service , International Conference, pp. 835
840, 2009.
[5] C. Di Brina, R. Niels, A. Overvelde, G. Levi, and W. Hulstijn, Dynamic
time warping: a new method in the study of poor handwriting., Human
movement science, vol. 27, no. 2, pp. 24255, 2008.
[6] J. Coleman, Introducing speech and language processing. Press syndicate of the University of Cambridge, 2005.
[7] J. Deller, J. Hansen, and J. Proakis, Discrete Time Processing of Speech
Signals. Wiley-Interscience, 2000.
[8] M. Muller, Information Retrieval for Music and Motion. Springer, 2007.
[9] V. Niennattrakul and C. A. Ratanamahatana, On Clustering Multimedia
Time Series Data Using K-Means and Dynamic Time Warping, 2007
International Conference on Multimedia and Ubiquitous Engineering
(MUE07), pp. 733738, 2007.
[10] E. K. y M. Pazzani, Derivative Dynamic Time Warping, Science,
pp. 111, 2000.
[11] J. Martinez, J. Vitola, A. Sanabria, and C. Pedraza, Fast parallel audio
fingerprinting implementation in reconfigurable hardware and gpus, in
Programmable Logic (SPL), 2011 VII Southern Conference on, pp. 245
250, april 2011.
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Calibration
DUT
Deembedding
P2
P1
I. INTRODUCTION
Modeling and characterizing the small-signal behavior of
semiconductor devices on-wafer require reliable experimental
data, which are collected using test equipment that introduces
systematic errors [1]. These errors can be removed using
mathematical algorithms that move the measurement reference
plane closer to the device-under-test (DUT) [2]. Ideally, this
reference plane must see only the DUT so that the
experimental data contain only information about the desired
device.
When performing on-wafer measurements, the correction
algorithms are categorized in two types: calibration and
deembedding procedures. In essence, these two types of
procedures are used with the same purpose. However, the term
calibration procedure is used to refer to the procedure that
removes the errors introduced by the parasitics associated with
the cables, connectors, probes, and other accessories needed to
apply and sense signals to and from the DUT [3], [4]. On the
other hand, a deembedding procedure is that used to remove
the effects associated to the on-wafer pads and interconnects
that serve as interface between the DUT and the probing pads.
For clarifying the difference between these two procedures,
Fig. 1 shows the measurement planes after performing
calibration and deembedding of measured two-port network
parameters.
Whereas the calibration procedure is typically performed
by using data measured off-wafer to an impedance-standardsubstrate (ISS) provided by the probe manufacturer [3], for
carrying out a deembedding, measuring additional on-wafer
dummy structures is needed [5],[6]. Unfortunately, these
dummy structures take precious space from the die, which
increases the corresponding cost and in many cases is not
available. For this reason, it is desirable to use the minimum
This project was sponsored by CONACyT Mexico under grant #128818 and
scholarship #213385
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Y3
Z1
Z2
Y1
Y2
P1
P2
Z3
Fig. 3. Model representing the DUT embedded in the parasitic effect from
pad structures.
Y3
Fig. 2. Micrographs of the fabricated test structures.
Y1
Y3
Z1
Z2
Y2
Y1
P1
P2
Z3
P2
Y2
P1
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ISSN 977-2177-128009
THRU
50j
25j
DUT
Low
impedance
P2
High
impedance
High
impedance
P1
100j
THRU S11
10j
250j
One step
deembedding
(blue)
Two step
deembedding
(red)
10
25
50
100
250
-10j
-250j
Measurement
(black)
Fig. 6. Model that represents the thru structure.
-25j
-100j
-50j
Z ref =50
P1
P2
Z ref =50
S 11
Low
impedance
25j
100j
THRU S21
10j
250j
Two step
deembedding
(red)
where the matrix Zsh represents the experimental Zparameters associated with the short structure.
From (1) and (2) it is clear that the matrix operations used
in both deembedding procedures are simple and can be easily
implemented in any software that allows data processing.
Thus, the reason why the 1SD could be preferred by
microwave and device engineers is because it only uses one
dummy structure. However, in this case, there is a penalty in
accuracy which is discussed afterwards.
IV. COMPARISON USING THRU AND LOAD STRUCTURES
For comparing the 1SD and 2SD procedures, the
deembedded measurements corresponding to the thru and
load structures were compared.
Ideally, after deembedding the effect of the pads from the
measurements of the thru structure, the DUT correspond to a
small line which ideally presents a series impedance equal to
zero. A more realistic model, however, is that shown in Fig.
6. Assuming that the parasitic capacitance introduced by this
small line is very small, the equivalent circuit model for
obtaining the reflection parameter S11 is illustrated in Fig. 7.
In this case, an RF source with a reference impedance (in this
case of 50 ) applies a signal to the port-1 and the port-2 is
terminated with the same reference impedance. Since S11 is
obtained as:
(3)
where ZL is the sum of the low impedance associated with the
thru plus the reference impedance at port-2, then it is
expected that the result approximately corresponds to a
10
25
50
100
250
-10j
-25j
-100j
-50j
One step
deembedding
-250j (blue)
Measurement
(black)
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ISSN 977-2177-128009
LOAD
50j
25j
DUT
50
10j
High
impedance
High
impedance
P1
100j
deembedding
(blue)
Two step
deembedding
(red)
P2
10
25
50
100
250j
250
-10j
-250j
Measurement
(black)
-25j
-100j
-50j
Fig. 12. S11 for the load plotted in a Smith Chart up to 30 GHz.
P1
Z ref
50
P2
50j
25j
S11
100j
LOAD S21
Z ref =50
Two step
deembedding
(red)
10j
10
25
50
100
250
One step
deembedding
(blue)
-10j
-25j
250j
-250j
Measurement
(black)
-100j
-50j
Fig. 13. S21 for the load plotted in a Smith Chart up to 30 GHz.
V. DISCUSSION
A final comparison is carried out in this section to point
out the differences between the two studied methods when
applied to DUTs with relatively low and high impedances. As
mentioned before, the 1SD neglects the series parasitics
associated with the test fixture. These impedances are in the
order of a few ohms and can be neglected when measuring
the high-impedance DUTs; for instance, a MOS capacitor.
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-6.0
-10
|S11| (dB)
|S11| (dB)
LOAD
Raw measurement
One step deembedding
Two step deembedding
-7.5
-9.0
-20
-30
THRU
Raw measurement
One step deembedding
Two step deembedding
-40
-10.5
0.0
-0.5
|S21| (dB)
|S21| (dB)
-3
LOAD
Raw measurement
One step deembedding
Two step deembedding
-4
-5
-1.0
THRU
Raw measurement
One step deembedding
Two step deembedding
-1.5
-2.0
10
15
20
25
30
f (GHz)
10
15
20
25
30
f (GHz)
Fig. 15. Magnitude of the reflection and transmission parameters for the load
structure up to 30 GHz.
Fig. 14. Magnitude of the reflection and transmission parameters for the thru
structure up to 30 GHz.
ACKNOWLEDGMENT
The authors thank imec vzw for supplying the test
structures.
REFERENCES
[1] V. Camarchia, V. Teppati, S. Corbellini, M. Pirola, "Microwave
Measurements Part I Non-linear Measurements," IEEE Instrumentation
& Measurement Magazine, vol. 10, no.3, pp.34-39, June 2007.
[2] G. Engen and C. A. Hoer, Thru-Reflect-Line: An Improved Technique
for Calibrating the Dual Six-Port Automatic Network Analyser, IEEE
Trans. Microw. Theory Tech. vol. 27, no.12, pp.987-993, Dec. 1979.
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zeus.escuder@eotec.com
sarroyo@inaoep.mx
adiazsan@inaoep.mx
I. INTRODUCTION
Current research in prosthetics has been focused on the
development of prosthetic hands and prosthetic legs [1]-[2].
Nowadays, most of the implementations of mechanical and
myoelectric prosthetic elbows [3] are serial and with a single
degree of freedom (DOF), such as: Utah Arm [4], and the
Edinburgh Arm [5]. In contrast, a complete and functional
prosthetic elbow must have 3 motorized-axes in order to
provide 3 DOFs [5]-[6].
For such devices, the control the parallel mechanism is an
unavoidable requirement. There are several ways for
prosthesis control, such as voice commands, switches with
programmed routines, movements of any part of the user's
body and myolectric signals [9]. The acquisition of
myoelectric signals using superficial electrodes (sMES) have
been recently used for that purpose. Their special
characteristics in time and frequency have been chosen to
realize a refined movement command, and provide a
functional movement similar to the biological elbow
mechanism. Several methods are proposed to classify
myoelectric signal for prosthesis control [10]-[13]. Recent
studies have shown that, depending on the level of Maximum
Voluntaries Contraction (MVC), the probability density
function of the sMES may become more Laplacian than
Gaussian.
Therefore,
by
assuming
non-Gaussian
distributions, this paper propose the use of higher order
statistics as feature extractor for the classification of sMES
In [14], the use of high order statistics is proposed to
extract the characteristics of this kind of signals. In order to
II.
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ISSN 977-2177-128009
M k (1 , 2 ,L k ) =
where N is the length of each data record, and l1, l2 are the
maximum and minimum lag of the cross moment functions
respectively.
IV. ARCHITECTURAL DESIGN
Despite its complexity, the evaluation process can be
simplified by converting the Equation 6 into an iterative
matrix multiplication to compute the third-order cross
moment, as described in [7] and [21]. Let Mi be a matrix
whose elements are samples of third-order cross moments
defined in Equation 6. Mi is given by equation 1, where i =
q, q + 1,, q, and q is the maximum lag of third order
cross moment function.
In that way, all the third-order cross moments are evaluated
by computing the entries for matrix Mi for different values of
i. So that, if the entries for matrix Mi were calculated by
performing the multiplication auxiliary matrices XYi, the
third-order samples matrix Mi, are equal to the product of X,
Yi and Z matrices, where X is a (2q+1)*N matrix, Z is an
N*(2q+1) rectangular matrix (Z=X(x2T)) and Yi is a diagonal
square matrix with entries x0(0)x3(i), x0(1)x3(1 + i),
x0(2)x3(2 + i), x0(n)x3(N-1 + i), where x0(0)x3(i) is the
non zero element in the first row, x0(1)x3(1 + i) is the non
zero element in the second row, and so on. The complete
formulations to construct the matrices are show in Equation 7.
M k , x ( 1 , 2 ) = E x(t )C x(t + i )
i =1
(1)
0
0
0
L
M
M
0
x
1 (0)
Mi =
x1 (0)
x1 (1)
x1 (2)
x1 (1)
M
M
x1 (q) x1 (q + 1)
C 2 , x ( 1 ) = E {x ( t ) x ( t + 1 ) }
C 3 , x ( 1 , 2 ) = E {x (t ) x (t + 1 ) x ( t + 2 )}
(2)
C 2 , x ( 1 )C 2 , x ( 2 3 )
0
L x1 (N q 1)
L x1 (N q)
M
0
M
M
L x1 (N 2) x2 (0)
*
L x1 (N 1) x2 (1)
0
L
M
x (N q)
M
M
2
0
L
x2 (N q 1)
L x2 (q)
M
M
L x2 (2q 1)
L x2 (2q)
*Y
i
L
M
M
M
0
L
0
L
(3)
(4)
(5)
C 2 , x ( 2 )C 2 , x ( 3 1 )
C 2 , x ( 3 )C 2 , x ( 1 2 )
where E{x(t)} is the expectation operator, x(t) is the sMES
sample, and represent the order of cumulant to be computed.
If x(n) is a 0 mean process, the K-th-order cumulant are equal
to the k-th cross moments, so 1, 2,and 3 values are
considered constants to calculate the third and quarter order
cumulants [20]. Therefore the higher order cross moment
(7)
C 4 , x ( 1 , 2 , 3 )
= E {x (t ) x (t + 1 ) x (t + 2 ) x (t + 3 )}
1 l2
x0 (n)xl1 (n + 1 )Lxl 2 (n + k ) (6)
N nl1
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ISSN 977-2177-128009
reported in Table I.
As show in Table II, the higher percentage values for
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TABLE I
IMPLEMENTATION RESULTS
[3]
[4]
[5]
[6]
[7]
VI. CONCLUSIONS
[8]
TABLE II
[9]
TYPE
Flexion
Extension
Pronation
Supination
Percentage
Frequency
Time
Domain
73.7 (8.56)
76.2 (4.30)
50.3 (7.19)
75.20 (3.15)
68.8 (5.80)
106.13MHz
th
3 Order
3Features
90.0 (5.12)
63.7 (2.24)
68.8 (5.68)
89.0 (6.19)
85.4 (4.56)
82.73MHz
th
3 Order
4Features
93.4 (4.27)
89.7 (3.54)
88.8 (6.23)
92.6 (4.20)
89.37 (4.80)
44.57MHz
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
ACKNOWLEDGMENT
Authors would like to thank the National Council of
Science and Technology (CONACyT) of Mxico for the
financial support given through the scholarship number
104369.
REFERENCES
[1]
[2]
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Resumen
Este artculo describe la implementacin de un robot
en forma de medusa basado en un FPGA Spartan 3
de Xilinx (Arreglo de compuertas programables) con
movimiento de avance hacia adelante y atrs con un
control PWM (Modulacin por ancho de pulso) y el
mismo robot controlado ahora con un PIC
(controlador de interfaz perifrico) con
comunicacin de bluetooth y una interface en matlab
GUI (interface grfica de usuario) con comunicacin
de bluetooth y pc.
Estos controles se desarrollaron para lograr una
versatilidad en el control teleoperada y el desarrollo
de prototipos de robots a bajo costo.
Tambin el desarrollo de la ecuacin matemtica de
uno de los tentculos aplicando la metodologa de
Euler Lagrange utilizando Simulink para
desarrollar un control de bloques PD solo como
simulacin pero sin implementarla dentro del robot.
II.
I.
INTRODUCCION
DESCRIPCION
DEL
MODELADO Y CONTROL.
Donde:
El brazo est formado por 2 eslabones rgidos de
longitudes
y . Y masas
y
m2
respectivamente. Las uniones 1 y 2 son
rotacionales. Los desplazamientos del robot se
llevarn a cabo en el plano vertical x-y (Fig.1).
La distancia entre los ejes de giro y los centros de
masas se denota por
y
respectivamente. Y
expresan los momentos de inercia de los
eslabones con respecto al eje que pasa a travs de
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Los ngulos
que se mide desde la posicin
vertical hacia abajo y
que se mide a partir de la
extensin del eslabn 1 hasta el eslabn 2, siendo
ambos positivos en sentido contrario al
movimiento de las manecillas del reloj.
(5)
[
[
][ ]
][ ]
[ ]
Para el clculo de las coordenadas de masa para el
eslabn 2 en el plano x-y son:
El control Proporcional-Derivativo (PD) es una
extensin inmediata del control Proporcional con
retroalimentacin de velocidad.
La ley de control est formada no solo por un
trmino proporcional al error de posicin como
el controlador Proporcional con retroalimentacin
de velocidad, sino tambin por otro trmino
proporcional a su derivada al error de velocidad .
Donde:
=Par aplicado al eslabn 1
=Par aplicado al eslabn 2
[
]
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]
(10)
[ ] [
[
]
III.
ELECTRNICA
DISEO Y CONSTRUCCION
DEL PROTOTIPO
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SOFTWARE DE CONTROL
VI.
RESULTADOS
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VII.
CONCLUSIONES
AGRADECIMIENTOS
Agradezco a Conacyt por el financiamiento y a la
Facultad de Ciencias de la Electrnica por el
apoyo de la realizacin de este proyecto.
REFERENCIAS
[1] Balaguer C. Aracil R. Barrientos A., Pein L.F.
Fundamentos de Robtica, McGraw-Hill, 1997.
[2] J. O. Gray, Recent developments in advanced
robotics and intelligent systems, Comput.
Control Eng. J., vol. 7, no. 6, pp. 267276, Dec.
1996.
[3] Carrasco Rodrigo Cipriano Aldo. Sistema de
Guiado para un robot mvil basado en lgica
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Edmundo Gutirrez
National Institute of Astrophysics, Optics and Electronics
Luis Enrique Erro No. 1, Puebla, 72840, Mxico
Email: edmundo@inaoep.mx
I.
INTRODUCTION.
NEGF FORMALISM.
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(1)
!!! !
!!
(2)
(3)
! = ! !! , ! = ! !!
(4)
Where,
= ! !
!!
(5)
! !
()
! !
! !
(6)
!!!!
!! !
!!
+1
, ! () =
!!!!
!! !
!!
+1
(7)
Fig. 2. Energy band diagrams under (a) low drain bias and
(b) high drain bias. The parameter is the gate voltage.
The well-known structure that shows the result of
considering the electrons as quantum waves is the doublebarrier structure, which consists of two tunneling barriers in
series. The Fig. 3 shows the resultant transmission for the
double-barrier with a height of 0.4 eV. Note that electrons
with energy E=0.3 eV have a unity transmission probability.
The Fig. 4 depicts the corresponding current-voltage
relationship ! !" . We considered the effective mas of the
gallium arsenide at room temperature for all the simulations.
IV.
TWO-DIMENSIONAL ANALISYS
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Fig. 4. Drain current (! ) from a series of applied drainsource voltages (!" ) to a double-barrier structure.
A. Diferent barrier heights (B=0)
In order to visualize the activation of the different
transmission modes, the simulated transmission of the
nanowire under study (6 nm wide and 15 nm long) is shown in
Fig. 5. For an absent potential barrier (barrier height = 0), it
was obtained a ballistic transmission. The onset energies of
the different transmission modes are clearly shown by the
discontinuities (E=0.2, 0.5, 1.2, 2.1, 3.3, 4.6). Thus, one
transversal mode propagates for the range of energy between
0.2 and 0.5eV; two transversal modes propagate for the range
of energy between 0.5 and 1.2eV and so on. Note that the
transmission becomes continuous and lowers in magnitude in
the presence of a potential barrier as expected (Fig. 5).
B. Including the magnetic field ( 0)
The influence of a perpendicular magnetic field (normal to
the surface of the two-dimensional structure) is added to the
analysis. Because the structure under analysis is too small,
very high intensities of a magnetic field are needed to observe
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(8)
!!
= ( )
!!
(9)
!!
= (1 2)
!!
(10)
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V.
CONCLUSIONS
Fig. 11. Relationship I! V! of the three-port twodimensional system in a magnetic field with opposite
directions.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
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