Crusoe Processor

SEMINAR REPORT
(SUBMITTED IN PARTIAL FULFILMENT OF THE AWARD OF DEGREE OF BACHELOR OF

TECHNOLOGY)
ON
SESSION 2009-2010
UNDER THE GUIDANCE OF
Mrs. Nida Haseeb

(Seminar Co-ordinator)
SUBMITTED BY
Vikas Kumar Mishra

IV YEAR INFORMATION TECHNOLOGY
ROLL No. : 0600115059
INTEGRAL UNIVERSITY LUCKNOW

Phone No.: 0522-2890812, 2890730, 3096117
Fax: 0522-2890809
Web: www.integraluniversity.ac.in
SEMINAR REPORT on “CRUSOE PROCESSOR”
CERTIFICATE
This is to certify that VIKAS KUMAR MISHRA has completed
necessary Seminar work & prepared the bonafied report on CRUSOE
-PROCESSOR in satisfactory manner as the partial fulfillment for the
requirement of the degree of B.Tech (Information Technology) Of
INTEGRAL UNIVERSITY, LUCKNOW under the guidance of his
faculty within his time limit and his full effort to make his Seminar good.
Mr. M. M. Tripathi Mr. Rizwan Beg

(Seminar Co-ordinator) (HOD - CSE/IT)
Mrs. Nida Haseeb

Miss. Nikhat Akhtar

Submitted By: VIKAS KUMAR MISHRA (0600115059) 2

ACKNOWLEDGEMENT
I take the opportunity to express my sincere thanks to Mrs.
Nida Haseeb (Department Of CSE/IT) for her valuable advice and
guidance for the success of this seminar. I also thank Dr. Rizwan
Beg, HOD, (CSE/IT Dept). and all other staff of the department for
their kind co-operation extended to me. Also I am extending my
gratitude to everyone who helped me in the successful presentation
of this seminar.
I am thankful to all my friends who helped me in completing

my seminar a successful one. I am also thankful to all the people
who were directly or indirectly involved me in helping to complete
my seminar report.
Vikas Kumar Mishra

Roll No.:0600115059
B.Tech ( Final Year )
Information Technology

INDEX
SNO. TOPIC PAGE

NO.
1. Introduction 5
2. Architecture 16
3. Hierarchy model 20
4. Instruction set 23
5. Performance 24
6. Crusoe v/s Pentium die size 25
7. Code morphing software 26
8. Drawbacks 27
9. Conclusion 28
10. Refrences 29

1.INTRODUCTION
Mobile computing has been the buzzword for quite a long time.
Mobile computing devices like laptops, webslates & notebook PCs
are becoming common nowadays. The heart of every PC whether a
desktop or mobile PC is the microprocessor. Several
microprocessors are available in the market for desktop PCs from
companies like Intel, AMD, Cyrix etc.The mobile computing market
has never had a microprocessor specifically designed for it. The
microprocessors used in mobile PCs are optimized versions of the
desktop PC microprocessor.
Mobile computing makes very different demands on processors than

desktop computing, yet up until now, mobile x86 platforms have
simply made do with the same old processors originally designed for
desktops. Those processors consume lots of power, and they get
very hot. When you're on the go, a power-hungry processor means

you have to pay a price: run out of power before you've finished, run
more slowly and lose application performance, or run through the
airport with pounds of extra batteries. A hot processor also needs
fans to cool it; making the resulting mobile computer bigger, clunkier
and noisier.
A newly designed microprocessor with low power consumption will

still be rejected by the market if the performance is poor. So any
attempt in this regard must have a proper 'performance-power'
balance to ensure commercial success. A newly designed
microprocessor must be fully x86 compatible that is they should run
x86 applications just like conventional x86 microprocessors since
most of the presently available software's have been designed to
work on x86 platform.
Crusoe is the new microprocessor which has been designed specially

for the mobile computing market. It has been designed after
considering the above mentioned constraints. This microprocessor
was developed by a small Silicon Valley startup company called
Transmeta Corp. after five years of secret toil at an expenditure of
$100 million. The concept of Crusoe is well understood from the
simple sketch of the processor architecture, called 'amoeba'. In this
concept, the x86-architecture is an ill-defined amoeba containing
features like segmentation, ASCII arithmetic, variable-length
instructions etc. The amoeba explained how a traditional
microprocessor was, in their design, to be divided up into hardware
and software.
Thus Crusoe was conceptualized as a hybrid microprocessor that is it

has a software part and a hardware part with the software layer
surrounding the hardware unit. The role of software is to act as an
emulator to translate x86 binaries into native code at run time. Crusoe
is a 128-bit microprocessor fabricated using the CMOS process. The
chip's design is based on a technique called VLIW to ensure design
simplicity and high performance. Besides this it also uses
Transmeta's two patented technologies, namely, Code Morphing
Software and Longrun Power Management. It is a highly integrated
processor available in different versions for different market
segments.

In electronics, Crusoe is a family of microprocessors from Transmeta.

They use a VLIW hardware "core", upon which runs a software
abstraction layer, or virtual machine, known as the Code Morphing
Software (CMS). The CMS translates machine code instructions
received from programs running on the chip into native instructions
for the core. In this way, the chips can emulate the instruction set of
other computer architectures.
Currently, this is used to allow the chips to emulate the Intel x86
instruction set. In theory, it is possible for the CMS to be modified to
handle other instruction streams (i.e. to emulate other
microprocessors).
The addition of an abstraction layer between the x86 instruction

stream and the hardware means that the hardware architecture can
change without breaking compatibility, just by modifying the CMS. For
example Efficeon, the second-generation Crusoe, has a 256-bit-wide
VLIW core versus 128-bit in the first generation.
Crusoe performs in software some of the functionality traditionally

implemented in hardware (e.g. instruction re-ordering), resulting in
simpler hardware with fewer transistors. The relative simplicity of the
hardware means that Crusoe consumes less power (and therefore
generates less heat) than other x86-compatible microprocessors
running at the same frequency.
The name is taken from the novel Robinson Crusoe.
Transmeta (NASDAQ: TMTA) is a company that develops computing

technologies with a focus on reducing power consumption in
electronic devices. It was founded in 1995 by Bob Cmelik, Dave
Ditzel [1], Colin Hunter, Ed Kelly, Doug Laird, Malcolm Wing, and
Greg Zyner as a US-based corporation that designed very long
instruction word code morphing (Microcoded) microprocessors. So
far, it has produced two x86-compatible CPU architectures: Crusoe
and Efficeon. These CPUs have appeared in ultra-portable laptops,
blade servers, tablet PCs, a personal cluster computer, and a silent

desktop, where low power consumption and heat dissipation are of

primary importance. HistoryThroughout Transmeta's first few years,
little was known about exactly what it would be offering. Its web site
went online in mid-1997, and for approximately two and a half years
displayed nothing but the text "This web page is not yet here."
Information gradually came out of the company, suggesting of a very
long instruction word-based (VLIW) design that translated x86 code
into its own native code. As Intel's then-forthcoming "Merced"
processor was also a VLIW design which could translate x86 code,
speculation arose suggesting that Transmeta's product could have
supercomputer-level processing power while actually being cheaper
to manufacture than any offering by Intel, AMD or Cyrix.
In fact, Transmeta marketed their microprocessor technology as

extraordinarily innovative and revolutionary in the low-power market
segment. They had hoped to be both power and performance leaders
in the x86 space. But initial reviews of the Crusoe indicated the
performance fell significantly short of projections. [2] Also, during
Crusoe development Intel and AMD significantly ramped up speeds
and began to address increasing concerns about power consumption.
So Crusoe was rapidly cornered into a low-volume, small form factor
(SFF), low-power segment of the market.
In response, Transmeta quickly re-designed its technology, and

produced the Efficeon processor. The Efficeon claimed to have twice
the performance of the original Crusoe CPU at the same frequency.
But the performance was still weak relative to the competition, and
the complexity of the chip had increased significantly. This greater
size and power consumption may have diluted a key market
advantage Transmeta's chips had previously enjoyed over the
competition.
Transmeta has employed a number of industry luminaries such as

Linus Torvalds and Dave D. Taylor. Initially, its purpose was kept
secret, but partially because it had such talent amongst its staff, the
industry was constantly abuzz with rumors in addition to 'conspiracy
theories' resulting in excellent press relations (PR).
Torvalds left Transmeta in June 2003 to dedicate himself to the

further development of the Linux kernel.

As an example of technology media hype, the company was once

named as the Most important company in Silicon Valley in an Upside
magazine editorial. Less well reported was that the company was
never profitable while it was a chip vendor. In 2002, it had a loss of
$114 million dollars, in 2003 a loss of $88 million, in 2004 a loss of
$107 million.
As of January 2005 the company announced a strategic restructuring

away from being a chip product company to an intellectual property
company. That is, instead of selling chips, it will sell technology for
use by other chip makers. In February 2005, there was wild
speculation that AMD might buy Transmeta. In March 2005
Transmeta announced that it was laying off 68 people, leaving 208
employees. About half of the remaining employees were to work on
propagating the LongRun2 power optimization technology within
Sony products. Sony was reported to be a key licensee of this
Transmeta technology. TimelineFounded in 1995.
Corporate launch on January 19, 2000. [3]
On November 13, 2000, Transmeta announces their initial public
offering at $21/share. Stock skyrocketed to $46/share making it the
last of the great high tech IPOs of the bubble not surpassed by a high
tech company again until Google's IPO in 2004.
In July of 2002, Transmeta experience first set of layoffs equaling
40% of the company. [4]
On May 31, 2005, Transmeta announced the signing of asset
purchase and license agreements with Hong Kong's Culture.com
Technology Limited led by Chu Bong-Foo, the inventor of the Cangjie
method and one of the founding fathers of modern Chinese
computing. However, due to delays in obtaining the necessary
technology export licenses from the US Department of Commerce,
the parties announced the termination of this agreement on February
9, 2006.
On August 10 2005, Transmeta announced its first ever profitable
quarter. On March 20 2006, GameSpot reported that Transmeta is
working on an "unnamed" Microsoft project, probably the Origami.
[1]
On October 11 2006, Transmeta announced that it had filed a lawsuit
against Intel Corporation for the infringement on ten of Transmeta's
US patents. The lawsuit, filed with the US District Court of Delaware,

requested an injuction against Intel's continuing sales of infringing

products and also requested monetary compensation for damages.
On February 7 2007, Transmeta closed its engineering services
departments and terminated 75 employees. The company announced
that it would no longer develop and sell hardware, but would focus on
the development and licensing of intellectual property. [5]
On July 6 2007, AMD invested $7.5 million in Transmeta. AMD plans

to use Transmeta's patent portfolio related to energy-efficient
technologies. [6]
Origins as a stealth startup
The company began as a stealth startup. Transmeta attempted to
staff the company in secret, although speculation online was not
uncommon [7]. One source of speculation was the company's bare-
bones webpage. On November 12, 1999, a cryptic comment in the
HTML appeared [8]:
Yes, there is a secret message, and this is it: Transmeta's policy has
been to remain silent about its plans until it had something to
demonstrate to the world. On January 19th, 2000, Transmeta is going
to announce and demonstrate what Crusoe processors can do.
Simultaneously, all of the details will go up on this Web site for
everyone on the Internet to see. Crusoe will be cool hardware and
software for mobile applications. Crusoe will be unconventional,
which is why we wanted to let you know in advance to come look at
the entire Web site in January, so that you can get the full story and
have access to all of the real details as soon as they are available.
The company was largely successful in hiding its ambitions until the
official announcement. Over 2000 non-disclosure agreements (NDAs)
were signed during the stealth period [9].
Lawsuit against Intel Corporation
On October 11, 2006, Transmeta announced that they have filed a
lawsuit against Intel Corporation for infringement of ten Transmeta
U.S. patents covering computer architecture and power efficiency
technologies.
The complaint charges that Intel has infringed and is infringing

Transmeta's patents by making and selling a variety of
microprocessor products including at least Intel's Pentium III, Pentium
4, Pentium M, Core and Core 2 product line. TechnologyThe actual
Transmeta processors are in-order very long instruction word (VLIW)

cores. To execute x86 code, a pure software-based instruction

translator dynamically compiles or emulates x86 code sequences,
using execution-hotspot guided heuristics. While similar technologies
existed (WABI for Sun, FX!32 for Alpha and IA-32 EL for Itanium) in
the 1990s, the Transmeta approach has set a much higher bar for
compatibility—able to execute all x86 instructions from initial boot up
to the latest multimedia instructions—while retaining most of its core
performance.
Transmeta claims several technical benefits to this approach:

As the market leaders Intel and/or AMD would extend the core x86
instruction set, Transmeta could quickly upgrade their product with a
software upgrade rather than requiring a respin of their hardware.
Performance and power can be tuned in software to meet market
needs
It would be relatively simple to fix hardware design or manufacturing
flaws in the hardware using software workarounds.
More time could be spent concentrating on enhancing the capabilities
of the core or reducing its power consumption without worrying about
16 years of backward compatibility to the x86 architecture.
The processor could emulate multiple other architectures, possibly
even at the same time. (At its initial Crusoe launch, Transmeta
demonstrated pico-Java and x86 running intermixed on the native
hardware.)
Prior to Crusoe release, rumors indicated Transmeta was relying on

these benefits to develop a hybrid PowerPC and x86 processor. But
Transmeta would initially concentrate solely on the extremely low-
power x86 market.
The ability to quickly update products without a hardware respin was

demonstrated in 2002 with an in-the-field upgrade (a download) to
enhance CPU performance of the Crusoe based HP Compaq
TC1000 tablet PC. It was used again in 2004 when NX bit and SSE3
support were added to the Efficeon product line without requiring
hardware changes. In the field upgrades were rare in practice due to
system hardware vendors not wanting to incur additional customer
support costs or spend additional money on QA for the potential

upgrades or bug fixes to shipped products they had already closed

the revenue books on.
Viability
Transmeta lost much credibility and endured significant criticism due
to the poor initial Crusoe showing with large discrepancies between
projections and actuals for both performance and power. Although
power consumption was somewhat better than Intel and AMD
offerings, the end user experience (i.e. battery life) only showed a
marginal overall improvement. [2] First, the Code Morphing Software
(CMS) combined with cache architecture artificially inflated
comparisons between benchmarks and real-world applications. This
is due to the repetitive nature of benchmarks and their small
footprints. The CMS software overhead may have actually been a key
cause of much lower performance for many real-world applications;
the simple VLIW core architecture could not compete on
computationally-intensive applications; and the southbridge interface
was limited by its low bandwidth for graphics or other I/O-intensive
applications. Some standard benchmarks even failed to run,
questioning the claim of full x86 compatibility. [3]
The Efficeon processor addressed many of Crusoe's shortcomings

and showed roughly a 2x real-world improvement over Crusoe. Its die
was considerably smaller than Pentium 4 and Pentium M, when
compared in the same process technology. Efficeon's die fabricated
in 90 nm is 68 mm², which is 60% of the Pentium 4 in 90 nm, at 112
mm², with both processors possessing a 1 MB L2 cache.
The notion of selling a product into a specific thermal envelope was

typically not understood by the mass of reviewers, who tended to
compare Efficeon to the gamut of x86 microprocessors, regardless of
power consumption or application. One such example of this criticism
suggests the performance still significantly lagged Intel's Pentium M
(Banias) and AMD's Mobile Athlon XP. [4]
For the 7 to 12 Watt thermal envelope in which Efficeon was

designed to compete, there are unsubstantiated claims that its
frequency far exceeded anything else in the market, at 1.5 GHz and 7
W, while the Centrino at the time could only operate within the 7 W
envelope when its frequency was reduced to 1.1 GHz. This claim also
admittedly considers only CPU frequency and ignores other

significant factors in overall performance, such as core cycles per

instruction (CPI), or memory performance and bandwidth, which have
varying impact on different benchmarks and system configurations.
Unfortunately for Transmeta, other components within a laptop

computer also consume power, such as the LCD display and hard
disk drive. Since laptops with Transmeta CPUs share these
components with regular laptops, the net increase in battery life was
not large enough to make much difference to customers. TriviaOn the
show 24, the fictional character Tony Almeida is listed as a former
systems validation analyst at Transmeta.
Very Long Instruction Word or VLIW refers to a CPU architecture

designed to take advantage of instruction level parallelism (ILP). A
processor that executes every instruction one after the other (i.e. a
non-pipelined scalar architecture) may use processor resources
inefficiently, potentially leading to poor performance. The
performance can be improved by executing different sub-steps of
sequential instructions simultaneously (this is pipelining), or even
executing multiple instructions entirely simultaneously as in
superscalar architectures. Further improvement can be achieved by
executing instructions in an order different from the order they appear
in the program; this is called out-of-order execution.
These three techniques all come at a cost: increased hardware

complexity. Before executing any operations in parallel, the processor
must verify that the instructions do not have interdependencies.
There are many types of interdependencies, but a simple example
would be a program in which the first instruction's result is used as an
input for the second instruction. They clearly cannot execute at the
same time, and the second instruction can't be executed before the
first. Modern out-of-order processors use significant resources in
order to take advantage of these techniques, since the scheduling of
instructions must be determined dynamically as a program executes
based on dependencies.

The VLIW approach, on the other hand, executes operation in parallel

based on a fixed schedule determined when programs are compiled.
Since determining the order of execution of operations (including
which operations can execute simultaneously) is handled by the
compiler, the processor does not need the scheduling hardware that
the three techniques described above require. As a result, VLIW
CPUs offer significant computational power with less hardware
complexity (but greater compiler complexity) than is associated with
most superscalar CPUs.
The Efficeon processor is Transmeta's second-generation 256-bit

VLIW design which employs a software engine to convert code
written for x86 processors to the native instruction set of the chip
(Code Morphing Software, aka CMS). Like its predecessor, the
Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses
computational efficiency, low power consumption, and a low thermal
footprint.
Efficeon most closely mirrors the feature set of Intel Pentium 4

processors, although, like AMD Opteron processors, it supports a
fully integrated memory controller, a HyperTransport IO bus, and the
NX bit, or no-execute x86 extension to PAE mode. NX bit support is
available starting with CMS version 6.0.4.
Efficeon's computational performance relative to mobile CPUs like

the Intel Pentium M is thought to be lower, although little appears to
be published about the relative performance of these competing
processors.
Efficeon comes in two package types: a 783 and a 592 ball grid array.
Its power consumption is moderate (with some consuming as little as
3 watts at 1 GHz and 7 watts at 1.5 GHz), so it can be passively
cooled.
Two generations of this chip were produced. The first generation

(TM8600) was manufactured using a TSMC 0.13 micrometre process
and productized at speeds up to 1.1 GHz. The second generation
(TM8800 and TM8820) was manufactured using a Fujitsu 90 nm
process and productized at speeds ranging from 1 GHz to 1.7 GHz).

Internally, the Efficeon has 2 arithmetic logic units, 2 load/store/add

units, 2 execute units, 2 floating-point/MMX/SSE/SSE2 units, one
branch prediction unit, one alias unit, and one control unit. This VLIW
Processor can execute a 256-VLIW word per cycle, which is called a
molecule and therefore has room and capability to execute 8 32-bit
commands (called atoms) per cycle.
The Efficeon has 128 k instruction + 64 k data level 1 cache and a

1Mb level 2 cache on the chip.
Additionally the Efficeon CMS (code morphing software) reserves a

small
portion of main memory (typically 32Mb) for its translation cache of
dynamically translated x86 instructions.
• Compact 474-pin ceramic BGA package is fully pin-compatible with

existing TM5400 and TM5600 models.
The Transmeta Crusoe processor is an ultra-low power, high-speed
microprocessor based on an advanced VLIW core
architecture. When used in conjunction with Transmeta’s x86 Code
Morphing software, the Crusoe processor provides
x86-compatible software execution using dynamic binary code
translation, without requiring code recompilation. In addition
to the VLIW core, the processor incorporates separate 64K-byte
instruction and data caches, a large 512K-byte L2
write-back cache, 64-bit DDR SDRAM memory controller, 64-bit SDR
SDRAM memory controller, and 32-bit PCI controller.
These additional functional units, which are typically part of the core
system logic that surrounds the microprocessor,
allow the Crusoe processor to provide a highly integrated and cost
effective platform solution for the x86 mobile.
market. The processor core operates from a 0.9-1.3V supply,
resulting in extremely low power consumption, even at high
operating frequencies. With power consumption during typical
operation as low as 150 milliwatts.

2.ARCHITECTURE
The Crusoe processor incorporates integer and floating point

execution units, separate
instruction and data caches, a level-2 write-back cache, memory
management unit, and
multimedia instructions. In addition to these traditional processor
features, the device
integrates a DDR SDRAM memory controller, SDR SDRAM memory
controller, PCI
bus controller and serial ROM interface controller. These additional
units are usually

part of the core system logic that surrounds the microprocessor. The
VLIW processor,
in combination with Code Morphing software and the additional
system core logic
units, allow the Crusoe processor to provide a highly integrated, ultra-
low power, high
performance platform solution for the x86 mobile market. The Crusoe
processor block
diagram is shown in Figure 1.
FIGURE 1 Crusoe Processor Block Diagram - Model TM5800
CPU Core
Integer unit
Floating point unit
MMU
L1 Instruction Cache
L1 Data Cache
64K
8-way set associative
64K
Unified TLB
256 entries
DDR SDRAM
Controller
SDR SDRAM
Controller
PCI Controller
&
Southbridge
Interface
DMA
Multimedia Instructions
64
64
Serial ROM
Interface
L2 WB Cache
512K

Bus
Interface
Model TM5800 Product Brief Crusoe Processor
7/5/2001 3 of 8
2.0 Processor Core
The Crusoe processor core architecture is relatively simple by
conventional standards.
It is based on a Very Long Instruction Word (VLIW) 128-bit instruction
set. Within this
VLIW architecture, the control logic of the processor is kept very
simple and software is
used to control the scheduling of instructions. This allows a simplified
and very
straightforward hardware implementation with an in-order 7-stage
integer pipeline and
a 10-stage floating point pipeline. By streamlining the processor
hardware and reducing
the control logic transistor count, the performance-to-power
consumption ratio can be
greatly improved over traditional x86 architectures.
The Crusoe processor includes a 64K-byte 8-way set-associative
Level 1 (L1) instruction
cache, and a 64K-byte 16-way set associative L1 data cache. The
TM5800 model
also includes an integrated 512K-byte Level 2 (L2) write-back cache
for improved
effective memory bandwidth and enhanced performance. This cache
architecture
assures maximum internal memory bandwidth for performance
intensive mobile applications,
while maintaining the same low-power implementation that provides a
superior
performance-to-power consumption ratio relative to previous x86
implementations.
Other than having execution hardware for logical, arithmetic, shift,
and floating point
instructions, as in conventional processors, the Crusoe processor has
very distinctive
features from traditional x86 designs. To ease the translation process
from x86 to the

core VLIW instruction set, the hardware generates the same

condition codes as conventional
x86 processors and operates on the same 80-bit floating point
numbers. Also, the
Translation Look-aside Buffer (TLB) has the same protection bits and
address mapping
as x86 processors. The software component of this solution is used
to emulate all other
features of the x86 architecture. The software that converts x86
programs into the core
VLIW instructions is called Code Morphing software. The combination
of Code Morphing
software and the VLIW core together act as an x86-compatible
solution.

3.HIERARCHY MODEL
.
Crusoe Processor Software Hierarchy
VLIW Processor
Code Morphing Software
x86 Operating System
(Windows ME, Windows 2000, Linux, etc.)
x86 BIOS
x86 Applications
x86 Compatible
Crusoe Processor Solution
x86 Software

IN

4.INSTRUCTION SET

5.PERFORMANCE
Performa

6.Crusoe vs. Pentium Die Size
Mobile PII Mobile PII Mobile PIII TM3120 TM5400

Process .25m .25m shrink .18m .22m .18m
On-chip
L1 Cache 32KB 32KB 32KB 96KB 128KB
On-chip
L2 Cache 0 256KB 256KB 0 256KB
Die Size 130mm2 180mm2 106mm2 77mm2 73mm2

7.C
1. X-86 in
through a s
8.Some drawbacks:
1. Code optimization does not start until a block of code has been
executed more the a few times.
2. Code translation requires clock cycles which could otherwise be

used in performing application computation.

9.Conclusion
1. Transmeta has build an X-86 processor based on VLIW(very
long instruction word) technology.
2. Code Morphing offers a new approach to the implementation

of an instruction set architecture.
3. Crusoe offers the power of a high performance Intel

processor consuming a fraction of power .

10.REFERENCES
http://www.wikipedia.org/
http://www.google.co.in/
http://www.esnips.com/
http://www.scribd.com/
www.transmeta.com
www.efficeon.org
www.crusoeseries.in

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SEMINAR REPORT

(SUBMITTED IN PARTIAL FULFILMENT OF THE AWARD OF DEGREE OF BACHELOR OF

UNDER THE GUIDANCE OF

Mrs. Nida Haseeb

Vikas Kumar Mishra

INTEGRAL UNIVERSITY LUCKNOW

Mr. M. M. Tripathi Mr. Rizwan Beg

Mrs. Nida Haseeb

Miss. Nikhat Akhtar

Submitted By: VIKAS KUMAR MISHRA (0600115059) 2

I am thankful to all my friends who helped me in completing

Vikas Kumar Mishra

Submitted By: VIKAS KUMAR MISHRA (0600115059) 3

SNO. TOPIC PAGE

6. Crusoe v/s Pentium die size 25

7. Code morphing software 26

Submitted By: VIKAS KUMAR MISHRA (0600115059) 4

Mobile computing makes very different demands on processors than

Submitted By: VIKAS KUMAR MISHRA (0600115059) 5

A newly designed microprocessor with low power consumption will

Crusoe is the new microprocessor which has been designed specially

Thus Crusoe was conceptualized as a hybrid microprocessor that is it

Submitted By: VIKAS KUMAR MISHRA (0600115059) 6

In electronics, Crusoe is a family of microprocessors from Transmeta.

The addition of an abstraction layer between the x86 instruction

Crusoe performs in software some of the functionality traditionally

The name is taken from the novel Robinson Crusoe.

Transmeta (NASDAQ: TMTA) is a company that develops computing

Submitted By: VIKAS KUMAR MISHRA (0600115059) 7

desktop, where low power consumption and heat dissipation are of

In fact, Transmeta marketed their microprocessor technology as

In response, Transmeta quickly re-designed its technology, and

Transmeta has employed a number of industry luminaries such as

Torvalds left Transmeta in June 2003 to dedicate himself to the

Submitted By: VIKAS KUMAR MISHRA (0600115059) 8

As an example of technology media hype, the company was once

As of January 2005 the company announced a strategic restructuring

Submitted By: VIKAS KUMAR MISHRA (0600115059) 9

requested an injuction against Intel's continuing sales of infringing

On July 6 2007, AMD invested $7.5 million in Transmeta. AMD plans

The complaint charges that Intel has infringed and is infringing

Submitted By: VIKAS KUMAR MISHRA (0600115059) 10

cores. To execute x86 code, a pure software-based instruction

Transmeta claims several technical benefits to this approach:

Prior to Crusoe release, rumors indicated Transmeta was relying on

The ability to quickly update products without a hardware respin was

Submitted By: VIKAS KUMAR MISHRA (0600115059) 11

upgrades or bug fixes to shipped products they had already closed

The Efficeon processor addressed many of Crusoe's shortcomings

The notion of selling a product into a specific thermal envelope was

For the 7 to 12 Watt thermal envelope in which Efficeon was

Submitted By: VIKAS KUMAR MISHRA (0600115059) 12

significant factors in overall performance, such as core cycles per

Unfortunately for Transmeta, other components within a laptop

Very Long Instruction Word or VLIW refers to a CPU architecture

These three techniques all come at a cost: increased hardware

Submitted By: VIKAS KUMAR MISHRA (0600115059) 13

The VLIW approach, on the other hand, executes operation in parallel