I HC QUC GIA THNH PH H CH MINH

TRNG I HC CNG NGH THNG TIN

--------------oOo--------------

Gio trnh
NGN NG M T PHN CNG
VERILOG
Bin son: TS. V c Lung
ThS. Lm c Khi
Ks. Phan nh Duy

2012

Gio trnh ngn ng Verilog HDL

Li ni u
Ngy nay, khi mch thit k vi hng triu cng logic c tch hp trong mt con Chip
th vic thit k mch v i dy kt ni bng tay tr nn bt kh thi, chnh t l do mt
khi nim ngn ng c mc tru tng cao dng m t thit k phn cng c
ra i, chnh l Verilog. Cng vi s ra i ca ngn ng m t phn cng Verilog l
hng lot cc cng c EDA (Electronic Design Automation) v CAD (Computer Aided Design)
gip cho nhng k s thit k phn cng to nn nhng con Chip c tch hp rt
cao, tc siu vit v chc nng a dng.
Gio trnh Ngn ng m t phn cng Verilog nhm gip sinh vin trang b kin
thc v thit k vi mch. Gio trnh tp trung vo mng thit k cc mch s vi mch t
hp v mch tun t. Gio trnh cng gii thiu v cc bc cn thc hin trong qu trnh
thit k vi mch t vic m t thit k, kim tra, phn tch cho n tng hp phn cng
ca thit k.
Gio trnh Ngn ng m t phn cng Verilog dng cho sinh vin chuyn ngnh K thut
my tnh v sinh vin cc khi in t. tip nhn kin thc d dng, sinh vin cn trang
b trc kin thc v thit k s v h thng s.
Gio trnh ny c bin dch v tng hp t kinh nghim nghin cu ging dy ca tc
gi v ba ngun ti liu chnh:

IEEE Standard for Verilog Hardware Description Language, 2006;

Verilog Digital System Design, Second Edition, McGraw-Hill;

The Complete Verilog Book, Vivek Sagdeo, Sun Micro System, Inc.
Nhm cung cp mt lung kin thc mch lc, gio trnh c chia ra lm 9 chng:

Chng 1: Dn nhp thit k h thng s vi Verilog. Chng ny s gii thiu

lch s pht trin ca ngn ng m t phn cng Verilog, bn cnh mt qui trnh thit
k vi mch s dng ngn ng m t phn cng Verilog cng c trnh by c th y.

Chng 2: Trnh by cc t kha c s dng trong mi trng m t thit k bi

Verilog.

Chng 3: Trnh by cc loi d liu c s dng trong thit k mch bi Verilog,

gm hai loi d liu chnh l loi d liu net v loi d liu bin.

Chng 4: Trnh by cc ton t cng nh cc dng biu thc c h tr bi Verilog.

Chng 5: Gii thiu cu trc ca mt thit k, phng thc s dng thit k con.

Chng 6: Trnh by phng php thit k s dng m hnh cu trc, trong phng

[Type text]

Page 2

Gio trnh ngn ng Verilog HDL

thc ny, module thit k c xy dng bng cch gi cc module thit k nh hn v kt
ni chng li.
Chng 7: Trnh by phng thc thit k s dng m hnh RTL bi php gn ni tip

v m hnh hnh vi s dng ngn ng c tnh tru tng cao tng t nh ngn ng lp
trnh. Phn thit k my trng thi s dng m hnh hnh vi cng c nu ra trong chng
ny.

Chng 8: Trnh by phng php thit k v s dng tc v v hm.

Chng 9: Gii thiu cc phng php kim tra chc nng ca thit k.
Do thi gian cng nh khi lng trnh by gio trnh khng cho php tc gi i su hn

v mi kha cnh ca thit k vi mch nh phn tch nh thi, tng hp phn cng, ...
c c nhng kin thc ny, c gi c th tham kho trong cc ti liu tham kho m gio
trnh ny cung cp.
Mc d nhm tc gi c gng bin son k lng tuy nhin cng kh trnh khi
nhng thiu st. Nhm tc gi mong nhn c nhng ng gp mang tnh xy dng t
qu c gi nhm chnh sa gio trnh hon thin hn.

Nhm tc gi

[Type text]

Page 3

Gio trnh ngn ng Verilog HDL

Contents
Li ni u.....................................................................................................................................2
1 Chng 1. Dn nhp thit k h thng s vi Verilog.........................................................13
1.1 Qui trnh thit k s............................................................................................................13
1.1.1 Dn nhp thit k........................................................................................................ 15
1.1.2 Testbench trong Verilog................................................................................................ 16
1.1.3 nh gi thit k.......................................................................................................... 16
1.1.3.1 M phng................................................................................................................16
1.1.3.2 K thut chn kim tra (assertion)...........................................................................18
1.1.3.3 Kim tra thng thng............................................................................................19

1.1.4 Bin dch v tng hp thit k.....................................................................................19

1.1.4.1 Phn tch.................................................................................................................20
1.1.4.2 To phn cng........................................................................................................20
1.1.4.3 Ti u logic..............................................................................................................20
1.1.4.4 Binding.....................................................................................................................21
1.1.4.5 Sp xp cell v i dy kt ni.................................................................................21

1.1.5 M phng sau khi tng hp thit k........................................................................... 22

1.1.6 Phn tch thi gian.........................................................................................................23
1.1.7 To linh kin phn cng..............................................................................................23
1.2 Ngn ng m t phn cng Verilog (Verilog HDL)..........................................................23
1.2.1 Qu trnh pht trin Verilog..........................................................................................23
1.2.2 Nhng c tnh ca Verilog.........................................................................................24
1.2.2.1 Mc chuyn mch.............................................................................................24
1.2.2.2 Mc cng...........................................................................................................24
1.2.2.3 tr hon gia pin n pin...................................................................................25
1.2.2.4 M t Bus................................................................................................................25
1.2.2.5 Mc hnh vi........................................................................................................25
1.2.2.6 Nhng tin ch h thng.........................................................................................25
1.2.2.7 PLI...........................................................................................................................25

1.2.3 S lc v Verilog.......................................................................................................25
1.3 Tng kt.............................................................................................................................. 26
[Type text]

Page 4

Gio trnh ngn ng Verilog HDL

1.4 Bi tp..................................................................................................................................26
2 Chng 2.

Qui c v t kha............................................................................................. 28

2.1 Khong trng.......................................................................................................................28

2.2 Ch thch.............................................................................................................................. 28
2.3 Ton t.................................................................................................................................28
2.4 S hc..................................................................................................................................28
2.4.1 Hng s nguyn............................................................................................................29
2.4.2 Hng s thc................................................................................................................ 32
2.4.3 S o...........................................................................................................................33
2.5 Chui....................................................................................................................................33
2.5.1.1 Khai bo bin chui................................................................................................33
2.5.1.2 X l chui...............................................................................................................34
2.5.1.3 Nhng k t c bit trong chui............................................................................34

2.6 nh danh, t kha v tn h thng....................................................................................34

2.6.1 nh danh vi k t \................................................................................................. 35
2.6.2 Tc v h thng v hm h thng...............................................................................35
2.7 Bi tp..................................................................................................................................36
3 Chng 3.

Loi d liu trong Verilog..................................................................................70

3.1 Khi qut.............................................................................................................................. 70

3.2 Nhng h thng gi tr........................................................................................................70
3.3 Khai bo loi d liu.......................................................................................................... 71
3.3.1 Gii thiu......................................................................................................................71
3.4 Khai bo loi d liu net ....................................................................................................72
3.4.1 Gii thiu......................................................................................................................72
3.4.2 Wire v Tri ....................................................................................................................73
3.4.3 Wired net ...................................................................................................................... 75
3.4.3.1 Wand v triand Nets................................................................................................75
3.4.3.2 Wor v Tri or............................................................................................................75

3.4.4 Tri reg net ..................................................................................................................... 76

[Type text]

Page 5

Gio trnh ngn ng Verilog HDL

3.4.5 Tri 0 v Tri 1 Nets......................................................................................................... 77
3.4.6 Supply0 v Supply1 Nets.............................................................................................. 77
3.4.7 Thi gian tr hon trn net ............................................................................................77
3.5 Khai bo loi d liu bin - reg......................................................................................... 79
3.6 Khai bo port.......................................................................................................................79
3.6.1 Gii thiu......................................................................................................................79
3.6.2 input...............................................................................................................................79
3.6.3 output.............................................................................................................................79
3.6.4 inout...............................................................................................................................80
3.7 Khai bo mng v phn t nh mt v hai chiu..............................................................80
3.7.1 Gii thiu......................................................................................................................80
3.7.2 Mng net ...................................................................................................................... 81
3.7.3 Mng thanh ghi............................................................................................................. 81
3.7.4 Mng phn t nh........................................................................................................81
3.8 Khai bo loi d liu bin.................................................................................................82
3.8.1 Gii thiu......................................................................................................................83
3.8.2 Integer............................................................................................................................83
3.8.3 Time...............................................................................................................................83
3.8.4 S thc (real) v thi gian thc (realtime)...................................................................83
3.9 Khai bo tham s................................................................................................................ 84
3.9.1 Gii thiu......................................................................................................................84
3.9.2 Tham s module (module parameter)........................................................................... 85
3.9.2.1 Parameter................................................................................................................85
3.9.2.1.1 Gii thiu.........................................................................................................85
3.9.2.1.2 Thay i gi tr ca tham s khai bo parameter............................................85
3.9.2.1.2.1 Pht biu defparam...................................................................................86
3.9.2.1.2.2 Php gn gi tr tham s khi gi instance ca module..............................87
3.9.2.1.3 S ph thuc tham s.....................................................................................91
3.9.2.2 Tham s cc b (local parameter)..........................................................................92

[Type text]

Page 6

Gio trnh ngn ng Verilog HDL

3.9.3 Tham s c t (specify parameter).............................................................................92
3.10 Bi tp................................................................................................................................94
4 Chng 4.

Ton t, Ton hng v Biu thc.......................................................................95

4.1 Biu thc gi tr hng s.................................................................................................... 95

4.2 Ton t.................................................................................................................................96
4.2.1 Ton t vi ton hng s thc.....................................................................................96
4.2.2 Ton t u tin..............................................................................................................97
4.2.3 S dng s nguyn trong biu thc.............................................................................98
4.2.4 Th t tnh ton trong biu thc..................................................................................99
4.2.5 Ton t s hc (+, -, *, /, %, **, +, -)...........................................................................99
4.2.6 Biu thc s hc vi tp thanh ghi (regs) v s nguyn (integer)............................101
4.2.7 Ton t quan h (>, <, >=, <=)...................................................................................102
4.2.8 Ton t so snh bng (==, !=, ===, !==)....................................................................103
4.2.9 Ton t logic (&&, ||, !).............................................................................................. 104
4.2.10 Ton t thao tc trn bit (&, |, ^, ~, ~^, ^~)..............................................................104
4.2.11 Ton t gim.............................................................................................................106
4.2.12 Ton t dch (>>, <<, >>>, <<<).............................................................................. 107
4.2.13 Ton t iu kin (?:)..............................................................................................108
4.2.14 Ton t ghp ni ({}) v Ton t lp ({{}})..........................................................109
4.2.14.1 Ton t ghp ni {}.............................................................................................109
4.2.14.2 Ton t lp {{}}...................................................................................................109

4.3 Ton hng.......................................................................................................................... 111

4.3.1 Vector bit-select v part-select addressing.................................................................. 111
4.3.2 a ch mng v phn t nh.....................................................................................112
4.3.3 Chui...........................................................................................................................113
4.3.3.1 Ton t chui........................................................................................................114
4.3.3.2 Gi tr chui m v vn tim n....................................................................114
4.3.3.3 Chui rng............................................................................................................115

4.4 Biu thc tr hon thi gian ti thiu, trung bnh, v ti a........................................... 115
[Type text]

Page 7

Gio trnh ngn ng Verilog HDL

4.5 Biu thc di bit..........................................................................................................117
4.5.1 Qui lut cho biu thc di bit............................................................................... 117
4.5.2 V d minh ha vn v biu thc di bit....................................................... 118
4.5.3 V d minh ha v biu thc t xc nh................................................................. 119
4.6 Biu thc c du...............................................................................................................120
4.6.1 Qui nh cho nhng loi biu thc............................................................................ 120
4.6.2 Nhng bc nh gi mt biu thc......................................................................... 121
4.6.3 Nhng bc nh gi mt php gn...........................................................................122
4.6.4 Tnh ton nhng biu thc ca hai s c du X v Z...............................................122
4.7 Nhng php gn v php rt gn...................................................................................... 122
4.8 Bi tp................................................................................................................................123
5 Chng 5. Cu trc phn cp v module................................................................................124
5.1 Cu trc phn cp............................................................................................................ 124
5.2 Module.............................................................................................................................. 124
5.2.1 Khai bo module..........................................................................................................124
5.2.2 Module mc cao nht................................................................................................. 126
5.2.3 Gi v gn c tnh mt module (instantiate)............................................................126
5.2.4 Khai bo port............................................................................................................... 129
5.2.4.1 nh ngha port......................................................................................................129
5.2.4.2 Lit k port............................................................................................................130
5.2.4.3 Khai bo port trong thn module...........................................................................130
5.2.4.4 Khai bo port u module.....................................................................................131
5.2.4.5 Kt ni cc port ca module c gi bng danh sch th t............................132
5.2.4.6 Kt ni cc port ca module c gi bng tn..................................................133
5.2.4.7 S thc trong kt ni port.....................................................................................134
5.2.4.8 Kt ni nhng port khng tng t nhau..............................................................135
5.2.4.9 Nhng qui nh khi kt ni port.............................................................................135
5.2.4.10 Loi net to ra t vic kt ni port khng tng t nhau..................................136
5.2.4.11 Kt ni nhng gi tr c du thng qua (port)....................................................137

5.3 Bi tp...............................................................................................................................137
[Type text]

Page 8

Gio trnh ngn ng Verilog HDL

6 Chng 6. M hnh thit k cu trc (Structural model).......................................................138
6.1 Gii thiu..........................................................................................................................138
6.2 Nhng linh kin c bn...................................................................................................138
6.2.1 Cng and, nand, or, nor, xor, xnor.............................................................................. 138
6.2.2 Cng buf v not...........................................................................................................139
6.2.3 Cng ba trng thi bufif1, bufif0, notif1, v notif0....................................................140
6.2.4 Cng tc MOS............................................................................................................ 141
6.2.5 Cng tc truyn hai chiu..........................................................................................142
6.2.6 Cng tc CMOS..........................................................................................................143
6.2.7 Ngun pullup v pulldown..........................................................................................144
6.2.8 M hnh mnh logic.............................................................................................. 145
6.2.9 mnh v gi tr ca nhng tn hiu kt hp........................................................146
6.2.9.1 S kt hp gia nhng tn hiu c mnh r rng...........................................146
6.2.9.2 mnh khng r rng: ngun v s kt hp.....................................................147
6.2.9.3 Tn hiu c mnh khng r rng v tn hiu c mnh r rng...................152

6.2.10 S suy gim mnh bng nhng linh kin khng tr........................................ 157
6.2.11 S suy gim mnh bng nhng linh kin tr................................................... 157
6.2.12 mnh ca loi net ..............................................................................................158
6.2.12.1 mnh ca net tri0, tri1...................................................................................158
6.2.12.2 mnh ca trireg.............................................................................................158
6.2.12.3 mnh ca net supply0, supply1.....................................................................158

6.2.13 tr hon cng (gate) v net ................................................................................. 158

6.2.14 tr hon min:typ:max...........................................................................................160
6.2.15 phn r in tch ca net trireg...........................................................................161
6.2.15.1 Qu trnh phn r in tch.................................................................................161
6.2.15.2 c t tr hon ca thi gian phn r in tch..................................................161

6.3 Nhng phn t c bn ngi dng t nh ngha (UDP)............................................... 163

6.3.1 nh ngha phn t c bn UDP................................................................................163
6.3.1.1 Tiu UDP..........................................................................................................165
6.3.1.2 Khai bo cng (port) UDP.....................................................................................165

[Type text]

Page 9

Gio trnh ngn ng Verilog HDL

6.3.1.3 Khai bo khi to UDP tun t.............................................................................166
6.3.1.4 Bng khai bo UDP...............................................................................................166
6.3.1.5 Gi tr Z trong UDP................................................................................................167
6.3.1.6 Tng hp cc k hiu............................................................................................167

6.3.2 UDP t hp................................................................................................................. 168

6.3.3 UDP tun t tch cc mc......................................................................................... 169
6.3.4 UDP tun t tch cc cnh.........................................................................................170
6.3.5 Mch hn hp gia UDP mch tch cc mc v UDP tch cc cnh..................... 171
6.3.6 Gi s dng UDP....................................................................................................... 172
6.4 M t mch t hp v mch tun t s dng m hnh cu trc....................................173
6.4.1 M t mch t hp.....................................................................................................173
6.4.2 M t mch tun t................................................................................................... 175
6.5 Bi tp................................................................................................................................178
7 Chng 7. M hnh thit k hnh vi (Behavioral model).......................................................220
7.1 Khi qut............................................................................................................................ 220
7.2 Php gn ni tip hay php gn lin tc - m hnh thit k RTL (continuous assignment)
..................................................................................................................................................220
7.2.1 Gii thiu....................................................................................................................220
7.2.2 Php gn ni tip khi khai bo net ............................................................................ 220
7.2.3 Pht biu php gn ni tip tng minh assign........................................................ 221
7.2.4 To tr hon (delay) cho php gn.........................................................................222
7.2.5 mnh php gn......................................................................................................223
7.3 Php gn qui trnh - m hnh thit k mc thut ton (procedural assignment)....224
7.3.1 Php gn khai bo bin............................................................................................... 227
7.3.2 Php gn qui trnh kn (blocking assignment) '='........................................................ 228
7.3.2.1 Mch t hp vi php gn qui trnh kn................................................................228

7.3.3 Php gn qui trnh h (non-blocking assignment)...................................................... 229

7.3.3.1 Mch tun t vi php gn qui trnh h................................................................233

7.4 Pht biu c iu kin...................................................................................................... 233

7.4.1 Cu trc if-else-if........................................................................................................ 235
[Type text]

Page 10

Gio trnh ngn ng Verilog HDL

7.5 Pht biu Case................................................................................................................... 236
7.5.1 Pht biu Case vi dont care................................................................................. 239
7.5.2 Pht biu case vi biu thc hng s........................................................................240
7.6 Pht biu vng lp............................................................................................................240
7.6.1 Cc pht biu lp........................................................................................................240
7.6.2 C php........................................................................................................................241
7.7 iu khin nh thi (procedural timing controls)..........................................................244
7.7.1 iu khin tr hon (delay control)............................................................................ 244
7.7.2 iu khin s kin (event control)............................................................................245
7.7.3 Pht biu wait..........................................................................................................246
7.8 Pht biu khi....................................................................................................................248
7.8.1 Khi tun t................................................................................................................248
7.8.2 Khi song song (fork-join)..........................................................................................249
7.8.3 Tn khi...................................................................................................................... 250
7.9 Cu trc qui trnh...............................................................................................................250
7.9.1 Cu trc initial............................................................................................................ 251
7.9.2 Cu trc always...........................................................................................................251
7.10 My trng thi (state machine)........................................................................................ 252
7.10.1 My trng thi Moore............................................................................................... 252
7.10.2 My trng thi Mealy................................................................................................255
7.11 Bi tp..............................................................................................................................258
8 Chng 8.

Tc v (task) v hm (function).........................................................................263

8.1 Phn bit gia tc v (task) v hm (function)................................................................263

8.2 Tc v v kch hot tc v................................................................................................264
8.2.1 nh ngha task............................................................................................................264
8.2.2 Khai bo task............................................................................................................... 265
8.2.3 Kch hot tc v v truyn i s............................................................................. 266
8.2.4 S dng b nh tc v v s kch hot ng thi................................................... 270
[Type text]

Page 11

Gio trnh ngn ng Verilog HDL

8.3 Hm v vic gi hm........................................................................................................ 270
8.3.1 Khai bo hm...............................................................................................................270
8.3.2 Tr v mt gi tr t hm...........................................................................................273
8.3.3 Vic gi hm.............................................................................................................. 273
8.3.4 Nhng qui tc v hm................................................................................................273
8.3.5 S dng nhng hm hng s.....................................................................................275
8.4 Bi tp................................................................................................................................276
9 Chng 9.

Kim tra thit k...............................................................................................277

9.1 Testbench........................................................................................................................... 277

9.1.1 Kim tra mch t hp................................................................................................278
9.1.2 Kim tra mch tun t...............................................................................................280
9.2 K thut to testbench....................................................................................................... 281
9.2.1 D liu kim tra......................................................................................................... 282
9.2.2 iu khin m phng.................................................................................................282
9.2.3 Thit lp gii hn d liu......................................................................................... 283
9.2.4 Cung cp d liu ng b......................................................................................... 284
9.2.5 Tng tc testbench....................................................................................................285
9.2.6 To nhng khong thi gian ngu nhin.................................................................. 287
9.2.6.1.1 end..................................................................................................................287

9.3 Kim tra thit k...............................................................................................................288

9.4 K thut chn (assertion) dng kim tra thit k........................................................ 289
9.4.1 Li ch ca k thut chn kim tra............................................................................289
9.4.2 Th vin thit k m (OVL).....................................................................................290
9.4.3 S dng k thut chn gim st.................................................................................291
9.5 Bi tp................................................................................................................................293

[Type text]

Page 12

Gio trnh ngn ng Verilog HDL

1 Chng 1. Dn nhp thit k h thng s vi Verilog

Khi kch thc v phc tp ca h thng thit k ngy cng tng, nhiu cng c h
tr thit k trn my tnh (CAD) c s dng vo qu trnh thit k phn cng. Thi k
u, nhng cng c m phng v to ra phn cng a ra phng php thit k, kim
tra, phn tch, tng hp v t ng to ra phn cng mt cch phc tp. S pht trin
khng ngng ca nhng cng c thit k mt cch t ng l do s pht trin ca nhng
ngn ng m t phn cng (HDLs) v nhng phng php thit k da trn nhng ngn ng
ny. Da trn nhng ngn ng m t phn cng (HDLs), nhng cng c CAD trong thit k
h thng s c pht trin v c nhng k s thit k phn cng s dng rng ri.
Hin ti, ngi ta vn ang tip tc nghin cu tm ra nhng ngn ng m t phn
cng tt hn. Mt trong nhng ngn ng m t phn cng c s dng rng ri nht l
ngn ng Verilog HDL. Do c chp nhn rng ri trong ngnh cng nghip thit k s,
Verilog tr thnh mt kin thc c i hi phi bit i vi nhng k s cng nh sinh
vin lm vic v hc tp trong lnh vc phn cng my tnh.
Chng ny s trnh by nhng cng c v mi trng lm vic c sn tng thch vi
ngn ng Verilog m mt k s thit k c th s dng trong qui trnh thit k t ng ca
mnh gip y nhanh tin thit k. u tin s trnh by tng bc v thit k phn
cp, thit k mc cao t vic m t thit k bng ngn ng Verilog n vic to ra phn
cng ca thit k . Nhng qui trnh v nhng t kha chuyn mn cng s c minh ha
phn ny. K tip s tho lun nhng cng c CAD hin c tng thch vi Verilog v
chc nng ca n trong mi trng thit k t ng. Phn cui cng ca chng ny s
ni v mt s c tnh ca Verilog khin n tr thnh mt ngn ng c nhiu k s
thit k phn cng la chn.

1.1 Qui trnh thit k s

Trong thit k mt h thng s s dng mi trng thit k t ng, qui trnh thit k
bt u bng vic m t thit k ti nhiu mc tru tng khc nhau v kt thc bng
vic to ra danh sch cc linh kin cng nh cc ng kt ni gia cc linh kin vi nhau
(netlist) cho mt mch tch hp vi ng dng c th (ASIC), mch in (layout) cho mt mch
tch hp theo yu cu khch hng (custom IC), hoc mt chng trnh cho mt thit b logic
c kh nng lp trnh c (PLD). Hnh 1.1 m t tng bc trong qui trnh thit k ny.
Bc u ca thit k, mt thit k s c m t bi s hn hp gia m t
mc hnh vi (behavioural) Verilog, s dng nhng gi (module) thit k Verilog
c thit k sn, v vic gn h thng cc bus v wire lin kt cc gi thit k ny
[Type text]

Page 13

Gio trnh ngn ng Verilog HDL

thnh mt h thng hon chnh.
K s thit k cng phi c trch nhim to ra d liu kim tra (testbench) xem thit
k ng chc nng hay cha cng nh dng kim tra thit k sau khi tng hp. Vic
kim tra thit k c th thc hin c bng vic m phng, chn nhng k thut kim tra,
kim tra thng thng hoc kt hp c ba phng php trn.
Sau bc kim tra nh gi thit k (bc ny c gi l kim tra tin tng hp
(presynthesis verification)), thit k s c tip tc bng vic tng hp to ra phn
cng thc s cho h thng thit k cui cng (ASIC, custom IC hay FPLD,). Nu h
thng thit k l ASIC, thit k s s c sn xut bi nh sn xut khc; nu l custom
IC, thit k s c sn xut trc tip; nu l FPLD, thit k s c np ln thit b
lp trnh c.

Hnh 1.1 Lung thit k ASIC

Sau bc tng hp v trc khi phn cng thc s c to ra, mt qu trnh m
phng khc (hu tng hp (postsynthesis)) phi c thc hin. Vic m phng ny, ta c
[Type text]

Page 14

Gio trnh ngn ng Verilog HDL

th s dng testbench tng t testbench s dng trong m phng tin tng hp
(presynthesis).
Bng phng php ny, m hnh thit k mc hnh vi v m hnh phn cng ca
thit k c kim tra vi cng d liu ng vo. S khc nhau gia m phng tin tng
hp v hu tng hp l mc chi tit c th t c t mi loi m phng.
Nhng phn tip theo s m t t m v mi khi trong Hnh 1.1.

1.1.1

Dn nhp thit k

Bc u tin trong thit k h thng s l bc dn nhp thit k. Trong bc ny,

thit k c m t bng Verilog theo phong cch phn cp t cao xung thp (topdown). Mt thit k hon chnh c th bao gm nhng linh kin mc cng hoc mc
transistor, nhng khi (module) phn cng c chc nng phc tp hn c m t mc
hnh vi, hoc nhng linh kin c lit k bi cu trc bus.
Do nhng thit k Verilog mc cao thng c m t mc m ti , n m
t h thng nhng thanh ghi v s truyn d liu gia nhng thanh ghi ny thng qua h
thng bus, v vy, vic m t h thng thit k mc ny c xem nh l mc
truyn d liu gia cc thanh ghi (RTL - Register Transfer Level). Mt thit k hon chnh
c m t nh vy s to ra c phn cng tng ng thc s r rng. Nhng cu trc
thit k Verilog mc RTL s dng nhng pht biu qui trnh (producedural
statements), php gn lin tc (continuous assignments), v nhng pht biu gi s dng cc
khi (module) xy dng sn.
Nhng pht biu qui trnh Verilog (procedural statements) c dng m t mc
hnh vi mc cao. Mt h thng hoc mt linh kin c m t mc hnh vi th tng
t vi vic m t trong ngn ng phn mm. V d, chng ta c th m t mt linh kin
bng vic kim tra iu kin ng vo ca n, bt c hiu, ch cho n khi c s kin no
xy ra, quan st nhng tn hiu bt tay v to ra ng ra. M t h thng mt cch qui trnh
nh vy, cu trc if-else, case ca Verilog cng nh nhng ngn ng phn mm khc u s
dng nh nhau.
Nhng php gn lin tc (continuous assignment) trong Verilog l nhng php gn cho
vic th hin chc nng nhng khi logic, nhng php gn bus, hoc m t vic kt ni
gia h thng bus v cc chn ng vo, ng ra. Kt hp vi nhng hm Boolean v nhng
biu thc c iu kin, nhng cu trc ngn ng ny c th c dng m t nhng linh
kin v h thng theo nhng php gn thanh ghi v bus ca chng.
Nhng pht biu gi s dng khi Verilog c thit k sn (instantiantion
statements) c dng cho nhng linh kin mc thp trong mt thit k mc cao
[Type text]

Page 15

Gio trnh ngn ng Verilog HDL

hn. Thay v m t mc hnh vi, chc nng, hoc bus ca mt h thng, chng ta c
th m t mt h thng bng Verilog bng cch kt ni nhng linh kin mc thp
hn. Nhng linh kin ny c th nh nh l mc cng hay transistor, hoc c th ln nh l
mt b vi x l hon chnh.

1.1.2

Testbench trong Verilog

Mt h thng c thit k dng Verilog phi c m phng v kim tra xem thit k
ng chc nng hay cha trc khi to ra phn cng. Trong qu trnh ny, nhng li thit
k v s khng tng thch gia nhng linh kin dng trong thit k c th c pht hin.
Vic chy m phng v ki m tra mt thit k i hi phi to ra mt d liu ng vo
kim tra v qu trnh quan st kt qu sau khi chy m phng, d liu dng kim tra ny
c gi l testbench. Mt testbench s dng cu trc mc cao ca Verilog to ra d
liu kim tra, quan st p ng ng ra, v c vic kt ni gia nhng tn hiu trong thit
k. Bn trong testbench, h thng thit k cn chy m phng s c gi ra (instantiate)
trong testbench. D liu testbench cng vi h thng thit k s to ra mt m hnh m
phng m s c s dng bi mt cng c m phng Verilog.

1.1.3

nh gi thit k

Mt nhim v quan trng trong bt k thit k s no cng cn l nh gi thit k.

nh gi thit k l qu trnh m ngi thit k s kim tra thit k ca h c sai st no
c th xy ra trong sut qu trnh thit k hay khng. Mt sai st thit k c th xy ra do s
m t thit k m h, do sai st ca ngi thit k, hoc s dng khng ng nhng khi
trong thit k. nh gi thit k c th thc hin bng m phng, bng vic chn
nhng k thut kim tra, hoc kim tra thng thng.

1.1.3.1 M phng
Chy m phng dng trong vic nh gi thit k, c thc hin trc khi thit k
c tng hp. Bc chy m phng ny c hiu nh m phng mc hnh vi, mc
RTL hay tin tng hp. mc RTL, mt thit k bao gm xung thi gian clock
nhng khng bao gm tr hon thi gian trn cng v dy kt ni (wire). Chy m phng
mc ny s chnh xc theo xung clock. Thi gian ca vic chy m phng mc
RTL l theo tn hiu xung clock, khng quan tm n nhng vn nh: nguy him tim n
c th khin thit k b li (hazards, glitch), hin tng chy ua khng kim sot gia
nhng tn hiu (race conditions), nhng vi phm v thi gian setup v hold ca tn hiu ng
vo, v nhng vn lin quan n nh thi khc. u im ca vic m phng ny l tc
chy m phng nhanh so vi chy m phng mc cng hoc mc transistor.
[Type text]

Page 16

Gio trnh ngn ng Verilog HDL

Chy m phng cho mt thit k i hi d liu kim tra. Thng thng trong mi
trng m phng Verilog s cung cp nhiu phng php khc nhau a d liu
kim tra ny vo thit k kim tra. D liu kim tra c th c to ra bng ha,
s dng nhng cng c son tho dng sng, hoc bng testbench. Hnh 1.2 m t hai cch
khc nhau nh ngha d liu kim tra ng vo ca mt cng c m phng. Nhng
ng ra ca cng c m phng l nhng dng sng ng ra (c th quan st trc quan).

Hnh 1.2. Hai cch khc nhau nh ngha d liu kim tra ng vo
chy m phng vi Verilog testbench, trong testbench s gi h thng thit k ra
kim tra, lc ny h thng thit k c xem nh l mt phn ca testbench, testbench s
cung cp d liu kim tra n ng vo ca h thng thit k. Hnh 1.3 m t mt on code
ca mt mch m, testbench ca n, cng nh kt qu chy m phng ca n di dng
sng ng ra. Quan st hnh ta thy vic chy m phng s nh gi chc nng ca mch
m. Vi mi xung clock th ng ra b m s tng ln 1. Ch rng, theo biu thi gian
th ng ra b m thay i ti cnh ln xung clock v khng c thi gian tr hon do cng
cng nh tr hon trn ng truyn. Kt qu chy m phng cho thy chc nng ca mch
m l chnh xc m khng cn quan tm n tn s xung clock.
Hin nhin, nhng linh kin phn cng thc s s c p ng khc nhau. Da trn nh
thi v thi gian tr hon ca nhng khi c s dng, thi gian t cnh ln xung clock
n ng ra ca b m s c tr hon khc khng. Hn na, nu tn s xung clock c
cp vo mch thc s qu nhanh so vi tc truyn tn hiu bn trong cc cng v
transistor ca thit k th ng ra ca thit k s khng th bit c.
Vic m phng ny khng cung cp chi tit v cc vn nh thi ca h thng thit
k c m phng. Do , nhng vn tim n v nh thi ca phn cng do tr hon
trn cng s khng th pht hin c. y l vn in hnh ca qu trnh m phng tin
tng hp hoc m phng mc hnh vi. iu bit c trong Hnh 1.3 l b m ca
[Type text]

Page 17

Gio trnh ngn ng Verilog HDL

ta m s nh phn. Thit k hot ng nhanh chm th no, hot ng c tn s no
ch c th bit c bng vic kim tra thit k sau tng hp.

Hnh 1.3. M t mt on code ca mt mch flip-flop

1.1.3.2 K thut chn kim tra (assertion)

Thay v phi d theo kt qu m phng bng mt hay to nhng d liu kim tra
testbench phc tp, k thut chn thit b gim st c th c s dng kim tra tun t
nhng c tnh ca thit k trong sut qu trnh m phng. Thit b gim st c t bn
trong h thng thit k, c m phng bi ngi thit k. Ngi thit k s quyt nh
xem chc nng ca thit k ng hay sai, nhng iu kin no thit k cn phi tha mn.
Nhng iu kin ny phi tun theo nhng c tnh thit k, v thit b gim st c
chn vo h thng thit k m bo nhng c tnh ny khng b vi phm. Chui thit
b gim st ny s sai nu mt c tnh no c t vo bi ngi thit k b vi
phm. N s cnh bo cho ngi thit k rng thit k khng ng chc nng nh mong
i. Th vin OVL (Open Verification Library) cung cp mt chui nhng thit b gim st
chn vo h thng thit k gim st nhng c tnh thng thng ca thit k.
Ngi thit k c th dng nhng k thut gim st ca ring mnh chn vo thit k v
[Type text]

Page 18

Gio trnh ngn ng Verilog HDL

dng chng kt hp vi testbench trong vic kim tra nh gi thit k.

1.1.3.3 Kim tra thng thng

Kim tra thng thng l qu trnh kim tra nhng c tnh bt k ca thit k. Khi
mt thit k hon thnh, ngi thit k s xy dng mt chui nhng c tnh tng ng
vi hnh vi ca thit k. Cng c kim tra thng thng s kim tra thit k m bo
rng nhng c tnh c m t p ng c tt c nhng iu kin. Nu c mt c
tnh c pht hin l khng p ng ng, c tnh c xem nh vi phm. c tnh
bao ph (coverage) ch ra bao nhiu phn trm c tnh ca thit k c kim tra.

1.1.4

Bin dch v tng hp thit k

Tng hp l qu trnh to ra phn cng t ng t mt m t thit k phn cng tng

ng r rng. Mt m t phn cng Verilog dng tng hp khng th bao gm tn hiu v
m t nh thi mc cng, hoc nhng cu trc ngn ng khc m khng dch sang nhng
phng trnh logic tun t hoc t hp. Hn th na, nhng m t phn cng Verilog
dng cho tng hp phi tun theo nhng phong cch vit code mt cch nht nh cho
mch t hp cng nh mch tun t. Nhng phong cch ny v cu trc Verilog tng
ng ca chng c nh ngha trong vic tng hp RTL.
Trong qui trnh thit k, sau khi mt thit k c m t hon thnh v kt qu m
phng tin tng hp ca n c kim tra bi ngi thit k, n phi c bin dch
tin gn hn n vic to thnh phn cng thc s trn silicon. Bc thit k ny i hi
vic m t phn cng ca thit k phi c ch ra, ngha l chng ta phi ch n mt
ASIC c th, hoc mt FPGA c th nh l thit b phn cng mc ch ca thit k. Khi
thit b mc ch c ch ra, nhng tp tin m t v cng ngh (technology files) ca phn
cng (ASIC, FPGA, hoc custom IC) s cung cp chi tit nhng thng tin v nh thi v
m t chc nng cho qu trnh bin dch. Qu trnh bin dch s chuyn i nhng phn
khc nhau ca thit k ra mt nh dng trung gian (bc phn tch), kt ni tt c cc
phn li vi nhau, to ra mc logic tng ng (bc tng hp), sp xp v kt ni (place
and route) nhng linh kin trong thit b phn cng mc ch li vi nhau thc hin chc
nng nh thit k mong mun v to ra thng tin chi tit v nh thi trong thit k.
Hnh 1.4 m t qu trnh bin dch v m t hnh nh kt qu ng ra ca mi bc bin
dch. Nh trn hnh, ng vo ca bc ny l mt m t phn cng bao gm nhng mc
m t khc nhau ca Verilog, v kt qu ng ra ca n l mt phn cng chi tit cho thit
b phn cng mc ch nh FPLD hay sn xut chip ASIC.

[Type text]

Page 19

Gio trnh ngn ng Verilog HDL

Hnh 1.4. M t qu trnh bin dch v m t hnh nh kt qu ng ra

1.1.4.1 Phn tch

Mt thit k hon chnh c m t dng Verilog c th bao gm m t nhiu mc
khc nhau nh mc hnh vi, h thng bus v dy kt ni vi nhng linh kin Verilog
khc. Trc khi mt thit k hon chnh to ra phn cng, thit k phi c phn tch v
to ra mt nh dng ng nht cho tt c cc phn trong thit k. Bc ny cng kim tra
c php v ng ngha ca m ng vo Verilog.

1.1.4.2 To phn cng

Sau khi to c mt d liu thit k c nh dng ng nht cho tt c cc linh kin
trong thit k, bc tng hp s bt u bng chuyn i d liu thit k trn sang
nhng nh dng phn cng thng thng nh mt chui nhng biu thc Boolean hay
mt netlist nhng cng c bn.

1.1.4.3 Ti u logic
Bc k tip ca qu trnh tng hp, sau khi mt thit k c chuyn i sang
mt chui nhng biu thc Boolean, bc ti u logic c thc hin. Bc ny nhm
mc ch lm gim nhng biu thc vi ng vo khng i, loi b nhng biu thc lp li,
ti thiu hai mc, ti thiu nhiu mc. y l qu trnh tnh ton rt hao tn thi gian v
cng sc, mt s cng c cho php ngi thit k quyt nh mc ti u. Kt qu ng ra
ca bc ny cng di dng nhng biu thc Boolean, m t logic di dng bng, hoc
netlist gm nhng cng c bn.

[Type text]

Page 20