TEPZZ - 5499B - T: European Patent Specification

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*EP001335499B1*
(11) EP 1 335 499 B1
(12) EUROPEAN PATENT SPECIFICATION
(45) Date of publication and mention
of the grant of the patent:
30.07.2014 Bulletin 2014/31
(21) Application number: 03250369.0
(22) Date of filing: 21.01.2003
(51) Int Cl.:
H04B 1/16
(2006.01)
H04M 1/73
(2006.01)
G06F 1/32
(2006.01)
(54) Semiconductor device and electronic device
Halbleiteranordnung und elektronisches Gert
Dispositif semiconducteur et appareil lectronique
(84) Designated Contracting States:
DE FR GB
(30) Priority: 06.02.2002 JP 2002029171
(43) Date of publication of application:
13.08.2003 Bulletin 2003/33
(73) Proprietor: Fujitsu Semiconductor Limited
Kohoku-ku, Yokohama-shi
Kanagawa 222-0033 (JP)
(72) Inventors:
Iwata, Jun
Taniguchi, Shoji
Kuroiwa, Koichi
Yamada, Yoshikazu
(74) Representative: Schultes, Stephan et al
Haseltine Lake LLP
Lincoln House, 5th Floor
300 High Holborn
London WC1V 7JH (GB)
(56) References cited:
US-A- 5 339 437 US-A- 5 485 623
US-A- 6 049 884 US-B1- 6 243 831
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Description
[0001] This invention relates to a semiconductor de-
vice and an electronic device and, more particularly, to
a semiconductor device including a first area to which
power is supplied intermittently and a second area to
which power is supplied continuously and an electronic
device including a first circuit to which power is supplied
intermittently and a second circuit to which power is sup-
plied continuously.
[0002] With many portable electronic devices, a tech-
nique for reducing consumption of power by stopping the
supply of power to circuits not used is adopted. With cel-
lular telephones, for example, consumption of power is
reduced by stopping the supply of power to a modem
(modulator/demodulator) and the like except at call time
to lengthen the life of a battery. Sometimes this technique
is called an intermittent receiving method.
[0003] Under this intermittent receiving method, data
which has been stored in a register, a memory, and the
like must be saved before stopping the supply of power.
Under conventional intermittent receiving methods, data
is read before stopping the supply of power and is saved
in a memory to which power is supplied continuously.
When the supply of power is resumed, the data which
has been stored in the memory is read and is restored.
[0004] US5485623 discloses an information processor
which writes data to a RAM before entering a suspend
state, in which power supply to minimum circuit compo-
nents (including the RAM) is maintained.
[0005] Fig. 13 is a view for describing a conventional
intermittent receiving method.
[0006] In this example, a unit comprises a central
processing unit (CPU) 10, a dual port random access
memory (DPRAM) 11, a system bus 12, and a large scale
integrated circuit (LSI) 13.
[0007] The CPU 10 controls each section of the device
according to programs which have been stored in the
DPRAM 11, and performs various operations.
[0008] The DPRAM 11 has stored programs executed
by the CPU 10 and data.
[0009] The system bus 12 connects the CPU 10,
DPRAM 11, and LSI 13 to one another so that data can
be exchanged among them.
[0010] The LSI 13 includes an intermittent control sec-
tion 14 and a power intermittence area 15. The LSI 13
encodes data to be sent and decodes received data.
[0011] The intermittent control section 14 performs the
process of intermittently supplying power to the power
intermittence area 15.
[0012] The power intermittence area 15 includes a
DPRAM 16 and a modem 17. The power intermittence
area 15 is an area to which power is supplied intermit-
tently under the control of the intermittent control section
14.
[0013] The DPRAM 16 temporarily stores data when
the modem 17 processes it.
[0014] The modem 17 performs the process of encod-
ing and decoding data.
[0015] Now, operation in the above conventional inter-
mittent receiving method will be described.
[0016] First, operation performed when data is saved
will be described.
[0017] Fig. 14 is a flow chart for describing operation
performed when data is saved. The following steps will
be performed according to this flow chart.
[0018] [Step S10] The modem 17 receives a request
to begin intermittent control from the intermittent control
section 14 (see (1) in Fig. 15).
[0019] [Step S11] The modem 17 notifies the CPU 10
that it received the request to begin intermittent control
(see (2) in Fig. 15).
[0020] [Step S12] The CPU 10 performs the process
of releasing the DPRAM 11 to save data which has been
stored in the modem 17 (see (3) in Fig. 15).
[0021] [Step S13] The CPU 10 notifies the modem 17
that the DPRAM 11 was released (see (4) in Fig. 15).
[0022] [Step S14] The modem 17 saves the data in the
DPRAM 11 via the system bus 12 (see (5) in Fig. 15).
[0023] [Step S15] When intermittent control is begun,
power to the power intermittence area 15 is turned off.
[0024] By performing the above process, data which
has been stored in the modem 17 can be saved in the
DPRAM 11.
[0025] Now, a process performed when data which has
been saved in the DPRAM 11 is restored to the modem
17 will be described.
[0026] Fig. 16 is a flow chart for describing the process
of restoring data which has been saved in the DPRAM
11 to the modem 17. The following steps will be per-
formed according to this flow chart.
[0027] [Step S30] The intermittent control section 14
notifies the modem 17 of a request to terminate intermit-
tent control and power is turned on (see (1) in Fig. 17).
[0028] [Step S31] The modem 17 performs setting
processes at intermittent control termination time.
that it begins a data restoration process (see (2) in Fig.
17).
[0030] [Step S33] The modem 17 restores data via the
system bus 12 (see (3) in Fig. 17).
that the restoration process is completed (see (4) in Fig.
17).
[0032] [Step S35] After receiving the notification of ter-
mination, the CPU 10 initializes the DPRAM 11 (see (5)
in Fig. 17).
[0033] By performing the above process, data which
has been saved in the DPRAM 11 can be restored to the
modem 17.
[0034] As described above, intermittent receiving en-
ables a reduction in consumption of power by intermit-
tently supplying power to the power intermittence area
15 at need.
[0035] Under the conventional method, however, data
must be transferred by the CPU 10 located outside the
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LSI 13. This will increase the load on the CPU 10.
[0036] Moreover, the system bus 12 is used to transfer
data. Therefore, no other pieces of data can be trans-
ferred before the transfer of the data is completed.
[0037] It is desirable to provide a semiconductor device
with an area to which power is supplied intermittently,
and an electronic device with a circuit to which power is
supplied intermittently, which can save and restored data
without increasing the load on a system
[0038] The invention is defined in the independent
claims, to which reference should now be made. Advan-
tageous features are set out in the sub-claims.
[0039] The above and other objects, features and ad-
vantages of the present invention will become apparent
from the following description when taken in conjunction
with the accompanying drawings which illustrate pre-
ferred embodiments of the present invention by way of
example.
Fig. 1 is a view for describing the principles under-
lying operation in examples useful for understanding
the present invention.
Fig. 2 is a view showing the structure of an embod-
iment of the present invention.
Fig. 3 is a flow chart for describing operation per-
formed when the supply of power to a power inter-
mittence area is stopped in the embodiment shown
in Fig. 2.
Fig. 4 is a view for describing how signals flow when
the supply of power to the power intermittence area
is stopped in the embodiment shown in Fig. 2.
formed when the supply of power to the power inter-
mittence area is resumed in the embodiment shown
in Fig. 2.
is resumed in the embodiment shown in Fig. 2.
Fig. 7 is a view showing the structure of another ex-
ample useful for understanding the present inven-
tion.
Fig. 8 is a view showing how an address space in
the DPRAM shown in Fig. 7 is divided.
mittence area is stopped in the example shown in
Fig. 7.
is stopped in the example shown in Fig. 7.
mittence area is resumed in the example shown in
Fig. 7.
is resumed in the example shown in Fig. 7.
Fig. 13 is a view for describing a conventional inter-
mittent receiving method.
mittence area is stopped in the example shown in
Fig. 13.
Fig. 15 is a view for describing operation performed
when the supply of power to the power intermittence
area is stopped in the example shown in Fig. 13.
mittence area is resumed in the example shown in
Fig. 13.
Fig. 17 is a view for describing operation performed
when the supply of power to the power intermittence
area is resumed in the example shown in Fig. 13.
[0040] Embodiments of the present invention will now
be described with reference to the drawings.
[0041] Fig. 1 is a view for describing the principles un-
derlying the operation of examples useful for understand-
ing the present invention.
[0042] As shown in Fig. 1, a semiconductor device ac-
cording to an example of the present invention comprises
a first area 31 and a second area 32. A memory 32a, a
save circuit 32b, a restoration circuit 32c, and a power
supply control circuit 32d are located in the second area
32.
[0043] Power is supplied intermittently to the first area
31.
[0044] Power is supplied continuously to the second
area 32.
[0045] The memory 32a is located in the second area
32. As described later, the memory 32a has a minimum
storage capacity necessary for storing data which needs
to be saved of data used in the first area 31.
[0046] The save circuit 32b saves data used in the first
area 31 in the memory 32a before the supply of power
to the first area 31 is stopped.
[0047] The restoration circuit 32c restores data saved
in the memory 32a to a predetermined circuit in the first
area 31 when power is supplied again to the first area 31.
[0048] The power supply control circuit 32d stops the
supply of power to the memory 32a after data being re-
stored by the restoration circuit 32c and begins the supply
of power to the memory 32a before the saving of data
being begun by the save circuit 32b.
[0049] Now, operation in Fig. 1 will be described.
[0050] First, operation performed when the supply of
power to the first area 31 is stopped will be described.
[0051] When the supply of power to the first area 31 is
stopped, data, which is used in the first area 31 and which
will be needed again in the case of the supply of power
being resumed, must be saved in the memory 32a. This
process will be performed in compliance with the follow-
ing procedures.
[0052] That is to say, the save circuit 32b obtains data
which will be needed in the case of the supply of power
being resumed of data stored in a register and memory
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(not shown) in the first area 31 and saves it in the memory
32a. In this case, information indicative of a storage lo-
cation, together with the above data, should be stored
for convenience of restoring the data.
[0053] When the saving of the data is completed, the
supply of power to the first area 31 is stopped and circuits
located in the first area 31 stop operating. Therefore, data
stored in registers and memories in this area will be lost.
[0054] Next, operation performed when the supply of
power to the first area 31 is resumed will be described.
[0055] When the supply of power to the first area 31 is
resumed, data saved in the memory 32a must be re-
stored. This process will be performed in compliance with
the following procedures.
[0056] That is to say, the restoration circuit 32c re-
stores data stored in the memory 32a to a predetermined
circuit in the first area 31. In this case, a location to which
the data should be restored can be specified easily by
referring to information indicative of the storage location.
[0057] When the restoring of the data is completed,
the power supply control circuit 32d stops the supply of
power to the memory 32a. As a result, the memory 32a
stops operating and unnecessary consumption of power
can be reduced.
[0058] As described above, with the semiconductor
device according to the present invention the dedicated
memory 32a for saving data is located in the semicon-
ductor device and data is saved in the memory 32a at
the time of the supply of power to the first area 31 being
stopped. As a result, the storage capacity of the memory
32a can be minimized according to the amount of data
to be saved. Data therefore can be saved without increas-
ing the scale of a circuit.
[0059] Moreover, the semiconductor device according
to the present invention includes the power supply control
circuit 32d to supply power only when data has been
saved in the memory 32a. Therefore, the amount of pow-
er consumed by the memory 32a can be reduced.
[0060] In Fig. 1, the power supply control circuit 32d
stops the supply of power only to the memory 32a. How-
ever, it is a matter of course that the power supply control
circuit 32d may stop the supply of power to the save circuit
32b and restoration circuit 32c.
[0061] Now, embodiments of the present invention will
be described.
[0062] Fig. 2 is a view showing the structure of an em-
bodiment of the present invention. As shown in Fig. 2, a
unit according to an embodiment of the present invention
comprises a CPU 10, a DPRAM 11, a system bus 12,
and an LSI (semiconductor device) 13.
tion 14, a power intermittence area 15, a save memory
50, a power control section 51, and a bus 52. The LSI 13
encodes data to be sent and decodes received data.
[0068] The power intermittence area 15 includes a
DPRAM 16 and a modem 17. The power intermittence
area 15 is an area to which power is supplied intermit-
tently.
[0069] The DPRAM 16 temporarily stores data when
the modem 17 processes it.
[0071] Data (hereinafter referred to as work data),
which is used by the modem 17 and which will be needed
when the supply of power is resumed, is saved in the
save memory 50. The storage capacity of the save mem-
ory 50 is set to a minimum capacity according to the
amount of work data to be stored.
[0072] The power control section 51 controls the sup-
ply of power to the save memory 50.
[0073] The bus 52 connects the DPRAM 16, modem
17, save memory 50, and power control section 51 to
one another so that data can be exchanged among them.
[0074] Now, operation in the above embodiment will
be described.
power to the power intermittence area 15 is stopped will
be described. Fig. 3 is a flow chart for describing opera-
tion performed when the supply of power to the power
intermittence area 15 is stopped. The following steps will
outputs a request to begin intermittent control to the mo-
dem 17 and power control section 51 (see (1) in Fig. 4).
[0077] [Step S51] The power control section 51 turns
on power to the save memory 50 (see (2) in Fig. 4).
[0078] [Step S52] The modem 17 saves work data in
the save memory 50 via the bus 52 (see (3) in Fig. 4). In
this case, information indicative of a location where the
work data has been stored, together with the work data,
is stored.
power to the power intermittence area 15 is turned off.
The supply of power to an area in the modem 17 which
controls communication with the intermittent control sec-
tion 14 is continued.
[0080] By performing the above process, work data in
the power intermittence area 15 can be saved in the save
memory 50 and the supply of power to the power inter-
mittence area 15 can be stopped.
[0081] Now, operation performed when the supply of
power to the power intermittence area 15 is resumed will
intermittence area 15 is resumed. The following steps
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will be performed according to this flow chart.
tent control and power to the power intermittence area
15 is turned on (see (1) in Fig. 6).
processes at intermittent control termination time. To be
concrete, the modem 17 performs the process of, for ex-
ample, initializing internal registers and the like.
[0084] [Step S72] The modem 17 restores work data
from the save memory 50 (see (2) in Fig. 6). In this case,
the modem 17 restores the work data to the original lo-
cation by referring to information indicative of the location
where the work data had been stored.
[0085] [Step S73] The modem 17 notifies the power
control section 51 that the restoring of the work data is
completed (see (3) in Fig. 6).
[0086] [Step S74] The power control section 51 turns
off power to the save memory 50 (see (4) in Fig. 6).
[0087] By performing the above process, work data
saved in the save memory 50 can be restored to the
power intermittence area 15 and the supply of power to
the power intermittence area 15 can be resumed.
[0088] In the above embodiment, the save memory 50
is located in the LSI 13 and work data is saved in the
save memory 50 via the bus 52. This prevents the CPU
10, DPRAM 11, and system bus 12 from being occupied
in the case of saving or restoring work data. As a result,
the load on the entire system caused by the process of
saving or restoring work data can be reduced.
[0089] Moreover, the storage capacity of the save
memory 50 can be set to a minimum capacity necessary
for storing work data. This prevents the scale of a circuit
from increasing.
[0090] Furthermore, when work data is not stored, the
supply of power to the save memory 50 is stopped by
the power control section 51. As a result, consumption
of power can be reduced.
[0091] My trial calculations show that consumption of
power should be reduced by about ten percent in this
embodiment, compared with the conventional structure
shown in Fig. 13.
[0092] Now, another example useful for understanding
the present invention will be described.
[0093] Fig. 7 is a view showing the structure of another
example useful for understanding the present invention.
As shown in Fig. 7, a unit according to another example
useful for understanding the present invention comprises
a CPU 10, a DPRAM 11, a system bus 12, and an LSI 13.
tion 14, a DPRAM 60, and a modem 17. The LSI 13 en-
codes data to be sent and decodes received data. In this
example part of the DPRAM 60 and the modem 17 are
located in a power intermittence area 15.
[0099] The power intermittence area 15 includes part
of the DPRAM 60 (the details of which will be described
later) and the modem 17. Power is supplied intermittently
to this area.
[0100] As shown in Fig. 8, an address space in the
DPRAM 60 is divided into a save area 60a and an ordi-
nary area 60b. The save area 60a is used for saving work
data. The ordinary area 60b is used for temporarily stor-
ing data at the time of the modem 17 processing it. Power
is supplied continuously to the save area 60a. On the
other hand, power is supplied intermittently to the ordi-
nary area 60b.
[0101] The storage capacity of the save area 60a is
set to a minimum capacity according to the amount of
work data to be stored.
[0103] Now, operation in the above example will be
described.
power to the power intermittence area 15 is stopped will
intermittence area 15 is stopped. The following steps will
outputs a request to begin intermittent control to the mo-
dem 17 (see (1) in Fig. 10).
[0106] [Step S91] The modem 17 saves work data in
the save area 60a in the DPRAM 60 (see (2) in Fig. 10).
In this case, information indicative of a location where
the work data has been stored, together with the work
data, is stored.
power to the modem 17 and the ordinary area 60b in the
DPRAM 60 is turned off.
[0108] By performing the above process, work data in
the power intermittence area 15 can be saved in the save
area 60a in the DPRAM 60 and the supply of power to
the power intermittence area 15 can be stopped.
[0109] Now, operation performed when the supply of
power to the power intermittence area 15 is resumed will
be described. Fig. 11 is a flow chart for describing oper-
ation performed when the supply of power to the power
intermittence area 15 is resumed. The following steps
will be performed according to this flow chart.
tent control and power to the power intermittence area
15 is turned on (see (1) in Fig. 12).
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processes at intermittent control termination time. To be
concrete, the modem 17 initializes registers and the like,
for example.
[0112] [Step S112] The modem 17 begins the process
of restoring work data from the save area 60a in the
DPRAM 60 (see (2) in Fig. 12). In this case, the modem
17 restores the work data to the original location by re-
ferring to information indicative of the location where the
work data had been stored.
[0113] By performing the above process, work data
saved in the save area 60a in the DPRAM 60 can be
restored to the modem 17 and the supply of power to the
power intermittence area 15 can be resumed.
[0114] In the above example, the DPRAM 60 is divided
into the save area 60a and the ordinary area 60b, power
is supplied continuously to the save area 60a, and work
data is saved in the save area 60a. This prevents the
CPU 10, DPRAM 11, and system bus 12 from being oc-
cupied in the case of saving or restoring work data. As a
result, the load on the entire system caused by the proc-
ess of saving or restoring work data can be reduced.
[0115] Moreover, the storage capacity of the save area
60a can be set to a minimum capacity necessary for stor-
ing work data. This prevents the scale of a circuit from
increasing.
[0116] As was not described in the above example, the
supply of power to the save area 60a may be stopped
when work data is not stored there. This enables a re-
duction in consumption of power. My trial calculations
show that consumption of power should be reduced by
about seven percent in this embodiment, compared with
the conventional structure shown in Fig. 13.
[0117] In the above examples the descriptions have
been given with a case where the present invention is
applied to a semiconductor device (LSI 13) as an exam-
ple. However, it is a matter of course that the present
invention is not limited to such a case. The present in-
vention is applicable to various electronic devices.
[0118] As has been described in the foregoing, a sem-
iconductor device including a first area to which power
is supplied intermittently and a second area to which pow-
er is supplied continuously, according to the present in-
vention, comprises a memory located in the second area,
a save circuit for saving data used in the first area in the
memory before stopping the supply of power, and a res-
toration circuit for restoring data saved in the memory to
a predetermined circuit in the first area. Therefore, by
locating a memory in the semiconductor device and sav-
ing data in the memory, an increase in the load on another
device in a system using the semiconductor device can
be prevented.
[0119] Furthermore, an electronic device including a
first circuit to which power is supplied intermittently and
a second circuit to which power is supplied continuously,
according to the present invention, comprises a memory
located in the second circuit, a save circuit for saving
data used in the first circuit in the memory before stopping
the supply of power, and a restoration circuit for restoring
data saved in the memory to a predetermined portion in
the first circuit. Therefore, data can be saved or restored
without increasing consumption of power.
[0120] The foregoing is considered as illustrative only
of the principles of the present invention.
[0121] It is not desired to limit the invention to the exact
construction and applications shown and described, but
only to the scope of the invention as defined in the ap-
pended claims.
Claims
1. A semiconductor device (13) including a first area
(15) to which power is supplied intermittently and a
second area to which power is supplied continuous-
ly, the semiconductor device (13) comprising:
a memory (50, 60a) located in the second area;
a circuit (17) located in the first area (15) and
configured to save data used in the first area
(15) to the memory (50, 60a) before the supply
of power is stopped, and to restore data which
has been saved in the memory (50, 60a) to the
circuit (17) when the supply of power is started
in the first area (15);
a system bus (12) configured to exchange data
with an external processor (10); and
a bus (52) which is independent of the system
bus (12),
characterised in that the circuit (17) is coupled,
via the bus (52) which is independent of the sys-
tem bus (12), to the memory (50, 60a), and in
that the circuit (17) is configured to use the bus
(52) independently of the system bus (12) to per-
form the saving and restoring of data between
the circuit (17) and the memory (50, 60a).
2. The semiconductor device (13) according to claim
1, wherein the memory (50, 60a) has a storage ca-
pacity corresponding to the amount of data used by
the circuit (17).
3. The semiconductor device (13) according to claim 1
or 2, further comprising a power supply control circuit
(51) configured to stop the supply of power to the
memory (50, 60a) after data has been restored by
the circuit (17) and to resume the supply of power to
the memory (50, 60a) before the saving of data has
begun by the circuit (17).
4. The semiconductor device (13) according to any one
of the preceding claims, the memory (50, 60a) locat-
ed in the second area comprises a first memory and
the semiconductor device further comprises a sec-
ond memory (16, 60b) located in the first area (15).
5. The semiconductor device according to claim 4,
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wherein the first memory and the second memory
are implemented in one memory device (60), and
wherein the first memory is a first memory area (60a)
of the one memory device (60) and the second mem-
ory is a second memory area (60b) of the one mem-
ory device (60).
6. The semiconductor device (13) according to claim
1, wherein the first area (15) is a first circuit to which
power is supplied intermittently and the second area
is a second circuit to which power is supplied con-
tinuously.
7. A method of operating a semiconductor device (13)
including a first area (15) to which power is supplied
intermittently and a second area to which power is
supplied continuously, the method comprising:
saving, by a circuit (17) located in the first area,
data used in the first area (15) to a memory (50,
60a) located in the second area before the sup-
ply of power is stopped; and
restoring, by the circuit (17), data which has
been saved in the memory (50, 60a) to the circuit
(17) when the supply of power is started in the
first area (15);
characterised in that the saving and restoring
of data are performed by the circuit (17) of the
semiconductor device (13) using a bus (52)
which couples the circuit (17) to the memory (50,
60a) independent of a system bus (12) provided
for exchanging data with an external processor
(10).
8. The method according to claim 7, further comprising
stopping the supply of power to the memory (50,60a)
after data has been restored and resuming the sup-
ply of power to the memory (50,60a) before the sav-
ing of data has begun.
Patentansprche
1. Halbleitervorrichtung (13) mit einem ersten Bereich
(15), an den Strom intermittierend geliefert wird, und
einen zweiten Bereich, an den Strom kontinuierlich
geliefert wird, wobei die Halbleitervorrichtung (13)
umfasst:
einen Speicher (50, 60a), der sich in dem zwei-
ten Bereich befindet;
eine Schaltung (17), die sich in dem ersten Be-
reich (15) befindet und konfiguriert ist zum Spei-
chern von Daten, die in dem ersten Bereich (15)
verwendet werden, in dem Speicher (50, 60a),
bevor die Stromversorgung gestoppt wird, und
zum Wiederherstellen von Daten, die in dem
Speicher (50, 60a) gespeichert wurden, in der
Schaltung (17), wenn die Stromversorgung in
dem ersten Bereich (15) gestartet wird;
einen Systembus (12), konfiguriert zum Aus-
tausch von Daten mit einem externen Prozessor
(10); und
einen Bus (52), der unabhngig von dem Sys-
tembus (12) ist,
dadurch gekennzeichnet, dass die Schaltung
(17) ber den Bus (52), der unabhngig von dem
Systembus (12) ist, mit dem Speicher (50, 60a)
gekoppelt ist, und darin, dass die Schaltung (17)
konfiguriert ist zur Verwendung des Busses
(52), unabhngig von dem Systembus (12), um
das Speichern und Wiederherstellen von Daten
zwischen der Schaltung (17) und dem Speicher
(50, 60a) durchzufhren.
2. Halbleitervorrichtung (13) nach Anspruch 1, wobei
der Speicher (50, 60a) eine Speicherkapazitt ent-
sprechend der Datenmenge aufweist, die durch die
Schaltung (17) verwendet wird.
3. Halbleitervorrichtung (13) nach Anspruch 1 oder 2,
ferner mit einer Stromversorgungs-Steuerschaltung
(51), konfiguriert zum Stoppen der Stromversorgung
fr den Speicher (50, 60a), nachdem Daten durch
die Schaltung (17) wiederhergestellt wurden, und
zum Wiederaufnehmen der Stromversorgung fr
den Speicher (50, 60a) bevor das Speichern von Da-
ten durch die Schaltung (17) begonnen hat.
4. Halbleitervorrichtung (13) nach einem der vorherge-
henden Ansprche, wobei der Speicher (50, 60a),
der sich in dem zweiten Bereich befindet, einen ers-
ten Speicher umfasst, und die Halbleitervorrichtung
ferner einen zweiten Speicher (16, 60b) umfasst, der
sich in dem ersten Bereich (15) befindet.
der erste Speicher und der zweite Speicher in einer
Speichervorrichtung (60) implementiert sind, und
wobei der erste Speicher ein erster Speicherbereich
(60a) der einen Speichervorrichtung (60) ist, und der
zweite Speicher ein zweiter Speicherbereich (60b)
der einen Speichervorrichtung (60) ist.
der erste Bereich (15) eine erste Schaltung ist, an
die Strom intermittierend geliefert wird, und der zwei-
te Bereich eine zweite Schaltung ist, an die Strom
kontinuierlich geliefert wird.
7. Verfahren zum Betreiben einer Halbleitervorrichtung
(13) mit einem ersten Bereich (15), in dem Strom
intermittierend geliefert wird, und einem zweiten Be-
reich, an den Strom kontinuierlich geliefert wird, wo-
bei das Verfahren umfasst:
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Speichern, durch eine Schaltung (17), die sich
in dem ersten Bereich befindet, von Daten, die
in dem ersten Bereich (15) verwendet werden,
in einem Speicher (50, 60a), der sich in dem
zweiten Bereich befindet, bevor die Stromver-
sorgung gestoppt wird; und
Wiederherstellen, durch die Schaltung (17), von
Daten, die in dem Speicher (50, 60a) gespei-
chert wurden, in der Schaltung (17), wenn die
Stromversorgung in dem ersten Bereich (15) ge-
startet wird;
dadurch gekennzeichnet, dass das Spei-
chern und Wiederherstellen von Daten durch die
Schaltung (17) der Halbleitervorrichtung (13)
durchgefhrt wird, unter Verwendung eines
Busses (52), der die Schaltung (17) mit dem
Speicher (50, 60a) unabhngig von einem Sys-
tembus (12) koppelt, der zum Austausch von
Daten mit einem externen Prozessor (10) be-
reitgestellt ist.
8. Verfahren nach Anspruch 7, ferner umfassend ein
Stoppen der Stromversorgung an den Speicher (50,
60a), nachdem Daten wiederhergestellt wurden, und
Wiederaufnehmen der Stromversorgung an den
Speicher (50, 60a), bevor das Speichern von Daten
begonnen hat.
Revendications
1. Dispositif semi-conducteurs (13) comprenant une
premire zone (15) laquelle une puissance est
fournie de manire intermittente et une deuxime
zone laquelle une puissance est fournie de mani-
re continue, le dispositif semi-conducteurs (13)
comprenant :
une mmoire (50, 60a) situe dans la deuxime
zone ;
un circuit (17) situ dans la premire zone (15)
et configur pour sauvegarder les donnes uti-
lises dans la premire zone (15) dans la m-
moire (50, 60a) avant que la fourniture de puis-
sance soit arrte, et pour rtablir les donnes
qui ont t sauvegardes dans la mmoire (50,
60a) dans le circuit (17) lorsque la fourniture de
puissance est dbute dans la premire zone
(15) ;
un bus de systme (12) configur pour changer
des donnes avec un processeur externe (10) ;
et
un bus (52) qui est indpendant du bus de sys-
tme (12),
caractris en ce que le circuit (17) est coupl,
par lintermdiaire du bus (52) qui est indpen-
dant du bus de systme (12), la mmoire (50,
60a), et en ce que le circuit (17) est configur
pour utiliser le bus (52) indpendamment du bus
de systme (12) pour effectuer la sauvegarde
et le rtablissement des donnes entre le circuit
(17) et la mmoire (50, 60a).
2. Dispositif semi-conducteurs (13) selon la revendi-
cation 1, dans lequel la mmoire (50, 60a) a une
capacit de mmorisation correspondant la quan-
tit de donnes utilises par le circuit (17).
cation 1 ou 2, comprenant en outre un circuit de com-
mande de fourniture de puissance (51) configur
pour arrter la fourniture de puissance la mmoire
(50, 60a) aprs que les donnes ont t rtablies
par le circuit (17) et pour reprendre la fourniture de
puissance la mmoire (50, 60a) avant que la sau-
vegarde des donnes par le circuit (17) ait dbut.
4. Dispositif semi-conducteurs (13) selon lune quel-
conque des revendications prcdentes, dans le-
quel la mmoire (50, 60a) situe dans la deuxime
zone comprend une premire mmoire et le dispo-
sitif semi-conducteurs comprend en outre une
deuxime mmoire (16, 60b) situe dans la premire
zone (15).
5. Dispositif semi-conducteurs selon la revendication
4, dans lequel la premire mmoire et la deuxime
mmoire sont mises en oeuvre dans un dispositif de
mmoire (60), et dans lequel la premire mmoire
est une premire zone de mmoire (60a) dudit un
dispositif de mmoire (60) et la deuxime mmoire
est une deuxime zone de mmoire (60b) dudit un
dispositif de mmoire (60).
cation 1, dans lequel la premire zone (15) est un
premier circuit auquel la puissance est fournie de
manire intermittente et la deuxime zone est un
deuxime circuit auquel la puissance est fournie de
manire continue.
7. Procd de mise en oeuvre dun dispositif semi-
conducteurs (13) comprenant une premire zone
(15) laquelle une puissance est fournie de manire
intermittente et une deuxime zone laquelle une
puissance est fournie de manire continue, le pro-
cd comprenant :
la sauvegarde, par un circuit (17) situ dans la
premire zone, des donnes utilises dans la
premire zone (15) dans une mmoire (50, 60a)
situe dans la deuxime zone avant que la four-
niture de puissance soit arrte ; et
le rtablissement, par le circuit (17), des don-
nes qui ont t sauvegardes dans la mmoire
(50, 60a) dans le circuit (17) lorsque la fourniture
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de puissance est dbute dans la premire zone
(15) ;
caractris en ce que la sauvegarde et le r-
tablissement des donnes sont effectus par le
circuit (17) du dispositif semi-conducteurs (13)
en utilisant un bus (52) qui couple le circuit (17)
la mmoire (50, 60a) indpendant dun bus de
systme (12) prvu pour lchange de donnes
avec un processeur externe (10).
8. Procd selon la revendication 7, comprenant en
outre larrt de la fourniture de puissance la m-
moire (50, 60a) aprs que les donnes ont t rta-
blies et la reprise de la fourniture de puissance la
mmoire (50, 60a) avant que la sauvegarde des don-
nes ait dbut.
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REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the readers convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description
US 5485623 A [0004]

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