TEPZZ - 876 B - T: European Patent Specification

Note: Within nine months of the publication of the mention of the grant of the European patent in the European
Patent
Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been
paid. (Art. 99(1) European Patent Convention).
Printed by Jouve, 75001 PARIS (FR)
(19)
E
P
1

2
8
7

6
2
3
B
1
*EP001287623B1*
(11) EP 1 287 623 B1
(12) EUROPEAN PATENT SPECIFICATION
(45) Date of publication and mention
of the grant of the patent:
23.07.2014 Bulletin 2014/30
(21) Application number: 01928820.8
(22) Date of filing: 24.04.2001
(51) Int Cl.:
H04L 27/20
(2006.01)
(86) International application number:
PCT/US2001/013216
(87) International publication number:
WO 2001/089103 (22.11.2001 Gazette 2001/47)
(54) DIGITAL WAVEFORM GENERATOR APPARATUS AND METHOD THEREFOR
DIGITALE SIGNALFORMGENERATORVORRICHTUNG UND VERFAHREN DAFR
APPAREIL ET PROCEDE POUR PRODUIRE DES FORMES DONDES NUMERIQUES
(84) Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU
MC NL PT SE TR
(30) Priority: 12.05.2000 US 569418
(43) Date of publication of application:
05.03.2003 Bulletin 2003/10
(73) Proprietor: Motorola Mobility LLC
Libertyville, IL 60048 (US)
(72) Inventors:
SOLAR, John
Algonquin, IL 60102 (US)
HIETALA, John
Phoenix, AZ 85048 (US)
(74) Representative: Boult Wade Tennant
Verulam Gardens
70 Grays Inn Road
London WC1X 8BT (GB)
(56) References cited:
US-A- 3 749 834 US-A- 5 151 661
US-A- 5 151 661 US-A- 5 959 984
US-B1- 6 239 636
NORMAN M FILIOL ET AL: "An Agile ISM Band
Frequency Synthesizer with Built-In GMSK Data
Modulation" IEEE JOURNAL OF SOLID-STATE
CIRCUITS, IEEE SERVICE CENTER,
PISCATAWAY, NJ, US, vol. 33, no. 7, 1 July 1998
(1998-07-01), pages 998-1008, XP011060763
ISSN: 0018-9200
BODAS A ET AL: "Low complexity GSM
modulator for integrated circuit
implementations" ASIC CONFERENCE AND
EXHIBIT, 1996. PROCEEDINGS., NINTH ANNUAL
IEEE INT ERNATIONAL ROCHESTER, NY, USA
23-27 SEPT. 1996, NEW YORK, NY, USA,IEEE, US,
23 September 1996 (1996-09-23), pages 103-106,
XP010198737 ISBN: 978-0-7803-3302-4
EP 1 287 623 B1
2
5
10
15
20
25
30
35
40
45
50
55
Description
FIELD OF THE INVENTION
[0001] The present invention relates generally to
waveform generation, and more particularly to a method
and apparatus for generating a digital waveform in a dual
mode wireless device.
BACKGROUND OF THE INVENTION
[0002] A number of different standards and technolo-
gies for operating wireless telephones exist today. In or-
der to operate properly, a wireless telephone must be
within the boundaries of a wireless telephone system that
supports the same technology and is able to operate at
the same frequency as the wireless telephone. As a re-
sult, dual mode wireless telephones exist today that are
designed for use in more than one wireless telephone
system. For example, a wireless telephone that operates
in both an Advanced Mobile Phone Service ("AMPS")
mode and a Global System for Mobile Communication
("GSM") mode is known. The object of such dual mode
combinations is generally to enable the user to transfer
a wireless telephone outside of their home service area
and increase the probability that the wireless telephone
will continue to have wireless service available.
[0003] FIG. 1 is a schematic diagram of data transmis-
sion flow in a known dual mode wireless device operable
in either the AMPS mode or the GSM mode. As illustrated
in FIG. 1, a dual mode wireless device, such as a wireless
telephone, includes a controller circuit 200 and a trans-
mitter circuit 202 connected along a bus 204. Both analog
and digital data signals, corresponding to voice and data,
are input from a microphone 206 and an interface 208 of
a computer device, for example, to a data source 210
located at the controller circuit 200. When the dual mode
wireless device is operated in an AMPS mode, the analog
signals from the microphone 206 are converted to digital
data by an A/D converter 214 located in the AMPS unit
212, and added to the digital data input to the data source
210 by the interface 208 of the computer device using
an adder 216. The resulting added signals output by the
adder 216 are received by an input register 218 located
within a digital signal processor 220 of the controller cir-
cuit 200.
[0004] On the other hand, when the wireless telephone
is operated in the GSM mode, the analog signals output
by the data source 210 after being received from the mi-
crophone 206 are converted to digital data signals by an
A/D converter 224 located in a GSM unit 222, and both
the digital data signals input by the data source 210 from
interface 208 of the computer device and the digital data
signals output from the A/D converter 224 are sent to an
interleaver 226 of the GSM unit 222. The interleaver 226
interleaves the digital data signals according to GSM pro-
tocol, and outputs the interleaved data signals to the input
register 218 of the digital signal processor 220.
[0005] Depending upon whether the device is being
operated in the AMPS or the GSM mode, the digital data
signals are transferred from the input register 218 to a
microprocessor 228 of the digital signal processor 220
to be packaged and buffered to form processed data that
is then output from the digital signal processor 220 to an
output register 230 of the controller circuit 200. The proc-
essed data is held in the output register 230 until a new
piece of data is required by the transmitting circuit 202,
at which time the processed data is transferred from the
output register 230 of the controller circuit 200 to the bus
204 connecting the controller circuit 200 to the transmitter
circuit 202. The processed data is transferred along the
bus 204 to an input register 232 of the transmitter circuit
202 and is transferred from the input register 232 to an
interpolator 234. The interpolator 234 interpolates the
processed data and outputs the resulting interpolated da-
ta to a modulator 236. The modulator 236 modulates the
interpolated data, and the resulting modulated data is
then output by the transmitter circuit 202 through an an-
tenna (not shown).
[0006] In the prior art dual mode wireless telephone of
FIG.1, each time the transmitter circuit 202 requests a
packet of data from the controller circuit 200, the request-
ed data packet must be generated by the signal proces-
sor 220 and transported along the bus 204 from the out-
put register 230 of the controller circuit 200 to the input
register 232 of the transmitter circuit 202. As a result,
each time the transmitter circuit 202 requests a packet
of data from the controller circuit 200, current processing
from the signal processor 220 must be interrupted to en-
able the signal processor 220 to generate the data pack-
et. As the rate of these interruptions increases, a bottle-
neck tends to form both between the signal processor
220 and the output register 230 of the controller circuit
200 and along the bus 204 between the controller circuit
200 and the transmitter circuit 202, corrupting reliability
of the data transmission. This bottleneck results from
noise that is caused from high clock rates at the bus 204,
which desensitize the receiver receiving the output from
the transmitter circuit 202, and from high current drain in
MIPS (million instructions per second) between the digital
signal processor 220 and the output register 230, which
lowers the battery life of the device.
[0007] One method available to reduce the interrupt
rate to the digital signal processor 220 caused by the
requests for data from the transmitter circuit 202 is for
the digital signal processor 220 to generate a large set
of data and create a buffer at output register 230 from
which the transmitter circuit 202 draws data in real time.
As a result, the interruptions of the digital signal processor
220 are reduced, occurring only when the buffer required
additional data. This buffer method reduces the interrupt
rate to the digital signal processor 220, allowing more
efficient operation so that lower MIPS are required by the
digital signal processor 220, reducing current drain on
the battery and increasing battery life. However, not all
supported integrated circuits include the necessary buff-
1 2
EP 1 287 623 B1
3
5
10
15
20
25
30
35
40
45
50
55
er capacity built into the controller circuit 200.
[0008] In addition, the signal from the interpolator 234
could be pre-distorted using analog components in the
present state of the art, in order to reduce the effects of
distortion caused by bandwidth limitations in the modu-
lator unit 236. To achieve analog pre-distortion and to
achieve modulated signal accuracy and cleanliness, ac-
tive operational amplifiers, switches, and extra inductors
and capacitors may need to be added to the transmitter
circuit 202 to obtain the required accuracy. These support
circuits increase the size and cost of the transmitter circuit
so that such as approach would be difficult and costly
using current technology. In addition, even if support was
available on the transmitter circuit 202, the higher data
rate involved in transporting the high speed data from
the output register 230 across the bus 204 to the input
register 232 of the transmitter circuit 202 would cause
radio interference back through the antenna, causing the
radio to be de-sensitized.
[0009] Accordingly, what is needed is dual mode wire-
less telephone device that minimizes bottlenecks by re-
ducing an interrupt rate of the signal processor while at
the same time reducing interference in neighboring
bands.
[0010] US patent no. US 5,151,661 describes a linear
FM waveform generator for radar systems. The linear
FM waveform generator includes a frequency slope reg-
ister coupled to a first stage integrator which in turn is
coupled to a second stage integrator, all of which operate
off a system clock. The output signal from the second
stage integrator represents phase as a quadratic function
of time. A stored sine look-up table is referenced to gen-
erate an output digital signal representing amplitude as
a function of time. The output digital signal is converted
to an analog linear FM waveform.
[0011] An article entitled An Agile ISM Band Frequen-
cy Synthesizer with Built-In GMSK Data Modulation Nor-
man M Filiol et al, IEEE Journal of Solid-state Circuits,
IEEE, vol. 33, no. 7, 1.7.1998, pages 998-1008,
XP011060763, describes a high-resolution fractional-N
RF frequency synthesizer which is controlled by a fourth-
order digital sigma-delta modulator.
[0012] An article entitled Low Complexity GSM Mod-
ulator for Integrated Circuit Implementations by Bodas
et al, ASIC Conference and Exhibit 1996, IEEE,
23.9.1996, pages 103-106, XP010198737, describes
generating the in-phase and quadrature signals directly
from the input binary data, bypassing the separate steps
of integrating and then calculating the sine and cosine
values.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013]
FIG. 1 (PRIOR ART) is a schematic diagram of data
transmission flow in a known dual mode wireless de-
vice.
FIG. 2 is a schematic diagram of a dual mode wire-
less device according to the present invention.
FIG. 3 is a schematic diagram of a digital signal proc-
essor of a dual mode wireless device according to
the present invention.
FIG. 4 is a schematic diagram of a modulator in a
dual mode cellular telephone according to the
present invention.
FIG. 5 is a schematic diagram of a parser unit of a
dual mode wireless device according to the present
invention.
FIG. 6 is a schematic diagram of a waveform gen-
erator of a dual mode wireless device according to
FIG. 7 is a schematic diagram of a coefficient gen-
FIG. 8 is a schematic diagram of a waveform gen-
FIG. 9 is a flowchart of a method of generating a
waveform in a dual mode wireless device according
to the present invention.
FIG. 10 is a flowchart of a method for generating a
waveform using parameters generated in a dual
mode wireless device according to the present in-
vention.
FIGS. 11a-d are graphic representations of a
smoothing of a waveform by a waveform generator
of a dual mode cellular telephone device according
to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EM-
BODIMENTS
[0014] FIG. 2 is a schematic diagram of a dual mode
wireless device operable in either an AMPS mode or a
GSM mode, according to the present invention. As illus-
trated in FIG. 2, a dual mode wireless device according
to the present invention, such as a cellular telephone
device, includes a controller circuit 20 and a transmitter
circuit 22. The controller circuit 20 includes an AMPS unit
26 for processing analog and digital signals in the AMPS
mode, an A/D converter 28, a digital signal processor 30,
an output register 32, and a GSM unit 34 for processing
analog and digital signals in the GSM mode. The trans-
mitter circuit 22 includes an input register 36, a parser
unit 38, a first waveform generator 40, a coefficient gen-
erator 42, a second waveform generator 44, a switch 46
for switching operation of the device between the AMPS
and GSM modes, and a modulator 48. The distortion
caused by modulator 48 can be corrected for by pre-
distorting the signal generated by the waveform gener-
ators 40 and 44. Data corresponding to operation in either
the AMPS mode or the GSM mode is transmitted along
a bus 50 connecting the controller circuit 20 and the trans-
mitter circuit 22.
[0015] FIG. 3 is a schematic diagram of a digital signal
3 4
EP 1 287 623 B1
4
5
10
15
20
25
30
35
40
45
50
55
processor of a dual mode wireless device, according to
the present invention. As illustrated in FIG. 3, the digital
signal processor 30 includes finite impulse response
(FIR) filters 66 and 68 and a switch 70. As illustrated in
FIGS. 2 and 3, a time domain voltage representation is
sent to the digital signal processor 30 from the digital
signal output by the A/D converter 28. Based on this time
domain voltage, the digital signal processor 30 generates
parameters related to position, slope and feedback which
are then output by the signal processor 30 to the output
register 32 and transmitted along the bus 50 to the input
register 36. The digital signal processor 30 evaluates the
voltage of the digital signal and generates the parameters
corresponding to operating requirements of the first
waveform generator 40. An algorithm within the digital
signal processor 30 then generates 12 bit position, 12 bit
slope and 3 bit feedback parameters that are transferred
to the first waveform generator 40.
[0016] The digital signal processor 30 algorithm must
optimize the performance of the error in the time domain
and frequency domain to meet the AMPS performance
specifications. Available straightforward, known determi-
nations of instantaneous slope and position will not meet
these requirements. Rather, a two-to-one decimation is
beneficial in order to reduce bottlenecks that occur along
the bus 50 between the controller circuit 20 and the trans-
mitter circuit 22. Using the switch 70, the first waveform
generator 40 interleaves the slope and position values,
and thus misses every other occurrence of either slope
or position. To reduce these effects, the digital signal
processor 30 algorithm must take into account future er-
rors in final output caused by the reduced data. A closed
solution to this requires knowledge about future input val-
ues, not available at the time parameters must be sent
to first waveform generator 40.
[0017] The present invention uses a matrix algebra
model of the first waveform generator 40 in which the
infinite linear algebra matrix model is appropriately trun-
cated to create a transfer function approximation to the
first waveform generator 40 operation. According to the
present invention, the matrix approximation is solved us-
ing pseudo inverse approximation to a least squared er-
ror model of all possible inputs and outputs for the first
waveform generator 40 to give an approximation to a
linear transformation equivalent of the first waveform
generator 40. A truncated version of the pseudo inverse
gives the coefficients for a finite impulse response (FIR)
filter equivalent to the precise infinite matrix solution
needed to determine the parameters for the first wave-
form generator 40 inputs. There are a unique set of FIR
filter coefficients generated for each of the eight feedback
settings possible in the region of support of the FIR filter
for the chosen 3 bit feedback bit size. These coefficients
are determined off-line and become a part of the algo-
rithm for the digital signal processor 30.
[0018] As illustrated in FIG. 3, according to the present
invention, the digital signal processor 30 will then FIR
filter the input digital signal using FIR filters 66 and 68.
FIR filter 68 generates the slope parameters, and FIR
filter 66 generates the position parameters for the first
waveform generator 40. The pair of FIR filters 66 and 68
are run for each value of feedback chosen. For current
drain versus distortion performance, a limited set of feed-
back values are chosen to complete-- with the greater
the number of possible values chosen, the greater the
possibility that the distortion will be reduced. However,
for each possible value not chosen, a corresponding
amount of current drain is saved. For all possible feed-
back values chosen in the competition, the distortion is
determined by comparing the error as the difference be-
tween the input and the waveform generator model out-
put. The lowest current drain, and thus the lowest MIPS
load on the digital signal processor 30, is for the special
case of where the feedback is equal to zero. In this way,
the present invention uses FIR filters to approximate the
coefficients needed for a time domain waveform gener-
ator.
[0019] In particular, when the cellular telephone device
of the present invention is operated in the AMPS mode,
the feedback parameter is set to disconnect for audio
data, or to an open connection so that feedback is a con-
stant value. The digital signal processor 30 performs the
evaluation by inputting a present data value of the digital
signal along with the past twenty data values, and sends
the twenty-one data values through the custom designed
finite impulse response filter, FIR filter 66, to generate a
first coefficient value corresponding to a slope value,
which is sent to output register 32 through switch 70.
When the next data is received by the digital signal proc-
essor 30, the oldest data value of the twenty-one data
values is removed and the next data value is inserted,
and the new twenty-one present data values are sent
through FIR filter 68 to generate a second coefficient val-
ue corresponding to position, which is sent to output reg-
ister 32 through switch 70, and the process continues
again, with the oldest data value being replaced by the
next data value.
[0020] According to the present invention, therefore, a
set of algorithms are developed offline, outside the cel-
lular phone, to generate the coefficients for the position
and slope that will be used by the first waveform gener-
ator 40 to generate the required waveform. Once de-
signed, the FIR filters 66, 68 are left as constants and
integrated into the digital signal processor 30. While FIR
filters are a generally known digital signal processing al-
gorithm and are typically used to smooth data or eliminate
noise, etc., according to the present invention, FIR filter
68, used to generate the second coefficients correspond-
ing to position, is designed as a low pass noise reducing
filter that tends to smooth the data, and FIR filter 66, used
to generate the first coefficients corresponding to slope
is actually more like a derivative filter that enhances the
noise-least squares approximation to position and least
squares approximation to slope.
[0021] As illustrated in FIG. 2, when the dual mode
cellular telephone device of the present invention is op-
5 6
EP 1 287 623 B1
5
5
10
15
20
25
30
35
40
45
50
55
erated in the AMPS mode, analog audio signals, for ex-
ample, along with digital signals, are transmitted from a
data source 23 along a path 24 to the AMPS unit 26. The
AMPS unit 26 processes the analog signals and outputs
a corresponding processed signal to the A/D converter
28. The A/D converter 28 converts the analog processed
signals to digital signals, and outputs the digital signals
to an input resister 52 of the digital signal processor 30.
The digital signals are transferred from the input register
52 to a compression unit 54 which compresses the digital
signals to generate parameters that are used by the first
waveform generator 40 in the transmitter circuit 22. The
compressed digital signals from the digital signal proc-
essor 30 are output to 15 bits of a 16 bit field of the output
register 32 and transmitted along the bus 50 from the
output register 32 to the input register 36 of the transmitter
circuit 22. The 16 bit signal is sent from the input register
36 to the parser unit 38 of the transmitter circuit 22.
[0022] The parser unit 38 parses the 15 bits of the 16
bit field and determines which section of the first wave-
form generator 40 to send the 15 bit word based on a de-
interleave process. The first waveform generator 40 de-
compresses the digital data and interpolates the resulting
decompressed data up to the data rate required by the
modulator 48. The modulator 48 modulates the wave-
form, and the resulting modulated waveform is output by
the modulator 48 to a remote cellular telephone device
through an antenna (not shown).
[0023] At the same time, a digital data stream gener-
ated when the cellular telephone device is operated in
the AMPS mode is transmitted directly from the AMPS
unit 26 of the controller circuit 22 to the 16
th
bit of the 16
bit field of the output register 32, and along the bus 50
from the output register 32 to the 16
th
bit of input register
36 of transmitter circuit 22. Input register 36 sends the
single bit of digital data as part of the 16 bit word sent to
the parser unit 38. Parser unit 38 updates the state history
of its internal digital data state history stream and sends
a function of the state history to the first waveform gen-
erator 40. The first waveform generator 40 produces an
interpolated filtered data sequence to the modulator 48,
as will be described below.
[0024] FIG. 4 is a schematic diagram of a modulator
in a dual mode wireless device according to the present
invention. As illustrated in FIG. 4, the modulator 48 is a
constant amplitude frequency modulation (FM) modula-
tor with phase coherency in which the frequency modu-
lation is accomplished by a phase lock loop (PLL). The
modulating element in this PLL is the divide by N in the
feedback path from a voltage controlled oscillator 56 to
a phase detector 58. Since non-integer division ratios are
required for fine grain modulation, a fractional N (FN)
divider 60 is used, such as disclosed in U.S. Patent No
5,093,632, for example. When phase locked, the PLL
output frequency from the voltage controlled oscillator 56
is N times the reference frequency feeding the phase
detector 58. In phase lock, the phase detector 58 receives
a signal output by the FN divider 60 and using a reference
oscillator 62, compares the phase of the two signals, and
outputs a current proportional to the phase difference. A
low pass filter 64 is positioned at the output of the phase
detector 58 to filter high frequency noise contained in the
output current of the phase detector 58. The stopband
of the low pass filter 64 attenuates the high frequency
noise and passes most of the intended signal from the
phase detector 58, however, the signal output by the
phase detector 58 is distorted by the passband of the low
pass filter 64. The waveform generator can be set up to
pre-distort the signal to precisely cancel the distortion
caused by the low pass filter 64. The output of the low
pass filter 64 drives the voltage controlled oscillator 56
which operates directly at the transmit frequency requir-
ing no up conversion.
[0025] FIG. 5 is a schematic diagram of a parser unit
of a dual mode wireless device according to the present
invention. As illustrated in FIG. 5, the parser unit 38 in-
cludes a logic unit 72, a state history register unit 74, a
state logic unit 76, and a de-interleave switch 78.
[0026] FIG. 6 is a schematic diagram of a waveform
generator of a dual mode wireless device according to
the present invention. As illustrated in FIG. 6, the first
waveform generator 40 includes adders 80 and 82 con-
nected in series with a slope register 84 and a position
register 86, a feedback selector 88, adders 90 and 92
connected in series with a slope register 100 and a po-
sition register 102, and a feedback selector 104. Adders
80 and 82, slope register 84, position register 86 and
feedback selector 88 form an audio waveform generator
portion 106, and adders 90 and 92, slope register 100,
position register 102 and feedback selector 104 form a
data waveform generator portion 108. The outputs of the
audio waveform generator portion 106 and data wave-
form generator portion 108 are combined using an adder
110 to form the output of the first waveform generator 40
consisting of the audio and Manchester signals com-
bined.
[0027] In particular, as illustrated in FIGS. 5 and 6, after
being sent to the parser unit 38 from input register 36,
the 16 bit word is de-interleaved by the parser unit 38
using de-interleave switch 78. The logic unit 72 parses
the 16 bit word into a 12 bit field, a 3 bit field, and a 1 bit
field. The 12 bit field is de-interleaved by de-interleave
switch 78 so as to be sent out as either a 12 bit slope
value or a 12 bit position value, while at the same time
the 3 bit field is sent out as a feedback value, and the 1
bit field is sent out as Manchester data. During synchro-
nization, the de-interleave switch 78 is initialized at a
slope setting, and toggles between a position and slope
setting each time a 16 bit word is received. It is under-
stood that although described as being initialized at the
slope setting, it is possible for the de-interleave switch
78 of the present invention to be initialized at a position
setting.
[0028] As a result, de-interleave switch 78 is positioned
at a slope setting, as illustrated in FIG. 4, and logic unit
72 parses the initial 16 bit word into a 12 bit slope value,
7 8
EP 1 287 623 B1
6
5
10
15
20
25
30
35
40
45
50
55
3 bit feedback, and 1 bit Manchester data value. The 12
bit slope value is sent from the parser unit 38 to slope
register 84 of the first waveform generator 40 along data
path 112 from de-interleave switch 78, the 3 bit feedback
value is sent along data path 116 from the logic unit 72
to feedback selector 88, and the 1 bit Manchester data
is sent from logic unit 72 to state history register unit 74
of parser unit 38. When a subsequent 16 bit word is sent
to the parser unit 38 from input register 36, the logic unit
72 parses the 16 bit word into a 12 bit position value, a
3 bit feedback value, and a 1 bit Manchester data value.
De-interleave switch 78 is positioned so that the 12 bit
position value is sent from parser unit 38 to position reg-
ister 86 along data path 114 from de-interleave switch
78, the 3 bit feedback value is sent along data path 116
from the logic unit 72 to feedback selector 88, and the 1
bit Manchester data is sent from logic unit 72 to the state
history register unit 74 of parser unit 38. The procedure
is then repeated with de-interleave switch 78 positioned
so that a 12 bit slope value is sent from the parser unit
38 to the first waveform generator 40, and so forth.
[0029] The state logic unit 76 uses the Manchester
state history data of the state history register unit 74 to
generate and send a single feedback value to feedback
selector 104 along data path 118. This generated value
determines whether a feedback value of approximately
negative one will be used to close the feedback path of
the data waveform generator 108, allowing oscillation to
create a smooth sinusoidal trajectory of the interpolated
Manchester signal. Output 120 of state logic unit 76 se-
lects one of three values in position register 102 of data
waveform generator 108, and output 122 of state logic
unit 76 selects one of three slope values in slope register
100 of data waveform generator 108 of waveform gen-
erator 40. The updates from state logic unit 76 to data
waveform generator 108 occur once every quarter cycle
of the nominal 10 kHz Manchester rate. After each 16 bit
word is sent from the digital signal processor 30, wave-
form generator 108 is run as many cycles as interpolation
points are needed. For example, in a typical AMPS mode,
twenty values are needed for each word sent.
[0030] According to the present invention, as illustrat-
ed in FIG. 6, the position registers 86 and 102 and the
slope registers 84 and 100 are set up as accumulators,
so that a next value is based upon a present value plus
a new input. For example, a new position value is ob-
tained by adding an old position value, i.e., a previous
value output by the position register 102, to a new slope
value output by the slope register 100, using adder 92.
In the same way, a new slope value is obtained by adding
an old slope, i.e., a previous value output by the slope
register 100 to a previous position value that is scaled
by hardware selected by the feedback value in feedback
circuit 104, then added using adder 90.
[0031] This process is iterated twenty-five times to pro-
duce twenty-five interpolated values for modulator 48.
Although, according to the present invention, twenty-five
iterations are used, it is understood that the number of
iterations chosen is based on the current drain and the
modulator loop bandwidth, and therefore may be more
or less than twenty-five, depending upon the specific ap-
plication requirements.
[0032] Once twenty-five iterations values have been
produced, a new slope and a new position value is output
from the parser unit 38 to the waveform generator 40 and
are used to generate the next twenty-five iterations, and
so forth. In this way, the present invention uses a sine
wave curve to move from one place to another, where a
new position is obtained by adding a previous position
and slope, and a new slope is obtained by adding an old
slope and the scaled value of a previous position. As a
result, by having negative feedback, an ideal digital os-
cillator is formed to enable a smooth transition from a
plus 8 kHz position to a negative 8 kHz position using
additions, rather than multiplication operations or look up
tables as in the prior art cellular telephone device.
[0033] FIG. 7 is a schematic diagram of a coefficient
the present invention. As illustrated in FIG. 2, the coeffi-
cient generator 42 is positioned on the transmitter circuit
22 so that when the cellular telephone device of the
present invention is operated in the GSM mode, digital
data is transmitted in sequences of ones and zeros from
GSM unit 34 of the controller circuit 20 to output register
32. The digital data is then transmitted along bus 50 to
input register 36 of transmitter circuit 22, and from input
register 36 to the coefficient generator 42.
[0034] As illustrated in FIG. 7, the coefficient generator
42 includes a first input 130 for inputting data into a first
adder section 132, a second input 134 for inputting data
into a second adder section 136 and a third input 138 for
inputting data into a third adder section 140. Each of the
adder sections 132, 136 and 140, respectively, includes
five adders 142, 144 and 146 and six multipliers 148, 150
and 152.
[0035] During start up of the dual mode cellular tele-
phone device of the present invention, eighteen param-
eters are loaded into a slope register section 154, an
acceleration register section 156, and a jerk register sec-
tion 158. The eighteen parameters are generated during
design of the cellular telephone device, taking into ac-
count pre-distortion requirements of the transfer function
of the phase lock loop of the modulator 48. As a result,
six first derivative values x1d[0]-x1d[5] corresponding to
slope are loaded in slope register section 154, six second
derivative values x2d[0]-x2d[5] corresponding to accel-
eration are loaded in acceleration register section 156,
and six third derivative values x3d[0]-x3d[5] correspond-
ing to jerk are loaded in jerk register section 158. Only
one value, as will be described below, is stored relative
to position since position is constant and therefore a sin-
gle value.
[0036] According to the present invention, when the
dual mode cellular telephone device is operated in the
GSM mode, a sequence of digital data values transferred
from GSM unit 34 along bus 50 from output register 32
9 10
EP 1 287 623 B1
7
5
10
15
20
25
30
35
40
45
50
55
to input register 36 is received at inputs 130, 134 and
138. The digital data values are shifted sequentially into
six transmit data registers TXDATA[5] - TXDATA[0] lo-
cated in each adder section 132, 136 and 140, starting
with transmit data register TXDATA[5]. Once six data val-
ues are shifted into transmit data registers TXDATA[5] -
TXDATA[0] of adder sections 132, 136 and 140 for any
instant in time, a slope value x1d, an acceleration value
x2d, and a jerk value x3d is generated based on the in-
serted values and the eighteen parameters loaded in
slope register 154, acceleration register 156 and jerk reg-
ister 158. This generation of value x1d, x2d and x3d is
performed by multiplying, using multipliers 148, 150 and
152, the parameters in slope register section 154, accel-
eration register section 156 and jerk register section 158
by a one or a negative one, depending upon the digital
data value in corresponding transmit data registers TX-
DATA[5] - TXDATA[0].
[0037] For example, once six data values have been
sequentially inserted in transmit data registers TXDA-
TA[5] - TXDATA[0] of adder sections 131, 136 and 140,
slope value x1d is generated by multiplying, using mul-
tipliers 148, the six first derivative values x1d[0] to x1d[5]
in slope register section 154 by a one or a negative one,
determined by the value in transmit data registers TX-
DATA[5]-TXDATA[0] of adder section 132. The resulting
positive and negative first derivative values x1d[0] to
x1d[5] then added using corresponding adders 142. Sim-
ilarly, acceleration value x2d is generated by multiplying,
using multipliers 150, the six first derivative values x2d[0]
to x2d[5] in acceleration register section 156 by a one or
a negative one, determined by the value in transmit reg-
isters TXDATA[5]-TXDATA[0] of adder section 136. The
resulting positive and negative second derivative values
x2d[0] to x2d[5] are then added using corresponding
adders 144. In the same way, jerk value x3d is generated
by multiplying using multipliers 152, the six third deriva-
tive values x3d[0] to x3d[5] in jerk register section 158
by a one or a negative one, determined by the value in
transmit data registers TXDATA[5]-TXDATA[0] of adder
section 140. The resulting positive and negative third de-
rivative values x3d[0] to x3d[5] are then added, using
corresponding adders 146.
[0038] For example, according to the present inven-
tion, if a sequence of 011010 is received at inputs 130,
134 and 138, the first stored slope value x1d[0] of slope
register section 154 is added, the second and third slope
values x1d[1] and x1d[2] are subtracted, the fourth slope
value x1d[3] is added, the fifth slope value x1d[4] is sub-
tracted, and the sixth slope value x1d[5] is added. Once
the summation is completed, the resulting total sum of
the slopes values x1d[0] to x1d[5] is output from coeffi-
cient generator 42 as the slope value x1d. Likewise, the
same operation is performed to obtain the acceleration
value x2d and the jerk value x3d so that the calculated
slope, acceleration, and jerk values x1d, x2d, and x3d
are all simultaneously loaded from coefficient generator
42 into the second waveform generator 44, along with
the position value, which does not change based upon
the sequence of data values.
[0039] Once the generated slope, acceleration, and
jerk values x1d, x2d, and x3d are loaded into the second
waveform generator 44, the digital data values in transmit
data registers TXDATA[5] - TXDATA[0] located in each
adder section 132, 136 and 140 are sequentially shifted
so that the last inserted value is remove from transmit
data register TXDATA[0], a new digital data value is in-
serted in transmit data register TXDATA[5], and the re-
maining values in transmit data registers TXDATA[1-TX-
DATA[4] are shifted upward so that the value previously
in transmit data register TXDATA[5] is shifted into TX-
DATA[4], the value previously in transmit data register
TXDATA[4] is shifted into TXDATA[3], and so forth. In
this way, once a new value is inserted, each adder section
132, 136 and 140 contains a newest value and five pre-
vious values. The process of either adding or subtracting
each of the six values to generate the single slope value
x1d, acceleration value x2d, and jerk value x3d based
upon the sequence of values input from the controller
circuit 20 to the coefficient generator 42 is then repeated.
[0040] As a result of the one bit per symbol nature of
the GSM modulation definition, the present invention uti-
lizes a multiplierless multiplication of the constants neg-
ative one and positive one. In the more general case, for
instance, where there is multiple bits per symbol, or in
CDMA or OFDM waveforms, a non-trivial multiplication
would occur. A multiplication by a positive one is per-
formed according to the present invention by simply add-
ing, likewise a multiplication by a negative one is per-
formed by simply subtracting. In this way, the dual mode
cellular telephone device of the present invention uses
a complete multiplierless operation implementation, with-
out lookup tables, for generating a GSM waveform.
[0041] FIG. 8 is a schematic diagram of a waveform
the present invention. As illustrated in FIG. 8, the second
waveform generator 44 includes a position register 160,
a slope register 162, and an acceleration register 164.
According to the present invention, a fixed value of
35555H, corresponding to 67 kHz, is initially stored in the
position register 160. The calculated values of slope x1d
and acceleration x2d from the coefficient generator 42
are input into the slope register 162 and the acceleration
register 164, respectively.
[0042] At each clock instant on a clock port during six-
teen clock periods, the output of each of the registers
160, 162 and 164 is input sixteen times by an adder so
that a new value is calculated by adding a present value
of each register to the previous value of the preceding
register. For example, a new value of position register
160 is generated by adding the present value of position
to the previous value of slope output by slope register
162 using a first adder 166. A new value of slope register
162 is generated at each of the sixteen clock period by
adding a present slope value to a previous value of ac-
celeration output by acceleration register 164 using a
11 12
EP 1 287 623 B1
8
5
10
15
20
25
30
35
40
45
50
55
second adder 168. In the same way, a new value of ac-
celeration is generated at each of the sixteen clock pe-
riods by adding a present acceleration value to a previous
value jerk x3d using a third adder 170. Once generated
by the coefficient generator 42, jerk value x3d is held
constant for the sixteen clock periods and therefore re-
mains the same.
[0043] In this way, the registers are shifted on each
sample of the clock and the adders from the previous
stage are added in. Each new value of position register
160 generated at each clock period is output by second
waveform generator 44 to the modulator 48. Once the
sixteen clock periods have ended, a new generated value
of slope x1d, acceleration x2d and jerk x3d from the co-
efficient generator are input by waveform generator 44
and the process is repeated for the next sixteen clock
periods, and so forth.
[0044] FIG. 9 is a flowchart of a method of generating
parameters for a waveform generator in a dual mode
wireless device according to the present invention. As
illustrated in FIG. 9, the eighteen parameters are loaded
into slope register section 154, acceleration register sec-
tion 156 and jerk register section in Step 300, and a new
digital data value is inserted into first transmit data reg-
ister TXDATA[5] of each adder section in Step 302. A
determination as to whether all transmit data registers
TXDATA[5]-TXDATA[0] are filled is made in Step 304,
and if all transmit data registers are not filled, digital data
values in transmit data registers TXDATA[5]-TXDATA[0]
are sequentially shifted into the next transmit data regis-
ter in Step 306, so that the digital data value in transmit
data register TXDATA[5] is shifted into transmit data reg-
ister TXDATA[4], transmit data register TXDATA[4] is
shifted into transmit data register TXDATA[3], and so
forth. The process then returns to Step 302 so that a new
digital data value is again inserted into first transmit data
register TXDATA[5] of each adder section.
[0045] If it is determined in Step 304 that all transmit
data registers TXDATA[5]-TXDATA[0] are filled, a deter-
mination is made in Step 308 as to whether a digital data
value in a transmit data register is a one or a zero by
determining whether the value is greater than zero. If the
digital data value is determined to be greater than zero,
the parameter corresponding to the transmit data register
is multiplied by one, Step 310, and if the digital data value
is determined not to be greater than zero, the parameter
corresponding to the transmit data register is multiplied
by negative one, Step 312.
[0046] A determination is then made in Step 314 as to
whether the process of multiplying the parameter corre-
sponding to each of the transmit data register TXDA-
TA[5]-TXDATA[0] by a one or a negative one has been
performed, and if all multiplications by a one or a negative
one have not been performed, the process goes to the
next transmit data register, Step 316, and the returns to
Step 308 so that the next transmit data register is multi-
plied by one or negative one, responsive to the digital
data value in the corresponding transmit data register. If
all multiplications by a one or a negative one have been
performed, the resulting products corresponding to each
of the adder sections 132, 136 and 140 are added, as
described above, to form output values x1d, x2d, and
x3d, Step 318. The output values x1d, x2d and x3d are
transmitted to the waveform generator, and then cleared,
Step 320 and the process returns to Step 306.
[0047] FIG. 10 is a flowchart of a method for generating
a waveform using parameters generated in a dual mode
wireless device according to the present invention. Start-
ing at the beginning of each frame, second waveform
generator 44 begins generating the waveform using the
method of the present invention. As illustrated in FIG. 10,
a determination is made in Step 322 as to whether the
transmission is at the beginning of a frame, such as a
time division multiple access, or TDMA frame, and if the
transmission is determined to be at the beginning of a
frame, a fixed value is loaded into a first register, i.e.,
position register 160, in Step 324. Output values x1d,
x2d and x3d from coefficient generator 42 are input by
waveform generator 44, in Step 326. For each instant of
the sixteen clock period, a present value of a last register,
i.e., acceleration register 164, is added to a predeter-
mined one of the output values, i.e., jerk value x3d, in
Step 328. In addition, a present value of each of the re-
maining registers, i.e., position and slope register 160,
162, is added to a previous value of a corresponding
previous register, in Step 328, so that a new output value
for registers 160, 162 and 164 is generated at each clock
period.
[0048] If it is determined in Step 322 that the transmis-
sion is not at the beginning of a frame burst, it is not
necessary to load the fixed value into position register
160, and therefore the process continues at Step 326.
[0049] Each new generated output value for position
register 160 is output by second waveform generator 44
to the modulator, Step 330, and a determination is made
in Step 332 as to whether the clock period has ended. If
the predetermined clock period has not ended, the proc-
ess returns to Step 328 so that new output values for
registers 160, 162 and 164 are generated for a next clock
period and a new generated output value for position
register 160 is output to modulator 48 Step 330. If it is
determined in Step 332 that the predetermined clock has
ended, the process returns to Step 322 an output value
is transmitted from the waveform generator 44 to the
modulator 48, and the process returns to Step 322.
[0050] FIGS. 11a-d are graphic representations of a
smoothing of a waveform by a waveform generator of a
dual mode wireless device according to the present in-
vention. As illustrated in FIG. 11a, the new jerk value x3d
remains constant for sixteen clock periods, illustrated by
a first straight line portion 172. After sixteen clock periods
a new set of values is input by the second waveform
generator 44 from the coefficient generator 42, including
a new jerk value that would then remain constant for six-
teen clock values, illustrated by a second straight line
portion 174. After those sixteen clock periods, the proc-
13 14
EP 1 287 623 B1
9
5
10
15
20
25
30
35
40
45
50
55
ess would be repeated again, and so on.
[0051] As illustrated in FIG. 11b, the acceleration starts
initially at the acceleration value x2d calculated by the
coefficient generator 42 and, rather than remaining con-
stant during the sixteen clock periods, the acceleration
at each of the sixteen periods would be the sum of the
previous acceleration and the jerk. Since the jerk is con-
stant, the acceleration would either ramp up or ramp
down during the sixteen periods, depending upon wheth-
er the jerk is a positive or a negative value.
[0052] As illustrated in FIG. 11c, the slope starts initially
at the slope value x2d calculated by the coefficient gen-
erator 42, and depending upon whether the acceleration
and jerk is a positive or a negative value, the slope rises
or falls at an ever increasing rate, so that a curvature
begins to form.
[0053] Finally, as illustrated in FIG 11d, by performing
successive integrations at each of the three registers
160, 162 and 164, once the process has been performed
by the position register 160, a smooth, slowly moving
waveform is formed. As a result, the second waveform
generator 44 of the present invention generates a smooth
tuning word so that frequency splatter is minimized and
interference with neighboring telephones is reduced.
[0054] While a particular embodiment of the present
invention has been shown and described, modifications
may be made. For example, although the present inven-
tion is described in terms of utilizing a first, second and
third derivative, any number of derivative values could
be used. In addition, it understood that the coefficient
generator of the present invention could include an ad-
ditional adder section and corresponding position regis-
ter section, to calculate the position value. It is therefore
intended to cover all such changes and modifications
which fall within the scope of the invention as defined in
the appended claims.
Claims
1. A dual mode wireless device, comprising:
a GSM unit (34) for transmitting sequences of
digital data values;
a coefficient generator (42) for generating output
parameter values for a GSM waveform, for re-
ceiving sequentially the digital data values of the
sequences of digital data values and for contain-
ing parameters corresponding to a modulator
(48) of the dual mode wireless device, the coef-
ficient generator (42) being arranged to gener-
ate the output parameter values by multiplying
each parameter by a one or a negative one,
based on corresponding digital data values of
the sequences of digital data values from the
GSM unit (34), and by adding the resulting prod-
ucts to generate the output parameter values;
and
a waveform generator (44) for generating the
GSM waveform using the generated output pa-
rameter values.
2. The dual mode wireless device of claim 1, further
comprising the modulator (48) for modulating the
GSM waveform generated by the waveform gener-
ator (44), wherein the coefficient generator (42) fur-
ther comprises:
a plurality of adder sections (132, 136, 140),
each having a plurality of adders (142, 144, 146)
and multipliers (148, 150, 152);
a plurality of register sections (154, 156, 158)
containing the parameters corresponding to the
modulator (48); and
a plurality of transmit data registers for sequen-
tially receiving the digital data values from the
GSM unit (34), wherein the coefficient generator
(42) is arranged to generate the output param-
eter values for the GSM waveform by multiply-
ing, using the multipliers (148, 150, 152), each
of the parameters in the plurality of register sec-
tions (154, 156, 158) by a one or a negative one,
responsive to the digital data values in the plu-
rality of transmit data registers, and by adding
the resulting products using adders (142, 144,
146) to form corresponding coefficient generator
output parameter values.
3. The dual mode wireless device of claim 2, where the
waveform generator (44) further comprises a plural-
ity of registers (160, 162, 164) for receiving the output
parameter values from the coefficient generator (42),
wherein the waveform generator (44) is arranged to
store a fixed value in a first register (160) of the plu-
rality of registers, and to generate a new value output
from a last register of the plurality of registers by
adding a present value of the last register and one
of the coefficient generator output parameter values,
and to generate a new value output from the remain-
ing registers of the plurality of registers by adding a
present value of each of the remaining registers of
the plurality of registers to a previous value of a cor-
responding preceding one of the plurality of regis-
ters.
4. The dual mode wireless device of claim 2, wherein
the coefficient generator (42) is arranged to receive
a new digital data value from the GSM unit (34) for
inputting to a first one of the plurality of transmit data
registers, in response to the generated output pa-
rameter values being input into the waveform gen-
erator (44), and the coefficient generator (42) is fur-
ther arranged to sequentially shift the digital data val-
ues in the plurality of transmit data registers.
5. The dual mode wireless device of claim 1, further
15 16
EP 1 287 623 B1
10
5
10
15
20
25
30
35
40
45
50
55
comprising the modulator (48) for modulating the
GSM waveform generated by the waveform gener-
ator (44), wherein the coefficient generator (42) fur-
ther comprises:
a first adder section (132), having first transmit
data registers, for calculating a first value, a sec-
ond adder section (136), having second transmit
data registers, for calculating a second value,
and a third adder section (140), having third
transmit data registers, the transmit data regis-
ters being arranged to sequentially receive the
digital data values from the GSM unit (34);
a first register section (154) containing prede-
termined first derivative values, a second regis-
ter section (156) containing predetermined sec-
ond derivative values, and a third register sec-
tion (158) containing predetermined third deriv-
ative values, wherein the coefficient generator
(42) is arranged to calculate: the first value by
multiplying each of the first derivative values by
one or negative one in response to the digital
data values in the first transmit data registers;
the second value by multiplying each of the sec-
ond derivative values by one or negative one in
response to the digital data values in the second
transmit data registers; and the third value by
multiplying each of the third derivative values by
one or negative one in response to the digital
data values in the third transmit data registers.
the coefficient generator (42) is arranged to multiply
the first derivative values, the second derivative val-
ues and the third derivative values by one in re-
sponse to the digital data values being equal to zero,
and negative one in response to the digital data val-
ues being equal to one.
the coefficient generator (42) is arranged to sequen-
tially shift the digital data values in the transmit data
registers, in response to the calculated values being
input into the waveform generator (44), and to re-
ceive a new digital value from the GSM unit (34) for
input to a first data transmit register of each of the
first transmit data registers, the second transmit data
registers, and the third transmit data registers.
the waveform generator (44) further comprises:
a first register (160) for receiving a fixed value,
a second register (162) for receiving the first val-
ue, and a third register (164) for receiving the
second value, wherein the waveform generator
(44) is arranged to calculate: a new value for the
first register (160) by adding a present value of
the first register to a previous value output by
the second register; a new value for the second
register by adding a present value of the second
register to a previous value output by the third
register; and a new value for the third register
by adding a present value of the third register to
the third value.
9. The dual mode wireless device of claim 3 or 8, where-
in the fixed value is equal to 35555H.
10. The dual mode wireless device of claim 2 or 9, the
modulator (48) further comprising a voltage control-
led oscillator (56), a phase detector (58) and a low
pass filter (64), wherein the modulator is a constant
amplitude frequency modulation modulator with
phase coherency in which frequency modulation is
accomplished using a phase lock loop, and wherein
a modulating element of the phase locked loop is a
divide by N divider (60) in a feedback path from the
voltage controlled oscillator (56) to the phase detec-
tor (58), and the low pass filter (64) is positioned at
an output of the phase detector (58) to filter high
frequency noise contained in output current of the
phase detector.
the coefficient generator (42) comprises:
a first adder section (132), having corresponding
first transmit data registers, for generating a first
value, a second adder section (136), having cor-
responding second transmit data registers, for
generating a second value, and a third adder
section (140), having corresponding third trans-
mit data registers, for calculating a third value,
the transmit data registers being arranged to se-
quentially receive the digital data values from
the GSM unit (34);
a first register section (154) containing prede-
termined first derivative values, a second regis-
ter section (156) containing predetermined sec-
ond derivative values, and a third register sec-
tion (158) containing predetermined third deriv-
ative values, wherein the coefficient generator
(42) is arranged to generate the first value, the
second value and the third value by multiplying
each of the first derivative values, the second
derivative values, and the third derivative val-
ues, respectively, by one in response to the cor-
responding digital values being equal to zero,
and by negative one in response to the corre-
sponding digital values being equal to one and
by adding the resulting products corresponding
to each of the first, second and third adder sec-
tions; and
the waveform generator (44) being arranged to
generate the GSM waveform based on the gen-
17 18
EP 1 287 623 B1
11
5
10
15
20
25
30
35
40
45
50
55
erated first value, second value and third value.
the coefficient generator (42) is arranged to sequen-
tially shift the digital data values in the transmit data
registers, in response to the calculated values being
input into the waveform generator (44), and to re-
ceive a new digital value from the GSM unit (34) for
input to the first transmit data registers, the second
transmit data registers, and the third transmit data
registers.
the waveform generator (44) further comprises:
a first register (160) for receiving a fixed value,
a second register (162) for receiving the first val-
ue, and a third register (164) for receiving the
second value, wherein the waveform generator
(44) is arranged to calculate: a new value for the
first register by adding a present value of the
first register to a previous value output by the
second register; a new value for the second reg-
ister by adding a present value of the second
register to a previous value output by the third
register; and a new value for the third register
by adding a present value of the third register to
the third value.
the fixed value is equal to 35555H.
15. The dual mode wireless device of claim 14, the mod-
ulator further comprising a voltage controlled oscil-
lator (56), a phase detector (58) and a low pass filter
(64), wherein the modulator is a constant amplitude
frequency modulation modulator with phase coher-
ency in which frequency modulation is accomplished
using a phase lock loop, and wherein a modulating
element of the phase locked loop is a divide by N
divider (60) in a feedback path from the voltage con-
trolled oscillator (56) to the phase detector (58), and
the low pass filter (64) is positioned at an output of
the phase detector (58) to filter high frequency noise
contained in output current of the phase detector.
the predetermined first derivative values, second de-
rivative values and third derivative values take into
account pre-distortion requirements of the phase
lock loop of the modulator.
17. A method of generating a waveform in a dual mode
wireless device, comprising the steps of:
inserting (302, 304, 406) digital data values into
transmit data registers corresponding to each of
a plurality of adder sections (132, 136, 140);
multiplying (308, 310, 312, 314) parameters cor-
responding to a modulator (48) in each register
of a plurality of register sections (154, 156, 158)
by one or negative one in response to the digital
data values inserted in corresponding transmit
data registers;
adding (318) products resulting from the multi-
plying step corresponding to each of the plurality
of adder sections (132, 136, 140); and
outputting (320) first output values, correspond-
ing to each of the added products, to a GSM
waveform generator (44).
18. The method of claim 17, further comprising the steps
of:
determining (322) whether transmission is at the
beginning of a frame burst;
loading (324) a fixed value in a first register (160)
of the waveform generator (44) in response to
transmission being at the beginning of a frame
burst;
inputting (326) the first output values at corre-
sponding registers of the waveform generator
(44);
generating (328) new output values by adding
a present value of a last one of the registers and
a predetermined one of the first output values,
and adding a present value from each of the
remaining registers to a previous value of a cor-
responding preceding one of the registers;
outputting (330) the new output value generated
by the first register to a modulator (48) and de-
termining (332) whether a predetermined clock
period has ended; and
returning to the step of determining (322) wheth-
er transmission is at the beginning of a frame
burst in response to the predetermined clock pe-
riod having ended, and returning to the gener-
ating step in response to the predetermined
clock period not having ended.
Patentansprche
1. Bimodale drahtlose Vorrichtung, die Folgendes auf-
weist:
eine GSM-Einheit (34) zum bertragen von Se-
quenzen von digitalen Datenwerten;
einen Koeffizienzgenerator (42) zum Erzeugen
von Ausgabeparameterwerten fr eine GSM-
Wellenform, zum sequentiellen Empfangen der
digitalen Datenwerte der Sequenzen von digita-
len Datenwerten und zum Umfassen von Para-
metern, die einem Modulator (48) der bimodalen
drahtlosen Vorrichtung entsprechen, wobei der
Koeffizienzgenerator (42) so aufgebaut ist, dass
19 20
EP 1 287 623 B1
12
5
10
15
20
25
30
35
40
45
50
55
er die Ausgabeparameterwerte durch Multipli-
kation eines jeden Parameters mit einer Eins
oder einer negativen Eins erzeugt, basierend
auf entsprechenden digitalen Datenwerten der
Sequenzen von digitalen Datenwerten aus der
GSM-Einheit (34), und durch Addition der sich
ergebenden Ergebnisse zur Erzeugung der
Ausgabeparameterwerte; und
einen Wellenformgenerator (44) zur Erzeugung
der GSM-Wellenform unter Verwendung der er-
zeugten Ausgabeparameterwerte.
2. Bimodale drahtlose Vorrichtung nach Anspruch 1,
die des Weiteren den Modulator (48) zum Modulie-
ren der von dem Wellenformgenerator (44) erzeug-
ten GSM-Wellenform aufweist, wobei der Koeffizi-
enzgenerator (42) des Weiteren Folgendes auf-
weist:
eine Mehrzahl von Addiererabschnitten (132,
136, 140), wobei jeder eine Mehrzahl von Ad-
dierern (142, 144, 146) und Multiplikationsfak-
toren (148, 150, 152) aufweist;
eine Mehrzahl von Registerabschnitten (154,
156, 158), die die Parameter enthalten, die dem
Modulator (48) entsprechen; und
eine Mehrzahl von Sende-Datenregistern zum
sequentiellen Empfangen der digitalen Daten-
werte aus der GSM-Einheit (34), wobei der Ko-
effizienzgenerator (42) so aufgebaut ist, dass er
die Ausgabeparameterwerte fr die GSM-Wel-
lenform durch Multiplikation, unter Verwendung
der Multiplikationsfaktoren (148, 150, 152), ei-
nes jeden Parameters in der Mehrzahl von Re-
gisterabschnitten (154, 156, 158) mit einer Eins
oder einer negativen Eins erzeugt, ansprechend
auf die digitalen Datenwerte in der Mehrzahl von
Sende-Datenregistern, und durch Addition der
sich ergebenden Ergebnisse unter Verwendung
der Addierer (142, 144, 146) zur Bildung von
entsprechenden Koeffizienzgenerator-Ausga-
beparameterwerten.
wobei der Wellenformgenerator (44) des Weiteren
eine Mehrzahl von Registern (160, 162, 164) zum
Empfang der Ausgabeparameterwerte aus dem Ko-
effizienzgenerator (42) aufweist, wobei der Wellen-
formgenerator (44) so aufgebaut ist, dass er einen
Festwert in einem ersten Register (160) der Mehr-
zahl von Registern speichert, und eine neue Wert-
ausgabe aus einem letzten Register der Mehrzahl
von Registern durch Addieren eines aktuellen Werts
des letzten Registers und eines Werts der Koeffizi-
enzgenerator-Ausgabeparameterwerte erzeugt,
und eine neue Wertausgabe aus den brigen Regis-
tern der Mehrzahl von Registern durch Addieren ei-
nes aktuellen Werts von jedem der brigen Register
der Mehrzahl von Registern zu einem vorherigen
Wert eines entsprechenden vorherigen Registers
der Mehrzahl von Registern erzeugt.
wobei der Koeffizienzgenerator (42) so aufgebaut
ist, dass er einen neuen digitalen Datenwert aus der
GSM-Einheit (34) zur Eingabe in ein erstes Register
der Mehrzahl von Sende-Datenregistern empfngt,
ansprechend auf die Eingabe der sich ergebenden
Ausgabeparameterwerte in den Wellenformgenera-
tor (44), und wobei der Koeffizienzgenerator (42) des
Weiteren so aufgebaut ist, dass er sequentiell die
digitalen Datenwerte in der Mehrzahl von Sende-Da-
tenregistern verschiebt.
die des Weiteren den Modulator (48) zum Modulie-
ren der von dem Wellenformgenerator (44) erzeug-
ten GSM-Wellenform aufweist, wobei der Koeffizi-
enzgenerator (42) des Weiteren Folgendes auf-
weist:
einen ersten Addiererabschnitt (132) mit ersten
Sende-Datenregistern, zum Berechnen eines
ersten Werts, einen zweiten Addiererabschnitt
(136) mit zweiten SendeDatenregistern, zum
Berechnen eines zweiten Werts, und einen drit-
ten Addiererabschnitt (140) mit dritten Sende-
Datenregistern, wobei die Sende-Datenregister
so aufgebaut sind, dass sie die digitalen Daten-
werte aus der GSM-Einheit (34) sequentiell
empfangen;
einen ersten Registerabschnitt (154), der vor-
gegebene erste Ableitungswerte enthlt, einen
zweiten Registerabschnitt (156), der vorgege-
bene zweite Ableitungswerte enthlt, und einen
dritten Registerabschnitt (158), der vorgegebe-
ne dritte Ableitungswerte enthlt, wobei der Ko-
Folgendes berechnet: den ersten Wert durch
Multiplizieren eines jeden Werts der ersten Ab-
leitungswerte mit einer Eins oder einer negati-
ven Eins, ansprechend auf die digitalen Daten-
werte in den ersten Sende-Datenregistern; den
zweiten Wert durch Multiplizieren eines jeden
Werts der zweiten Ableitungswerte mit einer
Eins oder einer negativen Eins, ansprechend
auf die digitalen Datenwerte in den zweiten Sen-
de-Datenregistern; und den dritten Wert durch
Multiplizieren eines jeden Werts der dritten Ab-
leitungswerte mit einer Eins oder einer negati-
ven Eins, ansprechend auf die digitalen Daten-
werte in den dritten Sende-Datenregistern.
ist, dass er die ersten Ableitungswerte, die zweiten
21 22
EP 1 287 623 B1
13
5
10
15
20
25
30
35
40
45
50
55
Ableitungswerte und die dritten Ableitungswerte mit
einer Eins multipliziert, ansprechend darauf, dass
die digitalen Datenwerte gleich Null sind, und mit ei-
ner negativen Eins, ansprechend darauf, dass die
digitalen Datenwerte gleich Eins sind.
ist, dass er die digitalen Datenwerte in den Sende-
Datenregistern sequentiell verschiebt, ansprechend
auf die Eingabe der berechneten Werte in den Wel-
lenformgenerator (44), und einen neuen digitalen
Wert aus der GSM-Einheit (34) zur Eingabe in ein
erstes Sende-Datenregister eines jeden Registers
der ersten Sende-Datenregister, der zweiten Sende-
Datenregister und der dritten Sende-Datenregister
empfngt.
Folgendes aufweist:
ein erstes Register (160) zum Empfang eines
Festwerts, ein zweites Register (162) zum Emp-
fang des ersten Werts und ein drittes Register
(164) zum Empfang des zweiten Werts, wobei
der Wellenformgenerator (44) so aufgebaut ist,
dass er Folgendes berechnet: einen neuen Wert
fr das erste Register (160) durch Addition eines
aktuellen Werts des ersten Registers zu einem
vorherigen Wert, der von dem zweiten Register
ausgegeben wird; einen neuen Wert fr das
zweite Register durch Addition eines aktuellen
Werts des zweiten Registers zu einem vorheri-
gen Wert, der von dem dritten Register ausge-
geben wird; und einen neuen Wert fr das dritte
Register durch Addition eines aktuellen Werts
des dritten Registers zu dem dritten Wert.
9. Bimodale drahtlose Vorrichtung nach Anspruch 3
oder 8, wobei der Festwert gleich 35555H ist.
10. Bimodale drahtlose Vorrichtung nach Anspruch 2
oder 9, wobei der Modulator (48) des Weiteren einen
spannungsgesteuerten Oszillator (56), einen Pha-
sendetektor (58) und einen Tiefpassfilter (64) auf-
weist, wobei der Modulator ein Frequenzmodulati-
onsmodulator mit konstanter Amplitude und mit Pha-
sengleichheit ist, bei welchem die Frequenzmodu-
lation unter Verwendung eines Phasenregelkreises
erfolgt, und wobei ein Modulationselement des Pha-
senregelkreises eine Teilung durch den Teiler N (60)
in einem Rckkopplungsweg vom spannungsge-
steuerten Oszillator (56) zum Phasendetektor (58)
ist, und wobei der Tiefpassfilter (64) an einer Aus-
gabe des Phasendetektors (58) positioniert ist, um
hochfrequentes Rauschen zu filtern, das im Aus-
gangsstrom des Phasendetektors enthalten ist.
wobei der Koeffizienzgenerator (42) Folgendes auf-
weist:
einen ersten Addiererabschnitt (132), mit ent-
sprechenden ersten Sende-Datenregistern,
zum Erzeugen eines ersten Werts, einen zwei-
ten Addiererabschnitt (136), mit entsprechen-
den zweiten Sende-Datenregistern, zum Erzeu-
gen eines zweiten Werts und einen dritten Ad-
diererabschnitt (140), mit entsprechenden drit-
ten Sende-Datenregistern, zum Berechnen ei-
nes dritten Werts, wobei die Sende-Datenregis-
ter so aufgebaut sind, dass sie die digitalen Da-
tenwerte aus der GSM-Einheit (34) sequentiell
empfangen;
einen ersten Registerabschnitt (154), der vor-
gegebene erste Ableitungswerte enthlt, einen
zweiten Registerabschnitt (156), der vorgege-
bene zweite Ableitungswerte enthlt, und einen
dritten Registerabschnitt (158), der vorgegebe-
ne dritte Ableitungswerte enthlt, wobei der Ko-
den ersten Wert, den zweiten Wert und den drit-
ten Wert durch Multiplikation eines jeden Werts
jeweils der ersten Ableitungswerte, der zweiten
Ableitungswerte und der dritten Ableitungswer-
te mit einer Eins erzeugt, ansprechend darauf,
dass die entsprechenden digitalen Werte gleich
Null sind, und mit einer negativen Eins, anspre-
chend darauf, dass die entsprechenden digita-
len Werte gleich Eins sind, und durch Addition
der sich ergebenden Ergebnisse, die jeweils
dem ersten, zweiten und dritten Addiererab-
schnitt entsprechen; und
wobei der Wellenformgenerator (44) so aufge-
baut ist, dass er die GSM-Wellenform basierend
auf dem erzeugten ersten Wert, zweiten Wert
und dritten Wert erzeugt.
ist, dass er die digitalen Datenwerte in die Sende-
Datenregister sequentiell verschiebt, ansprechend
auf die Eingabe der berechneten Werte in den Wel-
lenformgenerator (44), und einen neuen digitalen
Wert aus der GSM-Einheit (34) zur Eingabe in die
ersten Sende-Datenregister, die zweiten Sende-Da-
tenregister und die dritten Sende-Datenregister
empfngt.
Folgendes aufweist:
ein erstes Register (160) zum Empfang eines
Festwerts, ein zweites Register (162) zum Emp-
fang des ersten Werts und ein drittes Register
23 24
EP 1 287 623 B1
14
5
10
15
20
25
30
35
40
45
50
55
(164) zum Empfang des zweiten Werts, wobei
der Wellenformgenerator (44) so aufgebaut ist,
dass er Folgendes berechnet: einen neuen Wert
fr das erste Register durch Addition eines ak-
tuellen Werts des ersten Registers zu einem vor-
herigen Wert, der von dem zweiten Register
ausgegeben wird; einen neuen Wert fr das
zweite Register durch Addition eines aktuellen
Werts des zweiten Registers zu einem vorheri-
gen Wert, der von dem dritten Register ausge-
geben wird; und einen neuen Wert fr das dritte
Register durch Addition eines aktuellen Werts
des dritten Registers zu dem dritten Wert.
wobei der Festwert gleich 35555H ist.
wobei der Modulator des Weiteren einen span-
nungsgesteuerten Oszillator (56), einen Phasende-
tektor (58) und einen Tiefpassfilter (64) aufweist, wo-
bei der Modulator ein Frequenzmodulationsmodula-
tor mit konstanter Amplitude und mit Phasengleich-
heit ist, bei welchem die Frequenzmodulation unter
Verwendung eines Phasenregelkreises erfolgt, und
wobei ein Modulationselement des Phasenregel-
kreises eine Teilung durch den Teiler N (60) in einem
Rckkopplungsweg vom spannungsgesteuerten
Oszillator (56) zum Phasendetektor (58) ist, und wo-
bei der Tiefpassfilter (64) an einer Ausgabe des Pha-
sendetektors (58) positioniert ist, um hochfrequen-
tes Rauschen zu filtern, das im Ausgangsstrom des
Phasendetektors enthalten ist.
wobei die vorgegebenen ersten Ableitungswerte,
zweiten Ableitungswerte und dritten Ableitungswer-
te Vorverzerrungsanforderungen des Phasenregel-
kreises des Modulators bercksichtigen.
17. Verfahren zur Erzeugung einer Wellenform in einer
bimodalen drahtlosen Vorrichtung, das die folgen-
den Schritte aufweist:
Einfgen (302, 304, 406) von digitalen Daten-
werten in Sende-Datenregister, die jedem Ad-
dierabschnitt einer Mehrzahl von Addiererab-
schnitten (132, 136, 140) entsprechen;
Multiplizieren (308, 310, 312, 314) von Parame-
tern, die einem Modulator (48) in jedem Register
einer Mehrzahl von Registerabschnitten (154,
156, 158) entsprechen, mit einer Eins oder einer
negativen Eins, ansprechend auf das Einfgen
der digitalen Datenwerte in entsprechende Sen-
de-Datenregister;
Addieren (318) von Ergebnissen, die sich aus
dem Multiplikationsschritt ergeben, entspre-
chend jedem der Mehrzahl von Addiererab-
schnitten (132, 136, 140); und
Ausgeben (320) von ersten Ausgabewerten, die
jedem der addierten Ergebnisse entsprechen,
an einen GSM-Wellenformgenerator (44).
18. Verfahren nach Anspruch 17, das des Weiteren die
folgenden Schritte aufweist:
Bestimmen (322), ob die bertragung am Be-
ginn eines Rahmen-Bursts ist;
Laden (324) eines Festwerts in ein erstes Re-
gister (160) des Wellenformgenerators (44), an-
sprechend darauf, dass die bertragung am Be-
ginn eines Rahmen-Bursts ist;
Eingeben (326) der ersten Ausgabewerte an
entsprechenden Registern des Wellenformge-
nerators (44);
Erzeugen (328) von neuen Ausgabewerten
durch Addieren eines aktuellen Werts eines letz-
ten Registers der Register zu einem vorgege-
benen Wert der ersten Ausgabewerte, und Ad-
dieren eines aktuellen Werts aus jedem der b-
rigen Register zu einem vorherigen Wert eines
entsprechenden vorherigen Registers der Re-
gister;
Ausgeben (330) des neuen Ausgabewerts, der
von dem ersten Register erzeugt wird, an einen
Modulator (48) und Bestimmen (332), ob ein vor-
gegebenes Taktintervall beendet ist; und
Zurckkehren zum Schritt des Bestimmens
(322), ob die bertragung am Beginn eines Rah-
men-Bursts ist, ansprechend auf das Ende des
vorgegebenen Taktintervalls, und Zurckkeh-
ren zum Erzeugungsschritt, ansprechend dar-
auf, dass das vorgegebene Taktintervall nicht
beendet ist.
Revendications
1. Dispositif sans fil double mode, comprenant :
une unit GSM (34) destine transmettre des
squences de valeurs de donnes numriques ;
un gnrateur de coefficients (42) destin g-
nrer des valeurs de paramtres de sortie pour
une forme donde GSM, recevoir squentiel-
lement les valeurs de donnes numriques des
squences de valeurs de donnes numriques
et contenir des paramtres correspondant
un modulateur (48) du dispositif sans fil double
mode, le gnrateur de coefficients (42) tant
agenc de manire gnrer les valeurs de pa-
ramtres de sortie en multipliant chaque para-
mtre par une unit ou une unit ngative, sur
la base de valeurs de donnes numriques cor-
respondantes des squences de valeurs de
donnes numriques en provenance de lunit
25 26
EP 1 287 623 B1
15
5
10
15
20
25
30
35
40
45
50
55
GSM (34), et en ajoutant les produits rsultants
en vue de gnrer les valeurs de paramtres de
sortie ; et
un gnrateur de formes donde (44) destin
gnrer la forme donde GSM en utilisant les
valeurs de paramtres de sortie gnres.
2. Dispositif sans fil double mode selon la revendica-
tion 1, comprenant en outre le modulateur (48) pour
moduler la forme donde GSM gnre par le gn-
rateur de formes donde (44), dans lequel le gn-
rateur de coefficients (42) comprend en outre :
une pluralit de sections de sommateurs (132,
136, 140), prsentant chacune une pluralit de
sommateurs (142, 144, 146) et de multiplica-
teurs (148, 150, 152) ;
une pluralit de sections de registres (154, 156,
158) contenant les paramtres correspondant
au modulateur (48) ; et
une pluralit de registres de transmission de
donnes pour recevoir squentiellement les va-
leurs de donnes numriques en provenance
de lunit GSM (34), dans lequel le gnrateur
de coefficients (42) est agenc de manire
gnrer les valeurs de paramtres de sortie pour
la forme donde GSM en multipliant, au moyen
des multiplicateurs (148, 150, 152), chacun des
paramtres dans la pluralit de sections de re-
gistres (154, 156, 158) par une unit ou une unit
ngative, en rponse aux valeurs de donnes
numriques dans la pluralit de registres de
transmission de donnes, et en ajoutant les pro-
duits rsultants en utilisant des sommateurs
(142, 144, 146) en vue de former des valeurs
de paramtres de sortie de gnrateur de coef-
ficients correspondantes.
tion 2, dans lequel le gnrateur de formes donde
(44) comprend en outre une pluralit de registres
(160, 162, 164) pour recevoir les valeurs de para-
mtres de sortie en provenance du gnrateur de
coefficients (42), dans lequel le gnrateur de for-
mes donde (44) est agenc de manire stocker
une valeur fixe dans un premier registre (160) de la
pluralit de registres, et gnrer une nouvelle va-
leur gnre en sortie partir dun dernier registre
de la pluralit de registres, en ajoutant une valeur
en cours du dernier registre et lune des valeurs de
paramtres de sortie de gnrateur de coefficients,
et gnrer une nouvelle valeur gnre en sortie
partir des registres restants de la pluralit de re-
gistres, en ajoutant une valeur en cours de chacun
des registres restants de la pluralit de registres
une valeur prcdente dun registre prcdant cor-
respondant de la pluralit de registres.
tion 2, dans lequel le gnrateur de coefficients (42)
est agenc de manire recevoir une nouvelle va-
leur de donnes numrique en provenance de lunit
GSM (34), appliquer un premier registre de la
pluralit de registres de transmission de donnes,
en rponse au fait que les valeurs de paramtres de
sortie gnres sont appliques au gnrateur de
formes donde (44), et le gnrateur de coefficients
(42) est en outre agenc de manire dcaler s-
quentiellement les valeurs de donnes numriques
dans la pluralit de registres de transmission de don-
nes.
tion 1, comprenant en outre le modulateur (48) pour
moduler la forme donde GSM gnre par le gn-
rateur de formes donde (44), dans lequel le gn-
rateur de coefficients (42) comprend en outre :
une premire section de sommateur (132), pr-
sentant des premiers registres de transmission
de donnes, pour calculer une premire valeur,
une deuxime section de sommateur (136), pr-
sentant des deuximes registres de transmis-
sion de donnes, pour calculer une deuxime
valeur, et une troisime section de sommateur
(140), prsentant des troisimes registres de
transmission de donnes, les registres de trans-
mission de donnes tant agencs de manire
recevoir squentiellement les valeurs de don-
nes numriques en provenance de lunit GSM
(34) ;
une premire section de registre (154) conte-
nant des premires valeurs de drives prd-
termines, une deuxime section de registre
(156) contenant des deuximes valeurs de d-
rives prdtermines, et une troisime section
de registre (158) contenant des troisimes va-
leurs de drives prdtermines, dans lequel
le gnrateur de coefficients (42) est agenc de
manire calculer : la premire valeur en mul-
tipliant chacune des premires valeurs de dri-
ves par une unit ou une unit ngative en r-
ponse aux valeurs de donnes numriques
dans les premiers registres de transmission de
donnes ; la deuxime valeur en multipliant cha-
cune des deuximes valeurs de drives par
une unit ou une unit ngative en rponse aux
valeurs de donnes numriques dans les
deuximes registres de transmission de
donnes ; et la troisime valeur en multipliant
chacune des troisimes valeurs de drives par
une unit ou une unit ngative en rponse aux
valeurs de donnes numriques dans les troi-
simes registres de transmission de donnes.
27 28
EP 1 287 623 B1
16
5
10
15
20
25
30
35
40
45
50
55
est agenc de manire multiplier les premires va-
leurs de drives, les deuximes valeurs de drives
et les troisimes valeurs de drives, par une unit,
en rponse au fait que les valeurs de donnes nu-
mriques sont gales zro, et, par unit ngative,
en rponse au fait que les valeurs de donnes nu-
mriques sont gales un.
est agenc de manire dcaler squentiellement
les valeurs de donnes numriques dans les regis-
tres de transmission de donnes, en rponse au fait
que les valeurs calcules sont appliques au gn-
rateur de formes donde (44), et recevoir une nou-
velle valeur numrique en provenance de lunit
GSM (34), appliquer un premier registre de trans-
mission de donnes de chacun des premiers regis-
tres de transmission de donnes, des deuximes
registres de transmission de donnes et des troisi-
mes registres de transmission de donnes.
(44) comprend en outre :
un premier registre (160) destin recevoir une
valeur fixe, un deuxime registre (162) destin
recevoir la premire valeur, et un troisime
registre (164) destin recevoir la deuxime va-
leur, dans lequel le gnrateur de formes donde
(44) est agenc de manire calculer : une nou-
velle valeur pour le premier registre (160), en
ajoutant une valeur en cours du premier registre
une valeur prcdente gnre en sortie par
le deuxime registre ; une nouvelle valeur pour
le deuxime registre, en ajoutant une valeur en
cours du deuxime registre une valeur prc-
dente gnre en sortie par le troisime
registre ; et une nouvelle valeur pour le troisime
registre, en ajoutant une valeur en cours du troi-
sime registre la troisime valeur.
tion 3 ou 8, dans lequel la valeur fixe est gale
35555H.
tion 2 ou 9, dans lequel le modulateur (48) comporte
en outre un oscillateur tension asservie (56), un
dtecteur de phase (58) et un filtre passe-bas (64),
dans lequel le modulateur est un modulateur de mo-
dulation de frquence amplitude constante avec
cohrence de phase, dans lequel la modulation de
frquence est mise en oeuvre en utilisant une boucle
verrouillage de phase, et dans lequel un lment
modulant de la boucle verrouillage de phase cor-
respond un diviseur de division par N (60) dans un
chemin de rtroaction allant de loscillateur tension
asservie (56) au dtecteur de phase (58), et le filtre
passe-bas (64) est positionn au niveau dune sortie
du dtecteur de phase (58) en vue de filtrer du bruit
haute frquence contenu dans un courant de sortie
du dtecteur de phase.
comprend :
une premire section de sommateur (132), pr-
sentant des premiers registres de transmission
de donnes correspondants, pour gnrer une
premire valeur, une deuxime section de som-
mateur (136), prsentant des deuximes regis-
tres de transmission de donnes correspon-
dants, pour gnrer une deuxime valeur, et une
troisime section de sommateur (140), prsen-
tant des troisimes registres de transmission de
donnes correspondants, pour calculer une troi-
sime valeur, les registres de transmission de
donnes tant agencs de manire recevoir
squentiellement les valeurs de donnes num-
riques en provenance de lunit GSM (34) ;
une premire section de registre (154) conte-
nant des premires valeurs de drives prd-
termines, une deuxime section de registre
(156) contenant des deuximes valeurs de d-
rives prdtermines, et une troisime section
de registre (158) contenant des troisimes va-
leurs de drives prdtermines, dans lequel
le gnrateur de coefficients (42) est agenc de
manire gnrer la premire valeur, la deuxi-
me valeur et la troisime valeur, en multipliant
chacune des premires valeurs de drives,
des deuximes valeurs de drives et des troi-
simes valeurs de drives, respectivement,
par une unit, en rponse au fait que les valeurs
numriques correspondantes sont gales z-
ro, et, par une unit ngative, en rponse au fait
que les valeurs numriques correspondantes
sont gales un, et en ajoutant les produits r-
sultants correspondant chacune des premi-
re, deuxime et troisime sections de
sommateurs ; et
le gnrateur de formes donde (44) est agenc
de manire gnrer la forme donde GSM sur
la base de la premire valeur gnre, de la
deuxime valeur gnre et de la troisime va-
leur gnre.
est agenc de manire dcaler squentiellement
les valeurs de donnes numriques dans les regis-
tres de transmission de donnes, en rponse au fait
29 30
EP 1 287 623 B1
17
5
10
15
20
25
30
35
40
45
50
55
que les valeurs calcules sont appliques au gn-
rateur de formes donde (44), et recevoir une nou-
velle valeur numrique, en provenance de lunit
GSM (34), destine tre applique aux premiers
registres de transmission de donnes, aux deuxi-
mes registres de transmission de donnes, et aux
troisimes registres de transmission de donnes.
(44) comprend en outre :
un premier registre (160) destin recevoir une
valeur fixe, un deuxime registre (162) destin
recevoir la premire valeur, et un troisime
registre (164) destin recevoir la deuxime va-
leur, dans lequel le gnrateur de formes donde
(44) est agenc de manire calculer : une nou-
velle valeur pour le premier registre, en ajoutant
une valeur en cours du premier registre une
valeur prcdente gnre en sortie par le
deuxime registre ; une nouvelle valeur pour le
deuxime registre, en ajoutant une valeur en
cours du deuxime registre une valeur prc-
dente gnre en sortie par le troisime
registre ; et une nouvelle valeur pour le troisime
registre, en ajoutant une valeur en cours du troi-
sime registre la troisime valeur.
tion 13, dans lequel la valeur fixe est gale 35555H.
tion 14, dans lequel le modulateur comporte en outre
un oscillateur tension asservie (56), un dtecteur
de phase (58) et un filtre passe-bas (64), dans lequel
le modulateur est un modulateur de modulation de
frquence amplitude constante avec cohrence de
phase, dans lequel la modulation de frquence est
mise en oeuvre en utilisant une boucle verrouillage
de phase, et dans lequel un lment modulant de la
boucle verrouillage de phase correspond un di-
viseur de division par N (60) dans un chemin de r-
troaction allant de loscillateur tension asservie (56)
au dtecteur de phase (58), et le filtre passe-bas (64)
est positionn au niveau dune sortie du dtecteur
de phase (58) en vue de filtrer du bruit haute fr-
quence contenu dans un courant de sortie du dtec-
teur de phase.
tion 15, dans lequel les premires valeurs de dri-
ves prdtermines, les deuximes valeurs de d-
rives prdtermines et les troisimes valeurs de
drives prdtermines tiennent compte des exi-
gences de prdistorsion de la boucle verrouillage
de phase du modulateur.
17. Procd de gnration dune forme donde dans un
dispositif sans fil double mode, comprenant les ta-
pes ci-dessous consistant :
insrer (302, 304, 406) des valeurs de donnes
numriques dans des registres de transmission
de donnes correspondant chacune dune plu-
ralit de sections de sommateurs (132, 136,
140) ;
multiplier (308, 310, 312, 314) des paramtres
correspondant un modulateur (48), dans cha-
que registre dune pluralit de sections de regis-
tres (154, 156, 158), par une unit ou une unit
ngative, en rponse aux valeurs de donnes
numriques insres dans des registres de
transmission de donnes correspondants ;
ajouter (318) des produits rsultant de ltape
de multiplication correspondant chacune de la
pluralit de sections de sommateurs (132, 136,
140) ; et
gnrer en sortie (320) des premires valeurs
de sortie, correspondant chacun des produits
additionns, vers un gnrateur de formes don-
de GSM (44).
18. Procd selon la revendication 17, comprenant en
outre les tapes ci-dessous consistant :
dterminer (322) si la transmission est au dbut
dune salve de trames ;
charger (324) une valeur fixe dans un premier
registre (160) du gnrateur de formes donde
(44), en rponse au fait que la transmission est
au dbut dune salve de trames ;
appliquer (326) les premires valeurs de sortie
au niveau de registres correspondants du g-
nrateur de formes donde (44) ;
gnrer (328) de nouvelles valeurs de sortie, en
ajoutant une valeur en cours dun dernier des
registres et lune prdtermine des premires
valeurs de sortie, et en ajoutant une valeur en
cours de chacun des registres restants une
valeur prcdente dun registre prcdant cor-
respondant des registres ;
gnrer en sortie (330) la nouvelle valeur de sor-
tie gnre par le premier registre, vers un mo-
dulateur (48), et dterminer (332) si une priode
dhorloge prdtermine a pris fin ; et
revenir ltape consistant dterminer (322)
si la transmission est au dbut dune salve de
trames, en rponse au fait que la priode dhor-
loge prdtermine a pris fin, et revenir ltape
de gnration, en rponse au fait que la priode
dhorloge prdtermine na pas pris fin.
31 32
EP 1 287 623 B1
18
EP 1 287 623 B1
19
EP 1 287 623 B1
20
EP 1 287 623 B1
21
EP 1 287 623 B1
22
EP 1 287 623 B1
23
EP 1 287 623 B1
24
EP 1 287 623 B1
25
EP 1 287 623 B1
26
EP 1 287 623 B1
27
REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the readers convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description
US 5151661 A [0010] US 5093632 A [0024]
Non-patent literature cited in the description
An Agile ISM Band Frequency Synthesizer with
Built-In GMSK Data Modulation. NORMAN M FILIOL
E. IEEE Journal of Solid-state Circuits. IEEE, 07 Jan-
uary 1998, vol. 33, 998-1008 [0011]
Low Complexity GSM Modulator for Integrated Circuit
Implementations. BODAS et al. ASIC Conference
and Exhibit. IEEE, 23 September 1996, 103-106
[0012]

TEPZZ - 876 B - T: European Patent Specification

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

TEPZZ - 876 B - T: European Patent Specification

Uploaded by

Copyright:

Available Formats

Note: Within nine months of the publication of the mention of the grant of the European patent in the European

You might also like