Digital Manual - 3rd Sem

SYLLABUS
1. Design and implementation of Adders and Subtractors using logic

gates.
2. Design and implementation of code converters using logic gates
(i) BCD to excess- code and voice versa
(ii) Binar! to gra! and vice-versa
. Design and implementation of " bit binar! Adder# subtractor and
BCD adder using $C %"&
". Design and implementation of 2Bit 'agnitude Comparator using
logic gates & Bit 'agnitude Comparator using $C %"&(
(. Design and implementation of 1) bit odd#even parit! c*ec+er
#generator using $C%"1&,.
). Design and implementation of 'ultiplexer and De-multiplexer using
logic gates and stud! of $C%"1(, and $C %"1("
%. Design and implementation of encoder and decoder using logic
gates and stud! of $C%""( and $C%"1"%
&. Construction and verification of " bit ripple counter and 'od-1, #
'od-12 -ipple counters
.. Design and implementation of -bit s!nc*ronous up#do/n counter
1,. $mplementation of S$S01 S$201 2$S0 and 2$20 s*ift registers using
3lip- flops.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 1
LIST OF EXPERIMENTS
1. Stud! of logic gates.
2. Design and implementation of adders and subtractors using logic
gates.
. Design and implementation of code converters using logic gates.
". Design and implementation of "-bit binar! adder#subtractor and
BCD adder using $C %"&.
5. Design and implementation of 2-bit magnitude comparator
using logic gates1 &-bit magnitude comparator using $C %"&(.
). Design and implementation of 1)-bit odd#even parit! c*ec+er#
generator using $C %"1&,.
%. Design and implementation of multiplexer and demultiplexer
using logic gates and stud! of $C %"1(, and $C %"1(".
&. Design and implementation of encoder and decoder using logic
gates and stud! of $C %""( and $C %"1"%.
.. Construction and verification of "-bit ripple counter and 'od-
1,#'od-12 ripple counter.
1,. Design and implementation of -bit s!nc*ronous up#do/n
counter.
11. $mplementation of S$S01 S$201 2$S0 and 2$20 s*ift
registers using flip-flops.
INDEX
EXP.
NO
DATE NAME OF THE EXPERIMENT PAGE
NO
MARKS SIGNATURE
EXPT NO. : T!D" O# LO$IC $%TE
D%TE :
%IM:
To study about logic gates and verify their truth tables.
%PP%&%T! &E'!I&ED:
T(EO&":
Circuit that takes the logical decision and the process are called logic
gates. Each gate has one or more input and only one output.
OR, A! and OT are basic gates. A!, OR and "#OR are
kno$n as universal gates. %asic gates form these gates.
%ND $%TE:
The A! gate performs a logical multiplication commonly kno$n as
A! function. The output is high $hen both the inputs are high. The output
is lo$ level $hen any one of the inputs is lo$.
&' o. CO()OET &)EC*+*CAT*O ,T-
.. A! /ATE *C 0123 .
4. OR /ATE *C 0154 .
5. OT /ATE *C 0121 .
1. A! /ATE 4 *6) *C 0122 .
5. OR /ATE *C 0124 .
7. "#OR /ATE *C 0137 .
0. A! /ATE 5 *6) *C 01.2 .
3. *C TRA*ER 8*T # .
9. )ATC: COR! # .1
O& $%TE:
The OR gate performs a logical addition commonly kno$n as OR
function. The output is high $hen any one of the inputs is high. The output
is lo$ level $hen both the inputs are lo$.
NOT $%TE:
The OT gate is called an inverter. The output is high $hen the
input is lo$. The output is lo$ $hen the input is high.
N%ND $%TE:
The A! gate is a contraction of A!#OT. The output is high
$hen both inputs are lo$ and any one of the input is lo$ .The output is lo$
level $hen both inputs are high.
NO& $%TE:
The OR gate is a contraction of OR#OT. The output is high $hen
both inputs are lo$. The output is lo$ $hen one or both inputs are high.
X-O& $%TE:
The output is high $hen any one of the inputs is high. The output is
lo$ $hen both the inputs are lo$ and both the inputs are high.
P&OCED!&E:
;i< Connections are given as per circuit diagram.
;ii< 'ogical inputs are given as per circuit diagram.
;iii< Observe the output and verify the truth table.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. )
%ND $%TE:
"M*OL: PIN DI%$&%M:
O& $%TE:
NOT $%TE:
"M*OL: PIN DI%$&%M:
X-O& $%TE :
"M*OL : PIN DI%$&%M :
2-INP!T N%ND $%TE:
"M*OL: PIN DI%$&%M:
3-INP!T N%ND $%TE :
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. +
NO& $%TE:
&E!LT:
EXPT NO. : DEI$N O# %DDE& %ND !*T&%CTO&
D%TE :
%IM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.
%PP%&%T! &E'!I&ED:
&l.o. CO()OET &)EC*+*CAT*O ,T-.
.. A! /ATE *C 0123 .
4. "#OR /ATE *C 0137 .
5. OT /ATE *C 0121 .
1. OR /ATE *C 0154 .
5. *C TRA*ER 8*T # .
1. )ATC: COR!& # 45
T(EO&":
(%L# %DDE&:
A half adder has t$o inputs for the t$o bits to be added and t$o
outputs one from the sum = &> and other from the carry = c> into the higher
adder position. Above circuit is called as a carry signal from the addition of
the less significant bits sum from the "#OR /ate the carry out from the
A! gate.
#!LL %DDE&:
A full adder is a combinational circuit that forms the arithmetic sum of
input? it consists of three inputs and t$o outputs. A full adder is useful to add
three bits at a time but a half adder cannot do so. *n full adder sum output
$ill be taken from "#OR /ate, carry output $ill be taken from OR /ate.
(%L# !*T&%CTO&:
The half subtractor is constructed using "#OR and A! /ate. The
half subtractor has t$o input and t$o outputs. The outputs are difference and
borro$. The difference can be applied using "#OR /ate, borro$ output can
be implemented using an A! /ate and an inverter.
#!LL !*T&%CTO&:
The full subtractor is a combination of "#OR, A!, OR, OT /ates.
*n a full subtractor the logic circuit should have three inputs and t$o outputs.
The t$o half subtractor put together gives a full subtractor .The first half
subtractor $ill be C and A %. The output $ill be difference output of full
subtractor. The e@pression A% assembles the borro$ output of the half
subtractor and the second term is the inverted difference output of first "#
OR.
LO$IC DI%$&%M:
(%L# %DDE&
T&!T( T%*LE:
% * C%&&" !M
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
,-Ma- .o/ !M: ,-Ma- .o/ C%&&":
!M 0 %1* 2 %*1 C%&&" 0 %*
LO$IC DI%$&%M:
#!LL %DDE&
#!LL %DDE& !IN$ T3O (%L# %DDE&
T&!T( T%*LE:
% * C C%&&" !M
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
,-Ma- .o/ !M:
!M 0 %1*1C 2 %1*C1 2 %*C1 2 %*C
,-Ma- .o/ C%&&":
C%&&" 0 %* 2 *C 2 %C
LO$IC DI%$&%M:
(%L# !*T&%CTO&
T&!T( T%*LE:
% * *O&&O3 DI##E&ENCE
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
0
,-Ma- .o/ DI##E&ENCE:

DI##E&ENCE 0 %1* 2 %*1
,-Ma- .o/ *O&&O3:
*O&&O3 0 %1*
LO$IC DI%$&%M:
#!LL !*T&%CTO&
#!LL !*T&%CTO& !IN$ T3O (%L# !*T&%CTO&:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 1)
T&!T( T%*LE:
% * C *O&&O3 DI##E&ENCE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
,-Ma- .o/ D4..e/en5e:
D4..e/en5e 0 %1*1C 2 %1*C1 2 %*1C1 2 %*C
,-Ma- .o/ *o//o6:
*o//o6 0 %1* 2 *C 2 %1C
P&OCEED!&E:
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# CODE CONVE&TO&
%IM:
To design and implement 1#bit
;i< %inary to gray code converter
;ii< /ray to binary code converter
;iii< %C! to e@cess#5 code converter
;iv< E@cess#5 to %C! code converter
%PP%&%T! &E'!I&ED:
.. "#OR /ATE *C 0137 .
4. A! /ATE *C 0123 .
5. OR /ATE *C 0154 .
1. OT /ATE *C 0121 .
5. *C TRA*ER 8*T # .
7. )ATC: COR!& # 55
T(EO&":
The availability of large variety of codes for the same discrete
elements of information results in the use of different codes by different
systems. A conversion circuit must be inserted bet$een the t$o systems if
each uses different codes for same information. Thus, code converter is a
circuit that makes the t$o systems compatible even though each uses
different binary code.
The bit combination assigned to binary code to gray code. &ince each
code uses four bits to represent a decimal digit. There are four inputs and
four outputs. /ray code is a non#$eighted code.
The input variable are designated as %5, %4, %., %2 and the output
variables are designated as C5, C4, C., Co. from the truth table,
combinational circuit is designed. The %oolean functions are obtained from
8#(ap for each output variable.
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. 1+
A code converter is a circuit that makes the t$o systems compatible
even though each uses a different binary code. To convert from binary code
to E@cess#5 code, the input lines must supply the bit combination of
elements as specified by code and the output lines generate the
corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A t$o#level logic diagram may be obtained directly from the %oolean
e@pressions derived by the maps. These are various other possibilities for a
logic diagram that implements this circuit. o$ the OR gate $hose output is
CA! has been used to implement partially each of three outputs.
LO$IC DI%$&%M:
*IN%&" TO $&%" CODE CONVE&TO&
,-Ma- .o/ $
3
:
$
3
0 *
3
,-Ma- .o/ $
2
:
,-Ma- .o/ $
1
:
,-Ma- .o/ $
0
:
T&!T( T%*LE:
7 *4na/8 4n-9: 7 $/a8 5o;e o9:-9: 7
*3 *2 *1 *0 $3 $2 $1 $0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
LO$IC DI%$&%M:
$&%" CODE TO *IN%&" CONVE&TO&
,-Ma- .o/ *
3
:
*3 0 $3
,-Ma- .o/ *
2
:
,-Ma- .o/ *
1
:
,-Ma- .o/ *
0
:
T&!T( T%*LE:
7 $/a8 Co;e 7 *4na/8 Co;e 7
$3 $2 $1 $0 *3 *2 *1 *0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
LO$IC DI%$&%M:
*CD TO EXCE-3 CONVE&TO&
,-Ma- .o/ E
3
:
E3 0 *3 2 *2 <*0 2 *1=
,-Ma- .o/ E
2
:
,-Ma- .o/ E
1
:
,-Ma- .o/ E
0
:
T&!T( T%*LE:
7 *CD 4n-9: 7 E>5e?? @ 3 o9:-9: 7
*3 *2 *1 *0 $3 $2 $1 $0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
1
>
>
>
>
>
>
0
1
1
1
1
0
0
0
0
1
>
>
>
>
>
>
1
0
0
1
1
0
0
1
1
0
>
>
>
>
>
>
1
0
1
0
1
0
1
0
1
0
>
>
>
>
>
>
LO$IC DI%$&%M:
EXCE-3 TO *CD CONVE&TO&
,-Ma- .o/ %:
% 0 X1 X2 2 X3 X4 X1
,-Ma- .o/ *:

,-Ma- .o/ C:
,-Ma- .o/ D:
T&!T( T%*LE:
7 E>5e?? @ 3 In-9: 7 *CD O9:-9: 7
*3 *2 *1 *0 $3 $2 $1 $0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
P&OCED!&E:
;i< Connections $ere given as per circuit diagram.
;ii< 'ogical inputs $ere given as per truth table
;iii< Observe the logical output and verify $ith the truth tables.
&E!LT:
EXPT NO. : DEI$N O# 4-*IT %DDE& %ND !*T&%CTO&
D%TE :
%IM:
To design and implement 1#bit adder and subtractor using *C 0135.
%PP%&%T! &E'!I&ED:
.. *C *C 0135 .
4. E"#OR /ATE *C 0137 .
5. OT /ATE *C 0121 .
5. *C TRA*ER 8*T # .
1. )ATC: COR!& # 12
T(EO&":
4 *IT *IN%&" %DDE&:
A binary adder is a digital circuit that produces the arithmetic sum of
t$o binary numbers. *t can be constructed $ith full adders connected in
cascade, $ith the output carry from each full adder connected to the input
carry of ne@t full adder in chain. The augends bits of =A> and the addend bits
of =%> are designated by subscript numbers from right to left, $ith subscript
2 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C
2
and it ripples
through the full adder to the output carry C
1
.
4 *IT *IN%&" !*T&%CTO&:
The circuit for subtracting A#% consists of an adder $ith inverters,
placed bet$een each data input =%> and the corresponding input of full adder.
The input carry C
2
must be eBual to . $hen performing subtraction.
4 *IT *IN%&" %DDE&/!*T&%CTO&:
The addition and subtraction operation can be combined into one
circuit $ith one common binary adder. The mode input ( controls the
operation. Chen (D2, the circuit is adder circuit. Chen (D., it becomes
subtractor.
4 *IT *CD %DDE&:
Consider the arithmetic addition of t$o decimal digits in %C!,
together $ith an input carry from a previous stage. &ince each input digit
does not e@ceed 9, the output sum cannot be greater than .9, the . in the sum
being an input carry. The output of t$o decimal digits must be represented in
%C! and should appear in the form listed in the columns.
A%C! adder that adds 4 %C! digits and produce a sum digit in %C!.
The 4 decimal digits, together $ith the input carry, are first added in the top
1 bit adder to produce the binary sum.
PIN DI%$&%M #O& IC 7483:
LO$IC DI%$&%M:
4-*IT *IN%&" %DDE&
LO$IC DI%$&%M:
4-*IT *IN%&" !*T&%CTO&
LO$IC DI%$&%M:
4-*IT *IN%&" %DDE&/!*T&%CTO&
T&!T( T%*LE:
In-9: Da:a % In-9: Da:a * %;;4:4on 9A:/a5:4on
%4 %3 %2 %1 *4 *3 *2 *1 C 4 3 2 1 * D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
LO$IC DI%$&%M:
*CD %DDE&
, M%P
" 0 4 <3 2 2=
T&!T( T%*LE:
*CD !M C%&&"
4 3 2 1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
P&OCED!&E:
;i< Connections $ere given as per circuit diagram.
;ii< 'ogical inputs $ere given as per truth table
;iii< Observe the logical output and verify $ith the truth tables.
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# M%$NIT!DE
COMP%&%TO&
%IM:
To design and implement
;i< 4 E bit magnitude comparator using basic gates.
;ii< 3 E bit magnitude comparator using *C 0135.
%PP%&%T! &E'!I&ED:
.. A! /ATE *C 0123 4
4. "#OR /ATE *C 0137 .
5. OR /ATE *C 0154 .
1. OT /ATE *C 0121 .
5. 1#%*T (A/*TF!E
CO()ARATOR
*C 0135 4
7. *C TRA*ER 8*T # .
0. )ATC: COR!& # 52
T(EO&":
The comparison of t$o numbers is an operator that determine one
number is greater than, less than ;or< eBual to the other number. A magnitude
comparator is a combinational circuit that compares t$o numbers A and %
and determine their relative magnitude. The outcome of the comparator is
specified by three binary variables that indicate $hether AG%, AD% ;or<
AH%.
A D A
5
A
4
A
.
A
2

% D %
5
%
4
%
.
%
2

The eBuality of the t$o numbers and % is displayed in a
combinational circuit designated by the symbol ;AD%<.
This indicates A greater than %, then inspect the relative magnitude of
pairs of significant digits starting from most significant position. A is 2 and
that of % is 2.
Ce have AH%, the seBuential comparison can be e@panded as
AG% D A5%
5
.
A "
5
A
4
%
4
.
A "
5
"
4
A
.
%
.
.
A "
5
"
4
"
.
A
2
%
2
.
AH% D A
5
.
%
5
A "
5
A
4
.
%
4
A "
5
"4A
.
.
%
.
A "
5
"
4
"
.
A
2
.
%
2

The same circuit can be used to compare the relative magnitude of
t$o %C! digits.
Chere, A D % is e@panded as,
A D % D ;A
5
A %
5
< ;A
4
A %
4
< ;A
.
A %
.
< ;A
2
A %
2
<

@
5
@
4
@
.
@
2

LO$IC DI%$&%M:
2 *IT M%$NIT!DE COMP%&%TO&
, M%P
T&!T( T%*LE
%1 %0 *1 *0 % B * % 0 * % C *
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
PIN DI%$&%M #O& IC 7485:
LO$IC DI%$&%M:
8 *IT M%$NIT!DE COMP%&%TO&
T&!T( T%*LE:
% * %B* %0* %C*
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
1) *IT ODD/EVEN P%&IT" C(EC,E& /$ENE&%TO&
%IM:
To design and implement .7 bit odd6even parity checker generator
using *C 01.32.
%PP%&%T! &E'!I&ED:
.. OT /ATE *C 0121 .
.. *C 01.32 4
4. *C TRA*ER 8*T # .
5. )ATC: COR!& # 52
T(EO&":
A parity bit is used for detecting errors during transmission of binary
information. A parity bit is an e@tra bit included $ith a binary message to
make the number is either even or odd. The message including the parity bit
is transmitted and then checked at the receiver ends for errors. An error is
detected if the checked parity bit doesn>t correspond to the one transmitted.
The circuit that generates the parity bit in the transmitter is called a =parity
generator> and the circuit that checks the parity in the receiver is called a
=parity checker>.
*n even parity, the added parity bit $ill make the total number is even
amount. *n odd parity, the added parity bit $ill make the total number is odd
amount. The parity checker circuit checks for possible errors in the
transmission. *f the information is passed in even parity, then the bits
reBuired must have an even number of .>s. An error occur during
transmission, if the received bits have an odd number of .>s indicating that
one bit has changed in value during transmission.
PIN DI%$&%M #O& IC 74180:
#!NCTION T%*LE:
INP!T O!TP!T
N9DAe/ o. (4gE Da:a
In-9:? <I0 @ I7=
PE PO FE IO
EVEN 1 0 1 0
ODD 1 0 0 1
EVEN 0 1 0 1
ODD 0 1 1 0
X 1 1 0 0
X 0 0 1 1
LO$IC DI%$&%M:
1) *IT ODD/EVEN P%&IT" C(EC,E&
T&!T( T%*LE:
I7 I) I5 I4 I3 I2 I1 I0 I71I)1I51I41I31I21111 I01 %5:4ve FE FO
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1
LO$IC DI%$&%M:
1) *IT ODD/EVEN P%&IT" $ENE&%TO&
T&!T( T%*LE:
I7 I) I5 I4 I3 I2 I1 I0 I7 I) I5 I4 I3 I2 I1 I0 %5:4ve FE FO
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1
1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# M!LTIPLEXE& %ND
DEM!LTIPLEXE&
%IM:
To design and implement multiple@er and demultiple@er using logic
gates and study of *C 01.52 and *C 01.51.
%PP%&%T! &E'!I&ED:
.. 5 *6) A! /ATE *C 01.. 4
4. OR /ATE *C 0154 .
5. OT /ATE *C 0121 .
4. *C TRA*ER 8*T # .
5. )ATC: COR!& # 54
T(EO&":
M!LTIPLEXE&:
(ultiple@er means transmitting a large number of information units
over a smaller number of channels or lines. A digital multiple@er is a
combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The selection of a particular input
line is controlled by a set of selection lines. ormally there are 4
n
input line
and n selection lines $hose bit combination determine $hich input is
selected.
DEM!LTIPLEXE&:
The function of !emultiple@er is in contrast to multiple@er function. *t
takes information from one line and distributes it to a given number of
output lines. +or this reason, the demultiple@er is also kno$n as a data
distributor. !ecoder can also be used as demultiple@er.
*n the .J 1 demultiple@er circuit, the data input line goes to all of the
A! gates. The data select lines enable only one gate at a time and the data
on the data input line $ill pass through the selected gate to the associated
data output line.
*LOC, DI%$&%M #O& 4:1 M!LTIPLEXE&:
#!NCTION T%*LE:
1 0 INP!T "
0 0 D0 G D0 11 01
0 1 D1 G D1 11 0
1 0 D2 G D2 1 01
1 1 D3 G D3 1 0
" 0 D0 11 01 2 D1 11 0 2 D2 1 01 2 D3 1 0
CI&C!IT DI%$&%M #O& M!LTIPLEXE&:
T&!T( T%*LE:
1 0 " 0 O!TP!T
0 0 D0
0 1 D1
1 0 D2
1 1 D3
*LOC, DI%$&%M #O& 1:4 DEM!LTIPLEXE&:
#!NCTION T%*LE:
1 0 INP!T
0 0 X G D0 0 X 11 01
0 1 X G D1 0 X 11 0
1 0 X G D2 0 X 1 01
1 1 X G D3 0 X 1 0
" 0 X 11 01 2 X 11 0 2 X 1 01 2 X 1 0
LO$IC DI%$&%M #O& DEM!LTIPLEXE&:
T&!T( T%*LE:
INP!T O!TP!T
1 0 I/P D0 D1 D2 D3
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. )0
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
PIN DI%$&%M #O& IC 74150:

PIN DI%$&%M #O& IC 74154:
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# ENCODE& %ND DECODE&
%IM:
To design and implement encoder and decoder using logic gates and
study of *C 0115 and *C 01.10.
%PP%&%T! &E'!I&ED:
.. 5 *6) A! /ATE *C 01.2 4
4. OR /ATE *C 0154 5
5. OT /ATE *C 0121 .
4. *C TRA*ER 8*T # .
5. )ATC: COR!& # 40
T(EO&":
ENCODE&:
An encoder is a digital circuit that perform inverse operation of a
decoder. An encoder has 4
n
input lines and n output lines. *n encoder the
output lines generates the binary code corresponding to the input value. *n
octal to binary encoder it has eight inputs, one for each octal digit and three
output that generate the corresponding binary code. *n encoder it is assumed
that only one input has a value of one at any given time other$ise the circuit
is meaningless. *t has an ambiguila that $hen all inputs are Kero the outputs
are Kero. The Kero outputs can also be generated $hen !2 D ..
DECODE&:
A decoder is a multiple input multiple output logic circuit $hich
converts coded input into coded output $here input and output codes are
different. The input code generally has fe$er bits than the output code. Each
input code $ord produces a different output code $ord i.e there is one to one
mapping can be e@pressed in truth table. *n the block diagram of decoder
circuit the encoded information is present as n input producing 4
n
possible
outputs. 4
n
output values are from 2 through out 4
n
E ..
PIN DI%$&%M #O& IC 7445:
*CD TO DECIM%L DECODE&:
PIN DI%$&%M #O& IC 74147:
LO$IC DI%$&%M #O& ENCODE&:
T&!T( T%*LE:
INP!T O!TP!T
"1 "2 "3 "4 "5 ") "7 % * C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
LO$IC DI%$&%M #O& DECODE&:
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. ))
T&!T( T%*LE:
INP!T O!TP!T
E % * D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
CONT&!CTION %ND VE&I#IC%TION O# 4 *IT &IPPLE
CO!NTE& %ND MOD 10/MOD 12 &IPPLE CO!NTE&
%IM:
To design and verify 1 bit ripple counter mod .26 mod .4 ripple
counter.
%PP%&%T! &E'!I&ED:
.. L8 +'*) +'O) *C 0107 4
4. A! /ATE *C 0122 .
5. *C TRA*ER 8*T # .
1. )ATC: COR!& # 52
T(EO&":
A counter is a register capable of counting number of clock pulse
arriving at its clock input. Counter represents the number of clock pulses
arrived. A specified seBuence of states appears as counter output. This is the
main difference bet$een a register and a counter. There are t$o types of
counter, synchronous and asynchronous. *n synchronous common clock is
given to all flip flop and in asynchronous first flip flop is clocked by e@ternal
pulse and then each successive flip flop is clocked by , or , output of
previous stage. A soon the clock of second stage is triggered by output of
first stage. %ecause of inherent propagation delay time all flip flops are not
activated at same time $hich results in asynchronous operation.
PIN DI%$&%M #O& IC 747):
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. )+
LO$IC DI%$&%M #O& 4 *IT &IPPLE CO!NTE&:
T&!T( T%*LE:
CL, '% '* 'C 'D
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
) 0 1 1 0
7 1 1 1 0
8 0 0 0 1
+ 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 1 1
13 1 0 1 1
14 0 1 1 1
15 1 1 1 1
LO$IC DI%$&%M #O& MOD - 10 &IPPLE CO!NTE&:
T&!T( T%*LE:
CL, '% '* 'C 'D
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
) 0 1 1 0
7 1 1 1 0
8 0 0 0 1
+ 1 0 0 1
10 0 0 0 0
LO$IC DI%$&%M #O& MOD - 12 &IPPLE CO!NTE&:
T&!T( T%*LE:
CL, '% '* 'C 'D
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
) 0 1 1 0
7 1 1 1 0
8 0 0 0 1
+ 1 0 0 1
10 0 1 0 1
11 1 1 0 1
12 0 0 0 0
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# 3 *IT "NC(&ONO!
!P/DO3N CO!NTE&
%IM:
To design and implement 5 bit synchronous up6do$n counter.
%PP%&%T! &E'!I&ED:
.. L8 +'*) +'O) *C 0107 4
4. 5 *6) A! /ATE *C 01.. .
5. OR /ATE *C 0154 .
1. "OR /ATE *C 0137 .
5. OT /ATE *C 0121 .
7. *C TRA*ER 8*T # .
0. )ATC: COR!& # 55
T(EO&":
A counter is a register capable of counting number of clock pulse
arriving at its clock input. Counter represents the number of clock pulses
arrived. An up6do$n counter is one that is capable of progressing in
increasing order or decreasing order through a certain seBuence. An up6do$n
counter is also called bidirectional counter. Fsually up6do$n operation of the
counter is controlled by up6do$n signal. Chen this signal is high counter
goes through up seBuence and $hen up6do$n signal is lo$ counter follo$s
reverse seBuence.
, M%P
T%TE DI%$&%M:
C(%&%CTE&ITIC T%*LE:
' '
:21
H ,
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
LO$IC DI%$&%M:
T&!T( T%*LE:
In-9:
!-/Do6n
P/e?en: :a:e
'
%
'
*
'
C
Ne>: :a:e
'
%21
'
*21
'
C21
%
H
%
,
%
*
H
*
,
*
C
H
C
,
C
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X 1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1
P&OCED!&E:
&E!LT:
EXPT NO. :
D%TE :
DEI$N %ND IMPLEMENT%TION O# (I#T &E$ITE&
%IM:
To design and implement
;i< &erial in serial out
;ii< &erial in parallel out
;iii< )arallel in serial out
;iv< )arallel in parallel out
%PP%&%T! &E'!I&ED:
.. ! +'*) +'O) *C 0101 4
4. OR /ATE *C 0154 .
5. *C TRA*ER 8*T # .
1. )ATC: COR!& # 55
T(EO&":
A register is capable of shifting its binary information in one or both
directions is kno$n as shift register. The logical configuration of shift
register consist of a !#+lip flop cascaded $ith output of one flip flop
connected to input of ne@t flip flop. All flip flops receive common clock
pulses $hich causes the shift in the output of the flip flop. The simplest
possible shift register is one that uses only flip flop. The output of a given
flip flop is connected to the input of ne@t flip flop of the register. Each clock
pulse shifts the content of register one bit position to right.
PIN DI%$&%M:
LO$IC DI%$&%M:
E&I%L IN E&I%L O!T:
T&!T( T%*LE:
CL,
e/4aI 4n e/4aI o9:
1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
) X 0
7 X 1
LO$IC DI%$&%M:
E&I%L IN P%&%LLEL O!T:
T&!T( T%*LE:
CL,
D%T%
O!TP!T
'
%
'
*
'
C
'
D
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LO$IC DI%$&%M:
P%&%LLEL IN E&I%L O!T:
T&!T( T%*LE:
CL, '3 '2 '1 '0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1
LO$IC DI%$&%M:
P%&%LLEL IN P%&%LLEL O!T:
T&!T( T%*LE:
CL,
D%T% INP!T O!TP!T
D
%
D
*
D
C
D
D
'
%
'
*
'
C
'
D
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
P&OCED!&E:
&E!LT:
PREPARATORY EXERCISE
1. Study of lo!" #t$%
&. D$%!' #'d !()l$($'t#t!o' of #dd$*% #'d %u+t*#"to*%
u%!' lo!" #t$%
,. D$%!' #'d !()l$($'t#t!o' of "od$ "o'-$*t$*% u%!'
lo!" #t$%
.. D$%!' #'d !()l$($'t#t!o' of ./+!t +!'#*y
#dd$*0%u+t*#"to* #'d BCD #dd$* u%!' IC 1.2,
3. D$%!' #'d !()l$($'t#t!o' of &/+!t (#'!tud$
"o()#*#to* u%!' lo!" #t$%4 2/+!t (#'!tud$ "o()#*#to*
u%!' IC 1.23
5. D$%!' #'d !()l$($'t#t!o' of 15/+!t odd0$-$' )#*!ty
"6$"7$* $'$*#to* u%!' IC 1.128
1. D$%!' #'d !()l$($'t#t!o' of (ult!)l$9$* #'d
d$(ult!)l$9$* u%!' lo!" #t$% #'d %tudy of IC 1.138 #'d
IC 1.13.
2. D$%!' #'d !()l$($'t#t!o' of $'"od$* #'d d$"od$*
u%!' lo!" #t$% #'d %tudy of IC 1..3 #'d IC 1.1.1
2007-08/Even/IV/ECE/EC1258/DE/LM Page No. +0
:. Co'%t*u"t!o' #'d -$*!f!"#t!o' of ./+!t *!))l$ "ou't$* #'d
Mod/180Mod/1& *!))l$ "ou't$*
18. D$%!' #'d !()l$($'t#t!o' of ,/+!t %y'"6*o'ou%
u)0do;' "ou't$*
11. I()l$($'t#t!o' of SISO4 SIPO4 PISO #'d PIPO %6!ft
*$!%t$*% u%!' fl!)/flo)%

Digital Manual - 3rd Sem

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Digital Manual - 3rd Sem

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SYLLABUS

1. Design and implementation of Adders and Subtractors using logic

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