High Frequency Link Inverters and Multiresonant Controllers

High Frequency Link Inverters and
Multiresonant Controllers
A Thesis
Submitted for the Degree of
Doctor of Philosophy
In the Faculty of Engineering
By
DIPANKAR DE
Department of Electrical Engineering

Indian Institute of Science
Bangalore - 560 012
India
October 2010
In
The Memory of
My Beloved
Grandfather
Late Sisir Kumar Sil
and
Grandmother
Late Rajlaxshmi Sil
Acknowledgements
I sincerely thank my guide Prof. V. Ramanarayanan for accepting me as his research student.
I am deeply indebted to him for his guidance, encouragement, and financial support provided
to me during my research period. I thank him for giving me several opportunities to interact
with industries namely, L & T (Bangalore), Glastronix (Bangalore), Electrotherm (Ahmadabad), Electrohms (Bangalore), C-DAC (Thiruvananthapuram). I am sure that there must
be his silent influence on rest of my life.
It is an opportunity for me to thank Prof. V. T. Ranganathan for all that I have learnt
from him. I had never before experienced teaching so clear, inspiring and interesting as he
used to do. My heart-full thank to him for the course on advanced AC Drives.
It is my privilege to thank Prof. Udaya Kumar for his excellent courses on Electromagnetics and computational methods for Electrostatics which help me to think these subjects from a different point of view.
I like to thank Dr. V. John, Prof. G. Narayanan, Prof. Gopakumar (CEDT), Prof. L.
Umanand (CEDT), Dr. M. K. Gunashekaran (CEDT) and Dr. Kuruvilla (CEDT) for their
advice and suggestions.
I thank Dr. D. Panda, Dr. G. Venkataraman and Mr. M. Bhandari for their financial
support to me for attending IECON-2009 conference.
I gratefully acknowledge the IISc administration for providing excellent hostel and mess
facilities.
I thank Mr. Channegowda and other office staff members, Mrs. Silvi Jose, Mr. J. R.
Raju and other members of Newtech Systems for their co-operations. Special thanks to Mr.
Paul for providing valuable technical information during my research work.
The encouragement and support provided by the Chairman, Department of Electrical
Engineering in absence of my guide are deeply acknowledged.
i
ii
Acknowledgements
I enjoyed working with Chaitanya, Nilanjan, Bhukia, Sravan, Pandey, Modi, Raghava,
Sourabh, Tripathi, Vijay, Amith Karanath, Anusyutha, Kamalesh, Anirban, Soumitra, Amit,
Sivaprasad, Anirudh, Sugantha, Pavan, Nimesh, Binoj, Arun, Dinesh, Parikshit, Karuppuswamy, Srinath, and Debasish. I thank them all for creating a healthy atmosphere in the
lab. I shall never forget the indescribable and joyful experiances during the four PEG tours
organized by us. I thank all other PEG members and my friends Hindol and Kaushik.
I would have not reached this stage without the restless support and limitless patience of
my family members. I am grateful to my parents, sister and brother for their encouragement
and well wishes for my research work.
Abstract
High frequency link power converters for DC 3 AC applications are investigated. Low
cost, reduced size, galvanic isolation and efficient large boosting of voltage level are the key
motivations behind the selection of such topologies. This thesis proposes high frequency
link 3 inverters for three wire and four wire systems. The proposed topologies have the
simplest power circuit configuration and commutation requirements among all high frequency
link topologies reported in the literature. A full load efficiency greater than 90% is achieved
with a passive snubber.
The effect of various circuit non-idealities are common and important for desirable performances of these topologies. A few such issues are highlighted. Firstly, the special commutation requirement of the power circuit causes a non-linear distortion in the output voltages
and thus makes the gain of the power converter time varying. A simple compensation technique is adopted to mitigate the problem. Secondly, the high frequency transformer should
operate with only switching frequency component. However, in the practical situations a
significant amount of low frequency component gets injected into the transformer and results
in peaky transformer magnetizing current unless it is over designed. A suitable measure is
incorporated in the proposed topologies to achieve a magnetic protection.
The power circuit topology is used as stand-by AC power supply. These are of interest
for Uninterruptible Power Supply (UPS) and Micro-grid applications. One of the main
objectives of such supplies is to provide a high quality and highly reliable power to the
connected loads. A voltage regulation loop based on proportional + multiresonant controller
is proposed to achieve excellent quality of the output voltage with unbalanced and nonlinear loadings. The factors influencing regulation and stability of the voltage waveform
are identified and necessary modifications are carried out to improve the performance. The
potential of this voltage regulation loop along with P/Q droop technique and a simple
iii
iv
Abstract
resistive virtual output impedance loop is exploited to achieve decentralized paralleling of

inverters. A trade off between the output voltage power quality and the sharing accuracy
is examined. The total harmonic distortion and degree of unbalance in the output voltage
waveform are experimentally measured well below the specified limit for stand alone AC
supplies with an excellent sharing accuracy.
Some of the grid interactive modes are addressed for the completeness of the work. A
shunt compensator system and a double conversion system based on the same high frequency
link converter are experimentally evaluated. These systems can find their application in UPS
systems. A few important observations on the power circuit performances are indicated.
Contents
Acknowledgements
Abstract
iii
List of Tables
ix
List of Figures
xi
Nomenclature
xxi
1 Introduction
1.1
Scope of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 State of the Art
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
High Frequency Power Converter Topologies . . . . . . . . . . . . . . . . . .
2.2.1
Modulation before Isolation . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Modulation after Isolation . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Extension to DC 3 AC Power Conversion . . . . . . . . . . . . . . . . . .
11
2.4
High Frequency Transformer Design . . . . . . . . . . . . . . . . . . . . . . .
13
2.5
Review of Voltage Regulation Loop for Stand-by AC Power Supplies . . . . .
14
2.6
Review of Paralleling Techniques . . . . . . . . . . . . . . . . . . . . . . . .
16
2.6.1
Basic Principles of Decentralized Paralleling . . . . . . . . . . . . . .
16
2.6.2
General Structure of the Controller for Decentralized Paralleling . . .
18
vi
Contents
2.7
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 High Frequency Link Converter and Associated Issues
19
21
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
3.2
The Proposed DC 3 AC High Frequency Link Converter . . . . . . . . .
21
3.2.1
The Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
3.2.2
Extension to 3-phase 4-wire Case . . . . . . . . . . . . . . . . . . . .
23
3.2.3
Commutation Requirements . . . . . . . . . . . . . . . . . . . . . . .
24
3.2.4
Illustration on Zero Sequence Current Path
. . . . . . . . . . . . . .
24
Non-linear Distortion in the Output Voltages . . . . . . . . . . . . . . . . . .
26
3.3.1
Calculation of Open Loop Converter Gain . . . . . . . . . . . . . . .
27
3.3.2
Experimental Verifications . . . . . . . . . . . . . . . . . . . . . . . .
33
Improved Utilization of High Frequency Transformer . . . . . . . . . . . . .
35
3.4.1
Control over the Magnetizing Current . . . . . . . . . . . . . . . . . .
37
3.4.2
Selection of High Frequency Transformer . . . . . . . . . . . . . . . .
40
3.4.3
Characterization of HF Transformer . . . . . . . . . . . . . . . . . . .
40
3.4.4
Modelling of the High Frequency Transformer . . . . . . . . . . . . .
43
3.4.5
Effect of Various Circuit Parameters . . . . . . . . . . . . . . . . . .
44
3.4.6
Closed Loop Solution . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.4.7
Controller Design and On Line Tuning . . . . . . . . . . . . . . . . .
47
3.4.8
Experimental Investigation . . . . . . . . . . . . . . . . . . . . . . . .
49
Active Clamp based Regenerative Snubber . . . . . . . . . . . . . . . . . . .
53
3.5.1
System Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
3.5.2
Inverter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
3.5.3
Rectifier Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
3.5.4
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
3.3
3.4
3.5
3.6
4 Proportional + Multiresonant Controller based Decentralized Parallel Operation
71
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
4.2
Voltage Regulation Loop with Proportional + Resonant Controller . . . . . .
71
4.2.1
72
Inner Current Loop and Damping of Resonance Oscillation . . . . . .
vii
Contents
4.2.2
4.3
4.4
Outer Voltage Loop and Stability Analysis . . . . . . . . . . . . . . .
73
Proportional + Multiresonant Controller and Stability Issues . . . . . . . . .
75
4.3.1
Extension to Non-linear Loads . . . . . . . . . . . . . . . . . . . . . .
75
4.3.2
Proposed Control Scheme . . . . . . . . . . . . . . . . . . . . . . . .
76
4.3.3
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
Decentralized Parallel Operation . . . . . . . . . . . . . . . . . . . . . . . . .
83
4.4.1
The Proposed Control Structure . . . . . . . . . . . . . . . . . . . . .
84
4.4.1.1
Calculation of P and Q for Each Phase . . . . . . . . . . .
85
4.4.1.2
3 P/Q Droop Characteristics . . . . . . . . . . . . . . . .
87
4.4.1.3
Voltage Reference Generation with Virtual Resistive Output

Impedance Loop . . . . . . . . . . . . . . . . . . . . . . . .
4.4.1.4
Proportional + Multiresonant Controller Based Voltage Regulation Loop . . . . . . . . . . . . . . . . . . . . . . . . . .
88
Start up PLL . . . . . . . . . . . . . . . . . . . . . . . . . .
89
Controller Design and Parameter Selection . . . . . . . . . . . . . . .
90
4.4.2.1
Inner Voltage Regulation Loop . . . . . . . . . . . . . . . .
90
4.4.2.2
Virtual Resistive Output Impedance Loop . . . . . . . . . .
92
4.4.2.3
Outer P/Q Sharing Loop . . . . . . . . . . . . . . . . . . .
95
4.4.3
Simulation Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . .
97
4.4.4
Experimental Evaluation . . . . . . . . . . . . . . . . . . . . . . . . .
98
4.4.1.5
4.4.2
4.5
88
4.4.4.1
Steady State Performance . . . . . . . . . . . . . . . . . . . 100
4.4.4.2
Transient Performance with Start Up PLL . . . . . . . . . . 103
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5 Grid Interactive Modes
107
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.2
Active Shunt Compensator System . . . . . . . . . . . . . . . . . . . . . . . 107

5.2.1
5.2.2
Structure and Design of the PLL . . . . . . . . . . . . . . . . . . . . 108

5.2.1.1
SRF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.2.1.2
Resonant Filter Based PLL . . . . . . . . . . . . . . . . . . 109
5.2.1.3
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . 110
5.2.1.4
Performance Comparison with LPF based PLL . . . . . . . 113
Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . . . 114
viii
Contents
5.2.3
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.2.3.1
Steady State Performance of the Power Converter under Balanced Grid Condition . . . . . . . . . . . . . . . . . . . . . 123
5.2.3.2
5.3
Double Conversion UPS System . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.3.1
The Proposed Structure . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.2
Transformer Construction . . . . . . . . . . . . . . . . . . . . . . . . 129
5.3.3
Closed Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.3.4
5.4
Transient Performance under Grid Voltage Unbalance . . . . 123
5.3.3.1
Load Side Controller . . . . . . . . . . . . . . . . . . . . . . 133
5.3.3.2
Grid Side Controller . . . . . . . . . . . . . . . . . . . . . . 133
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6 Conclusions
139
6.1
Summary of the Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.2
Scope of Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
A Protection for High Frequency Link Converter
143
A.1 HF Link Current based Protection . . . . . . . . . . . . . . . . . . . . . . . 143

A.2 Other Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
B Digital Controller Platform
147
B.1 Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

B.2 Software Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
B.3 Programming the Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
C Photographs of the Test Setup
151
References
157
List of Publications
165
List of Tables
3.1
Power Circuit Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.2
HF Transformer Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4.1
Power and Control Circuit Details . . . . . . . . . . . . . . . . . . . . . . . .
80
4.2
Details of High frequency link 3 4-wire Inverters . . . . . . . . . . . . . . .
85
4.3
Logic relationship between inverter on and . . . . . . . . . . . . . . . .
90
4.4
Controller Parameters and Droop Coefficients . . . . . . . . . . . . . . . . . 100
5.1
Three winding HF Transformer Details . . . . . . . . . . . . . . . . . . . . . 132
ix
List of Tables
List of Figures
2.1
High frequency link topology with modulation in the primary side of the
isolation transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Commutation requirements in the primary side . . . . . . . . . . . . . . . .
2.3
Commutation requirements in the secondary side . . . . . . . . . . . . . . .
2.4
Commutation requirements for the topology in Fig. 2.1 . . . . . . . . . . . .
2.5
Topology derivation [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
High frequency link topology with modulation in the secondary side of the
isolation transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7
Commutation requirements for the topology in Fig. 2.6 . . . . . . . . . . . .
10
2.8
DC to three phase AC high frequency link topology I . . . . . . . . . . . .
12
2.9
DC to three phase AC high frequency link topology II . . . . . . . . . . . .
12
2.10 Effect of interleaved winding and mmf plot . . . . . . . . . . . . . . . . . . .
13
2.11 1 equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.12 Single voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.13 Multi-loop with inner current loop . . . . . . . . . . . . . . . . . . . . . . . .
15
2.14 Communication based paralleling technique . . . . . . . . . . . . . . . . . .
16
2.15 Equivalent circuit of an inverter connected to a load bus . . . . . . . . . . .
16
2.16 Equivalent circuit of two parallel connected inverters . . . . . . . . . . . . .
17
2.17 General block diagram of the controller for decentralized paralleling [25] . . .
18
3.1
Proposed DC to three phase AC high frequency link topology . . . . . . . .
22
3.2
Proposed three phase four wire high frequency link converter . . . . . . . . .
23
3.3
Sample waveform to describe commutation requirements . . . . . . . . . . .
25
3.4
Path of zero sequence current in a simplified case (only R phase is loaded) .
26
xi
xii
List of Figures
3.5
The sample waveforms to illustrate zero voltage distortion problem . . . . .
3.6
Compensation in modulation signal for saw-tooth carrier, left : actual modu-
27
lating signal k (dotted), compensation 4k (firm), right : modified modulating

signal k + 4k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
29
Uncompensated (THD = 6.9%) and compensated (THD = 0.4%) pole voltage

averaged over switching cycle for saw-tooth carrier . . . . . . . . . . . . . . .
29
3.8
Triangular carrier with V link . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.9
Compensation in modulation signal for triangular carrier, left : actual modulating signal k (dotted), compensation 4k (firm), right : modified modulating
signal k + 4k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.10 Uncompensated (THD = 6.2%) and compensated (THD = 0.4%) pole voltage
averaged over switching cycle for triangular carrier . . . . . . . . . . . . . . .
31
3.11 Saw tooth carrier (p = 2) with V link . . . . . . . . . . . . . . . . . . . . . .
31
3.12 Compensation in modulation signal for saw-tooth carrier with p = 2, left :

actual modulating signal k (dotted), compensation 4k (firm), right : modified
modulating signal k + 4k . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.13 Uncompensated (THD = 3.6%) and compensated (THD = 0.3%) pole voltage
averaged over switching cycle for saw-tooth carrier (p = 2) . . . . . . . . . .
32
3.14 Measured voltage of V link, CH1 : 100V/div, time : 20sec/div . . . . . . .
34
3.15 hVRO iTs without compensation, CH1 : 100V/div, time : 10msec/div . . . . .
35
3.16 Fourier spectrum of hVRO iTs in Fig. 3.15: THD = 13.2% . . . . . . . . . . .
35
3.17 hVRO iTs with compensation, CH1 : 100V/div, time : 10msec/div . . . . . . .
36
3.18 Fourier spectrum of hVRO iTs in Fig. 3.17: THD = 6.1% . . . . . . . . . . . .
36
3.19 Commutation requirements with base comparison line M . . . . . . . . . . .
38
3.20 Sample waveform to describe the effect of different position of M on Im . . .
39
3.21 An approximate equivalent circuit of the transformer at 20kHz: Lm =1.66mH,

RP =0.075, RS =1.2, Llp =1.25H, Lls =20H, Rc =15k . . . . . . . . . .
41
3.22 Setup to characterize the HF transformer . . . . . . . . . . . . . . . . . . . .
41
3.23 Measured voltage (CH1: 50V /div) and current (CH2: 10A/div), time: 10sec/div 42
3.24 Measured m Im curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
3.25 Simulink model of the HF transformer . . . . . . . . . . . . . . . . . . . . .
43
3.26 Simulation result without saturation controller: Im , its filtered value and
zoomed value at certain interval . . . . . . . . . . . . . . . . . . . . . . . . .
46
xiii
List of Figures
3.27 Block diagram of saturation controller . . . . . . . . . . . . . . . . . . . . .
47
3.28 Simulation result with saturation controller: Im , its filtered value and zoomed
value at certain interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
3.29 Comparison of dynamic responses with fixed and on-line varying controller
parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
3.30 Experimental setup with digital controller . . . . . . . . . . . . . . . . . . .
51
3.31 Output 1 voltage: CH1: 100V /div, time: 10msec/div . . . . . . . . . . . .
51
3.32 Effect of various circuit parameters and loading on the magnetizing current and controller response: (a) Filtered Im without saturation controller
(1.2A/div), time: 5msec/div; (b) Controller is activated transiently and filtered Im (1.2A/div), time: 20msec/div; (c) Filtered Im with saturation controller (1.2A/div), time: 5msec/div; (d) Controller performance at turn on
and filtered Im (0.24A/div), time: 2msec/div
. . . . . . . . . . . . . . . . .
52
3.33 DC to three phase AC high frequency link topology with snubber structure-I
(with separate diode bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
3.34 DC to three phase AC high frequency link topology with snubber structure-II
(with a single diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
3.35 DC to three phase AC high frequency link topology with snubber structure-III
(active clamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
3.36 Power circuit with various circuit parameters . . . . . . . . . . . . . . . . . .
55
3.37 Key waveforms in inverter mode with particular AC side current (as in Fig.
3.38 Fig. 3.40)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
3.38 Active equivalent circuits in inverter mode for a particular half switching cycle:
(i) interval 1, (ii) interval 2, (iii) interval 3, (iv) interval 4 . . . . . . . . . . .
57
(v) interval 5, (vi) interval 6, (vii) interval 7, (viii) interval 8 . . . . . . . . .
58
(ix) interval 9, (x) interval 10, (xi) interval 11, (xii) interval 12 . . . . . . . .
59
3.41 Active equivalent circuits in rectifier mode for a particular half switching cycle:
(i) interval 1, (ii) interval 2, (iii) interval 3, (iv) interval 4 . . . . . . . . . . .
64
(v) interval 5, (vi) interval 6, (vii) interval 7, (viii) interval 8 . . . . . . . . .
65
xiv
List of Figures
(ix) interval 9, (x) interval 10, (xi) interval 11, (xii) interval 12 . . . . . . . .
66
3.44 Measured voltage of Vlink without snubber circuit, CH1 : 100V/div, time :
5sec/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
3.45 Measured voltage of vlink with active clamp, CH1 : 100V/div, time : 5sec/div 68
3.46 Measured generated control pulses, CH1 : A (5V/div), CH2 : B (5V/div),
CH3 : Ssn (5V/div), time : 10sec/div . . . . . . . . . . . . . . . . . . . . .
69
3.47 Efficiency comparison of active clamp with passive snubber . . . . . . . . . .
69
4.1
Inner current loop and plant . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
4.2
73
4.4
Root locus plot of current loop . . . . . . . . . . . . . . . . . . . . . . . . .

IL (s)
Bode plot of
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IL (s)
P + resonant controller for fundamental component . . . . . . . . . . . . . .
4.5
P + multi-resonant controller for fundamental and harmonic (5th and 7th )
4.3
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
73
74
75
4.6
Bode plot of voltage loop for different values of Ki5 and Ki7 in
. . . . .
76
4.7
Simulation result: oscillatory output voltage with Ki5 = Ki7 = 4 1 . . . .
77
4.8
Proposed control structure for outer voltage loop . . . . . . . . . . . . . . .
77
4.9
Bode plot of voltage loop for selected values of Ki5 and Ki7 with and without
lead-lag compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
4.10 Simulation result with selected values of Ki5 and Ki7 and lead-lag compensator 78
4.11 Experimental setup with digital controller . . . . . . . . . . . . . . . . . . .
79
4.12 Three phase unbalanced load currents (CH1, CH2, CH3: 3A/div) and zero
sequence current through fourth wire (CH4: 5A/div) Time: 5msec/div . . .
81
4.13 Three phase output voltage under unbalanced loading (CH1, CH2, CH3:
100V /div) Time: 5msec/div . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
4.14 R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with
low values of Ki5 and Ki7 , time: 10msec/div . . . . . . . . . . . . . . . . . .
82
4.15 Fourier spectrum of a-phase output voltage in Fig. 4.14: THD = 6.94% . . .
82
4.16 R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with
Ki5 = Ki7 = 4 1 and without lead-lag compensation, time: 10msec/div
83
4.17 R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with selected values of Ki5 and Ki7 and with lead-lag compensation, time: 10msec/div 83
xv
List of Figures
4.18 Fourier spectrum of R-phase output voltage in Fig. 4.17: THD = 2.88% . . .
84
4.19 Two 3 4-wire inverters in parallel . . . . . . . . . . . . . . . . . . . . . . .
85
4.20 Per phase active and reactive power calculation . . . . . . . . . . . . . . . .
86
4.21 3 droop technique for three-phase four-wire system
86
. . . . . . . . . . . . .
4.22 Reference generation for the output voltage controller with virtual output
impedance loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
4.23 Start up PLL with inverter active status signal . . . . . . . . . . . . . . . . .
87
4.24 Proportional + multiresonant controller based inner voltage regulation loop .
88
4.25 (a) 1 equivalent circuit of the power circuit (b) Inverter equivalent circuit
with the closed loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
91
4.26 Design of the inner voltage loop in z-domain . . . . . . . . . . . . . . . . . .
92
4.27 Closed loop Bode plot of the voltage loop, G(z) . . . . . . . . . . . . . . . .
93
4.28 The output impedance Zo1 with and without tie wire impedance . . . . . . .
94
4.29 Effect of tie wire impedance on Zo1 and Zo2 . . . . . . . . . . . . . . . . . .
95
4.30 Effective output impedance Zo1e with RD1 variation (without considering tie
wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
4.31 Effect of increasing RD on |Zo2e |/|Zo1e | and on the phase difference 4 between Zo1e and a pure resistance at different frequencies . . . . . . . . . . . .
97
4.32 Effect of tie wire impedance on Zo1e and Zo2e . . . . . . . . . . . . . . . . . .
98
4.33 Locus of the pole location of the outer P/Q sharing loop with RD variation .
99
4.34 Simulation result: unbalanced load sharing and the 3 output voltages . . .
99
4.35 Simulation result: harmonics load sharing and the 3 output voltages . . . . 101
4.36 Simulation result: trade off between error in sharing accuracy (ESA), voltage
unbalance ratio (VUR), total harmonic distortion of the output voltage (THD)101
4.37 Sharing of non-linear loads: CH1: a-phase output voltage Vca (180 V/div),
CH2: INV#1 a-phase output current Ioa1 (4 A/div), CH3: INV#2 a-phase
output current Ioa2 (2 A/div), time: 5 ms/div . . . . . . . . . . . . . . . . . 102
4.38 The Fourier spectrum of Vca in Fig. 4.37 . . . . . . . . . . . . . . . . . . . . 102
4.39 Sharing of unbalanced loads: CH1: Ioa1 (2 A/div), CH2: Ioa2 (1 A/div), CH3:
Iob1 (2 A/div), CH4: Iob2 (1 A/div), time: 10 ms/div . . . . . . . . . . . . . 103
4.40 Three phase output voltages with unbalanced loads: CH1: Vca (90 V/div),
CH2: Vcb (90 V/div), CH3: Vcc (90 V/div), time: 10 ms/div . . . . . . . . . 103
xvi
List of Figures
4.41 Experimental result: trade off between error in sharing accuracy (ESA), voltage unbalance ratio (VUR), total harmonic distortion of the output voltage
(THD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.42 Transient turn on of INV#2 when INV#1 is supplying non-linear loads without start up PLL: CH1: INV#1 a-phase inductor current ILa1 (4 A/div), CH2:
INV#2 a-phase inductor current ILa2 (2 A/div), time: 20 ms/div . . . . . . 104
4.43 Transient turn on of INV#2 when INV#1 is supplying non-linear loads with
start up PLL: CH1: INV#1 a-phase inductor current ILa1 (4 A/div), CH2:
INV#2 a-phase inductor current ILa2 (2 A/div), time: 20 ms/div . . . . . . 105
4.44 Transient turn on of INV#2 when INV#1 is supplying unbalanced loads with
start up PLL: CH1: ILa1 (4 A/div), CH2: ILa2 (2 A/div), CH3: ILb1 (4 A/div),
CH4: ILb2 (2 A/div), time: 20 ms/div . . . . . . . . . . . . . . . . . . . . . . 105
4.45 Performance of the inverters with a transient increase in the load current:
CH1: Ioa1 (4 A/div), CH2: Ioa2 (2 A/div), time: 20 ms/div . . . . . . . . . . 106
5.1
Conventional SRF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.2
Stationary and rotating reference frame . . . . . . . . . . . . . . . . . . . . . 109
5.3
SRF PLL with low pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.4
Modified PLL with resonant filter . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5
Overall closed loop form of the PLL . . . . . . . . . . . . . . . . . . . . . . . 111
5.6
Variation of cut and its effect . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.7
Approximation of the resonant filter for controller design . . . . . . . . . . . 112
5.8
Bode plot of the open loop transfer function of the PLL . . . . . . . . . . . . 113
5.9
Simulated results: Transient performance of the LPF based PLL under grid
voltage unbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
5.10 Simulated results: Transient performance of the RF based PLL under grid
voltage unbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.11 Power Circuit of the shunt compensator
. . . . . . . . . . . . . . . . . . . . 116
5.12 Grid voltage transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.13 Resonant Filter based PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.14 Converter current transformation . . . . . . . . . . . . . . . . . . . . . . . . 117
5.15 Load current transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
5.16 Generation of current controller references . . . . . . . . . . . . . . . . . . . 117
List of Figures
xvii
5.17 Proportional + multiresonant current controllers (P + MRC) and reverse

transformation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.18 Performance of the system without resonant filter in the DC voltage feedback
path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.19 Performance of the system with resonant filter in the DC voltage feedback path119
5.20 Bode plot of - and - axis current controller . . . . . . . . . . . . . . . . . 119
5.21 Experimental result of converter turn on transient with unbalanced loads:
CH1, CH2: R- and Y- phase grid current before and after shunt compensator
is turned on (2.4 A/div), time: 20 ms/div . . . . . . . . . . . . . . . . . . . 121
5.22 Experimental result of converter turn on transient with non-linear loads: CH1,
CH2, CH3: 3 grid current before and after shunt compensator is turned on
(6 A/div), time: 20 ms/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.23 Harmonic content in grid current (Fig. 5.22) before turning on the converter
(THD: 32.4%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.24 Harmonic content in grid current (Fig. 5.22) after turning on the converter
(THD: 3.5%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.25 Experimental result of converter turn on transient with reactive loads: CH1:
R-phase grid voltage (80 V/div), CH2: R-phase grid current before and after
shunt compensator is turned on (1.2 A/div), time: 20 ms/div . . . . . . . . . 123
5.26 Experimental arrangement to test the compensator under grid voltage unbalance124
5.27 Experimental transient performance of the proposed PLL with unbalance in
the grid voltage: CH1, CH2: unit vectors sine and cose (5 V/div), CH3:
Vgrn (200 V/div), CH4: Vgbn (200 V/div), time: 10 ms/div . . . . . . . . . . 124
5.28 Experimental transient performance of the proposed PLL with unbalance in
the grid voltage: CH1: D axis grid voltage Vgd (400 V/div), CH2: D axis grid
voltage after resonance filter Vgdf (400 V/div), CH3: estimated frequency e
(250 rad/s/div), CH4: estimated phase angle e (2 rad/div), time: 20 ms/div 125
5.29 Transient load currents with grid voltage unbalance: CH1, CH2, CH3: 3
load currents (6 A/div), time: 20 ms/div . . . . . . . . . . . . . . . . . . . . 125
5.30 Transient converter currents with grid voltage unbalance: CH1, CH2, CH3:
3 converter currents (8 A/div), time: 20 ms/div . . . . . . . . . . . . . . . 126
xviii
List of Figures
5.31 Transient grid currents with grid voltage unbalance: CH1, CH2: R- and Yphase grid currents (6 A/div), CH3: B- phase grid current before voltage
unbalance and current through short circuited path between b and n after
voltage unbalance (6 A/div), time: 20 ms/div . . . . . . . . . . . . . . . . . 126
5.32 Transient DC bus voltage with grid voltage unbalance: CH1, Vdc (24 V/div),
time: 1 s/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.33 General structure of a double conversion UPS system . . . . . . . . . . . . . 128
5.34 Basic DC 3 AC high frequency link topology . . . . . . . . . . . . . . . . 129
5.35 The proposed double conversion system . . . . . . . . . . . . . . . . . . . . . 130
5.36 The interleaved winding structure . . . . . . . . . . . . . . . . . . . . . . . . 131
5.37 Load side controller in synchronously rotating coordinate system . . . . . . . 131
5.38 Grid side controller in synchronously rotating coordinate system . . . . . . . 131
5.39 Block diagram of the experimental set-up . . . . . . . . . . . . . . . . . . . . 134
5.40 Generated unit vectors for grid side control: CH1: sin (2 V/div), CH2: cos
(2 V/div), time: 20 msec/div . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.41 Unity power factor operation in the grid side: CH1: Vgr (160 V/div), CH2:
Igr (2 A/div), time: 10 msec/div
. . . . . . . . . . . . . . . . . . . . . . . . 135
5.42 Three phase output voltages (load side): CH1, CH2, CH3: 90 V/div, time: 5
msec/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.43 CH1: transformer secondary (S2) voltage (500 V/div), CH2: transformer
secondary (S2) current (2 A/div), time: 5 msec/div . . . . . . . . . . . . . . 136
5.44 Zoomed Fig. 5.43: CH1: transformer secondary (S2) voltage (500 V/div),
CH2: transformer secondary (S2) current (2 A/div), time: 20 sec/div . . . 137
A.1 Arrangement of high frequency link current based protection . . . . . . . . . 144
A.2 Protection feature, CH1: enable signal en (10V /div), CH2: high frequency
link current IP (50A/div), time: 10sec/div . . . . . . . . . . . . . . . . . . 145
B.1 The basic structure of the digital controller board . . . . . . . . . . . . . . . 148
C.1 Photograph of the primary side H-bridge (MOSFET based) . . . . . . . . . . 151
C.2 Photograph of the high frequency transformer and the current sensor for protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
C.3 Photograph of the secondary side cycloconverter (IGBT based) . . . . . . . . 152
List of Figures
xix
C.4 Photograph of the FPGA based digital controller board used with interface
card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
C.5 Photograph of the protection, commutation and indicator board [4-layer Printer
Circuit Board (PCB)] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
C.6 Photograph of the two paralleled cycloconverters (with vertical gate driver
cards) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
C.7 Photograph of the entire laboratory set-up . . . . . . . . . . . . . . . . . . . 156
xx
List of Figures
Nomenclature
Symbols
: Definitions
Vdc
: DC bus voltage
Vlink
: Cycloconverter link voltage (or V link/VP N )
Ts
: Switching Period
: Switching Frequency
R, Y , B
B
A, B, A,
: Three phases (or a, b, c)

: H-bridge devices
X, Y
: Synchronous rectifier devices
Sr , Sy , S b
: Output side inverter devices
VP
: Transformer Primary Voltage
VS
: Transformer Secondary Voltage
IP
: Transformer Primary Current
IS
: Transformer Secondary Current
Im
: Magnetizing Current
RP
: Transformer primary resistance
Llp
: Transformer primary leakage inductance
RS
: Transformer secondary resistance
Lls
: Transformer secondary leakage inductance
Rc
: Resistance representing core loss component
Lm
: Transformer magnetizing inductance
Cl
: Cycloconverter side lumped capacitance
Ll
: Total leakage inductance of the transformer
Csn
: Snubber capacitor for the active clamp
: Gain of the converter

xxi
xxii
Nomenclature
Kc
: Current controller proportional gain
Kp
: Voltage controller proportional gain
Ki1
: Voltage controller steady state gain for fundamental
Ki3
: Voltage controller steady state gain for 3rd harmonic
Ki5
: Voltage controller steady state gain for 5th harmonic
Ki7
: Voltage controller steady state gain for 7th harmonic
cut1
: Cut-off frequency for fundamental controller
cut3
: Cut-off frequency for 3rd harmonic controller
cut5
: Cut-off frequency for 5th harmonic controller
cut7
: Cut-off frequency for 7th harmonic controller
: Lead-lag compensator time constant-1
: Lead-lag compensator time constant-2
: Filter inductance
: Filter capacitance
rL
: Resistance of the filter inductance
Pi
: Instantaneous active power
Qi
: Instantaneous reactive power
P3ph
: Positive sequence 3 active power
Q3ph
: Positive sequence 3 reactive power
RD
: Resistive virtual output impedance
: Sampling time
: Droop frequency coefficient
: Droop amplitude coefficient
: Phase angle of the grid voltage
: Angular frequency of the grid voltage
: Estimated phase angle
: Estimated angular frequency
Chapter 1
Introduction
1.1
Scope of the Thesis
Power electronics converters can be broadly classified as DC DC, AC DC, DC AC

and AC AC converters [1]. The focus of the work presented in this thesis is in the DC
AC power conversion area. The stand alone AC power supplies are very well known in
Uninterruptible Power Supply (UPS) systems and in recently emerging Micro-grid systems.
One of the main objectives of such supplies is to provide a high quality and highly reliable
power to the connected loads. Moreover, in certain situations where available DC bus voltage
is limited (low voltage PV cell or battery), a large step up with adequate efficiency is essential.
The thesis deals with a suitable DC - 3 AC converter topology based on high frequency
transformer. A large reduction in size and cost of the isolation transformer can be achieved
due to high frequency operation. The transformer ensures an efficient scale up of the voltage
level. This thesis addresses various disadvantages of the power circuit and attempts to solve
some of them. The high power quality is ensured by output LC filter and associated closed
loop control.
The availability of reliable electric power demands paralleling of power converter units.
Again interconnection between various signals among paralleled units (in a centralized paralleling system) poses a restriction to their individual locations. Hence a decentralized or
communication-less paralleling is more attractive in the above mentioned applications. The
disadvantages of decentralized paralleling technique are poor sharing accuracy due to uncertain tie-wire impedances and degradation of power quality level of the load voltages. A
suitable paralleling scheme (decentralized) for DC AC (3) high frequency link converters
with a trade-off between the sharing accuracy and the load voltage power quality is addressed
1
Chapter 1. Introduction
in this thesis.
Grid paralleling or grid interactive operation is another important aspect in these systems.
A shunt compensator system for both balanced and unbalanced grid voltage conditions is
investigated. Such a compensator can find application in line interactive UPS systems. The
thesis also focuses on a high frequency link based double conversion UPS system.
1.2
Contributions of the Thesis
The important contributions of the thesis are as follows:

Development of DC - 3 AC high frequency link converter with the simplest power
circuit configuration and commutation requirements.
Open loop compensation of non-linear distortion in the output 3 AC voltages (due
to the special commutation requirements of the power converter).
Improved utilization of high frequency transformer with a saturation controller.
Extension of the power circuit to 3 4-wire case to cater to unbalanced loads.
Development of proportional + multiresonant controller for voltage regulation loop to
achieve a high quality output voltages with non-linear loads.
Decentralized paralleling of high frequency link inverters of unequal power ratings with
the voltage regulation loop and a simple virtual resistive output impedance loop for
excellent sharing of all sorts of loads (balanced, unbalanced and harmonics).
Application of the high frequency link power converter as grid connected shunt compensator under both balanced and unbalanced grid voltage conditions.
Implementation of a double conversion UPS system with a three winding high frequency
transformer (no bulky DC link capacitor and easy interfacing of different voltage levels
of the load, grid and battery).
1.3. Organization of the Thesis
1.3
Organization of the Thesis
The work presented in this thesis is organized as follows:

Chapter 2 gives an overview of various high frequency link topologies and discusses about
their relative merits and demerits. The chapter also gives a complete picture of stand alone
AC power supplies with output LC filter. The various conventional closed loop control
techniques are highlighted. Finally, a brief literature survey about parallel operation of
inverters is reported. More importance is given to decentralized paralleling techniques.
Chapter 3 explains in detail the proposed HF link topology for DC 3 AC applications. Detailed description of its principle of operation and commutation requirements are
presented. Due to the commutation requirements of the power circuit a non-linear distortion is observed in the output voltage waveforms. This distortion makes the converter gain
non-linear and time varying. A simple compensation technique is suggested to mitigate the
problem. The high frequency link power converter topology is then extended to 3 four-wire
case by using a center tapped high frequency transformer. The zero sequence current path
is analysed by a simple case study. The final part of the chapter includes the effect of various circuit non-idealities on high frequency transformer and associated poor utilization of
the transformer. A closed loop solution based on magnetizing current feedback is explained
to overcome the problem. The simulation and experimental results for these solutions are
presented.
Chapter 4 presents the concept of proportional + multiresonant controller for voltage
regulation loop. The control structure helps to achieve an excellent output voltage power
quality with unbalanced and non-linear loadings. The stability study of voltage regulation
loop is examined and an addition of a lead-lag compensator to improve relative stability
margins is explained. Next, decentralized parallel operation of two high frequency link
inverters (of unequal ratings) is reported. The decentralized operation is achieved by P/Q
droop technique and the sharing accuracy is improved with a virtual output impedance loop.
The design procedures of various stages of the controller are explained. The simulation and
experimental results from the paralleled inverters are presented.
Chapter 5 describes the grid interactive modes of operation of the high frequency link
converter. A shunt compensator technique is adopted to make grid current harmonics free,
balanced and at unity power factor. The closed loop current control is implemented using
proportional + multiresonant controller highlighted in chapter 4. A resonant filter is used
Chapter 1. Introduction
in the phase locked loop and in the DC voltage controller to make the system suitable for
the unbalanced conditions. Next, a double conversion UPS system with three winding high
frequency transformer is explained. The bulky DC link capacitor is totally eliminated with
the added advantage of isolation between the input and the output and easy interfacing of
different voltage levels of the grid, load and battery. The experimental results are presented.
Chapter 6 summarizes the contributions of the entire work and also presents the scope
for future work.
Chapter 2
State of the Art
2.1
Introduction
Power circuit topologies and their control techniques are under continuous evolution. This
chapter presents a review of high frequency link topology evolution from very basic topologies
to modern fast switching device based topologies. Conventional methods of output voltage
regulation and LC resonance damping and their relative advantages and disadvantages are
discussed. At the end, certain aspects of decentralized paralleling techniques are highlighted
and reviewed. The features of the most desirable converter topology and control strategy
are identified.
2.2
High Frequency Power Converter Topologies
High frequency link power conversion is being widely applied for a variety of power converters in uninterruptible power supply systems, hybrid electric vehicles, renewable energy
processing units, active rectifiers etc. This type of power converters provides galvanic isolation between input and output and a large reduction in size and weight of the isolation
transformer [2, 3]. The reduction in size and cost is achieved due to high frequency operation
of the isolation transformer at the cost of increased number of switching devices and associated losses. As the number of devices is large, there exists a large variety of high frequency
link converter topologies depending upon the position and functionality of the devices. The
high frequency link converters are broadly classified in the following types:
Modulation before isolation
Modulation after isolation
5
Chapter 2. State of the Art
Let us first concentrates on these two configurations with the help of DC DC power
converter topologies. The same power circuit configurations can be easily used for DC 1
AC application by just modifying the commutation techniques.
S1
S3
S2
S4
Figure 2.1: High frequency link topology with modulation in the primary side of the isolation
transformer
A
B
Vp
Vdc
Vdc
Figure 2.2: Commutation requirements in the primary side
2.2.1
Modulation before Isolation
The simplest and oldest high frequency link DC DC topology is shown in Fig. 2.1 [4, 5].
It has a PWM inverter in the primary side of the transformer and a synchronous rectifier or
cycloconverter on the secondary side. Fig. 2.1 shows the realization of the switching devices
for bi-directional power carrying capability. The commutation scheme for the primary side
inverter (H-bridge) and the secondary side synchronous rectifier are shown in Fig. 2.2 and
2.2. High Frequency Power Converter Topologies
Input
r
Output
r
Output
Figure 2.3: Commutation requirements in the secondary side
A
B
S1
S2
S3
S4
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
HBRIDGE
OUTPUT
r
r
11
00
00
11
00
11
11
00
00
11
00
11
0
1
DEADTIME 1
0
OVERLAP 1
0
Figure 2.4: Commutation requirements for the topology in Fig. 2.1
Fig. 2.3 respectively. The H-Bridge is operated with phase modulation technique. The
switching sequences and the output waveforms of the H-Bridge are shown in Fig. 2.2. The
legs of the H-bridge are operated from two independent 50% duty ratio pulses which are
phase shifted from each other. By controlling this phase shift, it is possible to vary the
output from the bridge. The phase shifted pulses A and B control the operation of the
leg containing S1, S2 and the leg containing S3, S4 respectively. On the other hand, the
synchronous rectifier rectifies the transformer output in such a way that it is possible to
apply both positive or negative DC voltage to the load. The output from the synchronous
rectifier depends on the control input r in synchronism with one of the control inputs of
H-bridge (Fig. 2.3). If it is required to apply positive voltage to load then r is same as
A (control input for H-bridge). On the other hand, for negative voltage output r will be
complement of A. The H-bridge is a voltage source inverter (VSI). Therefore, the switches
S1, S2 and S3, S4 ought to have dead-time during their commutation. This is shown in Fig.
2.4. The cycloconverter may be seen as a current source inverter (CSI) and therefore the
switches r and r have to commutate with overlap (Fig. 2.4). The commutation in CSI (zero
voltage switching) are lossless commutation and the associated switching losses are ideally
zero.
The major disadvantage of this topology is the presence of devices of bi-directional voltage blocking capability. This phenomena limits the power density of the system and also
complicates the bus bar configuration in the cycloconverter side. As the modulation is carried
out in the primary side of the transformer the possibility of flux control is lost.
2.2.2
Modulation after Isolation
This power circuit topology can easily be derived from the topology previously described.
If we concentrate only on the cycloconverter at the secondary side of the transformer (Fig.
2.1 is partially redrawn in Fig. 2.5), it consists of devices of bi-directional voltage blocking capability. In order to eliminate the need of devices of bi-directional voltage blocking
capability let us now introduce two extra conducting paths P and N (dotted line in Fig.
2.5(a)) in the cycloconverter side [6]. The load current can now free-wheel through only one
switch and one diode, thus making the free-wheeling conduction loss half. Moreover, this is
achieved without affecting the functionality of the circuit. The modified circuit is redrawn
in Fig. 2.5(b). It is evident that the new topology is not only functionally compatible with
2.2. High Frequency Power Converter Topologies
c
5
1
N
P
2
6
a
b
(a)
P
2
8
c
a
b
3
d
5
(b)
Figure 2.5: Topology derivation [6]
P
Vlink
A
Vp
Vs
Figure 2.6: High frequency link topology with modulation in the secondary side of the
isolation transformer
10
CB
CA
B
Vp
or
Vs
11
00
00
11
00
11
11
00
00
11
00
11
1
0
0
1
0
1
1
0
0
1
0
1
Zero Portion
Y
Overlap
VPN
Figure 2.7: Commutation requirements for the topology in Fig. 2.6

the original cycloconverter but also has similar construction like indirect matrix converter
[7]. The complete power circuit is shown in Fig. 2.6.
The detailed commutation requirements for this topology is shown in Fig. 2.7. The
primary side inverter legs (A and B in Fig. 2.6) are operated at 50% duty ratio with a
small phase shift between them. These gate pulses for A and B are generated from phase
and B
are the compliments of A and B
shifted carrier CA and CB respectively. Again, A
respectively (Fig. 2.7) with small dead time to prevent shoot through of the DC source. The
phase shift between A and B introduces a zero voltage portion in primary (Vp) as well as
secondary (Vs) voltage waveform. The synchronous rectifier switches (X and Y) have small
2.3. Extension to DC 3 AC Power Conversion
11
overlap (shown in Fig. 2.7) to keep current path continuous. Again, this overlap of X and
Y takes place within the zero portion of the secondary voltage (Vs) in order to avoid dead
short circuit of the secondary voltage. The cycloconverter link voltage (Vlink or VP N ) is not
a fixed DC but has some zero portion in it. The next stage is a standard VSI which takes
Vlink as its input and generates the desired output voltage.
2.3
Extension to DC 3 AC Power Conversion
When we consider a DC to three phase system with high frequency isolation, a set of alternate
topologies are feasible. The simple step is to combine three single phase units to form a three
phase unit as shown in Fig. 2.8. Because of full bridge construction the secondary voltage is
small for a particular output line to line voltage requirement. This helps to select a device
of lower voltage rating at the cycloconverter side. Moreover, from circuit operation point of
view it is a simple extension of single phase case. But this circuit topology is not common
because of large device count (36), three separate isolation transformers and high conduction
losses.
Fig. 2.9 shows another DC to three phase AC high frequency link topology which is
widely discussed in the literature [8, 9, 10, 11]. In this topology the primary side inverter
operates in square wave mode and modulation is carried out in the PWM cycloconverter at
the secondary side. The number of switching devices are reduced to 16 in this topology. But
the secondary voltage requirement is higher compared to the previous topology because of
half bridge construction of the cycloconverter. This higher secondary voltage can easily be
achieved by increasing number of turns of the isolation transformer. During the switching
instant of PWM cycloconverter devices, the stored energy in the leakage inductance produces
high voltage spikes across the devices. To mitigate such voltage surge, snubber circuits
are inevitable in such topology. In [10], active voltage clamper was used to reduce the
snubber loss. In [11], the requirement of voltage clamper was eliminated by exploiting
self turning off of devices with naturally commutated phase angle control. However, the
cycloconverter requires device current dependent commutation in order to produce desired
AC output voltage and to maintain continuity in the current path in each phase inductor.
Again, presence of bi-directional voltage blocking devices greatly affects power density of the
system.
In this thesis two modified and simple structures of high frequency link inverter for
12
Figure 2.8: DC to three phase AC high frequency link topology I
R
Y
B
Figure 2.9: DC to three phase AC high frequency link topology II

three-phase three-wire and four-wire systems are proposed. They are explained in the next
chapter.
2.4. High Frequency Transformer Design
2.4
13
High Frequency Transformer Design
The performance of the power circuit deviates from the ideal one because of presence of the
leakage inductance of the isolation transformer. Hence a special attention need to be paid
to the high frequency transformer design. The leakage inductance of any transformer can
be reduced to a great extent by making interleaved transformer winding [12, 13, 14]. Fig.
2.10 shows the core window with and without interleaved winding and corresponding mmf
plots along the length of the core. The peaks of the mmf distribution is significantly reduced
Primary
0
1
1
0
0
1
0
1
0
1
0000
1111
0
1
0000
1111
0
1
0000
1111
0
1
0000
1111
0
1
0000
1111
0
1
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
1111
0000
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
Secondary
1111
0000
0000
1111
0000
1111
0000
1111
0000
1111
0000
1111
00000
11111
0000
1111
00000
11111
0000
1111
00000
11111
0000
1111
00000
11111
0000
1111
00000
11111
0000
1111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
00000
11111
Primary
0
1
0
1
1
0
0
1
0
1
0
1
00
11
0
1
00
11
0
1
00
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0
1
00
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11111
00000
00000
11111
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11111
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11111
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11111
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11111
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11111
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11111
00000
11111
00000
11111
00000
11111
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
mmf
Secondary
11
00
0
1
00
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00
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0
1
00
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00
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0
00 1
11
00
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0 11
1
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0 11
1
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1
0
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0
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0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
mmf
(a)
(b)
Figure 2.10: Effect of interleaved winding and mmf plot

because of interleaved winding. Again, the leakage flux is given by
l =
mmf
<l
(2.1)
where <l is the reluctance of the leakage path. As a result the leakage inductance of the
transformer reduces to a low value at the cost of increased complexity in the transformer
design. From (2.1) the leakage inductance can be expressed as
Ll =
N2
<l
(2.2)
where N is the number of turns. Hence, Ll can also be reduced by selecting a core of higher
cross-section area (so that N is less) and of higher window height (so that <l is more).
The next consideration is skin effect due to high frequency operation. The skin depth
can approximately be expressed in terms of frequency of operation (f ), absolute permeability
14
() and conductivity () as follows

r
=
1
f
(2.3)
Equation (2.3) implies that current density at a depth from the surface of conductor
becomes 37% of its value at surface. If a thick conductor is chosen for transformer winding,
it will cause a high conduction loss. A reasonable approach is to select thin conductor of
diameter < 2 and put suitable number of parallel wires to carry desired current.
The losses in transformer core consists of hysteresis and eddy current loss. Both of these
losses are very low in ferrite core because of smaller values of peak flux density (Bmax ) and
high resistivity (). Hence ferrite core is a reasonable choice for such design.
2.5
Review of Voltage Regulation Loop for Stand-by

AC Power Supplies
An equivalent (1 equivalent) circuit of voltage source inverter is shown in Fig. 2.11. The
figure also shows the filter and the connected load. The objective of putting LC filter is to
provide a sinusoidal voltage to the loads. In order to maintain desired output voltage quality
with load variation, it is essential to have a closed loop voltage controller. Fig. 2.12 shows
the single voltage loop control structure. This control scheme eliminates the need of current
sensors but fails to achieve high steady state and transient responses with adequate stability
margin. All three control objectives can be ensured with multi-loop control (shown in Fig.
2.13). Only a proportional controller is enough for inner current loop though it produces a
significant phase shift at operating frequency. A large gain associated with the outer voltage
controller is essential in order to compensate the phase shift and to ensure negligible steady
state error. Again, in multi-loop or cascaded loop controller, the bandwidth of the voltage
controller can not be increased beyond certain value. Hence, the inner current loop plays a
significant role on damping of resonance oscillation due to the output LC filter.
The control structure of voltage regulation loop for a three wire system can easily
be implemented either in synchronously rotating frame (usually applied for controlling
speed/torque and flux in AC motor drives systems [15, 16]) or in stationary reference frame
[17]. Hybrid approaches (stationary + synchronously rotating frame) were also reported in
literature [18]. In all these controller structures the basic objective is to provide a large gain
2.5. Review of Voltage Regulation Loop for Stand-by AC Power Supplies
15
L
+
VSI
Load
Figure 2.11: 1 equivalent circuit
V*
Voltage
Controller
V
Plant
Figure 2.12: Single voltage loop
V*
Voltage
Controller
I*
Current
Controller
Plant
Figure 2.13: Multi-loop with inner current loop

to the desired frequency components such that steady state error remains within acceptable
tolerance limit. For a three-wire system the performances are nearly identical with a little deviation in implementation efforts. But inclusion of fourth wire introduces additional
complexity in synchronously rotating frame based control strategy. It requires positive, negative and zero sequence controllers [19, 20, 21], complicated transformations and separation
of different sequence components. Moreover, zero sequence controller handles time varying
quantities and thus produces significant steady state error. The same performance can be
achieved with less implementation complexity using proportional + resonant controller in
stationary reference frame [17, 22]. This controller structure is derived from DC controllers
by suitable transformation in [23].
The proportional + resonant controller in stationary reference frame is not sufficient
to maintain output voltage Total Harmonic Distortion (THD) with non-linear loadings. An
improved controller structure is described in this thesis to mitigate the problem (proportional
+ multiresonant controller) in chapter 4.
16
2.6
Review of Paralleling Techniques
The parallel operation of stand alone AC supplies are becoming more and more popular in
UPS systems and micro-grid systems. The simplest way to parallel two different voltage
sources is to use a common voltage controller and individual current controllers with the
current references generated from the common voltage controller (Fig. 2.14). If the inverters
are of unequal ratings the total current reference (iL ) can be divided accordingly to generate
the individual current references. This controller structure can also be viewed as masterslave paralleling technique where one unit is operated as voltage mode (as master) to fix
the common voltage for the loads and the other unit is controlled in current mode (as
slaves) to cater to desired load currents. These paralleling technique ensures an excellent
sharing accuracy with a very good output voltage quality. However, it also requires physical
interconnections of various communication signals and poses a restriction on the location of
the modules. In order to avoid the communications, the droop method is usually applied
and such paralleling is known as decentralized or communication-less paralleling technique.
0.5
V*
+
Voltage
Controller
i*L1
i*L
0.5
i*L2
Current
Controller
Inverter1
Current
Controller
Inverter2
iL1
+
iL2
Figure 2.14: Communication based paralleling technique
2.6.1
Basic Principles of Decentralized Paralleling

S = P + jQ
E
0
To loads
Z
Figure 2.15: Equivalent circuit of an inverter connected to a load bus
2.6. Review of Paralleling Techniques
17
The equivalent circuit of an inverter connected to a load bus is shown in Fig. 2.15. The
complex power S delivered to load bus is given by,
S = P + jQ
(2.4)
where the expressions of active and reactive powers (P and Q) depend on the impedance Z.
If it is purely inductive i.e. Z = jX, the expression of the active and reactive power becomes
EV
sin
X
EV cos V 2
Q =
X
P =
(2.5)
On the other hand, if Z is resistive in nature i.e. Z = R, (2.5) modifies to

V2
EV
cos
R
R
EV
Q =
sin
R
P =
(2.6)
Fig. 2.16 shows two inverters with their respective impedances Z1 and Z2 connected to
a common load. Depending upon the situation, these output impedance Z1 and Z2 could
be either resistive or inductive (or a combination of both). Hence, it is very difficult to
uniquely define the relationship among P , Q, E, [from (2.5) and (2.6)] and the desired
droop characteristics. Moreover, the impedances Z1 and Z2 may not be in proper ratio with
the rating of the inverters.
V
Z1
E1
I1
0
I2
Z2
E2
Load
inverter#1
inverter#2
Figure 2.16: Equivalent circuit of two parallel connected inverters
18
2.6.2
General Structure of the Controller for Decentralized Paralleling
The simplest way to solve the above problem is to put decoupling inductors. But such
arrangement makes the system more bulky and also increases the losses. An elegant way
to handle the situation is to incorporate a virtual output impedance by the control action.
With suitably designed virtual output impedance, the system effectively experience either
inductive or resistive output impedance and the power sharing accuracy improves. It has
been shown in the literature that if a resistive output impedance is virtually imposed, it
improves the damping of the system and harmonic current sharing ability [24]. With the
resistive behaviour of the system (the output impedance), the frequency and the amplitude
of the inverter output voltage reference can be expressed as (2.7).
= + mQ
(2.7)
E = E nP
where and E are the output voltage frequency and amplitude at no load and m and
n are the droop frequency and amplitude coefficients respectively. Along with this droop
characteristics the general block diagram of the control scheme for decentralized paralleling
Vc
Io
PQ
calculation
P
P/Q
droop
Q
Voltage
reference
generation
V*c_p
V*c Voltage
+
regulation
loop
Inverter
is shown in Fig. 2.17 [25].

Io
virtual output
impedance Z D
Figure 2.17: General block diagram of the controller for decentralized paralleling [25]
In Fig. 2.17, P and Q are calculated from the inverter output voltage and current (Vc and
Io ). By using (2.7), E and can be evaluated from P and Q. Vc is the reference voltage
to the voltage regulation loop. The virtual impedance loop reduces the reference to the
voltage regulation loop proportionally with Io . ZD is the virtual output impedance and Vcp
is the reference voltage without this droop. The effective paralleling of two or more inverters
should obey two basic criteria. Firstly, there should not be any circulating current among
the converters at steady state. This is ensured by the droop characteristics (P/Q droop
2.7. Conclusion
19
block). Secondly, the load sharing should be as accurate as possible in spite of the tie wire
impedance mismatch. This is ensured by suitable design of the virtual output impedance.
However, to maintain the harmonic contents in the output voltage within desired limit,
the resistive output impedance loop requires a set of band pass filters (to extract each of
the harmonic components). In this thesis, another closed loop structure is proposed with
similar flexibility to limit the THD of the output voltage waveform. The resistive output
impedance loop is made highly simplified by eliminating the band pass filters using a voltage
regulation loop with resonant peaks at the desired frequencies. This controller structure is
well known as proportional + multiresonant controller. In [17, 26, 27], the proportionalresonant controller based decentralized parallel operations are reported. The same concept
is attempted to extend for non-linear and unbalanced loads in the present work. A trade off
is maintained between the THD of the output voltages and the sharing accuracy by suitable
design of the controller and the virtual resistive output impedance loop. In [28, 29], the
GH and Q G droop controls are employed to share harmonics and unbalanced currents
among DG units. The work described in this thesis is an alternative method to achieve
the same objective. Moreover, the same sharing accuracy for all sorts of loads (balanced,
unbalanced and harmonics) is ensured by a single output impedance loop in spite of the tie
wire impedance mismatch.
2.7
Conclusion
In this chapter, high frequency link power converters are reviewed from their inception to the
present. Several converter topologies and their principle of operations are discussed. Various
aspects of special concern with high frequency transformer design are explained.
State-of-the-art of stand-by AC power supplies and their control techniques are highlighted. It is concluded that for three phase four-wire systems stationary domain control
techniques are superior compared to synchronously rotating reference frame controllers. Finally, different paralleling techniques are also reviewed and the relative merits and demerits
of decentralized parallel operation are discussed.
20
Chapter 3
High Frequency Link Converter and
Associated Issues
3.1
Introduction
This chapter deals with the proposed DC 3 AC high frequency link power converter
topology, its principle of operation and commutation requirements. The power circuit configuration is then extended to three phase four wire case by using a center-tapped high
frequency transformer. Some second order effects on the power circuit performances like
non-linear distortion in the output AC voltages and poor utilization of the high frequency
transformer are explained and analysed. The root of these problems are identified and experimentally mitigated with suitable compensation techniques. Finally, an active clamp based
regenerative snubber circuitry to improve the overall efficiency of the high frequency link
power converter system is presented.
3.2
The Proposed DC 3 AC High Frequency Link

Converter
This section focuses on a new high frequency link DC to three phase AC power converter.
The least number of switching devices among other high frequency link DC to three phase AC
converters, improved power density due to absence of devices of bidirectional voltage blocking
capability, simple commutation requirements and isolation between input and output are
the integral features of this topology. The various aspects of power circuit operations are
addressed.
21
22
Chapter 3. High Frequency Link Converter and Associated Issues

Vlink
A
Sr
Sy Sb
+
r
Vp
A
B
Isolation Y
Transformer
Primary side
Inverter
R
Y
B
Vs
X
Sr Sy Sb
Secondary side
Synchronous
Rectifier
Output side
three phase
VSI
LC filter
Figure 3.1: Proposed DC to three phase AC high frequency link topology
3.2.1
The Power Circuit
The proposed scheme is shown in Fig. 3.1. The topology is a direct extension of high
frequency link configurations with modulation after isolation [6] with modified configurations
in the cycloconverter side. It has five cascaded stages as follows.
Primary side inverter
High frequency isolation transformer
Secondary side synchronous rectifier
Output side three phase VSI
Output LC filter
The primary side inverter operates in quasi-square wave mode and the secondary side
synchronous rectifier rectifies the high frequency transformer output. Finally, the output
side three phase VSI converts the rectified DC to three phase AC [30, 31]. This structure
provides very simple commutation scheme and requires only 14 switching devices of unidirectional voltage blocking capacity. This highly improves the compactness of the PCB
layout at cycloconverter side. Moreover, the switching of the synchronous rectifier devices
(X and Y) are near lossless (limited by the leakage inductance of the transformer). It is
possible to have different switching frequency for the output three phase VSI and primary
side inverter. This feature allows to operate the primary side inverter at a reasonable high
frequency (say, 20 kHz) as it determines the transformer size and the switching frequency of
3.2. The Proposed DC 3 AC High Frequency Link Converter
23
the three phase VSI can be selected smaller (say, 10 kHz) compared to that of the primary
side inverter (to reduce the switching loss). This is another attractive flexibility in circuit
operation compared to the previous structure. But for a better performance (as explained
in the next section), the switching frequency for the primary side inverter should be integer
multiple of that for the output side VSI.
3.2.2
Extension to 3-phase 4-wire Case
The majority of loads fed by AC power supplies and uninterruptible power supply (UPS)
systems are non-linear and unbalanced in nature [21, 32]. In case of unbalanced load if load
neutral is kept floating (as in three wire systems), it shifts from its balanced location causing
severe over voltage or under voltage across different phases. To prevent neutral shift the only
solution is to use four wire systems. Conventionally, three leg VSI with DC bus mid-point
as fourth wire, four leg VSI and three leg VSI with output delta-star transformer are used
to achieve a four wire system [33, 34, 35, 36, 37, 38]. In this section a three phase four
wire system with high frequency transformer isolation is proposed (Fig. 3.2). The isolation
between input and output are inevitable for certain applications like medical facilities due
to safety reasons. In such situations this topology provides compact isolation at the cost of
extra devices and associated losses.
P
A
+
Vp
Sr
Sy
R
Y
B
r
y
Vs
Sb
Sr
Sy
Sb
N
O
Primary side Isolation Secondary side Output side
Inverter
transformer Synchronous three phase
Rectifier
VSI
LC filter
Figure 3.2: Proposed three phase four wire high frequency link converter
24
The modified power circuit structure for three-phase four-wire system is shown in Fig.
3.2. The mid-point of high frequency transformer acts as the fourth wire and thus eliminates
the requirement of an additional leg in the cycloconverter side. A RC snubber is added
after synchronous rectifier to absorb the stored energy in the leakage inductance of the
isolation transformer. The better snubber circuitry will be discussed in the final section of
this chapter. The detailed commutation requirements of the power circuit are described in
next subsection.
3.2.3
Commutation Requirements
The power circuit requires certain commutation procedures (shown in Fig. 3.3) for its safe
operation. The primary side inverter legs (A and B in Fig. 3.2) are operated at 50% duty
ratio with a small phase shift between them. These gate pulses for A and B are generated
and B
are the compliments of
from phase shifted carrier CA and CB respectively. Again, A
A and B respectively (Fig. 3.2) with small dead time to prevent shoot through of the DC
source. The phase shift between A and B introduces a zero voltage portion in the primary
(Vp) as well as the secondary (Vs) voltage waveform. The synchronous rectifier switches (X
and Y) have small overlap (shown in Fig. 3.3) to keep current path continuous. Again, this
overlap of X and Y takes place within the zero portion of the secondary voltage (Vs) in order
to avoid dead short circuit of the secondary voltage. The zero portions and overlap zones
are shown larger compared to actual one for clarity. The cycloconverter link voltage (VP N )
is not a fixed DC but have some zero portion in it (VP N = VP O - VN O ). The centre point
O of the high frequency transformer acts as the fourth wire. The next stage is a standard
three phase VSI which takes VP N as its input and generates three phase output voltages.
The switches Sr , Sy , Sb are modulated with same carrier CA to produce pole voltages (Sr
and VrO are shown in Fig. 3.3). In case of unbalanced load, the fourth wire carries zero
sequence component of unbalanced load current and helps to maintain rated voltages across
each phase.
3.2.4
Illustration on Zero Sequence Current Path
As described in the previous section that the fourth wire takes the zero sequence current
and allows the power circuit to cater to unbalanced loads. Fig. 3.4 describes the paths of
common mode or zero sequence current in the secondary side of the transformer under a
3.2. The Proposed DC 3 AC High Frequency Link Converter

CB
CA
A
Vp / Vs
Zero Portion
X
Y
Overlap
VPO
VNO
Sr
VrO
Figure 3.3: Sample waveform to describe commutation requirements
25
26
simple situation where only R-phase is loaded and other two phases are open circuited (so
that entire R-phase current flows through the fourth wire). The primary side inverter and
Y- and B-phase legs of output side VSI are not shown in the figure for simplicity. For a
given direction of common mode current, depending on status of switches X, Y and Sr four
different modes are possible (Fig. 3.4 (a), (b), (c), (d)). The important point to note here is
that the transformer sees a high frequency (switching frequency) current whereas the actual
zero sequence current is at fundamental frequency. Hence transformer carries common mode
current without getting into saturation.
(a) X and S r
X
ON
Mode 1
Sr
(b) X and S r
ON
X
Mode 2
r
Y
(c) Y and S r
X
ON
Mode 3
Sr
Sr
r
Y
(d) Y and S r
ON
X
Mode 4
r
Y
Sr
Sr
Sr
Sr
r
Y
Sr
Figure 3.4: Path of zero sequence current in a simplified case (only R phase is loaded)
3.3
Non-linear Distortion in the Output Voltages
The presence of zero portion in the cycloconverter link voltage (V link = VP O VN O in

Fig. 3.3) causes a non-linear distortion in the three phase output voltages. This distortion
makes the total harmonic distortion poor and excites the resonating modes of the output LC
filter. This also affects the open loop gain of the converter. In this section, the open loop
gain of the converter is calculated considering the non-linear distortion produced by quasi-
3.3. Non-linear Distortion in the Output Voltages
27
square wave operation of the primary side inverter. The suitable compensation technique is
mathematically derived and verified through simulation and experimental results.
3.3.1
Calculation of Open Loop Converter Gain
The calculation of open loop gain of any system is important because it helps in controller
design and decoupling of d and q axis parameters in synchronously rotating frame based
control scheme. The zero portion in Vlink (Fig. 3.3) produces a non-linear distortion at the
output voltages. If the band width of the voltage controller is sufficiently high then this
adverse effect can be mitigated but the gain of the converter is still non-linear with time.
To overcome the above problem, the actual modulating signals of the output side VSI are
modified as per the following analysis. The effect of leakage inductance of the isolation
transformer, dead time on the primary side inverter and the output side VSI are ignored in
the calculation. The compensation techniques for dead time in voltage source inverters were
reported in [39, 40, 41].
Zero portion in link voltage
N V dc
Vlink
Ts /2
Carrier CA
+V p
k=k1
k=k2
k=k3
k=k4
Vp
VRO (k=k1)
+N V dc /2
N V dc /2
VRO (k=k2)
VRO (k=k3)
VRO (k=k4)
Figure 3.5: The sample waveforms to illustrate zero voltage distortion problem
28
Let, switching period = Ts , total zero portion in DC link voltage (Vlink ) in one switching
cycle = Ts , carrier peak = VP , value of the modulating signal = k, DC source voltage
= VDC , turns ratio of isolation transformer = 1 : N and 1 is denoted by . Then, if
DC link zero portion is ignored (as in ideal situation) R-phase pole voltage (with respect to
mid-point O of the isolation transformer) averaged over a switching cycle is given by
VDC N k
(3.1)
2VP
In order to analyse the the nature of the problem, four different values of modulating signals
hVRO iTs =
for a particular leg (say R phase) and respective pole voltages are shown in Fig. 3.5 with
carrier CA and Vlink . The zero portion in the link voltage (Vlink ) is also present in R phase
pole voltage as shown by hatched portion in Fig. 3.5. The four values of modulating signals
are selected in such a way that each of them represents a different zone. Each of these zones,
the values of hVRO iTs are affected by the zero portion in V link in different manner. The
mathematical expressions of hVRO iTs in these four zones can be calculated as

VDC N k
hVRO iTs =
; VP < k VP
2
VP
= 0
; 0 < k VP
(3.2)
VDC N k
=
; VP < k 0
2 VP
VDC N
=
; VP < k VP
2
Now, if we compare (3.2) with (3.1), it clearly indicates that, presence of the zero portion
in the link voltage distorts hVRO iTs waveform.
Let us introduce a compensation 4k with the modulating signal k for the output side VSI
to nullify the adverse effect. In (3.2), the expression of hVRO iTs in the first range becomes

VDC N k
4k
+{
}
(3.3)
2
VP
VP
The equation (3.3) is identical to (3.1) if 4k = VP . Again, if we look to the expression
of hVRO iTs in the second range of (3.2), it is independent on k. To make it dependent on
k we assume 4k VP so that k + 4k falls in the first range in (3.2). This implies that
4k = VP is also sufficient to correct distortions in the second range. Similarly, for the
other ranges the value of 4k can be found out and they are as follows
4k = VP ; 0 < k VP VP
= 0
; VP + VP < k 0
(3.4)
29
0.5
0.5
k+k
k,k
0.5
0.5
1
0
0.01
0.02
Time (sec)
0.01
0.02
Time (sec)
Figure 3.6: Compensation in modulation signal for saw-tooth carrier, left : actual modulating
<Vro>Ts with compensation (Volts)
<Vro>Ts without compensation (Volts)
signal k (dotted), compensation 4k (firm), right : modified modulating signal k + 4k
200
100
100
200
0
200
100
100
200
0.01 0.02
Time (sec)
0.01 0.02
Time (sec)
Figure 3.7: Uncompensated (THD = 6.9%) and compensated (THD = 0.4%) pole voltage
averaged over switching cycle for saw-tooth carrier
The actual modulating signal k, compensation 4k and modified modulating signal k+4k
are shown in Fig. 3.6 and hVRO iTs with and without compensation are shown in Fig. 3.7
30

N V dc
Vlink
Ts /2
+V p
Carrier
Vp
0.5
0.5
k+k
k,k
Figure 3.8: Triangular carrier with V link
0.5
0.5
1
0
0.01
0.02
Time (sec)
0.01
0.02
Time (sec)
Figure 3.9: Compensation in modulation signal for triangular carrier, left : actual modulating
signal k (dotted), compensation 4k (firm), right : modified modulating signal k + 4k
If the carrier is triangular instead of saw-tooth as shown in Fig. 3.8 with the zero portions
in the link voltage, the compensation technique becomes slightly complicated (Fig. 3.9, Fig.
3.10). The expression of 4k is given by
4k = VP
; VP < k VP VP
= VP ; VP + VP < k VP
= k
(3.5)
; VP k VP
When the frequency of the primary side inverter and the output side VSI are not same
200
100
100
200
0
31
200
100
100
200
0.01 0.02
Time (sec)
0.01 0.02
Time (sec)
averaged over switching cycle for triangular carrier
N V dc
Vlink
Ts /4
+V p
Carrier
Vp
Figure 3.11: Saw tooth carrier (p = 2) with V link

the complication in generating modified modulating signal increases dramatically. If the
switching frequency of the primary side inverter is selected as an integer (denoted by p)
multiple of that for the output side VSI then it easier to compensate for the distortion.
This is because under this condition the locations of zero portions are fixed in the switching
period. Again, in such situation, saw tooth carrier provides much simpler compensation
requirements compared to triangular ones from the point of view of implementation. Fig.
3.11 shows the position of saw-tooth carrier with Vlink for p = 2. In such situation the
32
0.5
0.5
k+k
k,k
0.5
0.5
1
0
0.01
0.02
Time (sec)
0.01
0.02
Time (sec)
Figure 3.12: Compensation in modulation signal for saw-tooth carrier with p = 2, left :
actual modulating signal k (dotted), compensation 4k (firm), right : modified modulating
signal k + 4k
200
100
100
200
0
0.01 0.02
Time (sec)
200
100
100
200
0
0.01 0.02
Time (sec)
averaged over switching cycle for saw-tooth carrier (p = 2)
33
compensation 4k can be expressed as (3.6). Fig. 3.12 and Fig. 3.13 show the corresponding
compensation in the modulating signal and its effect respectively.
VP
2
= VP
VP
;0 < k
2
VP
;
< k VP
2
(3.6)
VP
= 0
; < k 0
2
VP
= VP ; VP < k
2
2
For a general case where the switching frequency of the primary side inverter is p (integer)
4k =
times the output side VSI switching frequency, by inspection this analysis can be extended
as (3.7).
VP
p
2
=
VP
p
= ........
4k =
= VP
= 0
VP
p
VP
2VP
;
<k
p
p
;0 < k
(p 1)VP
< k VP
p
VP
; < k 0
p
2VP
VP
;
<k
p
p
;
(3.7)
= VP
p
= ........
(p 1)
(p 1)VP
=
VP ; VP < k
p
p
From (3.4)(3.7), it is important to note that the modulation index of k is limited to
in order to avoid over modulation. Again, the expressions derived above are only valid
for particular position of the carrier with the zero portions in Vlink . However, with such a
modification the combined gain of the modulator and converter is linear and given by
G=
3.3.2
VDC N
2VP
(3.8)
Experimental Verifications
In order to verify the effectiveness of the proposed converter and the theoretical analysis
an experimental prototype of 1 kVA is made and tested under open loop. The details of
the power circuit is given in Table. 3.1. Fig 3.14 shows the dc link voltage (Vlink ) with
34
zero portions in it. These zero portions cause the non-linear distortion in the pole voltage
(averaged over switching cycle) as shown in Fig. 3.15 (only for R phase). Fig. 3.17 shows the
pole voltage (averaged over switching cycle) after the suitable compensation is done. The
corresponding total harmonic distortions are shown in Fig. 3.16 and Fig. 3.18 respectively.
The perfect sinusoidal obtained in the simulation result is not achieved because of other nonidealities like dead-time in the primary side inverter, the leakage inductance of the isolation
transformer etc.
Table 3.1: Power Circuit Details

Attributes
Value
Power Rating
1 kVA
Input
120V DC
Output
220V L-L 3 AC
Switching Frequency
20 kHz
Turns ratio of transformer
1:4
Figure 3.14: Measured voltage of V link, CH1 : 100V/div, time : 20sec/div
3.4. Improved Utilization of High Frequency Transformer
35
Harmonics as a percentage of fundamental
Figure 3.15: hVRO iTs without compensation, CH1 : 100V/div, time : 10msec/div
100
80
60
40
20
0
0
10
15
Harmonics Order
20
25
Figure 3.16: Fourier spectrum of hVRO iTs in Fig. 3.15: THD = 13.2%
3.4
Improved Utilization of High Frequency Transformer
In high frequency link power converters, the transformer should be designed to operate
with high frequency components. But in the practical situations with DC to 1 AC power
conversion (or DC to 3 4-wire AC power conversion with unbalanced loadings) the instantaneous power flows at double the fundamental frequency. Presence of dead-time and overlap
36
Figure 3.17: hVRO iTs with compensation, CH1 : 100V/div, time : 10msec/div
100
80
60
40
20
0
0
10
15
Harmonics Order
20
25
Figure 3.18: Fourier spectrum of hVRO iTs in Fig. 3.17: THD = 6.1%
also cause the transformer to operate with some amount of DC and fundamental frequency
current. Thus HF transformer sees a low frequency voltage pattern because of impedance
drop. Moreover, mismatch in the device drops and dead-time in the primary side inverter
injects a significant amount of DC flux into the transformer. As a result, the high frequency
transformer need to be over-designed to avoid saturation problem. Moreover, such operation
37
increases the conduction loss in the primary side inverter (due to the increased magnetizing
current).
In this section, the root of the problem is first justified by an approximate lumped parameter non-linear model of the HF transformer. Though there exists a number of ways
to model HF transformer [42, 43, 44], a simple experimental method is followed here. The
information of magnetizing current is extracted using a single hall effect sensor. A control
algorithm based on magnetizing current feedback is proposed to ensure the operating point
of HF transformer to swing within the designed band in B-H curve. The design of the controller becomes highly complicated due to the saturation effect and associated non-linearity.
Moreover, a simple PI controller with fixed gains fails to maintain guaranteed performance
under transient condition. A on line tuning method of the PI controller parameters based
on the evaluated B-H curve is proposed to mitigate the problem.
3.4.1
Control over the Magnetizing Current
In order to understand the control over the magnetizing current, the commutation scheme
is redrawn in Fig. 3.19 with a little modification. Let us consider the effect of the position
of the base comparison line M (Fig. 3.19) on the magnetizing current. This consideration
is important because it helps to establish the basis of control law. In order to explain the
phenomena a portion of Fig. 3.19 is redrawn in Fig. 3.20 with the magnetizing current.
For nominal position of M (firm line), A, B and VP are drawn in firm line. It can be seen
from Fig. 3.20 that the average value of VP over a switching cycle is zero and hence there is
no associated DC flux (or Im ) at the end of the switching cycle. At this point the effect of
the primary side resistance and core saturation are not considered. Hence the magnetizing
current is linear and can be expressed as
1
Im =
Lm
Z
VP dt
(3.9)
When M is moved up by a small amount x then the positive half of VP becomes more
compared to the negative half (shown in dotted line in Fig. 3.20). As a result the effective
average value injected to the transformer over a switching cycle is given by
hVP iTs =
Vdc
x
Vc
(3.10)
38
CB
M
+Vc
CA
Vc
B
VP
or
VS
11
00
00
11
00
11
11
00
00
11
00
11
1
0
0
1
0
1
1
0
0
1
0
1
Zero Portion
X
Overlap
VPN
Figure 3.19: Commutation requirements with base comparison line M

where Vdc is the input DC voltage. Due to this net DC voltage, the magnetizing current will
have small DC shift 4b at the end of one switching period Ts as given in (3.11).
4b =
1
Vdc
x Ts
Lm
Vc
(3.11)
Alternatively, if x is negative this shift will be in the opposite direction. Again, from Fig.
3.19 it is clear that when x varies the entire encircled portion moves in a particular direction
depending on the polarity and magnitude of x. It is interesting to note that this variation
CB
M
+Vc
CA
Vc
39
0
x
VP
Im
VP
Im
b
Figure 3.20: Sample waveform to describe the effect of different position of M on Im
does not alter the cycloconverter link voltage (Vlink ) other than the position of zero portion
in it. Hence this modulation strategy indirectly eliminates the variation of the open loop
converter gain.
40
3.4.2
Selection of High Frequency Transformer
The design of high frequency transformer is quite challenging and critical for high frequency
power converter. Its design procedures are well discussed in literature [45, 46, 47]. Considering those aspects, the HF transformer is designed and its details are given in Table. 3.2.
Table 3.2: HF Transformer Details
3.4.3
kVA Rating
1 kVA
Frequency
20 kHz
Core
E65/32/27 Ferrite
Primary
14 turns SWG#21 8
Secondary
56 turns SWG#21 2
Winding
Interleaved
Air gap
No
Saturation flux density
470 mT at 25 C, 370 mT at 100 C
Designed peak flux density
250 mT
Characterization of HF Transformer
The experimental characterization of the HF transformer is very important in order to predict its behaviour. The method followed in the present case is based on a set of measurement
using network analyser (AP instruments) [48, 49, 50]. The equivalent circuit with different
parameter values are shown in Fig. 3.21. Inter winding capacitance and various high frequency effects are ignored in the equivalent circuit.
The magnetic saturation behaviour of the HF transformer is not included in the above
equivalent circuit. A simple experimental procedure is adopted to find out the m Im
curve of the magnetic material [51]. When the secondary of a transformer is open circuited
the voltage equation of the transformer is given by
VP = RP IP +
dm
dt
(3.12)
IP
41
IS
1:4
RP
Llp
Ic
Lls
Im
RS
VP
VS
Rc
Lm
Figure 3.21: An approximate equivalent circuit of the transformer at 20kHz: Lm =1.66mH,

RP =0.075, RS =1.2, Llp =1.25H, Lls =20H, Rc =15k
where VP is the instantaneous voltage across the primary winding, RP is its resistance and
IP the primary current. The flux linkage m is
Z
m = (VP RP IP )dt
(3.13)
The flux-linkage can be computed for different values of current with help of (3.13). The
experimental setup is shown in Fig. 3.22. The primary of the transformer is connected in
series with a rheostat (Rh) and electronic switch (S) to a dc source VIN , with the secondary
of transformer open circuited. A voltage pulse is applied by turning on the switch (S). The
IP
Rh
VP
a
VIN
60V
+
15V
Figure 3.22: Setup to characterize the HF transformer

duration of the voltage is made adequate to make the current to reach nearly 30% more
than the rated current. The voltage VP (VP = VIN IP Rh) and the current IP , through the
42
primary are recorded (shown in Fig. 3.23). The data stored in oscilloscope is transferred
to the computer and numerical integration of (3.13) is performed. The measurement result
is shown in Fig. 3.24. The flux linkage for negative half cycle is found out by a similar
experiment with the primary terminals (a and b) interchanged.
Figure 3.23: Measured voltage (CH1: 50V /div) and current (CH2: 10A/div), time:
10sec/div
10
Current (Amp)
10
3
0
1
Fluxlinkage (Wbturns)
Figure 3.24: Measured m Im curve
3
3
x 10
3.4.4
43
Modelling of the High Frequency Transformer
The analysis of the system and controller design require suitable modelling of the system. With help of the data obtained from the experimental measurements, an approximate modelling of the HF transformer is carried out (shown in Fig. 3.25). The back emf
LUT ( m Im )
+
VP
EP
Im
IP
RP
+
+
IS
RS
VS
Figure 3.25: Simulink model of the HF transformer
(EP = VP IP RP ) is integrated to get flux-linkage information. From this flux-linkage the

magnetizing current is obtained from a look up table (LUT). The effect of hysteresis loop,
thermal effects are neglected in this LUT construction. The omission of core losses is justified
here because in linear operating condition, Im Ic from Fig. 3.21. In saturated condition
Im is even higher compared to that in unsaturated core. Hence from the point of view of
closed loop control objective we can safely ignore core loss component. Again the voltage
drops in Llp and Lls are negligibly small compared to the resistive drops (in RP and RS ) due
to the low frequency currents. Hence these terms are not included in Fig. 3.25. The primary
0
current (IP ) is nothing but the reflected secondary current (IS = IS N ) plus the magnetizing
current (Im ). This model is used to observe the effect on magnetizing current when the HF
link converter is loaded with 1 RL load.
44
3.4.5
Effect of Various Circuit Parameters
The voltage equation of the transformer primary (ignoring the leakage inductance) can be
written as
dm
dt
(3.14)
dm
VP un + VP c RP (N IS + Im ) =
dt
= uncontrolled portion of VP which is basically governed by mismatch in the
VP RP IP =
where VP un
device drops and dead time; VP c = controlled part of VP which we can vary by changing x
(as shown in the previous subsection). The rate of change of the mutual flux m can be
expressed as
dm
m dIm
dIm
=
= Lm
(3.15)
dt
Im dt
dt
The magnetizing inductance of the transformer, Lm is not a fixed quantity but depends on
the point of operation of the transformer in m Im curve. Let us concentrate on a small
portion around any particular point in m Im curve so that Lm is assumed to be constant
over there (say, equal to Lmp ). Hence we can rewrite (3.14) as follows
dIm
VP c + VP un RP N IS = RP Im +Lmp
|{z}
|
{z
}
|{z}
dt
control disturbance
control
input
input
(3.16)
variable
From (3.16), the disturbance transfer functions can be evaluated as follows

Im (s)
1
=
VP un (s)
RP
Im (s)
IS (s)
1
Lmp
1+s
RP
1
= N
Lmp
1+s
RP
(3.17)
These two transfer functions give the effect of various circuit parameters and operating
conditions on the magnetizing current. The DC gain of these two transfer functions are fixed
but the cut-off frequency varies with Lmp value. In unsaturated case this cut-off frequency
is 45.2 rad/sec. With saturation of the core this cut-off frequency will gradually increase.
The effect of dead time can be modelled as

Vdc
Vdc
; IP > 0
VP un(dt) =
(2A 1)
1 2B
2
2
Vdc
Vdc
=
1 2A
(2B 1) ; IP < 0
2
2
(3.18)
45
B, B
have a certain amount of delay (dead time) at their
where the logic signals A, A,
rising edge. From (3.18) it can be seen that VP un(dt) depends on the dead time intervals,
their mismatch and polarity of the primary current. Typical value of dead time used in the
present application is approximately 1 sec.
As the devices for the H-bridge are MOSFETs, the modelling of the device drop requires
its ON state resistance (r = 0.04) and anti-parallel diode forward voltage drop (VD =
1.3V ). These effects can be expressed as (3.19).

Vdc
A A B + B
2

+ VDA A + VDB B ; IP > 0
IP rA A + rB B

Vdc
A A B + B
=
2

; IP < 0
+IP rA A + rB B + VDA A + VDB B
VP un(dp) =
(3.19)
VP un(dp) depends on rA , rA , rB , rB , VDA , VDA , VDB , VDB , their differences and magnitude as
well as polarity of IP . Again, IP depends upon the secondary current IS (or load current) and
the magnetizing current of the transformer. Hence, it is a highly cross coupled phenomena
and can be understood better by simulation studies.
The simulation result in Fig. 3.26 shows the combined effect of the dead time (dead
time of leg A is decreased to 950 nsec from 1 sec), mismatch in the device drops (rA is
made equal to 0.045 from 0.04 and VDA is fixed to 1.35V from 1.3V ) and load currents
(with associated commutation requirement for the cycloconverter) on Im . Though these
variations of the parameters are arbitrary, it can easily be noticed that Im and its average
value have deviated well apart from its ideal shape. The low frequency component in current
can not be eliminated because of unavoidable commutation requirement and shape of the
load current. Again the winding resistance plays a dual role in this regard. Firstly, it
protects the transformer from getting into deep saturation. On the other hand, low frequency
impedance drop across the transformer winding causes flux walking problem. Hence any
effort to decrease the winding resistance by increasing copper volume is not an effective
solution. In such a scenario, closed loop control can guard the non-idealities of the system
as discussed in the next subsection.
46
Figure 3.26: Simulation result without saturation controller: Im , its filtered value and
zoomed value at certain interval
3.4.6
Closed Loop Solution
As we have seen previously, the primary side converter is basically operated as open loop.
Hence this converter can be exploited to solve the above problem in closed loop form. The
proposed control strategy is shown in Fig. 3.27. The magnetizing current is first filtered by
a low pass filter to eliminate the HF component. In practical implementation this filtering
is important from two aspects. Firstly, ADC sampling need not be too fast and secondly,
47
HF transformer magnetizing current should not be disturbed by this closed loop control.
However, this filtered magnetizing current is forced to zero by a PI controller. This control
action ensures the operation of the transformer at the center of the B-H curve without
affecting the high frequency swing (20 kHz) of the operating point along the B-H curve.
The controller varies the magnitude (x) of the base line M (in Fig. 3.19) in order to achieve
desired control objective.
VPun
ref = 0
+
VPc
Modulator
Hbridge
IS
Plant
HF
Transformer
Im
ADC
Filter
Digital Controller
Figure 3.27: Block diagram of saturation controller

With the above control strategy, the operation of the transformer is shown in Fig. 3.28.
The swing of magnetizing current in Fig. 3.28 is within the desired band.
3.4.7
Controller Design and On Line Tuning
From (3.16) and Fig. 3.27, the control transfer function can be written as
Im (s)
Vdc
=
x(s)
VP
1/RP
Lmp
1+s
RP
(3.20)
Where Vdc /VP is the combined gain of the modulator and the H-bridge. Hence the overall
loop transfer function of the system becomes
KP (1 + sTi ) Vdc / (VP RP )
1
s
Lmp
sTi
1+
1+s
c
RP
(3.21)
48
Figure 3.28: Simulation result with saturation controller: Im , its filtered value and zoomed
value at certain interval
where KP = proportional gain of the controller; Ti = integral time constant of the controller;
c = cut-off frequency of the low pass filter. c is selected as 12566 rad/sec (0.1 times
switching frequency in rad/sec). From pole-zero cancellation in (3.21),
Ti =
Lmp
RP
(3.22)
49
Again, in order to achieve a band width of 1 kHz, KP is given by,

KP =
2 1000 VP Lmp
Vdc
(3.23)
In (3.22) and (3.23), both Ti and KP depends on Lmp (which varies with saturation). Hence
fixed PI controller parameters do not ensure desired performance. This phenomena demands
on line tuning of PI controller parameters. Lmp is calculated from Im feedback and m
Im LUT (as obtained previously) in order to get KP and Ti on line. These variable PI
controller parameters ensure the desired band width and stability with a very good phase
margin of 63 . If the band width is attempted to increase further the phase margin becomes
poor. However, if it is desired to have a simple implementation in certain application, a
compromised controller performance can be achieved by selecting a fixed value of Lmp in
(3.22) and (3.23). The fixed value of Lmp can be selected as the geometric mean of the
nominal and saturated magnetizing inductance. Fig. 3.29 shows the difference in response
of filtered Im with fixed controller parameters and with on-line varying controller parameters.
With fixed controller parameters, the response has high overshoot and more settling time.
3.4.8
Experimental Investigation
The laboratory set-up with digital controller is shown in Fig. 3.30. A single Hall effect sensor
is used to sense the magnetizing current as it gives direct information of flux in magnetic
core. Single turn primary and N turn secondary (as turns ratio = 1 : N ) are passed through
the hall sensor in opposite direction to extract Im information. The measured signal is
converted to proportional voltage signal and filtered by RC filter. This filtered signal is sensed
by the digital controller through an analog-to-digital converter (ADC) for the controlling
purpose. Before turning on the power circuit the controller takes 10 samples of the feedback
signal (through ADC). The average values of these 10 samples gives the offset present in
the measurement. Next, the main closed loop control starts with the corrected values of
the magnetizing current (by subtracting the computed offset from the actual measurement).
Finally, the digital controller provides desired control pulses to the H-bridge. The same
controller also gives commands to the cycloconverter to get desired output 1 AC voltage.
The experimental results are shown in Fig. 3.31 3.32. Fig. 3.31 shows the output single
phase AC voltage (230V rms). The effect of different non-idealities in the power circuit is
reflected in the filtered magnetizing current Im when saturation controller is not activated
50
Filtered Im (Amp)
2
1
0
1
2
3
0.04
0.06
0.08
Time (sec)
0.1
0.12
(a) With fixed controller parameters
Filtered Im (Amp)
2
1
0
1
2
3
0.04
0.06
0.08
Time (sec)
0.1
0.12
(b) With on-line varying controller parameters
Figure 3.29: Comparison of dynamic responses with fixed and on-line varying controller
parameters
(Fig. 3.32(a)). In Fig. 3.32(b) the controller is activated transiently and filtered Im is forced
to follow zero reference with a good dynamic response. The steady state performance of the
controller is shown in Fig. 3.32(c). Another vary important issue is turn on transient of the
high frequency transformer. Whenever the converter is turned on some sort of DC flux is
51
injected into the transformer. Fig. 3.32(d) shows the transient response of the controller
when H-bridge is just turned on. The improvement in utilization of the HF transformer
is noticeable. Moreover, an audible aperiodic noise which was present without saturation
controller is completely eliminated by the proposed scheme. The concept can be seamlessly
Input
Converter
Cyclo
Converter
Hbridge
+
LOAD
modified to center-tap transformer configuration for a three phase four wire system.
Hall effect
Sensor
Filter
Digital
Controller
Figure 3.30: Experimental setup with digital controller
Figure 3.31: Output 1 voltage: CH1: 100V /div, time: 10msec/div
52
Figure 3.32: Effect of various circuit parameters and loading on the magnetizing current and controller response: (a) Filtered Im without saturation controller (1.2A/div),
time: 5msec/div; (b) Controller is activated transiently and filtered Im (1.2A/div), time:
20msec/div; (c) Filtered Im with saturation controller (1.2A/div), time: 5msec/div; (d)
Controller performance at turn on and filtered Im (0.24A/div), time: 2msec/div
3.5. Active Clamp based Regenerative Snubber
3.5
53
Active Clamp based Regenerative Snubber
Let us concentrate on any standard power converter (e.g. switched-mode DC-DC converters,
inverters or active rectifiers); one side of the power circuit is voltage source type and another
side is current source type. But this basic power conversion rule is not satisfied in case of
high frequency link converters because of a finite leakage inductance of isolation transformer.
As a result, the cycloconverter devices experience large over voltage stresses during their
commutation process. Hence, use of snubber circuit is indispensable in such topologies.
HF Inverter
Active Rectifier
PWM Inverter
Figure 3.33: DC to three phase AC high frequency link topology with snubber structure-I
(with separate diode bridge)
HF Inverter
Active Rectifier
PWM Inverter
D
C sn
Figure 3.34: DC to three phase AC high frequency link topology with snubber structure-II
(with a single diode)
54

HF Inverter
Active Rectifier
PWM Inverter
S sn
+
C sn
Figure 3.35: DC to three phase AC high frequency link topology with snubber structure-III
(active clamp)
The proposed high frequency link power converter for three phase output is redrawn in
Fig. 3.33. The conventional dissipative RCD snubber is also shown in Fig. 3.33. The full
bridge diode rectifier absorbs the energy stored in the leakage inductance and dissipates in
the resistance. If we take a close look at the power circuit construction the diode bridge
rectifier is already present in the power circuit structure itself (active rectifier part). Hence
the snubber structure can be modified as Fig. 3.34. In this construction three diodes can be
saved. But the snubber losses in Fig. 3.33 and Fig. 3.34 reduce the efficiency of the overall
system. In order to an achieve regenerative action the diode D (in Fig. 3.34) can be replaced
by an active device with anti-parallel diode (as shown in Fig. 3.35). In this case, the leakage
energy absorbed by the capacitor can be transferred back to source and thus the unwanted
losses in the snubber circuit can be eliminated.
In [6, 30], the active clamp high frequency link power converters are studied and analysed.
However, they are limited to DC 1 systems. This section extends the system analysis
for rectifier and inverter mode of operation to DC 3 systems. An attempt has been
made to achieve a simple commutation scheme.
3.5.1
System Analysis
The circuit configuration with the leakage inductance (Ll ) of the isolation transformer and
the cycloconverter link capacitance (Cl ) is shown in Fig. 3.36. Ll represents the total leakage
inductance (primary leakage referred to secondary + secondary leakage) of the transformer
and Cl represents the lumped capacitance of the cycloconverter link including all device
55
vlink
X
Ll
+
Vdc
Cl
il
1:N
A
S rt
Y + S sn
C sn
vsn
i sn
S rb
S yt
iR
S yb
S bt
iY
iB
S bb
Figure 3.36: Power circuit with various circuit parameters

capacitance. The magnetizing inductance of the transformer is not shown in the figure
as the magnetizing current has a free-wheeling path in the input side inverter and it does
not affect the snubber performance at the cycloconverter side. Fig. 3.37 shows the key
waveforms of the active clamp HF link three phase inverter assuming a particular direction
of load current in one half of a switching cycle in inverter mode (The particular direction
of load current is shown in Fig. 3.38 Fig. 3.40). For the PWM inverter sine triangle
PWM strategy is followed and Sr , Sy , Sb are the three raw pulses coming out from the
digital controller. Then these three pulses are processed in a hard-wired logic to generate
total 6 pulses (Srt , Srb , Syt , Syb , Sbt , Sbb ) with appropriate dead time or blanking time (not
shown in Fig. 3.37). The active switch (Ssn ) in the snubber circuit should be ON at the
correct instant depending on the PWM inverter switches (Srt , Srb , Syt , Syb , Sbt , Sbb ) and
active rectifier switches (X and Y ). During the overlap portion of X and Y, Ssn should be
off to prevent short-circuit across the snubber capacitor (Csn ). By turning on Ssn during
each free-wheeling of the load currents, it is possible to pump the absorbed leakage energy
to the DC source. In the next subsection, Fig. 3.36 is analysed in different stages according
to the conduction states of various switches and their corresponding anti-parallel diodes. In
the system analysis the following assumptions are made
Load current ripples are zero or load inductance is infinite.
Device drops and switching times are zero.
Winding resistance of the HF transformer is negligible.
Effect of dead-time in the HF inverter and PWM inverter is ignored.
56
A
B
X
Y
Sr
Sy
Sb
S sn
NV dc
vlink
t10
t1
t3
t2
t8
IR
il
t 10
(I RIY)
t3
(I RIY)
isn
t
10
t4 t6
vsn
t1
t2 t5
t7 t9
t 11
t 12
Ts /2 t1
Figure 3.37: Key waveforms in inverter mode with particular AC side current (as in Fig.
3.38 Fig. 3.40))
Csn Cl .
3.5.2
Inverter Mode
In inverter mode of operation, the equivalent active circuits in different intervals within one
half of the switching period are shown in Fig. 3.38 Fig. 3.40. Though for a particular
direction of load current (IR , IY , IB ) the analysis is carried out, in different switching cycle
the following analysis is equally valid with different values and sequences of IR , IY and IB .
(i)
Ll
57
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(ii)
Ll
S sn
Cl
C sn
(iii)
Ll
S sn
Cl
C sn
(iv)
Ll
S sn
Cl
C sn
S rb
Figure 3.38: Active equivalent circuits in inverter mode for a particular half switching cycle:
(i) interval 1, (ii) interval 2, (iii) interval 3, (iv) interval 4
0
Interval 1 (t = t1 : t = t2 through t = t1 )
Assume the PWM cycle begins when the load current is free-wheeling through anti-parallel
diodes of Srb (Drb ), Syb , Sbb . The snubber capacitor Csn discharges through Ssn and the
stored energy is transferred back to the source. The time domain equations for this interval
58
(v)
Ll
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(vi)
Ll
S sn
Cl
C sn
(vii)
Ll
S sn
Cl
C sn
(viii)
Ll
S sn
Cl
C sn
S rb
(v) interval 5, (vi) interval 6, (vii) interval 7, (viii) interval 8
can be expressed as (3.24) where
1 =
1
Ll Csn
(ix)
Ll
59
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(x)
Ll
S sn
Cl
C sn
(xi)
Ll
S sn
Cl
C sn
(xii)
Ll
S sn
Cl
C sn
S rb
(ix) interval 9, (x) interval 10, (xi) interval 11, (xii) interval 12
r
Csn
sin {1 (t t1 )}
Ll
+il (t1 ) cos {1 (t t1 )}
r
Ll
vsn (t) = N Vdc + il (t1 )
sin {1 (t t1 )}
Csn
+ (Vsn (t1 ) N Vdc ) cos {1 (t t1 )}

0
vlink (t) = vsn (t)
f or t = t1 : t1
il (t) =
(N Vdc Vsn (t1 ))
(3.24)
60

0
At t = t1 , Ssn is switched off and the system reaches its steady state.
0
When Srt is turned on, the load current (IR ) starts discharging the link capacitance (Cl ).
The mathematical expressions are given in (3.25). In (3.25) 0 is given by
1
Ll Cl
r
Cl
sin {0 (t t2 )}
il (t) =
(N Vdc Vlink (t2 ))
Ll
+IR + (il (t2 ) IR ) cos {0 (t t2 )}
r
Ll
vlink (t) = N Vdc + (il (t2 ) IR )
sin {0 (t t2 )}
Cl
+ (Vlink (t2 ) N Vdc ) cos {0 (t t2 )}

0
vsn (t) = vsn (t2 )
f or t = t2 : t2
0 =
(3.25)
At t2 the link capacitance voltage (vlink ) becomes zero and all the four diodes in the active
rectifier start conducting to maintain the load current. Hence the expressions for il (t) and
vlink (t) are changed to
N Vdc
0
t t2
Ll
vlink (t) = 0
il (t) =
vsn (t) =
(3.26)
0

f or t = t2 : t3
vsn (t2 )
Hence the DC voltage source is exerted on Ll and the transformer secondary current starts
to ramp up.
0
When il (t) becomes equal to IR then Ll resonates with Cl to bring the link voltage quickly
to clamp capacitor voltage vsn and the corresponding expressions are
r
Cl
il (t) =
(N Vdc Vlink (t3 ))
sin {0 (t t3 )}
Ll
+IR + (il (t3 ) IR ) cos {0 (t t3 )}
r
Ll
vlink (t) = N Vdc + (il (t3 ) IR )
sin {0 (t t3 )}
Cl
+ (Vlink (t3 ) N Vdc ) cos {0 (t t3 )}

0
vsn (t) = vsn (t2 )
f or t = t3 : t3
(3.27)
61
At t3 , vlink reaches to vsn and the link voltage gets clamped to vsn . The resonance between
Ll and Csn pumps energy into Csn . The mathematical equations are similar to (3.27) with
0
vsn (t) = vlink (t) and t3 , 0 , Cl are being replaced by t3 , 1 , Csn respectively.
Interval 4 (t = t4 : t = t5 )
When all the leakage energy is absorbed in Csn , then Dsn stops conducting and steady
current equal to IR flows through Ll
il (t) = IR
(3.28)
vlink (t) = N Vdc

vsn (t) =
vsn (t4 )
f or t = [t4 : t5 ]
At t = t5 , switch Syb is turned off and Y-phase load current continues its path through Dyt .
The extra energy stored in Ll charges Cl and Csn in resonating manner and the link voltage
is clamped to vsn . The governing equations for this interval are same as (3.27) with t3 , 0 ,
IR , and Cl are replaced by t5 , 1 , IR IY , and Csn respectively.
At t = t6 , the current through Ll drops to IR IY and the current through Dsn becomes
zero. The link voltage maintains at N Vdc .
At t = t7 , A is turned off and anti-parallel diode of A starts conducting. As a result the
At the same time
current in the HF link inverter starts to free-wheel through DA and B.
il starts dropping as negative voltage is applied across it and the link capacitance starts to
discharge. The corresponding expressions are
r
Cl
il (t) = Vlink (t7 )
sin {0 (t t7 )} + IR IY
Ll
vlink (t) = vlink (t7 ) cos {0 (t t7 )}
vsn (t)
= vsn (t6 )
f or t = [t7 : t8 ]
(3.29)
62
When the link capacitor is completely discharged (t = t8 ) the all four diodes of the active
rectifier start to carry the load current IR IY . During this time Y is first turned on and
then X is turned off without affecting any circuit dynamics.
il (t) =
0
(3.30)
vlink (t) = 0
vsn (t) =
vsn (t6 )
f or t = [t8 : t9 ]
At t = t9 , the HF inverter switch B is turned on and Ll sees N Vdc applied across it. As a
result, the current through Ll starts increasing in negative direction.
il (t) =
N Vdc
(t t9 )
Ll
(3.31)
vlink (t) = 0
vsn (t) =
vsn (t6 )
f or t = [t9 : t10 ]
00
Interval 10 (t = t10 : t = t11 through t10 , t10 )

When the current through Ll increases up to the level of the load current (IR IY ) a

0
resonating phenomena occurs first between Ll and Cl t10 : t10 and then between Ll and
0
00
0
Csn t10 : t10 . The governing equations are similar to that in given for interval 3 with t3 , t3
0
are replaced by t10 , t10 respectively. When the leakage energy absorbed in Csn completely,
00

il (t) = (IR IY ) and vlink (t) = N Vdc for t = t10 : t11 .
Interval 11 (t = t11 : t = t12 )

In this interval Sbb is turned off and the load current starts to flow through top three devices.
The excess energy stored in Ll resonates with Csn and the bus voltage is clamped to vsn .
63
The resonating capacitor voltage and leakage inductor current can be written as
r
Csn
il (t) = (N Vdc vlink (t11 ))
sin {1 (t t11 )}
Ll
+il (t11 ) cos {1 (t t11 )}
r
Ll
sin {1 (t t11 )}
vsn (t) = N Vdc + il (t11 )
Csn
+ (vsn (t11 ) N Vdc ) cos {1 (t t11 )}
vlink (t) = vsn (t)
(3.32)
f or t = [t11 : t12 ]
Interval 12 (t = t12 : t = Ts /2 t1 )
At t = t12 , Ssn is turned on and the absorbed energy in Csn starts to transfer back to the
DC source. The governing equations for this interval are same as (3.32) with t11 , t12 are
replaced by t12 , Ts /2 t1 respectively.
3.5.3
Rectifier Mode
In case of rectifier mode, the current directions of R, Y, B phases are assumed exactly
opposite to that of the inverter mode (with same pattern of PWM signals given in Fig.
3.37). The corresponding equivalent active circuits are given in Fig. 3.41 Fig. 3.43. The
different intervals in the rectifier mode are explained in brief.
Interval 1
In this interval, the load current is free-wheeling through Srb , Dyb , Dbb and the energy stored
in Csn is fed back to DC side through Ssn .
Interval 2
When Srb is turned off the link capacitance initially discharges and then charges in a resonating manner with Ll . When vlink reaches to vsn , it is clamped to that value and the leakage
energy gets absorbed in Csn .
Interval 3
This interval starts when Syt is turned on. The change in the load current starts discharging
the link capacitance Cl and on the other hand negative magnitude of the current through Ll
64
(i)
+
Ll
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(ii)
+
Ll
S sn
Cl
C sn
(iii)
Ll
S sn
Cl
C sn
(iv)
Ll
S sn
Cl
C sn
S rb
Figure 3.41: Active equivalent circuits in rectifier mode for a particular half switching cycle:
(i) interval 1, (ii) interval 2, (iii) interval 3, (iv) interval 4
starts decreasing.
(v)
Ll
65
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(vi)
Ll
S sn
Cl
C sn
(vii)
Ll
S sn
Cl
C sn
(viii)
Ll
S sn
Cl
C sn
S rb
(v) interval 5, (vi) interval 6, (vii) interval 7, (viii) interval 8
Interval 4
When il becomes equal to (IR IY ), Ll starts resonating with Cl to bring the bus voltage
quickly up to vsn where it gets clamped and the leakage energy is absorbed in Csn . When
all the leakage energy is absorbed in Csn , Dsn is turned off.
66
(ix)
Ll
S sn
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S rb
S yb
S bb
S rt
S yt
S bt
S yb
S bb
S rt
Cl
C sn
(x)
Ll
S sn
Cl
C sn
(xi)
Ll
S sn
Cl
C sn
(xii)
Ll
S sn
Cl
C sn
S rb
(ix) interval 9, (x) interval 10, (xi) interval 11, (xii) interval 12
Interval 5
Next, A is turned on and the current on the HF bridge starts free-wheeling through A and
DB . The leakage inductance sees vlink across it and thus negative magnitude of il starts
increasing till vlink comes to zero.
67
Interval 6
At the beginning of this interval, Y is turned on and as a result all four devices of active
rectifier start to conduct. The free-wheeling in the HF inverter continues as there is no
voltage to change the current through the leakage inductance.
Interval 7
When X is turned off, then initially the leakage inductance current flows through DY (antiparallel diodes of Y ). Hence both load current and the leakage inductance current start to
charge Cl till the current through Ll reverses and equal to IR IY .
Interval 8
is turned off the current starts to flow through DA and DB . As a result, il increases
When B
to bring the link voltage towards N Vdc .
Interval 9
This interval is same as interval 4.
Interval 10
When Sbt is turned on, the load current starts to free-wheel through Drt , Syt , Sbt . the link
capacitor starts to discharge.
Interval 11
This interval starts when current through Ll changes its direction. This mode is similar as
interval 4.
Interval 12
At this interval Ssn is turned on and energy is transferred to the DC side through Ll .
68
Figure 3.44: Measured voltage of Vlink without snubber circuit, CH1 : 100V/div, time :
5sec/div
Figure 3.45: Measured voltage of vlink with active clamp, CH1 : 100V/div, time : 5sec/div
3.5.4
Experimental Results
The cycloconverter link voltage without any snubber capacitor is shown in Fig. 3.44. Because of the high voltage spikes at the cycloconverter link voltage it is almost impossible
to safely operate the system under nominal input voltage condition. Fig. 3.45 shows the
cycloconverter link voltage with active clamp circuit. It can be seen that the resonating
energy between Ll and Cl is absorbed by the clamped circuitry and associated over voltages
are avoided. The gate pulses for Ssn along with the control pulses for the H-bridge are shown
in Fig. 3.46. The active switch is turned on at the desired instant.
The efficiency comparison between the dissipative snubber (Fig. 3.34) and the active
clamp based snubber or regenerative snubber (Fig. 3.35) is carried out in Fig. 3.47. An
3.6. Conclusions
69
Figure 3.46: Measured generated control pulses, CH1 : A (5V/div), CH2 : B (5V/div), CH3
: Ssn (5V/div), time : 10sec/div
Figure 3.47: Efficiency comparison of active clamp with passive snubber

efficiency improvement of nearly 3% (at full load) is achieved because of the active clamp
circuit.
3.6
Conclusions
The proposed high frequency link power circuits are studied with various loading conditions.
Though the commutation scheme required for the topology is simple in nature it does not
70
ensure desired performances of the power circuit. A few such situations are studied and
suitable solutions are proposed. The proposed methods are well justified by the simulation
and experimental studies. The power circuit configuration is modified for three phase fourwire case to make it convenient for unbalanced loads (without using any split capacitor
configuration). This configuration will be studied in more detail along with closed loop
control in the next chapter.
Chapter 4
Proportional + Multiresonant
Controller based Decentralized
Parallel Operation
4.1
Introduction
The closed loop control of filtered inverter output voltage (by LC filter) is the major concern
of this chapter. The concentration is paid on a three-phase four-wire system and a general
loading situation (unbalanced and non-linear) is considered. Sinusoidal domain proportional
+ multiresonant controller is used for this purpose. The stability issues and LC resonance
damping are presented. Finally, the concept is extended to decentralized paralleling of
inverters. A simple output impedance is virtually imposed with proportional + multiresonant
controller based voltage regulation loop to achieve an excellent sharing accuracy for all sorts
of loads.
4.2
Voltage Regulation Loop with Proportional + Resonant Controller
For 3-phase 4-wire systems, the sinusoidal domain controllers are easier to implement and
more effective in performance compared to synchronously rotating reference frame controllers. This section gives an introduction with sinusoidal domain proportional + resonant
controller as an outer voltage regulation loop with an inner current loop (for better dynamic
response). The design procedures and stability issues are explained.
71
72
Chapter 4. Proportional + Multiresonant Controller based Decentralized Parallel Operation
4.2.1
Inner Current Loop and Damping of Resonance Oscillation
First, let us consider the configuration of the inner current loop. The inner loop variable
used here is inductor current for better resonance damping and power circuit protection [22].
Fig. 4.1 shows the configuration of the current loop with a proportional controller. Vi is the
IL (s)
inverter output voltage and
is the plants transfer function when the disturbance input
Vi (s)
Io is ignored. The plant transfer function is given by
IL (s)
sC
=
Vi (s)
1 + s2 LC
(4.1)
It is marginally stable and susceptible to resonance oscillation. From (4.1), the closed loop
transfer function can be derived as
sC
IL (s)
=
IL (s)
1 + sKc GC + s2 LC
(4.2)
Equation (4.2) clearly indicates that if the current controller gain (Kc ) is increased, better
damping of resonance oscillation can be achieved. Fig. 4.2 shows the corresponding root
locus for various values of Kc . For Kc 0.167, the oscillatory behaviour of the system is
completely eliminated. The closed loop transfer function in (4.2) is approximated as
I L*
Current
Controller
Power
Converter
Kc
Vi*
Vi
Plant
I L (s)
IL
Vi (s)
IL
Figure 4.1: Inner current loop and plant
IL (s)
sC
IL (s)
1 + sKc GC
(4.3)
for design verifications of the outer loop. This assumption is valid because there is considerable amount of steady state phase and magnitude error in current loop. This is clear from
the Bode plot of the closed loop transfer function for the inner current loop (shown in Fig.
4.3).
4.2. Voltage Regulation Loop with Proportional + Resonant Controller
73
Root Locus
6000
4000
Imaginary Axis
Gain = 0.167
2000
0
2000
4000
6000
8000 7000 6000 5000 4000 3000 2000 1000
Real Axis
Figure 4.2: Root locus plot of current loop

Bode Diagram
Magnitude (dB)
10
0
10
20
30
Phase (deg)
40
90
45
0
45
90
0
10
10
10
10
Frequency (Hz)
Figure 4.3: Bode plot of
4.2.2
IL (s)
IL (s)
Outer Voltage Loop and Stability Analysis
From the inner current loop gain function (Fig. 4.3), it may appear that a simple PI controller
with high bandwidth may be used to achieve voltage control. In such a case, the DC gain of
the loop will be infinity. It is found that such a controller gives rise to starting problems since
this high DC gain sometimes leads the control to get into over-modulation. Therefore the
74
strategy to obtain stable operating point as well as good steady state performance requires
unconventional compensator design.
The structure of the outer voltage loop with P + resonant controller is shown in Fig. 4.4.
Because of limitations in practical implementations true resonant controller can not be used
[17]. Fig. 4.4 shows the approximate resonant controller with cut off frequency cut . The
output of the voltage controller is the reference input for the inner current controller (the
inductor current reference IL ). Fig. 4.4 also shows the approximate current loop transfer
function (as given in (4.3)) and load current Io as disturbance input. Ignoring the disturbance
Voltage Controller
Vc*
KP +
K i cut s
s2 + 2 cut s + 2o
I L*
I L (s)
I L*(s)
Io
IL
sC
1+K c GsC
Plant
1
sC
Vc
Vc
Figure 4.4: P + resonant controller for fundamental component
input, the characteristics equation of the outer voltage loop is given in (4.4).

s3 Kc GC +s2 {1 + Kp + 2cut Kc GC}+s (2 + 2Kp + Ki ) cut + o2 Kc GC +o2 (1 + Kp ) = 0
(4.4)
The stability criteria can be checked from Routh array as follows.
s3 : Kc GC
(2 + 2Kp + Ki ) cut + o2 Kc GC
s2 : 1 + Kp + 2cut Kc GC
o2 (1 + Kp )
s1 : (2 + 2Kp + Ki ) cut +
s0 : o2 (1 + Kp )
2cut (Kc GCo )2

1 + Kp + 2cut Kc GC
0
0
(4.5)
As for all possible values of Kp > 0 and Ki > 0 the first row of Routh array has no sign
change, the system stability is ensured for all values of Kp and Ki . Hence, it is possible to
achieve a high steady state response for fundamental frequency o . This controller structure
shown in Fig. 4.4 is a single phase equivalent of three phase controller. This control structure
is sufficient to handle both balanced and unbalanced loading conditions.
4.3. Proportional + Multiresonant Controller and Stability Issues
4.3
4.3.1
75
Proportional + Multiresonant Controller and Stability Issues

Extension to Non-linear Loads
When the load on the power supply is non-linear in nature (like rectifier load), the output
voltage contains predominantly 5th and 7th harmonics other than fundamental. The control
structure shown in Fig. 4.4 is not sufficient to reject the disturbing effect of the load current
on the output voltage. Two separate resonant controllers (as shown in Fig. 4.5) for 5th and
7th harmonic components are added with the fundamental in the outer voltage loop [52]. The
Voltage Controller
Vc*
Vc
K i cut s
KP + 2
s + 2 cut s + 2o
I L*
Ki5 cut5 s
s2 + 2 cut5 s + (5o)2
Ki7 cut7 s
s2 + 2 cut7 s + (7o)2
Figure 4.5: P + multi-resonant controller for fundamental and harmonic (5th and 7th ) components
magnitudes of Ki5 and Ki7 determine the steady state error for 5th and 7th harmonic components respectively. The stability analysis for this controller structure using Routh array
criteria involves very complicated mathematical calculations. To maintain the simplicity, an
alternate procedure (using bode plots) is used to determine the controller parameters. When
Ki5 and Ki7 are set to zero then controller structure is suitable only for linear loads (Fig.
4.6). Now if these values are increased gradually (for example 0, 2, 4 1 etc. in Fig. 4.6),
the steady state error for 5th and 7th harmonic components decreases and on the other hand,
the phase margin gradually drops. Finally, for Ki5 = Ki7 = 6 1 (corresponds to a magnitude > 40 dB at 5th and 7th harmonic frequencies) the steady state error is less than 1% for
these two harmonic components. Hence from this design criteria, Ki5 and Ki7 are selected.
Of course, these values can be further increased to achieve better performance. However, for
76
Ki5 = Ki7 = 4 1 it can be seen from the bode plot that the phase margin is significantly
low and its effect leads to an unwanted oscillation in the output voltage waveform (Fig. 4.7).
For Ki5 = Ki7 = 6 1 (corresponds to desired steady state error for harmonic components)
the system is unstable (phase margin = 1 ). In order to mitigate such problem and to
reduce the steady state error for harmonics below desired limit, the control structure need
to be modified as explained in the next subsection.
Bode Diagram
Magnitude (dB)
50
0
Ki5 =Ki7 =0
50
Ki5 =Ki7 =2
100
Ki5 =Ki7 =4
Ki5 =Ki7 =6
Phase (deg)
150
90
0
90
180
270
10
10
Frequency (Hz)
10
10
Figure 4.6: Bode plot of voltage loop for different values of Ki5 and Ki7 in 1
4.3.2
Proposed Control Scheme
From Fig. 4.6, it is interesting to note that the magnitude plot of the open-loop transfer
function of the voltage loop is crossing 0 dB line at 40 dB/dec for the selected values of Ki5
and Ki7 (dotted line). This can be compensated by adding a suitable lead-lag compensator
as shown in Fig. 4.8.
The design procedure given in [53] is followed here to select the
parameters of lead-lag compensator. For a specified phase margin of 45 the design procedure
is explained in brief as follows.
Additional phase lead required (m ) = specified phase margin phase margin of the
uncompensated system (i ) + , where is the margin of safety required by the fact that
gain crossover frequency will increase due to compensation. By iterative method [53] is
selected as 3 . Hence, m = 45 (1) + 3 = 49 . If = x , the ratio x can be found out
77
200
200
0.16
Load Current (Amp)
Output Voltage (Volt)
0.165
0.17
0.175 0.18 0.185

Time (sec)
0.19
0.195
0.2
0.165
0.17
0.175 0.18 0.185

Time (sec)
0.19
0.195
0.2
4
2
0
2
4
0.16
Figure 4.7: Simulation result: oscillatory output voltage with Ki5 = Ki7 = 4 1
Vc*
Vc
K i cut s
KP + 2
s + 2 cut s + 2o
Ki5 cut5 s
1+s
1+s
I L*
Leadlag
Compensator
s2 + 2 cut5 s + (5o)2
Ki7 cut7 s
s2 + 2 cut7 s + (7o)2
Figure 4.8: Proposed control structure for outer voltage loop
as [53],
x=
1 sinm
= 0.1398
1 + sinm
(4.6)
1
From Fig. 4.6 (dotted line), the frequency corresponding to the gain 20log( ) is 24818
x
rad/sec (say m ). The difference between original phase margin of the uncompensated
system (i ) and phase margin of the uncompensated system at this new expected crossover
frequency m should be less than . If it is not so, the above procedure need to be iterated
78
Bode Diagram
Magnitude (dB)
50
0
50
Without Compensation
With Compensation
100
Phase (deg)
150
90
0
90
180
270
10
10
Frequency (Hz)
10
10
Figure 4.9: Bode plot of voltage loop for selected values of Ki5 and Ki7 with and without
200
200
0.16
Load Current (Amp)
Output Voltage (Volt)
lead-lag compensation
0.165
0.17
0.175 0.18 0.185

Time (sec)
0.19
0.195
0.2
0.165
0.17
0.175 0.18 0.185

Time (sec)
0.19
0.195
0.2
4
2
0
2
4
0.16
Figure 4.10: Simulation result with selected values of Ki5 and Ki7 and lead-lag compensator
with an higher value of . Next, the value of and can be calculated as
=
1
= 108 sec = x = 15 sec
xm
(4.7)
The lead-lag compensator corrects the phase margin to a great extent with the selected
79
values of Ki5 and Ki7 (Fig. 4.9) and helps to achieve negligibly small steady state error
for harmonic components. Again from Fig. 4.9, the gain margin is also quite high for the
compensated system. Adequate gain margin and phase margin ensures an oscillation free
output voltage (Fig. 4.10). The controller parameters are listed in Table. 4.1. In Table. 4.1,
Pout , Vin , Vo , f , 1 : N , L, C, Kc , Kp , Ki , Ki5 , Ki7 , cut , cut5 , cut7 , and denote power
rating, input, output, switching frequency, turns ratio of the transformer, filter inductance,
filter capacitance, current controller proportional gain, voltage controller proportional gain,
voltage controller steady state gain for fundamental, voltage controller steady state gain for
5th harmonic component, voltage controller steady state gain for 7th harmonic component,
cut-off frequency for fundamental controller, cut-off frequency for 5th harmonic controller,
cut-off frequency for 7th harmonic controller, time constant-1 and time constant-2 of lead-lag
compensator respectively.
4.3.3
The laboratory setup with digital controller is shown in Fig. 4.11. Three inductor currents
and three output capacitor voltages are sensed through analog-to-digital converters (ADCs)
and the FPGA controller performs the desired control action as described in the previous
section. Finally, the optically isolated and buffered gate pulses are given to the power circuit.
Proposed
Power
Converter
Gate Driver and

Optical Isolation
FPGA
Controller
Figure 4.11: Experimental setup with digital controller
L
O
A
D
80
Table 4.1: Power and Control Circuit Details

Symbol
Value
Pout
1kV A
Vin
120V DC
Vo
220V L-L 3 4-wire
20kHz
1:N
1:4
4 mH
10 F
Kc
1.28
Kp
0.0125 1
Ki
1.8 1
Ki5
6 1
Ki7
6 1
cut
31.41 rad/sec
cut5
157.08 rad/sec
cut7
219.9 rad/sec
108 sec
15 sec
Fig. 4.12 shows the unbalanced three phase currents with R-phase load completely open
circuited. The fourth wire current is also shown in the same figure. It contains common
mode switching components other than fundamental due to unbalance. The corresponding
output three phase voltages are shown in Fig. 4.13. The unbalance in the voltages is 3.2%
according to the defination of unbalance given in (4.8).
unbalance =
maximum RM S V oltage minimum RM S V oltage

100%
Rated RM S V oltage
(4.8)
81
Figure 4.12: Three phase unbalanced load currents (CH1, CH2, CH3: 3A/div) and zero
sequence current through fourth wire (CH4: 5A/div) Time: 5msec/div
Figure 4.13: Three phase output voltage under unbalanced loading (CH1, CH2, CH3:
100V /div) Time: 5msec/div
Next, the performance of the system is investigated with non-linear rectifier type loads.
Fig. 4.14 shows the R-phase output voltage and load current when Ki5 and Ki7 are kept low
(to maintain stable operation) and lead-lag compensation is not added and the corresponding
Fourier spectrum are shown in Fig. 4.15. If the steady state gains of the harmonic controllers
82
Figure 4.14: R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with low
values of Ki5 and Ki7 , time: 10msec/div
100
80
60
40
20
10
15
Harmonics Order
20
25
Figure 4.15: Fourier spectrum of a-phase output voltage in Fig. 4.14: THD = 6.94%
are increased to reduce the harmonic content in the output voltage further, an oscillatory
behaviour is observed in the voltage waveform (Fig. 4.16). Fig. 4.17 shows R-phase output
voltage with the load current after the lead-lag compensation is added (with desired values of
Ki5 and Ki7 ) and the Fourier spectrum of the voltage is shown in Fig. 4.18. It is interesting
to note that the total harmonic distortion (THD) of the output voltage is improved from
6.94% to 2.88%.
4.4. Decentralized Parallel Operation
83
Figure 4.16: R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with Ki5
= Ki7 = 4 1 and without lead-lag compensation, time: 10msec/div
Figure 4.17: R-phase output voltage (CH1: 100V /div) and current (CH2: 2A/div) with
selected values of Ki5 and Ki7 and with lead-lag compensation, time: 10msec/div
4.4
Decentralized Parallel Operation
The proportional + multiresonant voltage controller based communication-less paralleling

technique is proposed in this section. The proposed control scheme combines the band pass
filters in the virtual output impedance loop and the voltage controller and requires a simple
design procedure. It helps to achieve excellent sharing accuracy (for all kinds of loads:
balanced, unbalanced and harmonics) and the output voltage waveform quality along with
a simple virtual output impedance loop.
84
100
80
60
40
20
10
15
Harmonics Order
20
25
Figure 4.18: Fourier spectrum of R-phase output voltage in Fig. 4.17: THD = 2.88%
4.4.1
The Proposed Control Structure
The power circuit of the three-phase four-wire paralleled inverters are shown in Fig. 4.19.
The high frequency link topology based three-phase four-wire inverters are used for parallel
operation. The inverters are of unequal power ratings [54] and their parameters are listed in
Table. 4.2. The non-linear and unbalanced loads are also shown in Fig. 4.19. The inverters
are connected to the load through tie wires. The control objectives are to share the load
(unbalanced and non-linear) current in the same proportion to the ratings of the inverters.
The proposed control scheme of the decentralized paralleling is shown in Fig. 4.20 Fig.
4.24 and it consists of five different stages as follows:
calculation of P and Q for each phase
3 P/Q droop characteristics
voltage reference generation with virtual output impedance loop
proportional + multiresonant controller based voltage regulation loop
start up phase locked loop (PLL)
85
Inverter
#
1
Nonlinear
and
Unbalanced
Inverter
#
2
Loads
Tie wire
Figure 4.19: Two 3 4-wire inverters in parallel
Table 4.2: Details of High frequency link 3 4-wire Inverters
4.4.1.1
INV#1
INV#2
Rating
1 kVA
0.5 kVA
4 mH
8 mH
rL
0.1
0.18
10 F
5 F
Output Voltage
220 V L-L
220 V L-L
Switching frequency
20 kHz
20 kHz
Tie wire
0.04 + j0.006
0.06 + j0.009
Calculation of P and Q for Each Phase
The active and reactive power shared by the converter are evaluated from the measured
signals. Fig. 4.20 shows the calculation of P and Q for each of the phases. The output
capacitor voltage Vc and the output current shared by the converter Io are used to determine
86

Vca I oa
Vcb I ob
o
90
90
1
P ia
Vcc I oc
90
1
Qia
P ib
1
Qib
P ic
Qic
LPF
LPF
LPF
LPF
LPF
LPF
Pa
Qa
Pb
Qb
Pc
Qc
Figure 4.20: Per phase active and reactive power calculation

E*
Pa
Pb
Pc
Qa
Qb
Q3ph
Qc
P 3ph
E*m
*
+
ref
Figure 4.21: 3 droop technique for three-phase four-wire system

the instantaneous active and reactive power as follows.
Pi
= Vc Io
Qi = Vc Io (90 )
(4.9)
where Pi and Qi are the instantaneous active and reactive powers respectively. The 90
phase shift in Io is required to calculate the reactive power. Then, Pi and Qi are processed by
low pass filters (LPF) in order to eliminate the oscillatory component. The cut off frequencies
of the low pass filters are selected as one decade below the line frequency.
87
R D I oa
E*m
= t
LUT
120
+
120
sine
LUT
sine
*
Vcb
V*cc
R D I oc
E*m
*
Vca
R D I ob
E*m
sine
LUT
Figure 4.22: Reference generation for the output voltage controller with virtual output
impedance loop
Vca
Vd
V*d = 0
ff
Vcb
Vcc
dq
Vq
= t
pll
0
ref
inverter_on
(logic signal)
Figure 4.23: Start up PLL with inverter active status signal

4.4.1.2
3 P/Q Droop Characteristics
Total three phase active and reactive power can be obtained by simply adding per phase
P and Q values. These three phase active powers (P3ph and Q3ph ) do not contain any
oscillatory component (due to low pass filtering in Fig. 4.20) and thus can be treated as
positive sequence active and reactive powers. The frequency and magnitude of the voltage
references of each phase are determined by P3ph and Q3ph as follows (Fig. 4.21)
Em
= E nP3ph = E n (Pa + Pb + Pc )
ref = + mQ3ph = + m (Qa + Qb + Qc )
(4.10)
Leadlag
V*ia
I *La
+
Compensator
P + Multiresonant
Controller
with resonant peaks
at , 3 , 5 , 7
Leadlag
V*ib
I *Lb
+
Compensator
Leadlag
Compensator
I *Lc
+
V*ic
+
I Lc
Vcc
Voltage Controller
Compensator
for stability
Vcb
I Lb
P + Multiresonant
Controller
with resonant peaks
at , 3 , 5 , 7
Vcb
V*cc
Vca
I La
Vca
V*cb
INVERTER
P + Multiresonant
Controller
with resonant peaks
at , 3 , 5 , 7
V*ca
Modulator and driver
88
Vcc
Current
Controller
Figure 4.24: Proportional + multiresonant controller based inner voltage regulation loop
The droop characteristics [in (4.10)] guarantee to bring the phase angles and voltage magnitudes of the units to a equilibrium point and thus eliminate circulating current completely
at steady state.
4.4.1.3
Voltage Reference Generation with Virtual Resistive Output Impedance

Loop
With the help of the generated amplitudes (Em

) and frequency (ref ), the voltage references
can be obtained as (Fig. 4.22),
Vca
Em
sin (t) RD Ioa

V = E sin (t 120 ) RD Iob

cb m
Vcc
Em
sin (t + 120 ) RD Ioc
(4.11)
At the present moment, assume that ref and are same (the detailed explanations will
be given later). In (4.11), RD represents the virtual resistive output impedance. Its design
procedure is explained in the next section.
4.4.1.4
Proportional + Multiresonant Controller Based Voltage Regulation Loop
The block diagram of the inner voltage regulation loop based on P + multiresonant controller is shown in Fig. 4.24. The controller structure is suitable for linear, non-linear and
89
unbalanced loads due to its resonant peaks at 0 , 30 , 50 , 70 . Note that a resonant peak
at 30 is added with the previously described control structure (in previous section). It helps
to improve the output voltage waveform with third harmonics loads. The transfer function
of the controller is given by,
Ki1 cut1 s
Ki3 cut3 s
2 + 2
+ 2cut1 s + (0 )
s + 2cut3 s + (30 )2
Ki7 cut7 s
Ki5 cut5 s
+
+
2
s2 + 2cut5 s + (50 )
s2 + 2cut7 s + (70 )2
= Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)
Gc (s) = Kp +
s2
(4.12)
where Kp is the proportional constant, Ki1 , Ki3 , Ki5 , Ki7 are the resonant constants for
the frequency components 0 , 30 , 50 , 70 respectively; cut1 , cut3 , cut5 , cut7 are the
respective cutoff frequencies; R1 (s), R3 (s), R5 (s), R7 (s) are the transfer functions of the
respective resonant parts. The design procedures of these parameters in connection with the
parallel operation are explained in the next section.
In Fig. 4.24, the error voltages are given to the controllers and the controller outputs are
passed through the lead-lag compensator [LL (s)] in order to achieve a stable voltage loop
(discussed in the previous section). The dynamic response of the system can be improved
further by adding a inductor current loop (optional). The current controllers are proportional
type and its proportional gain can be calculated as,
Kc =
L
G4T
(4.13)
where L is the output inductor of the inverter, G is the gain of the converter and 4T is
the sampling time. The current controller outputs are added with the feed-forward output
capacitor voltages to relieve the burden on the current controllers. Next, three inverter
reference voltages (Via , Vib , Vic ) are given to the power circuit through the modulator and
driver.
4.4.1.5
Start up PLL
When one inverter is already in operation and the next unit need to be turned on (as a
parallel unit), there is no information about the phase angle of the former. The conventional
large initial droop start up works well when the phase angle difference between two units is
small. But in practical situation it could be a large value. In such cases phase locked loop
90
based start up is more convenient to completely eliminate the circulating current at start
up.
The d-q frame based start up PLL [55] is shown in Fig. 4.23. Any other configuration
of the PLL also can be used. In Fig. 4.23 are first converted to 2 phase () and then
to d-q coordinate system. The d-axis component of the output capacitor voltage is forced
to zero by a PI controller. The output of the PI controller is added with the feedforward
frequency term (f f ) to generate pll . If this frequency (pll ) is integrated to generate
(which inturn is used for d-q transformation), the PLL gets closed. As the phase angle is a
continuous quantity, hence only a single integrator is used (in Fig. 4.22) to generate = t.
The frequency input to this integrator () is either pll or ref (frequency reference from
the droop blocks in Fig. 4.21) depending upon the inverter on status/logic signal. Table.
4.3 gives the relationship of inverter on and . Before the inverter is turned on the PLL
synchronizes (hence voltage references in Fig. 4.22) with the bus voltages and keeps the
converter ready to be switched on. Whenever it turns on, the logic signal inverter on goes
high and transfers the system under the droop characteristics.
Table 4.3: Logic relationship between inverter on and
Inverter status
inverter on
OFF
pll
ON
ref
4.4.2
Controller Design and Parameter Selection
4.4.2.1
Inner Voltage Regulation Loop
The 1 equivalent of 3 4-wire system is shown in Fig. 4.25(a). The dynamic equation of
the system can be written as (4.14).
dIL
= Vi Vc rL IL
dt
dVc
C
= IL Io
dt
By eliminating IL from (4.14) we have,
L
LC
d2 Vc
dVc
dIo
+ rL C
+ Vc + L
+ rL Io = Vi
2
dt
dt
dt
(4.14)
(4.15)
Vi
Vc
Ztie
Zoe (s)
Io
V*c_p G(s)
Vc
load
1
inverter
equivalent
IL
rL
91
(b)
(a)
Figure 4.25: (a) 1 equivalent circuit of the power circuit (b) Inverter equivalent circuit with
the closed loop
This is the differential equation describing the plant. On the other hand, if we concentrate
on the controller part we can write from (4.12),
Vi = [(Vc Vc ) {Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)} LL(s) IL ] Kc G
(4.16)
where LL(s) is the transfer function of the lead-lag compensator and Kc is the proportional
gain of the current controller. By combining (4.15) and (4.16) and putting IL = Io + sCVc
we get,
Vc = G(s)Vc Zo (s)Io
(4.17)
where G(s) and Zo (s) are respectively the control transfer function and the output impedance
transfer function and are given in (4.18).
{Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)} LL(s)kc G
1 + (rL C + Kc GC)s + LCs2 + {Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)} LL(s)Kc G
rL + Kc G + sL
Zo (s) =
2
1 + (rL C + Kc GC)s + LCs + {Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)} LL(s)Kc G
(4.18)
G(s)
In (4.18), G(s) is the closed loop transfer function of the voltage loop. The open loop transfer
function of the voltage loop is given by,
Gop (s) =
{Kp + R1 (s) + R3 (s) + R5 (s) + R7 (s)} LL(s)Kc G

1 + (rL C + Kc GC)s + LCs2
(4.19)
In order to select the controller parameters and to investigate about the stability of the
voltage controller, Gop (s) is converted to discrete domain [Gop (z)] using MATLAB. This
discrete transfer function also includes the effect of the sampling time. The resonant peaks
of the voltage controller (at 0 , 30 , 50 , 70 ) are chosen greater than 40dB (Fig. 4.26) so
that the steady state errors at these frequencies remain less than 1%. Fig. 4.26 also shows
92
the location of the closed loop poles (as coloured squares) in z-plane. The position of all
these poles inside the unit circle implies a stable system. The relative stability of the system
can also be judged from the phase margin (50 ) and gain margin (11dB) of the system. The
bandwidth of the voltage loop is selected as 2 kHz (Fig. 4.26) to ensure a high dynamic
response. The bode plot of the closed loop transfer function G(z) is shown in Fig. 4.27. Fig.
4.27 shows that G(z) provides unity gain and zero phase shift at desired frequencies 0 , 30 ,
50 , 70 (the frequencies are shown with blue vertical lines).
Figure 4.26: Design of the inner voltage loop in z-domain
4.4.2.2
Virtual Resistive Output Impedance Loop
Once the voltage loop parameters are selected, the output impedance Zo (s) gets fixed. Fig.
4.28 shows the bode plot of Zo (z) [Zo (s) in discrete domain] with and without the effect
of the tie wire for inverter-1. The tie wire impedance are shown in Table. 4.2. It can be
observed that Zo (z) without tie wire have very low gains at 0 , 30 , 50 and 70 . The use of
P + multiresonant controller helps to achieve this behaviour and thus eliminates the effect of
the inverter output inductor drop on the output voltage waveform quality. But the presence
93
Figure 4.27: Closed loop Bode plot of the voltage loop, G(z)
of the tie wire impedance causes a significant change in the overall output impedance (Fig.
4.28). The tie wire impedances for the various inverters are usually different and it leads
to a mismatch in the output impedances of the inverters. This effect is shown in Fig. 4.29.
The tie wire impedances are intentionally taken different (Table. 4.2). For perfect parallel
operation between INV1 and INV2, the phase angles of Zo1 and Zo2 should be same and the
magnitude ratio |Zo2 |/|Zo1 | should be equal to KV A1 /KV A2 (= 2 in the present case). But
it can be observed from Fig. 4.29 the situation is well apart from the ideal.
In order to improve the sharing accuracy a small value of RD (as virtual output impedance
loop) is added. Equation (4.17) can be rewritten as

Vc = G(s) Vcp RD Io Zo (s)Io
= G(s)Vcp Zoe (s)Io
(4.20)
where Zoe (s) = Zo (s)+RD G(s) is the effective output impedance of the inverter. The inverter
equivalent circuit with closed loop and the tie wire impedance (Ztie ) is shown in Fig. 4.25(b).
94
Figure 4.28: The output impedance Zo1 with and without tie wire impedance
Let us first investigate the effect of increasing RD on Zoe without taking into account the
tie wire impedance. With increasing RD , Zoe becomes more and more resistive at desired
frequencies (Fig. 4.30) and interestingly, the magnitudes and phase angles of the effective
output impedance at 0 , 30 , 50 , 70 approach towards a same magnitude (20logRD ) and
a same phase angle (0 ) respectively. Due to this behaviour of Zoe the sharing of all sorts of
loads (balanced, unbalanced and harmonics) can be treated identically.
Next important consideration is the selection of RD . Fig. 4.31 shows the effect of increasing RD on the overall output impedance mismatch between the two inverters (considering the
tie wire impedances). It can be noticed that when RD1 = 0.4 and RD2 = 0.8 (RD2 = 2RD1 )
the effect of tie wire impedance is almost invisible. By increasing RD further the situation
can be made still better but the output voltage waveform quality degrade with increasing
RD (explained in the next subsection). With the final values of RD1 and RD2 , the bode plot
of Zo1e and Zo2e with the tie wires are shown in Fig. 4.32.
95
Figure 4.29: Effect of tie wire impedance on Zo1 and Zo2

4.4.2.3
Outer P/Q Sharing Loop
In order to investigate the dynamic behaviour and the stability of the outer P/Q sharing
loop, a small signal analysis [25, 56] is carried out. Considering the effect of the low pass
filter the dynamic equation of the system can be written as
+ 4
4
= m4Q3ph
+ 4E = n4P3ph
4E
(4.21)
where the perturbed values are indicated by 4, and is the time constant of the low pass
filter. 4P3ph and 4Q3ph can be expressed as,
4P3ph
4Q3ph
3V
[cos4E Esin4]
RD
3V
=
[sin4E + Ecos4]
RD
=
(4.22)
96
Figure 4.30: Effective output impedance Zo1e with RD1 variation (without considering tie
wire)
By combining (4.21) and (4.22) we get the state space representation of the system as
X = AX, where the system matrix A and the states X are given as
A=
0
1
0
4
1
mV
mEV
cos
3
sin
3

RD
RD
; X = 4
nEV
nV
1
4E
3
sin
0 3
cos +
RD
RD
(4.23)
The characteristics equation of the system |sI A| = 0 gives the location of the system
poles. These poles with various values of RD are mapped in z-domain (with the information
of the sampling time) and the corresponding locus is shown in Fig. 4.33. It can be observed
that with increasing value of RD the relative system stability improves and system dynamics
becomes more damped. But the system dynamics can not be improved to a great extend by
varying RD ; the droop/boost control scheme [24, 57] can be adopted for this purpose. On
97
Figure 4.31: Effect of increasing RD on |Zo2e |/|Zo1e | and on the phase difference 4 between
Zo1e and a pure resistance at different frequencies
the other hand, the droop coefficients (m, n) are selected such that the respective parameters
of the voltage references (ref , E) degrade by less than 1% of their rated nominal values at
the rated loading conditions. All the control parameters are listed in Table. 4.4. Please note
that the cut off frequencies are chosen smaller compared to that in the previous section to
get better performances.
4.4.3
Simulation Studies
In order to check the sharing accuracy of the proposed scheme a simulation study is made.
The power circuit and control circuit details provided in Table. 4.2 and Table. 4.4 are used
for the simulation studies. Fig. 4.34(a) and Fig. 4.34(b) show the sharing of unbalanced
loads and the corresponding voltages with RD1 = 0.04 and RD1 = 0.4 (RD2 = 2RD1 )
respectively. The same study with harmonic loads is shown in Fig. 4.35(a) and Fig. 4.35(b).
98
Figure 4.32: Effect of tie wire impedance on Zo1e and Zo2e

From Fig. 4.34 and Fig. 4.35, it can be observed that the sharing accuracy improves (error
in sharing decreases) and the output voltage waveform quality (voltage unbalance ratio and
THD) degrades with increasing values of RD . This observation is summarized with a series
of values of RD (by repetitive simulation studies) in Fig. 4.36.
4.4.4
Experimental Evaluation
Two 3 4-wire inverters (1 kVA and 0.5 kVA) are tested in parallel. The details of the power
circuit is given in Table. 4.2. In order to avoid large tie wires, separate impedances are used
to achieve the effect of the tie wire impedances (given in Table. 4.2). For closed loop control
implementation an FPGA based digital controller is used. The various controller parameters
and the droop coefficients are listed in Table. 4.4. The experimental results are presented
99
Figure 4.33: Locus of the pole location of the outer P/Q sharing loop with RD variation
(a) With RD1 = 0.04 and RD2 = 0.08
(b) With RD1 = 0.4 and RD2 = 0.8
Figure 4.34: Simulation result: unbalanced load sharing and the 3 output voltages
100 Chapter 4. Proportional + Multiresonant Controller based Decentralized Parallel Operation
Table 4.4: Controller Parameters and Droop Coefficients

Parameters
INV#1
INV#2
unit
Kp
7.2
3.6
Ki1
3192
1596
Ki3
2316
1158
Ki5
3548
1774
Ki7
3258
1629
cut1
3.14
3.14
rad/s
cut3
9.42
9.42
rad/s
cut5
15.70
15.70
rad/s
cut7
21.99
21.99
rad/s
Kc
0.33
0.66
1.57 103
3.14 103
rad/s/VAR
1.8 103
3.6 103
V/W
RD
0.4
0.8
in the following subsections.

4.4.4.1
Steady State Performance
The sharing accuracy of the inverters is first verified at steady state with non-linear and
unbalanced loads. Fig. 4.37 shows the a-phase output currents (Ioa1 and Ioa2 ) of the inverters with non-linear loads. It can be seen that the inverters are sharing the load current
proportionately to their power rating. The a-phase output voltage (Vca ) is also shown in
the same figure. The harmonic contents in Vca is shown in Fig. 4.38. The total harmonic
distortion of Vca is less than 3.0%.
Fig. 4.39 shows the unbalanced loading on the inverters. The b- and c- phase loads
are resistive in nature and equal; a-phase load is resistive-capacitive type and the current
magnitude is also different from that of b- and c- phase load currents. The Fig. 4.39 shows
(a) With RD1 = 0.04 and RD2 = 0.08
101
(b) With RD1 = 0.4 and RD2 = 0.8
Figure 4.35: Simulation result: harmonics load sharing and the 3 output voltages
Figure 4.36: Simulation result: trade off between error in sharing accuracy (ESA), voltage
unbalance ratio (VUR), total harmonic distortion of the output voltage (THD)
Figure 4.37: Sharing of non-linear loads: CH1: a-phase output voltage Vca (180 V/div),
CH2: INV#1 a-phase output current Ioa1 (4 A/div), CH3: INV#2 a-phase output current
Ioa2 (2 A/div), time: 5 ms/div
Figure 4.38: The Fourier spectrum of Vca in Fig. 4.37

only a- and b- phase output currents for both the inverters. The result demonstrates the
effectiveness of the proposed control algorithm to share the unbalanced and reactive loads
accurately. The corresponding 3 voltage waveforms are shown in Fig. 4.40. The degree
of unbalance in the 3 output voltages is noticeably small. Fig. 4.41 shows the trade off
between the output voltage quality and the sharing accuracy with various values of RD1 .
It can be noticed that the performances measured are nearly similar to that in simulation
103
Figure 4.39: Sharing of unbalanced loads: CH1: Ioa1 (2 A/div), CH2: Ioa2 (1 A/div), CH3:
Iob1 (2 A/div), CH4: Iob2 (1 A/div), time: 10 ms/div
Figure 4.40: Three phase output voltages with unbalanced loads: CH1: Vca (90 V/div),
CH2: Vcb (90 V/div), CH3: Vcc (90 V/div), time: 10 ms/div
studies. As the simulation study does not include various non-idealities like dead-time in the
inverter, delay in the measurements etc., the experimental evaluation slightly deviates from
the simulation studies. The performance of the system is compatible with the recommended
standards for stand alone AC power supplies [58].
4.4.4.2
Transient Performance with Start Up PLL
Fig. 4.42 shows the transient turn on of the second converter without start up PLL when
inverter#1 is already in operation. The circulating current among the inverters becomes
very high immediately after the turn of the second converter. Fig. 4.43 and Fig. 4.44
Figure 4.41: Experimental result: trade off between error in sharing accuracy (ESA), voltage
unbalance ratio (VUR), total harmonic distortion of the output voltage (THD)
Figure 4.42: Transient turn on of INV#2 when INV#1 is supplying non-linear loads without
start up PLL: CH1: INV#1 a-phase inductor current ILa1 (4 A/div), CH2: INV#2 a-phase
inductor current ILa2 (2 A/div), time: 20 ms/div
show the start up of the second converter with start up PLL with linear and non-linear
loads respectively. With the start up PLL the circulating current is eliminated almost
completely. It can be observed that the second converter picks up its desired load within
three fundamental cycles after the starting.
Fig. 4.45 shows the transient sharing accuracy of the inverters during a sudden increase
in the load current. The inverters are found to be quite effective in sharing the load current
4.5. Conclusions
105
Figure 4.43: Transient turn on of INV#2 when INV#1 is supplying non-linear loads with
start up PLL: CH1: INV#1 a-phase inductor current ILa1 (4 A/div), CH2: INV#2 a-phase
inductor current ILa2 (2 A/div), time: 20 ms/div
Figure 4.44: Transient turn on of INV#2 when INV#1 is supplying unbalanced loads with
start up PLL: CH1: ILa1 (4 A/div), CH2: ILa2 (2 A/div), CH3: ILb1 (4 A/div), CH4: ILb2
(2 A/div), time: 20 ms/div
even during the transients.
4.5
Conclusions
The voltage regulation loop based on proportional + multiresonant controller is explained

in this chapter. The experimental results show that an excellent output waveform quality
can be achieved with harmonics loads by using such voltage regulation loops. A stability
problem is identified and solved by using a lead-lag compensator. Next, the decentralized
Figure 4.45: Performance of the inverters with a transient increase in the load current: CH1:
Ioa1 (4 A/div), CH2: Ioa2 (2 A/div), time: 20 ms/div
parallel operation is described. The communication-less operation is achieved by using P/Q
droop technique. The sharing accuracy is improved by adopting a resistive virtual output
impedance loop. This output impedance loop along with proportional + multiresonant
controller offers a trade off between the output voltage waveform quality and the sharing
accuracy. The selection of various control parameters need to be done depending upon the
requirements. The simulation and experimental results are provided in order to verify the
effectiveness of the the proposed scheme.
Chapter 5
Grid Interactive Modes
5.1
Introduction
The first part of this chapter focuses on a shunt compensator suitable for both balanced
and unbalanced operating conditions of the grid. The controller structure is same as that
discussed in the previous chapter. Only difference is that here the controller is used for
the current loop instead of the voltage regulation loop. A resonant filter is used in the DC
bus loop and in the phase locked loop to filter out the unwanted components and thus to
improve the system performance. Next, a three winding high frequency transformer based
double conversion UPS system is explained with its construction, transformer design and
brief control technique. The simulation and experimental justifications are included for the
completeness of the work.
5.2
Active Shunt Compensator System
This section explains an active shunt compensator suitable for reactive, unbalanced and
harmonic loads under both balanced and unbalanced operating conditions of the grid. The
stationary reference frame based controller with multiple resonant peaks (proportional +
multiresonant controller) is used in order to achieve high accuracy of current compensation.
However, the performance of the system depends to a great extent on the PLL structure
or unit vector generation process. Under unbalanced grid voltage condition, Synchronous
Reference Frame (SRF) PLL becomes inefficient because of the presence of double the fundamental frequency components in D- and Q- axis voltages. A resonant filter based PLL is
used to mitigate the problem. The same situation is true for the DC bus voltage controller.
The details of the PLL and the closed loop structure are discussed.
107
108
Chapter 5. Grid Interactive Modes
ff
V*
gd = 0
+
Vgd
Vgq
dq
1
s
ryb
Vgrn
Vgyn
Vgbn
Figure 5.1: Conventional SRF PLL
5.2.1
Structure and Design of the PLL
5.2.1.1
SRF PLL
The phase locked loop based on the transformation to synchronously rotating frame is shown
in Fig. 5.1. The three phase line-to-neutral grid voltages (Vgrn , Vgyn , Vgbn ) are first transformed to stationary coordinate system. The line-to-neutral grid voltages can be expressed as
Vgrn
Vgyn = Vm
Vgbn
sin

2
sin
3

2
sin +
3
; = t
(5.1)
where, and are the angular frequency and the phase angle of the grid voltages respectively.
With the help of the estimated phase angle e , the voltages in coordinate system are
converted to DQ frame (synchronously rotating frame with the voltage space vector V ).
Fig. 5.2 shows the stationary and rotating reference frames. In order to align the grid
voltage space vector with the Q-axis, the D-axis component Vgd is forced to zero by a PI
controller (Fig. 5.1). The output of the PI controller is added with feed-forward frequency
term (f f ) to generate estimated frequency (e ). The estimated phase angle e , which is
obtained by integrating e , is again used for coordinate transformation process. At steady
state, e tracks and Vgd remains at zero value. This PLL ensues high dynamic and steady
state performance with balanced input voltage condition.
However, if the grid voltage is unbalanced in nature, a double the fundamental frequency
component gets superimposed with the DC part of the D- and Q- axis quantities (Vgd and
5.2. Active Shunt Compensator System
109
Figure 5.2: Stationary and rotating reference frame
ff
V*gd = 0
+
LPF
Vgd
Vgq
dq
1
s
ryb
Vgrn
Vgyn
Vgbn
Figure 5.3: SRF PLL with low pass filter

Vgq ). This phenomena highly limits the performance of SRF-PLL. To suppress the frequency
component at 2e , conventionally a low pass filter is used in the loop as shown in Fig. 5.3.
This PLL structure (Fig. 5.3) improves the steady state tracking ability of the PLL but
the use of the low pass filter affects the transient performance. Moreover, any attempt
to enhance the dynamic performance would lead to a significant tracking error in the phase
angle. A different and more effective configuration of filter is described in the next subsection
to mitigate the problem.
5.2.1.2
Resonant Filter Based PLL
The structure of the improved PLL is shown in Fig. 5.4. A resonant filter is used in the
PLL system instead of the low pass filter. The transfer function of the resonant filter is 2nd
order and is given in (5.2) [59, 60, 61].
F (s) =
s2 + 402
s2 + 2cut s + 402
(5.2)
110
V*
gd = 0
+
ff
2 e
Resonant
Filter
Vgd
Vgq
dq
1
s
ryb
Vgrn
Vgyn
Vgbn
Figure 5.4: Modified PLL with resonant filter

This filter gives a very high attenuation at frequency 20 and provides unity gain and no
phase shift at frequencies other than certain band around 20 . The width of the band is
decided by cut . This filter structure eliminates the effect of unbalance on the unit vector
generation almost completely provided its parameters are selected properly as explained in
the next subsection. Moreover, 0 can be tuned from the estimated frequency information
e . This ensures the filtering accuracy in-spite of the grid frequency variation.
5.2.1.3
Design Procedure
When we transform (5.1) to synchronously rotating frame (using e ), the D- and Q- axis
components of the grid voltage can be expressed as [55],
"
# "
#
Vgd
Vm sin ( e )
=
Vgq
Vm cos ( e )
(5.3)
If it is assumed that phase difference e is very small, Vgd is simplified as,

Vgd Vm ( e )
(5.4)
From (5.4), one can easily form the entire closed loop structure of the PLL (see Fig. 5.5).
Hence, the open loop gain of the PLL is given by
Vm
1 Kp (1 + sT )
s2 + 402
s
sT
s2 + 2cut s + 402
(5.5)
where Kp and T are the gain and the time constant of the PI controller respectively. Before
selecting the gains of the PI controller let us first concentrate on the filter parameter selection.
111
ff
Vm
Vgd +
s2 + 4 20
s2 + 2 cut s + 4 20
Kp (1+sT)
sT
1
s
Figure 5.5: Overall closed loop form of the PLL

If the cut off frequency cut is selected less than 20 (under-damped) it leads to an oscillatory
behaviour and settling time increases. On the other hand, if cut is selected greater than
20 (over-damped) it causes sluggish response and associated band width of the loop gets
limited. Hence it is best to select cut = 20 to achieve a critically damped system. The
bode plots for different values of cut are shown in Fig. 5.6.
Figure 5.6: Variation of cut and its effect

In order to select the gains of the PI controller, the resonant filter is approximated as
a simple low pass filter. The bode plots in Fig. 5.7 show that this approximation is quite
112
Figure 5.7: Approximation of the resonant filter for controller design

justified if the frequency range below 300 rad/s is considered. With this approximation the
open loop transfer function of the PLL is modified to
Vm
1 Kp (1 + sT ) 1
s
sT
1 + s
(5.6)
where is the time constant of the low pass filter. As this is an approximated transfer
function, direct pole zero cancellation is not desirable. Hence, the design is carried out with
the help of symmetrical optimum method
T
= 4
Kp =
1
2Vm
(5.7)
The bandwidth of the system can be improved further by adjusting the values of T and Kp .
With the final values of T and Kp the bode plot of the open loop transfer function is shown
in Fig. 5.8. The band width of the PLL is 160 rad/s with an phase margin of 55 .
113
Figure 5.8: Bode plot of the open loop transfer function of the PLL
5.2.1.4
Performance Comparison with LPF based PLL
The LPF based PLL and the RF based PLL are simulated in order to compare their performances. Fig. 5.9 shows the direct axis grid voltage before and after the filter (Vgd and Vgdf ),
estimated frequency (e ) and phase angle (e ), unit vectors (sine and cose ) when a LPF
is used before the PI controller in SRF PLL. The same set of waveforms with resonant filter
based PLL are shown in Fig. 5.10. In both the figures, an unbalance in the grid voltage has
been created at t = 0.15 sec. Hence, thereafter Vgd starts oscillating at frequency 20 . The
LPF based PLL can not able to eliminate this oscillation even during steady state (see Vgdf
and e in Fig. 5.9). There is no such steady state oscillations in the corresponding waveforms
in Fig. 5.10 as that particular component is completely filtered out by the resonant filter.
Again, the transient response of the RF based PLL is faster compared to the LPF based
PLL (Fig. 5.9 and Fig. 5.10).
114
Figure 5.9: Simulated results: Transient performance of the LPF based PLL under grid
voltage unbalance
5.2.2
Compensation Techniques
The modified PLL is used to synchronize a shunt compensator (suitable for harmonic and
unbalanced loads) with the grid. The power circuit of the shunt compensator is shown in Fig.
115
Figure 5.10: Simulated results: Transient performance of the RF based PLL under grid
voltage unbalance
5.11. The power converter is three phase four wire in nature (high frequency link topology
highlighted in the previous chapter) and it is connected in shunt with 3 4-wire ac mains. A
set of unbalanced and non-linear loads (shown in Fig. 5.11) are also connected at the point
of common coupling (PCC). The control objectives are as follows:
116
Shunt
Compensator
Grid
I ir
Power
Converter
PCC
I iy
I ib
I lr I ly I lb
Nonlinear
/Unbalanced
Loads
Figure 5.11: Power Circuit of the shunt compensator

(1) The grid current should only contain the fundamental components of the load with
unity power factor.
(2) The grid current should be balanced in nature.
(3) The power converter will continue to operate under extreme unbalanced grid voltage
conditions (say, due to fault).
Hence, the power converter should absorb all the reactive, unbalanced and harmonic content
of the load current. The entire closed loop block diagram is shown in Fig. 5.12 Fig. 5.17.
Vgrn
Vgyn
Vgbn
ryb
0
Vg
Vg
Vg0
Figure 5.12: Grid voltage transformation

Fig. 5.12 and Fig. 5.13 show the transformations of the grid voltages to three orthogonal
coordinate system (0) and the resonant filter based PLL respectively. The PLL generates the unit vectors (cose and sine ) and the estimated grid frequency (e ). The similar
117
Vgd
Vg
Vg
Vg0
Vgq
dq0
sin e
cos e
e
RF based
PLL
Vg0
Figure 5.13: Resonant Filter based PLL
I ir
I iy
I ib
I i
Ii
Ii0
ryb
0
Figure 5.14: Converter current transformation
I l
I lr
I ly
I lb
Il
ryb
0
Il0
dq0
I ld
I lq
I l0
Figure 5.15: Load current transformation

sin e
cos e
*
Vdc
2 0
~
I lq
I lq
Vdc
*
I iq
HPF
I ld
I l0
*
I id
I i*
dq0
I i*
1
*
I i0
1
I i*0
Figure 5.16: Generation of current controller references

transformations (to 0 coordinate system) of the converter currents (Iiryb ) and load currents (Ilryb ) are shown in Fig. 5.14 and Fig. 5.15 respectively. The balanced active part
(fundamental) of the load is represented by the DC portion of Ilq . Hence this DC portion
is removed by putting a high pass filter (HPF) [in Fig. 5.16] in order to generate one part
of the desired current reference (Q-axis) of the power converter. As there is a small loss in
118
I i*
+
Ii
*
I i0
P + MRC
with resonant
peaks at
0 , 5 0 , 7 0
P + MRC
with resonant
peaks at
0 , 3 0 , 9 0
V*ir
Vg / G
I i
V*i
Ii0
ryb
V*i
V*iy
V g / G
Shunt Compensator
Power Circuit
P + MRC
with resonant
peaks at
0 , 5 0 , 7 0
MODULATOR
*
I i
V*ib
V*i 0
Vg0 / G
Figure 5.17: Proportional + multiresonant current controllers (P + MRC) and reverse transformation
125
0
120
115
5
0.26
IGR, IGY, IGB (A)
Vdc (V)
ILR, ILY, ILB (A)
130
5
0.27
0.28
Time (sec)
0.29
0.3
110
0.26
0.27
0.28
Time (sec)
0.29
0.3
2
0
2
0.26
0.265
0.27
0.275
0.28
Time (sec)
0.285
0.29
0.295
0.3
Figure 5.18: Performance of the system without resonant filter in the DC voltage feedback
path
the DC bus it is required to have a DC bus voltage controller. Thus the output of the DC
bus voltage controller gives the 2nd part of the Q-axis current reference. It is interesting to
note that the DC bus supplies the oscillatory components while compensating unbalanced
loads. This phenomena is shown in Fig. 5.18. This leads to a DC bus oscillation at double
the fundamental frequency and associated non-linearity in the grid current (see Fig. 5.18).
119
130
Vdc_filterd (V)
130
Vdc (V)
125
120
115
IGR, IGY, IGB (A)
110
0.26
0.27
0.28
Time (sec)
0.29
0.3
125
120
115
110
0.26
0.27
0.28
Time (sec)
0.29
0.3
2
0
2
0.26
0.265
0.27
0.275
0.28
Time (sec)
0.285
0.29
0.295
0.3
Figure 5.19: Performance of the system with resonant filter in the DC voltage feedback path
Figure 5.20: Bode plot of - and - axis current controller

Hence, this particular component (at 20 ) present in the DC bus (which is unavoidable in
nature) should not be seen by the DC voltage controller. Similar to the PLL system, the
same resonant based filter can be incorporated in the feedback path. With the resonant filter,
120
the 20 component is completely filtered out and the desired grid current can be achieved
(see Fig. 5.19). This DC bus controller is not required when there is a separate DC source or
when another controlled active front end is connected to the DC bus. Similarly, the D-axis
and 0-axis current references (Iid

, Ii0
) are obtained from Ild and Il0 directly by multiplying
by 1. The negative sign is required in order to preserve the chosen current directions.
These current references are, then, transferred back to 0 domain with the help of the unit
vectors (Fig. 5.16).
Fig. 5.17 shows 3 stationary reference frame controllers for the -, -, 0- axis converter
currents. The controller is proportional + multiresonant controller (P + MRC) with resonant
peaks at desired frequencies [17, 62, 63]. The non-linear and unbalanced load currents
may contain frequency components at 0 , 30 , 50 , 70 , 90 , 110 , 130 , 150 etc. The
frequency components beyond 9th harmonics are usually small and ignored in the present
compensator design. When the load currents are transformed to 0-coordinate system,
and axis currents may contain fundamental, 5th , 7th harmonics and 0-axis current may
contain fundamental, 3th , 9th harmonics. Accordingly, the peaks of the resonant controller are
chosen as shown in Fig. 5.17. This controller structure makes shunt compensator suitable to
compensate non-linear and unbalanced loads. Again, these resonant controllers are adaptive
in nature with the grid frequency variations (with 0 = e ) [63]. It can be observed that the
controller in 0-domain requires less number resonant peaks compared to per phase basis
controllers (described in the previous chapter). Next, the output of the current controller are
subtracted from suitable feed-forward terms (the grid voltages) and given to the modulator.
Finally, the generated pulses from the modulator drive the converter.
The bode plot of the open loop transfer function of the - and - axis current loops
is shown in Fig. 5.20. The current loop contains the controller (P + MRC) and the first
order RL plant. The controller parameters are selected such that all the resonant peaks
are greater than 60 dB (in Fig. 5.20). This ensures a steady state error less than 0.1% for
desired frequency components. The bode plot also shows that the bandwidth of the current
loop is 1 kHz with an adequate phase margin. Similarly, the design can be carried out for
the 0-axis current controller.
121
Figure 5.21: Experimental result of converter turn on transient with unbalanced loads: CH1,
CH2: R- and Y- phase grid current before and after shunt compensator is turned on (2.4
A/div), time: 20 ms/div
Figure 5.22: Experimental result of converter turn on transient with non-linear loads: CH1,
CH2, CH3: 3 grid current before and after shunt compensator is turned on (6 A/div), time:
20 ms/div
5.2.3
The RF based PLL and the entire controller structure are implemented in an FPGA based
digital controller and interfaced with the same high frequency link power converter (1 kVA,
220 V L-L, 4-wire, 3). The experimental results are given in the following subsections. In
the following experimental results, the transient changes are made exactly at the middle of
the time scale.
122
Figure 5.23: Harmonic content in grid current (Fig. 5.22) before turning on the converter
(THD: 32.4%)
Figure 5.24: Harmonic content in grid current (Fig. 5.22) after turning on the converter
(THD: 3.5%)
123
Figure 5.25: Experimental result of converter turn on transient with reactive loads: CH1: Rphase grid voltage (80 V/div), CH2: R-phase grid current before and after shunt compensator
is turned on (1.2 A/div), time: 20 ms/div
5.2.3.1
Steady State Performance of the Power Converter under Balanced Grid

Condition
The performance of the power converter is first verified under balanced grid voltage condition with unbalanced and non-linear/harmonic loads. Fig. 5.21 shows the grid currents
with unbalanced loads. Before turning on the converter grid currents are nothing but the
unbalanced load currents. The R-phase load is almost half compared to the Y- and B- phase
loads (B-phase current is not shown in Fig. 5.21). After the converter is turned on, the grid
currents become almost balanced.
Similar results are shown in Fig. 5.22 and Fig. 5.25 when respectively non-linear and
reactive loads are connected at the PCC. Harmonic contents in the grid current (Fig. 5.22)
before and after the shunt compensation are shown in Fig. 5.23 and Fig. 5.24 respectively.
It can be observed from Fig. 5.21 Fig. 5.25 that the converter is effective enough to supply
the reactive, unbalanced and non-linear portion of the load currents.
5.2.3.2
Transient Performance under Grid Voltage Unbalance
Next, the power converter is tested with a sudden unbalance in the grid voltages. In order
to generate unbalanced grid condition, B-phase of the PCC is shorted with the neutral
(equivalent to LG fault). Immediately, after the short circuit is created B-phase circuit
breaker (in the grid side) will open and the converter and loads at the PCC will experience
124
Shunt
Compensator
Grid
I ir
Power
Converter
PCC
I iy
I ib
I lr I ly I lb
Nonlinear
/Unbalanced
Loads
1. direct
connection
2. Circuit breaker
open
Figure 5.26: Experimental arrangement to test the compensator under grid voltage unbalance
Figure 5.27: Experimental transient performance of the proposed PLL with unbalance in
the grid voltage: CH1, CH2: unit vectors sine and cose (5 V/div), CH3: Vgrn (200 V/div),
CH4: Vgbn (200 V/div), time: 10 ms/div
an unbalanced input voltage with rated voltages in R- and Y- phase and zero voltage in
B-phase (with respect to the neutral). The associated experimental arrangements are shown
in Fig. 5.26. Under such situation, transient performances of the PLL are shown in Fig.
5.27 Fig. 5.28. Fig. 5.27 shows the unit vectors, Vgrn and Vgbn . Under balanced condition,
sine is in the same phase with Vgrn . After the short circuit is made, Vgbn goes to zero but it
does not affect the unit vector generation process. The unbalance in the grid voltage causes
125
Figure 5.28: Experimental transient performance of the proposed PLL with unbalance in
the grid voltage: CH1: D axis grid voltage Vgd (400 V/div), CH2: D axis grid voltage
after resonance filter Vgdf (400 V/div), CH3: estimated frequency e (250 rad/s/div), CH4:
estimated phase angle e (2 rad/div), time: 20 ms/div
Figure 5.29: Transient load currents with grid voltage unbalance: CH1, CH2, CH3: 3 load
currents (6 A/div), time: 20 ms/div
oscillation at 20 in Vgd (Fig. 5.28). The resonance filter almost completely eliminates its
effect on Vgdf , e , and e . Fig. 5.29 5.31 shows the behaviour of the power circuit under
such voltage unbalance. As the B-phase voltage drops to zero, B-phase load current also
drops to zero and other phase load currents change slightly because of the nature of the load
(Fig. 5.29). The corresponding converter currents and grid currents are shown in Fig. 5.30
and Fig. 5.31 respectively. In Fig. 5.30, the B- phase converter current become sinusoidal
(Fig. 5.30, CH3 during unbalanced grid condition) in order to obey the control laws. This
126
Figure 5.30: Transient converter currents with grid voltage unbalance: CH1, CH2, CH3: 3
converter currents (8 A/div), time: 20 ms/div
Figure 5.31: Transient grid currents with grid voltage unbalance: CH1, CH2: R- and Yphase grid currents (6 A/div), CH3: B- phase grid current before voltage unbalance and
current through short circuited path between b and n after voltage unbalance (6 A/div),
time: 20 ms/div
current circulates through the converter and the short circuited path between B- phase and
the neutral. Fig. 5.31 shows that the grid current continues to flow in R- and Y- phases even
after the voltage transient. Only for B- phase, it gets diverted through short circuited path.
By the control action, the converter assumes this short circuit path as the third phase (B
phase) and continues to inject desired current through it. Fig. 5.32 shows the corresponding
transient response of the DC bus. The safe and reliable operation of the power converter
under extreme unbalanced grid voltage condition ensures its performance under all other
5.3. Double Conversion UPS System
127
Figure 5.32: Transient DC bus voltage with grid voltage unbalance: CH1, Vdc (24 V/div),
time: 1 s/div
minor grid voltage unbalances.
5.3
Double Conversion UPS System
UPS systems can be broadly classified in three types: standby, line-interactive and double
conversion. Among these three types of UPS systems, the double conversion type provides
the best performance from the point of view of load power quality (no transfer time associated
with the transition from nominal mode to stored energy mode) but a low efficiency and a
high cost. The block diagram of a double conversion UPS system is shown in Fig. 5.33.
In Fig. 5.33, the grid voltage is first rectified in order to form the DC link voltage by a
PWM rectifier. The PWM rectifier can also help to achieve good input current quality at
unity power factor. As the battery bank voltage level is different from the DC link voltage
level in many applications, a bidirectional DC-DC converter is usually put to interface the
DC link with the battery bank. Finally, at the output side the PWM inverter generates
the desired output voltage for the critical loads. In an alternate circuit configuration, the
DC link is made compatible with the battery bank voltage (so that they can be directly
connected) by using grid side and load side transformers. In this section another double
conversion UPS structure is proposed with high frequency link power conversion technique.
The main advantages of the system are as follows
The cost and size of the isolation transformer is low because of high frequency operation.
128
PWM
Rectifier
DC Link
PWM
Inverter
Load
Bidirectional
DCDC
Converter
Battery Bank
Figure 5.33: General structure of a double conversion UPS system
Different voltage levels of the grid, battery and load can be interfaced.
There is no bulky DC link capacitor (like indirect matrix converter).
5.3.1
The Proposed Structure
The basic topology of HF link DC 3 AC power converter is redrawn in Fig. 5.34.

The detailed commutation requirements of the power circuit and other associated issues are
reported in chapter 3. The high frequency link construction described above is rearranged
with a three winding transformer in order to form a double conversion UPS system and the
proposed scheme is shown in Fig. 5.35. The three windings of the high frequency transformer
are connected to the H-bridge (Primary P), grid side cycloconverter I (secondary I S1)
and load side cycloconverter II (secondary II S2). The H-bridge along with the first stages
(the synchronous rectifier) of each cycloconverter create two virtual DC links for the grid side
and the load side cycloconverters. From these virtual DC links the PWM inverter stages of
the cycloconverter -I and -II regulate the grid currents and the load voltages respectively. In
normal mode of operation as a UPS system, the energy is transferred to the load from the grid
through cycloconverter I, transformer winding S1, S2 and cycloconverter II. In stored energy
mode, the power is delivered to the load from the battery through H-bridge, transformer
winding P, S2 and cycloconverter II. In both these modes the magnetizing current of the
transformer is supplied by the H-bridge.
129
LC
Filter
Sync. Output PWM
Rectifier
Inverter
Hbridge
Cycloconverter
Figure 5.34: Basic DC 3 AC high frequency link topology
5.3.2
Transformer Construction
The design and fabrication of the high frequency transformer is very important from the
point of view of power circuit performance. Its improper design can lead to significant
amount of losses either in the transformer itself or in the other portion of the power circuit.
The high frequency effects, the core losses and the leakage inductance are the major concern
of any high frequency transformer design. Considering all these points the high frequency
transformer is designed and its design procedure is given below.
The power rating of the transformer should be same as the rating of the UPS system.
But in the present case all the three windings are not loaded equally. Firstly, it depends
upon the power flow paths in different modes. Secondly, in normal mode of operation, the
battery charging current and the load demand have to be supplied from the grid. Hence
the VA rating of S1 is taken 10% more than that of other two windings. The disadvantage
is that the copper in the transformer is not fully utilized. For square wave operation, the
voltages of the transformer are
VP = 4f Bm Ac NP
VS1 = 4f Bm Ac NS1
(5.8)
VS2 = 4f Bm Ac NS2
where f = frequency of operation = 20 kHz, Bm = maximum flux density = 0.2 T, Ac = core
area. As the window of the transformer accommodates all the three windings, the available
window area can be written as
k w Aw =
NP IP + NS1 IS1 + NS2 IS2

J
(5.9)
130
I gryb
Vgryb
Cyclo
Converter
I
I lryb
3 winding HF
Transformer
S1
S2
Cyclo
Converter
II
Vlryb
L
O
A
D
P
Hbridge
Vdc
Figure 5.35: The proposed double conversion system

where J = maximum allowable current density of the conductor = 2 106 A/m2 , kw =
window utilization factor = 0.3, Aw = window area of the core. From, (5.8) and (5.9) we
get,
VP IP + VS1 IS1 + VS2 IS2 = 4kw f Bm JAc Aw
VP IP + VS1 IS1 + VS2 IS2
Ac Aw =
4kw f Bm J
(5.10)
If we put VP IP = VS2 IS2 = 1000VA and VS1 IS1 = 1100VA (10% extra considering battery
charging during normal mode) in (5.10), Ac Aw is evaluated as 322916 mm4 . The selected
core is given in Table. 5.1. Next, the number of turns can be calculated as,
VP
8
4f Bm Ac
= NS2 = 32
NP =
NS1
(5.11)
The wire size can be computed from the RMS value of the currents (IP rms = 9.1A, IS1rms =
2.5A, IS2rms = 2.3A) and J. The selected values of the wires are listed in Table. 5.1.
A number of parallel wires are chosen to limit the high frequency effects on the winding
resistance. The windings are wound in interleaved manner in order to reduce the leakage
inductance as shown in Fig. 5.36. As the secondary winding S2 always takes the current and
the other two windings (P and S1) take current depending upon the modes of operation, in
the interleaved structure S1 and P are placed in either side of S2. This construction keeps
the leakage inductance low in both the modes of operation.
In spite of cautious design the leakage inductance can not be made zero. As a result
the cycloconverter devices experiences serious over voltages during commutation process of
131
1
0
00
11
00
11
00
11
0
1
0
1
00
11
0
1
0
1
0
1
00
11
0
1
00
11
0
1
0
1
00
11
00
11
00
11
0
1
0
1
00
11
00
11
00
11
0
1
0
1
0
1
00
11
0
1
00
11
0
1
0
1
00
11
00
11
00
11
0
1
0
1
00
11
00
11
00
11
0
1
0
1
0
1
00
11
0
1
00
11
0
1
011
1
00
00
001
11
011
011
1
00
001
11
00
11
01
01
0
S1 S2 P S1 S2 P
P S2 S1 P S2 S1
P Primary S1 Secondary I S2 secondary II
Figure 5.36: The interleaved winding structure
dq
Vlryb
Vld
V*ld
I ld
dq
dq
I lryb
Cycloconverter II
I lq
Vlq
Decoupling
MODULATOR
I *lq
V*lq
I *ld
Figure 5.37: Load side controller in synchronously rotating coordinate system
V*dc
Vgryb
dq
PLL
I lq / k
dq
I gd
dq
I gryb
2
3
Cycloconverter I
Vdc
I gq
Decoupling
MODULATOR
I *gq
+
Figure 5.38: Grid side controller in synchronously rotating coordinate system
its devices. A simple RC snubber is added in each cycloconverter link to reduce these over
voltage spikes across the devices.
132
Table 5.1: Three winding HF Transformer Details
5.3.3
Frequency
20 kHz
Turns ratio (P:S1:S2)
1:4:4
Core
2 E65/32/27 Ferrite
Primary
8 turns SWG#21 11
Secondary I
32 turns SWG#21 3
Secondary II
32 turns SWG#21 3
Winding
Interleaved
Closed Loop Control
The block diagram of the load side and the grid side controller are shown in Fig. 5.37 and
Fig. 5.38 respectively [15, 64, 65]. For simplicity only linear loads are considered. The
various circuit voltages and currents in Fig. 5.35, Fig. 5.37 and Fig. 5.38 are defined as
follows:
Vdc = DC battery voltage
Vgryb = 3 grid voltages
Igryb = 3 grid currents
Ilryb = 3 load side inductor currents
Vlryb = 3 load side capacitor voltages
Vldq = Load side capacitor voltages in DQ coordinate system
Ildq = Load side inductor currents in DQ coordinate system
Igdq = Grid side inductor currents in DQ coordinate system
= Estimated phase angle of the grid
Vdc = DC battery voltage reference
Vldq
= Load voltage references in DQ coordinate system
k = A quantity that ensures active power balance

5.3.3.1
133
Load Side Controller
The objective of the load side controller is to maintain rated load voltages in spite of the
load current variations. The feedback quantities (Vlryb and Ilryb ) are first converted to dq
coordinate system (Vldq and Ildq ). The desired output voltage reference is fixed by Vldq
.
The output of the dq voltage controllers are given to the current controllers for better
dynamic response. The outputs of the current controllers give the desired 3 references
for the modulator (after addition of decoupling terms and coordinate transformation). The
modulator generates desired switching command for cycloconverter II.
5.3.3.2
Grid Side Controller
On the other hand, the grid side controller maintains unity power factor at grid side and
desired DC battery voltage (only during normal mode of operation). The output of the DC
Ilq
battery voltage controller is added with feed-forward term
to relieve the burden on the
k
DC bus voltage controller. The factor k maintains active power balance between the grid
and the load in spite of the grid voltage variations. Igd

is set to zero for unity power factor
operation. Again the output of the current controllers are processed through decoupling
block (for decoupling of d and q axis quantities), dq to transformation and finally 2
phase to 3 phase transformation. The output of the modulator is given to cycloconverter I
to achieve desired control objectives.
The grid synchronization is carried out by a dq-PLL (phase locked loop) [55]. The unit
vectors generated by the PLL are used for transformation of 2 phase quantities () to dq
coordinate system.
5.3.4
The experimental setup is shown in Fig. 5.39. The grid voltages and load voltages are selected as 220V L-L. The battery voltage is 120V nominal with a maximum possible variation
from 110V to 135V. The closed loop control for the grid side and load side are carried out in
an FPGA based digital controller. The controller samples all the feedback signals through
analog-to-digital converters and generates the desired control pulses for cycloconverter -I and
-II. The H-bridge is operated in open loop (shown in dotted arrow). Before giving the pulses
to the power circuit they are passed through a commutation and protection board. This
134
I gryb
Vgryb
Cyclo
Converter
I
I lryb
3 winding HF
Transformer
S1
S2
Cyclo
Converter
II
Vlryb
L
O
A
D
P
Hbridge
Vdc
Commutation and Protection
FPGA based
Digital Controller card
Vgryb I gryb Vdc
I lryb Vlryb
Figure 5.39: Block diagram of the experimental set-up
board generates the desired dead-time, overlap required for the safe operation of the power
circuits. It also monitors the healthy operation of the entire system and brings the system
to rest in case of any fault, over-voltages or over-currents etc.
The experimental results are shown in Fig. 5.40 Fig. 5.44. Fig. 5.40 shows the
generated unit vectors sin and cos from the grid voltages. With the help of these unit
vectors the closed loop control for the grid side inverter is implemented. Fig. 5.41 shows
the unity power factor operation of the grid side converter. The R-phase grid voltage and
current are shown in this figure. Fig. 5.42 shows the three phase output voltages for the
loads. The high frequency transformer secondary (S2) voltage and current are shown in Fig.
5.43. The same waveform in zoomed manner is shown in Fig. 5.44. A high frequency ringing
is observed in these waveforms due to energy exchange between parasitic components like
leakage inductance, stray capacitance etc. This peaky current causes over current stresses
5.4. Conclusion
135
Figure 5.40: Generated unit vectors for grid side control: CH1: sin (2 V/div), CH2: cos
(2 V/div), time: 20 msec/div
Figure 5.41: Unity power factor operation in the grid side: CH1: Vgr (160 V/div), CH2: Igr
(2 A/div), time: 10 msec/div
on the power circuit components. The efficiency of the system is measured as 89% in normal
mode and 91% in stored energy mode under full load condition.
5.4
Conclusion
In this chapter, resonant filter and proportional + multiresonant controller based shunt compensator system is discussed. The controller design of the phase locked loop with the resonant
filter is explained. The experimental investigation is carried out under extreme unbalanced
condition of the grid. The performance of the shunt compensator is quite satisfactory under
136
Figure 5.42: Three phase output voltages (load side): CH1, CH2, CH3: 90 V/div, time: 5
msec/div
Figure 5.43: CH1: transformer secondary (S2) voltage (500 V/div), CH2: transformer secondary (S2) current (2 A/div), time: 5 msec/div
balanced and unbalanced condition of the grid. The performance of the grid connected shunt
compensator system can be improved by replacing the resonant filter by multiresonant filter
with high attenuation at 20 , 40 , 60 etc. Next, a double conversion UPS system based
on high frequency link topology is described. The topology is derived from the proposed
topology explained in chapter 3. The measured results show certain disadvantages of the
power circuit. An inductive-capacitive energy exchange leads to a peaky current through
the transformer and increases losses and current stresses on the devices. This peaky current depends upon the leakage inductance of the transformer (Ll ) and the cycloconverter
side lumped capacitance (Cl ) and increases with decreasing Ll , increasing Cl and increasing
5.4. Conclusion
137
Figure 5.44: Zoomed Fig. 5.43: CH1: transformer secondary (S2) voltage (500 V/div), CH2:
transformer secondary (S2) current (2 A/div), time: 20 sec/div
voltage rating of the cycloconverter. Hence a reliable design requires information about the
unknown circuit non-idealities.
138
Chapter 6
Conclusions
6.1
Summary of the Contributions
High frequency link power converters are studied as stand-by AC power supplies and very
simplified structures of such topology are proposed for DC to 3 AC applications (for both
three-wire and four-wire case). A number of issues in the proposed topology are identified,
analysed and solved.
Firstly, the commutation process of the power circuit requires an additional zero portion
in the cycloconverter link voltage for its safe operation. This zero portion in the cycloconverter link voltage creates a non-linear distortion in the output voltages and makes the gain
of the converter time varying. A simple modification in the modulating signal is proposed
to improve the situation. The various carrier possibilities are studied and a generalized situation with different switching frequencies in the primary side inverter and the output side
inverter is suggested.
Secondly, the high frequency transformer is expected to handle only high frequency components. But due to the loading pattern and various non-idealities of the power circuit like
dead time, overlap etc., a small amount of low frequency component gets injected into the
transformer. This phenomena leads to a poor utilization of the high frequency transformer
and a large magnetizing current. The primary side H-bridge is usually operated in open-loop
in the proposed power circuit configuration. This advantage is exploited to solve the above
flux-walking problem in closed form. The controller is implemented with on line varying
coefficients to achieve the desired dynamic response.
Thirdly, the power converter is used as a stand-by power supply to cater to unbalanced
and non-linear loads. The best controller structure identified for the purpose is proportional
139
140
Chapter 6. Conclusions
+ multiresonant controller. This control structure while used in the voltage regulation loop
leads to a stability problem and desired performance can not be achieved. A suitably designed
lead-lag compensator is added with the voltage loop to improve the stability margins. An
inner current loop is also used to facilitate resonance damping due to the output LC filter.
Next, an investigation is carried out for decentralized parallel operation of inverters.
The potential of proportional + multiresonant controller is used to simplify the structures
of the virtual output impedance loop. The proposed control structure helps to achieve an
excellent output voltage quality and sharing accuracy in spite of the mismatch in the tiewire impedance. A trade off between the sharing accuracy and the output voltage waveform
quality is examined. The THD and degree of unbalance in the output voltage is achieved
well below the specified limit for stand alone AC supplies. All these contributions are well
supported with simulation and experimental studies.
Finally, some of the grid interactive modes are examined for the completeness of the
work. The proportional + multiresonant controller is used in the current loop to achieve
a shunt compensation technique (based on same high frequency link topology). The shunt
compensator is tested under steady state and transient conditions. The unbalance in the
grid voltages and load currents create abnormal situation in the phase locked loop and in
the DC bus voltages. A resonant filter based PLL is adopted to solve these problems.
The proposed high frequency link topology is then extended to achieve a double conversion UPS system. A three winding high frequency transformer is used to interface the
load, grid and battery and to eliminate the bulky DC link capacitor. The experimental
result shows that a peaky resonating current flows through the transformer. This current
increases the losses and the current stress of the H-bridge and cycloconverter devices. This is
a disadvantage of the high frequency link topology and it poses restriction on the maximum
voltage rating of the system. This voltage rating depends on the circuit non-idealities like
the leakage inductance of the transformer, the cycloconverter side lumped capacitance and
hence an iterative design prototype building is essential for these systems.
6.2
Scope of Future Work
There is certainly good scope of future extension from the work described in this thesis.
They are listed as follows:
The high frequency link power converter consists of a large number of switching devices.
6.2. Scope of Future Work
141
Nearly half of the switching are naturally loss-less and the remaining are hard switched.
A study on soft switching technique can improve the efficiency of the converter.
The compensation for the non-linear distortion is implemented considering only zero
portion in the cycloconverter link voltage. It is possible to extend the same for the deadtime in the H-bridge and the output side inverter. The effect of these compensation
on parallel operation can also be examined.
The design procedure followed in this thesis for the proportional + multiresonant controller is purely based on iterative plotting of the loop frequency response (Bode plot).
A more general and analytical study on these controllers with non-linear loads can be
carried out.
Effective design of cycloconverter PCB or bus bar layout along with high frequency
transformer is a challenging task. More concentration can be put on these designs so
that the peaky current reported can be controlled.
142
Chapter 6. Conclusions
Appendix A
Protection for High Frequency Link
Converter
It is very important for any power electronics system to have a reliable and fast protection
features. These protections help to avoid unnecessary power circuit failures in case of any
faults or under abnormal loading conditions. For the proposed high frequency link converter
the protection scheme is developed and their descriptions are given in the following.
A.1
HF Link Current based Protection
A fast high frequency link current sensing based protection scheme is implemented to safely
shut down the system in case of any fault in the cycloconverter side. The primary current
of the isolation transformer is measured (Fig. A.1) and converted to a proportional voltage
signal using a current sensing card. This voltage signal is compared with maximum positive
and negative allowable threshold values. The output of two comparators are OR-ed and given
to SR latch. Whenever a fault occurs in the cycloconverter side or the system experiences
overloading, the high frequency link current exceeds the worst case value and enable signal
(en in Fig. A.1) is disabled. Two different comparators for positive and negative values
of current eliminate the unwanted delays in the tripping mechanism. The gate pulses for
the H-bridge and cycloconverter stageII are AND-ed with enable signal. Cycloconverter
stageI is current source type and hence it can not be switched off during fault condition
also. When the fault is removed, the pulses to the H-bridge and cycloconverter stageII are
released again by making clear signal high for a short duration.
The effectiveness of the protection scheme is checked by making a direct short circuit in
the cycloconverter side. The corresponding enable signal (en) and the high frequency link
143
144
Controller
Appendix A. Protection for High Frequency Link Converter
en
en
en
en
Deadtime
+
driver
Overlap
+
driver
Deadtime
+
driver
HBridge
Current
Sensing
Card
Cyclo
converter
stage I
Cyclo
converter
stage II
+ve max
+
R Q
ve max
clear
en
Figure A.1: Arrangement of high frequency link current based protection
current are shown in Fig. A.2. The protection algorithm takes less than 5 sec to trip the
system.
A.2. Other Protections
145
Figure A.2: Protection feature, CH1: enable signal en (10V /div), CH2: high frequency link
current IP (50A/div), time: 10sec/div
A.2
Other Protections
There are various other protections are designed based on DC voltage or AC current measurement [66]. They are listed as follows:
DC bus over-voltage protection
DC bus under-voltage protection
Over current protection
These protections are inevitable for the grid connected modes of operation. The various
thresholds are selected such that the HF link current based protection operates as a back-up
of these protections.
146
Appendix A. Protection for High Frequency Link Converter
Appendix B
Digital Controller Platform
An FPGA based digital controller [67, 68] is used for all the commutation purposes and
closed loop control implementations. The controller has the following features:
80 digital I/Os
16 Analog input channels (with 6.4 s A/D conversion time per channel)
8 Analog output channels (with a DAC settling time of 80 ns)
ALTERA EP2C70F672C8 FPGA with 68,416 logic elements
USB and CAN transceiver interfaces
On board SRAM (64K 18)
Three clocks at 20 MHz each
B.1
Hardware Architecture
The hardware architecture of the controller is as shown in Fig. B.1. The analog interfaces are
realized with 12 bit bipolar ADCs (AD7864AS1) and 12 bit current driven DACs (AD5447).
The fast DAC channels enable the observation of fast varying signals in the controller for
debugging purposes. All the 80 digital I/Os are buffered, and level shifted from 3.3V (FPGA
side) to 5V.
In order to interface the controller platform with the converter subsystems such as gate
drivers, sensor circuits etc., there is an interface card. This card mainly houses various
connectors for the digital and analog I/O in a convenient way, and also provides a small
keypad with 5 push button keys.
147
148
Appendix B. Digital Controller Platform
PC
Analog inputs
ADC
config.
device
Digital I/O
Bidirectional
Buffers
FPGA
Analog outputs
3
Clocks
(20 MHz)
DAC
PC
USB & CAN
SRAM
Figure B.1: The basic structure of the digital controller board
B.2
Software Organization
The control algorithms are developed in a software environment called Quartus [69] from
ALTERA. The programming can be done with one of the Hardware Description Languages
(HDL) such as VHDL, Verilog, or the FPGA manufacturers own HDL (AHDL). There is a
provision in Quartus to use a schematic/block diagram based tool to create the programs.
The VHDL and Verilog programs are portable to other FPGAs.
The software developed for the controller is better organized as modules of code/block.
Most of the function in a controller are reusable within the same system or other systems.
Hence, developing a user library of reusable code/block is helpful for future work. In the
present work, all the required software modules are developed as reusable blocks.
B.3. Programming the Controller
B.3
149
Programming the Controller
Once the program is developed, it can be transferred to the FPGA in three ways, namely
JTAG mode, active serial mode and passive serial mode. The board used for programming
can support JTAG and active serial modes of programming. JTAG mode is used in the
development time when continuous modification of the program is usual. In active serial
mode the program in the form of configurable data for the FPGA is permanently stored
in a EEPROM device known as configurable device [70]. During power-up, the FPGA
will configure itself by extracting the data from the configuration device. This mode of
programming is usually done when program development is finished. The configuration data
is sent to the FPGA from a Personal Computer (PC) through a ByteBlaster cable, which
is connected to a parallel port of the PC. In the FPGA controller board, separate connectors
are provided for JTAG and active serial connections.
150
Appendix B. Digital Controller Platform
Appendix C
Photographs of the Test Setup
Figure C.1: Photograph of the primary side H-bridge (MOSFET based)
151
152
Appendix C. Photographs of the Test Setup
Figure C.2: Photograph of the high frequency transformer and the current sensor for protection
Figure C.3: Photograph of the secondary side cycloconverter (IGBT based)
153
Figure C.4: Photograph of the FPGA based digital controller board used with interface card
154
Figure C.5: Photograph of the protection, commutation and indicator board [4-layer Printer
Circuit Board (PCB)]
155
Figure C.6: Photograph of the two paralleled cycloconverters (with vertical gate driver cards)
156
Figure C.7: Photograph of the entire laboratory set-up
References
[1] V. Ramanarayanan, Course Material on Switched Mode Power Conversion, IISc, Bangalore, 2006
[2] H. Krishnaswami, and V. Ramanarayanan, Control of high-frequency AC link electronic
transformer, IEE Proc.-Electr. Power Appl., vol. 152, no. 3, May. 2005, pp. 509-516.
[3] V. T. Ranganathan, P. D. Ziogas, and V. R. Stefanovic, A DC-AC power conversion
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High Frequency Link Inverters and

Department of Electrical Engineering

resistive virtual output impedance loop is exploited to achieve decentralized paralleling of

Scope of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . .

Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 State of the Art

High Frequency Power Converter Topologies . . . . . . . . . . . . . . . . . .

Modulation before Isolation . . . . . . . . . . . . . . . . . . . . . . .

Modulation after Isolation . . . . . . . . . . . . . . . . . . . . . . . .

Extension to DC 3 AC Power Conversion . . . . . . . . . . . . . . . . . .

High Frequency Transformer Design . . . . . . . . . . . . . . . . . . . . . . .

Review of Voltage Regulation Loop for Stand-by AC Power Supplies . . . . .

Review of Paralleling Techniques . . . . . . . . . . . . . . . . . . . . . . . .

Basic Principles of Decentralized Paralleling . . . . . . . . . . . . . .

General Structure of the Controller for Decentralized Paralleling . . .

3 High Frequency Link Converter and Associated Issues

The Proposed DC 3 AC High Frequency Link Converter . . . . . . . . .

The Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Extension to 3-phase 4-wire Case . . . . . . . . . . . . . . . . . . . .

Illustration on Zero Sequence Current Path

Non-linear Distortion in the Output Voltages . . . . . . . . . . . . . . . . . .

Calculation of Open Loop Converter Gain . . . . . . . . . . . . . . .

Improved Utilization of High Frequency Transformer . . . . . . . . . . . . .

Control over the Magnetizing Current . . . . . . . . . . . . . . . . . .

Selection of High Frequency Transformer . . . . . . . . . . . . . . . .

Modelling of the High Frequency Transformer . . . . . . . . . . . . .

Effect of Various Circuit Parameters . . . . . . . . . . . . . . . . . .

Closed Loop Solution . . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Design and On Line Tuning . . . . . . . . . . . . . . . . .

Active Clamp based Regenerative Snubber . . . . . . . . . . . . . . . . . . .

4 Proportional + Multiresonant Controller based Decentralized Parallel Operation

Voltage Regulation Loop with Proportional + Resonant Controller . . . . . .

Inner Current Loop and Damping of Resonance Oscillation . . . . . .

Outer Voltage Loop and Stability Analysis . . . . . . . . . . . . . . .

Proportional + Multiresonant Controller and Stability Issues . . . . . . . . .

Extension to Non-linear Loads . . . . . . . . . . . . . . . . . . . . . .

Proposed Control Scheme . . . . . . . . . . . . . . . . . . . . . . . .

Decentralized Parallel Operation . . . . . . . . . . . . . . . . . . . . . . . . .

The Proposed Control Structure . . . . . . . . . . . . . . . . . . . . .

Calculation of P and Q for Each Phase . . . . . . . . . . .

3 P/Q Droop Characteristics . . . . . . . . . . . . . . . .

Voltage Reference Generation with Virtual Resistive Output

Proportional + Multiresonant Controller Based Voltage Regulation Loop . . . . . . . . . . . . . . . . . . . . . . . . . .

Controller Design and Parameter Selection . . . . . . . . . . . . . . .

Inner Voltage Regulation Loop . . . . . . . . . . . . . . . .

Virtual Resistive Output Impedance Loop . . . . . . . . . .

Outer P/Q Sharing Loop . . . . . . . . . . . . . . . . . . .

Steady State Performance . . . . . . . . . . . . . . . . . . . 100

Transient Performance with Start Up PLL . . . . . . . . . . 103

5 Grid Interactive Modes

Active Shunt Compensator System . . . . . . . . . . . . . . . . . . . . . . . 107

Structure and Design of the PLL . . . . . . . . . . . . . . . . . . . . 108

SRF PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Resonant Filter Based PLL . . . . . . . . . . . . . . . . . . 109

Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . 110

Performance Comparison with LPF based PLL . . . . . . . 113

Compensation Techniques . . . . . . . . . . . . . . . . . . . . . . . . 114