Multiplier project

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR
filters, digital signal processors and microprocessors etc.

There are different entities that one would like to optimize when designing a VLSI circuit. These entities
can often not be optimized simultaneously, only improve one entity at the expense of one or more
others.The design of an efficient multiplier circuit in terms of power, area, and speed simultaneously,
has become a very challenging problem. Power dissipation is recognized as a critical parameter in
modern VLSI design field. In Very Large Scale Integration, low power VLSI design is necessary.
Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, convolution,
and other important DSP and multimedia kernels. The objective of a good multiplier is to provide a
physically compact, good speed and low power consuming chip. To save significant power consumption
of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power
dissipation. In this thesis, we propose high speed low-power multiplier algorithms. The booth multiplier
will reduce the number of partial products generated by a factor of 2. The adder will avoid the
unwanted addition and thus minimize the switching power dissipation. The proposed high speed low
power multiplier can attain speed improvement and power reduction in the Booth encoder when
compared with the conventional array multipliers. The power consumption concern and the little occupancy
are the major requirements of the fabrication of the DSP systems and other efficient performing
systems. The important criteria for improvement are the enhancing speed and space of the multiplier.
The speed and the space are relied on each other which mean increasing speed concludes with the more
consuming space.
We have focused to come out with a conclusion by studying more multipliers. We have studied three
different multipliers differently. We found that the serial multipliers needs more power consumption
compared to parallel multipliers. The project has three different multipliers called













With advances in technology, many researchers have tried and are trying to design multipliers which offer
either of the following- high speed, low power consumption, regularity of layout and hence less area or
even combination of them in multiplier. Thus making them suitable for various high speed, low power,
and compact VLSI implementations. However area and speed are two conflicting constraints. So
improving speed results always in larger areas. So here we try to find out the best trade off solution
among the both of them. Generally as we know multiplication goes in two basic steps. Partial product and
then addition. Hence in this paper we have first tried to design different adders and compare their speed
and complexity of circuit i.e. the area occupied. And then we have designed Wallace tree multiplier then
followed by Booths Wallace multiplier and have compared the speed and Power consumption in them.
While comparing the adders we found out that Ripple Carry Adder had a smaller area while having lesser
speed, in contrast to which Carry Select Adders are high speed but posses a larger area. And a Carry Look
Ahead Adder is in between the spectrum having a proper trade off between time and area complexities.
After designing and comparing the adders we turned to multipliers. Initially we went for Parallel
Multiplier and then Wallace Tree Multiplier. In the mean time we learned that delay amount was
considerably reduced when Carry Save Adders were used in Wallace Tree applications. Then we turned
to Booths Multiplier and designed Radix-4 modified booth multiplier and analyzed the performance of all
the multipliers.
After that we turned to different methods of power optimization, of which we could only complete a few
like we went for designing different recoding schemes and their corresponding partial product generator
scheme. After that we designed these recoders and PP generators and found out the time delays and area
covered and power consumed by each scheme. We took into consideration that since all the PP generators
take a huge amount of area we need to go for simplest of the designs for them and also side by side we
need to ensure that we dont have much switching actions in the circuit. 8
After this we even modified one of the recoding schemes to lower the delay and power required by the
circuit. The result of our project helps us to make a proper choice of different multipliers in fabricating in
different arithmetic units as well as making a choice among different adders in different digital
applications according to requirements. All the programs and results have been given in the following
sections. Further work on Low Power Techniques on different multipliers needs to be done in order to
make us choose a proper multiplier in accordance with the requirements by making the best possible trade
off choice between Speed and Power in different circumstances.