Blast Chip 3.

1 User Guide
Understanding Blast Chip 1-1
1. Understanding Blast Chip
This chapter introduces the Magma Blast Chip 3.1 system:
Blast Chip Basics
Blast Chip Solutions
Blast Chip Flow
Blast Chip Basics
Blast Chip is a family of products that includes RTL synthesis, timing optimization and
analysis, floorplanning, power planning, place and route, and RC extraction technologies.
The system integrates these technologies with a common, open data model. There are
no translations among the engines that implement these technologies, so inter-tool
communication is fast and performance is excellent.
This section describes basic components and benefits:
Magma Design Implementation Products on page 1-2
Controlling the Blast Chip System on page 1-3
Blast Chip Features on page 1-3
Blast Chip Benefits on page 1-4
Blast Chip 3.1 User Guide
1-2 Understanding Blast Chip
Magma Design Implementation Products
Blast Chip is Magmas complete RTL-to-GDSII chip design and implementation system
is comprised of Blast RTL and Blast Fusion:
Blast RTL, a gain-based synthesis tool that seamlessly integrates fast,
high-capacity synthesis into a complete RTL-to-GDSII solution.
Blast Fusion, a physical design system that provides a complete
netlist-to-GDSII flow for cell-based ICs. Blast Fusion includes optimization, place
and route, useful skew clock generation, floorplanning and power planning, RC
extraction and a single, built-in incremental timing analyzer.
Blast Chip includes all Blast Fusion capabilities and is designed with the capacity to
handle the synthesis, placement and routing of very large, high-performance chips and
blocks.
Magma provides additional products and options to the Blast Chip system:
Blast Noise, an optional product that works with Blast Chip and Blast Fusion to
automatically detect and correct crosstalk noise during physical design. Option to
Blast Chip and Blast Fusion.
Blast Plan, an optional product that works with Blast Chip and Blast Fusion.
With Blast Plan, Magma enables both top-down and bottom-up hierarchical
planning within a single environment. Utilizing a unique GlassBox abstraction
technique, Magma's system provides the capacity to handle the hierarchical
planning of very large designs. Option to Blast Chip and Blast Fusion.
Blast Logic, a product that reads in a netlist and constraints and generates
reports that logic designers use to better assess the timing feasibility of their
design before handing it off to layout. This early visibility into timing can enable
designers to avoid iterations between physical and logic design, significantly
reducing time to market.
Blast Chip 3.1 User Guide
Understanding Blast Chip 1-3
Controlling the Blast Chip System
The Blast Chip 3.1 system is composed of two main components:
Mantle, a binary executable that comprises all the technologies that engage and
control all components of the Blast Chip family of products.
A graphical user interface (GUI) component, a stand-alone Java application that
displays design views and reports, and provides the graphical interface for
applying constraints and editing a design.
You can control the Blast Chip system from your local workstation with commands and Tcl
scripts, or you can control the system through the GUI. The intuitive and powerful GUI is
based on a client-server model that permits both local and remote connection to the Blast
Chip system.
Whether you use scripts and enter commands or you use the GUI, you have direct and
complete access to the system data model and controls. This allows you to optimize
timing, force constraints, map and remap libraries, and optimize the physical design.
See Chapter 2, Controlling Blast Chip for more information about these methods.
Blast Chip Features
The Blast Chip system uses several basic features, including the following, to handle very
large designs:
A common data model shared by all tools
RTL synthesis
Hierarchical Verilog output
Physical synthesis
Built-in timing analyzer
Floorplanning and placement
Clock tree synthesis
Clock routing
Blast Chip 3.1 User Guide
1-4 Understanding Blast Chip
Power routing
Global routing
Detailed routing
Noise and crosstalk control
Internal DRC and LVS checking
Parasitic extraction
Technology for controlling electromigration, signal integrity, and minimum metal
area
A graphical user interface (GUI)
For more detailed information about features of specific components, click Products and
Technology on the Magma Design Automation home page (www.magma-da.com).
Blast Chip Benefits
Blast Chip provides the following benefits:
Faster time to market
Eliminate the time-consuming iteration cycles that can delay the completion of
your critical chip design project. You can create complex, high-quality deep
submicron designs in less time.
Better chip performance
Design chips with greater speed, smaller area, and lower power consumption.
Powerful optimization technology coupled with the Magma innovative SuperCell
technology ensures the highest performance for your design.
Greater design capacity
Synthesize several million gates at a timean order of magnitude larger than
possible using traditional synthesis tools. Because the Magma single data model
retains only one copy of your design data in memory during runtime, it uses
memory efficiently, further enabling increased capacity.
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Understanding Blast Chip 1-5
Enhanced quality and reliability
The Magma single unified data model architecture allows automatic detection and
active avoidance of potential signal integrity problems. The Blast Noise product
provides automatic detection and avoidance of crosstalk noise and delay, and
corrects potential signal electromigration problems. Additionally, both Blast Fusion
and Blast Chip provide automatic correction of potential antenna problems that
can lead to lower chip yields.
Blast Chip Solutions
Recognizing the need for entirely new approaches to IC design, implementation, and
analysis, Magma offers powerful solutions based on innovative, patent-pending
technologies. These solutions address the performance and time-to-market challenges of
todays deep submicron IC designs. Find overviews of these solutions in the following
sections:
FixedTiming Methodology
Single Unified Data Model on page 1-6
SuperCell Models on page 1-6
Silicon Integrity Technology on page 1-7
Gain-Based Synthesis on page 1-7
FixedTiming Methodology
The Magma FixedTiming methodology combines logical and physical design to ensure
better performance while eliminating iterations between synthesis and place and route.
With FixedTiming, Blast Fusion determines the designs optimal timing prior to detailed
routing. The system then dynamically controls the size, placement, and wire
interconnects of each cell. This correct-by-construction approach eliminates the need to
resynthesize in order to improve timing performance.
Blast Chip 3.1 User Guide
1-6 Understanding Blast Chip
Single Unified Data Model
Tight integration of tools and design data enable the Magma design and implementation
systems to meet the performance requirements of todays ICs. The Blast Chip system is
built on a single unified data model architecture. This memory-resident data model
contains all of the design data and provides all of the Magma design and optimization
engines and analysis tools with immediate access to continuously updated logical,
physical, timing, and other design information. Conventional synthesis and
place-and-route solutions are made up of point tools that each have their own local data
model and rely on a common database for sharing of data. In this scheme, design data
must be reformatted and imported and exported between the toolsa cumbersome,
error-prone, and memory-inefficient process. In contrast, with all the components sharing
exactly the same design data, the Blast Chip system can make rapid, accurate design
decisions that ensure optimal results.
SuperCell Models
To achieve optimal timing, each logic cell must have the proper drive strength for the load
that it is driving. Because interconnect delay cannot be determined or accurately
estimated during synthesis, the Blast Chip system continuously varies cell sizing during
place and route to maintain constant timing. Rather than using presized cells from the
target library, the Magma approach replaces each logic function with automatically
abstracted SuperCell models (functional placeholder cells with variable sizes and fixed
delay). Initial placement and routing of the SuperCell models allow Blast Chip to
determine the final optimal timing for all paths in the design. Blast Chip completes the
layout while continuously adjusting the size of each SuperCell so that the delay remains
constant. Finally, it replaces the SuperCell models with actual library cells that have the
proper drive strength. Because each cell is sized optimally for the load that it is driving,
Blast Chip systems deliver layouts that are well balanced electrically, are more compact,
and use less power.
Blast Chip 3.1 User Guide
Understanding Blast Chip 1-7
Silicon Integrity Technology
Meeting timing requirements is just one of the major challenges of deep submicron
design. Meeting power, reliability, and manufacturing requirements are equally important.
The Magma design, implementation, and analysis solutions leverage Silicon Integrity
technology to specifically address these issues. Blast Chip automatically delivers
compact, power-efficient layouts and prevents and corrects crosstalk noise and delay,
electromigration, and antenna problems throughout the place-and-route flow. This
correct-by-construction approach ensures high quality results without requiring
time-consuming manual intervention.
Gain-Based Synthesis
Using a gain-based approach to synthesis, the Magma Blast Chip system can quickly
synthesize entire chips. Conventional synthesis approaches evaluate many circuit
topologies for each logic functionand include many combinations of cell drive strengths.
This compute-intensive process significantly limits the capacity of these tools and forces
you to break large designs into many small blocks. Rather than determine cell size up
front, the Magma gain-based approach determines the optimal circuit topology without
having to evaluate multiple cell sizes. Because the optimization search space is much
smaller, Blast Chip can synthesize much larger designs than a conventional synthesis
tool.
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1-8 Understanding Blast Chip
Blast Chip Flow
Blast Chip combines several tools in a single system, but the system is more than an
integration of design tools. Because Blast Chip shares a common data model, there are
no inter-tool translations. Each engine shares its results with others through a common
database to achieve an optimum design solution.
See Chapter 5, Blast Chip Flow and Optimization for detailed information about the
steps in the Blast Chip 3.1 flow.
Other vendors integrate tools by translating from one proprietary data format to another.
Even tools from the same vendor often use separate and incompatible data formats that
must be translated from one tool to another.
To use the Magma design flow, Blast Chip requires that you provide RTL (or a
synthesized netlist) plus a Volcano database containing the logical and physical
libraries. The Volcano database is the Magma binary database format. If you have
physical libraries in a LEF or GDSII format, and a timing library in .lib format, you can
import these files instead of a Volcano database.
After Blast Chip reads the RTL, it synthesizes the design and imports the libraries. You
perform timing analysis, determine best timing, fix the circuit timing as a constraint, size
cells, determine the design size, place the design and fix its size, and route the design to
meet the timing constraints.
Because Blast Chip tools share a common data model, the design flow is more efficient.
Figure 1-1 on page 1-9 shows a high-level Blast Chip design flow.
Blast Chip 3.1 User Guide
Understanding Blast Chip 1-9
An important concept, illustrated in the high-level design flow, is that timing is optimized
and fixed at the very beginning of the design process. You determine the best timing that
you can achieve for a design and get sign-off before proceeding. After timing is fixed,
optimize the design size and area utilization. Then fix sizes, route power, route clocks,
route and optimize wire loads, and finish by exporting GDSII. There are no iterations to
achieve timing goals.
Figure 1-1: Blast Chip Design Flow
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1-10 Understanding Blast Chip
Blast Chip Phases
There are four distinct phases to the Blast Chip 3.1 flow:
Gain-Based Synthesis
Physical Synthesis on page 1-12
Clock Synthesis on page 1-13
SI-Driven Routing on page 1-14
Gain-Based Synthesis
Gain-based synthesis, shown in Figure 1-2 on page 1-11, imports RTL and synthesizes
the design (Blast Chip or Blast RTL), offering:
o Fast, gain-based synthesis
o Automatic clock gating
o Integrated data path synthesis
Blast Chip 3.1 User Guide
Understanding Blast Chip 1-11
Figure 1-2: Gain-Based Synthesis Flow
SI-driven
routing
Gain-based
synthesis
Physical
synthesis
Clock
synthesis
Timing
checkpoint
Blast Chip
Blast RTL
Blast Fusion
GDSII
Timing
.lib
Physical
GDSII, LEF
Verilog
VHDL RTL
Constraints
SDC
Early Silicon Performance
Early Silicon Performance
(ESP), a unique gain-based
methodology, provides early
visibility to your chips
post-layout performance.
The overall gain distribution
of the design is the key
gauge of timing
convergence.
The percentage of cells with
a gain less than one is the
timing ESP value.
As the timing ESP value
increases, the likelihood of
timing convergence
decreases.
Blast Chip 3.1 User Guide
1-12 Understanding Blast Chip
Physical Synthesis
Physical synthesis, shown in Figure 1-3, optimizes the physical design, offering:
o Floorplanning
o Gain-based optimization
o Sizing-driven placement
o Global routing
Figure 1-3: Physical Synthesis Flow
Blast Noise
Analyze,
avoid,
adjust
Track reordering,
wire spacing,
net shielding
SI-driven
routing
Gain-based
synthesis
Physical
synthesis
Clock
synthesis
Timing
checkpoint
Blast Chip
Blast RTL
Blast Fusion
RTL
GDSII
Clock shielding
Slew
equalization,
buffer insertion,
gate sizing
Floorplanning
I/O planning
Macro placement
Power planning
Gain-based
physical synthesis
Size-driven global placement
Logic restructuring
Buffering, cloning, trimming
Global routing
Size selection
Blast Chip 3.1 User Guide
Understanding Blast Chip 1-13
Clock Synthesis
Clock synthesis, shown in Figure 1-4, creates and optimizes clocks, offering:
o Multi-clock domain optimization
o Useful skew
o Clock shielding and routing
Figure 1-4: Blast Chip Design Flow: Clock Synthesis
Blast Noise
Analyze,
avoid,
adjust
SI-driven
routing
Gain-based
Synthesis
Physical
synthesis
Clock
synthesis
Timing
checkpoint
Blast Chip
Blast RTL
Blast Fusion
RTL
GDSII
Clock shielding
Track
reordering,
wire spacing,
net shielding
Slew
equalization,
buffer insertion,
gate sizing
Clock Optimization
Complete automated clock
implementation
Simultaneous optimization
of multiple clock domains
Useful skew
Clock Routing and Reliability
Full or partial clock shielding
Wide spacing or supply shields
Gated or hierarchical branch
process, voltage, and
temperature tolerant
optimization
Blast Chip 3.1 User Guide
1-14 Understanding Blast Chip
SI-Driven Routing
SI-driven routing, shown in Figure 1-5, eliminates signal integrity (SI) violations, offering:
o Antenna and noise avoidance
o Detailed routing
o DRC and LVS
Figure 1-5: Blast Chip Design Flow: SI-Driven Routine
SI-driven
routing
Blast Noise
Analyze,
avoid
adjust
Track reordering,
wire spacing,
net shielding
Gain-based
synthesis
Physical
synthesis
Clock
synthesis
Timing
checkpoint
Blast Chip
Blast RTL
Blast Fusion
RTL
GDSII
Clock shielding
Slew
equalization,
buffer insertion,
gate sizing
Aids to manufacturing
Antenna handling
Metal slotting and fill
Routing
Track route
Detailed route (subgrid
routing)
Built-in DRC and LVS
verification
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Understanding Blast Chip 1-15
Comparing the Design Flow Concepts and
Commands
The Blast Chip 3.1 system is comprised of the four major steps of the design flow
described in the following sections:
Gain-Based Synthesis on page 1-10
Physical Synthesis on page 1-12
Clock Synthesis on page 1-13
SI-Driven Routing on page 1-14
You can implement these steps through the pre-packaged scripts or customize them for a
specific design flow.
Figure 1-6 on page 1-16 shows the flow and some of the commands that you can use to
implements the processes. See Chapter 5, Blast Chip Flow and Optimization, for details
about the design flow implementation and fix scripts.
Blast Chip 3.1 User Guide
1-16 Understanding Blast Chip
Figure 1-6: Blast Chip Design Flow: Concepts and Commands
SI-driven
routing
Gain-based
synthesis
Physical
synthesis
Clock
synthesis
Timing
checkpoint
Blast Chip
Blast RTL
Blast Fusion
RTL
GDSII
fix wire
fix clock
fix cell
fix time -rtl
fix time
fix rtl
fix netlist
Netlist RTL
floorplanning
Blast
Chip
Blast RTL
Blast
Fusion
GDSII
Blast Chip Concept Flow Blast Chip Command Flow
Timing checkpoint