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12-Bit ADC AD1674
12-Bit ADC AD1674
AGND
A
AAAA
AA
A
AAAAAA
AA
CONTROL
10V
REF
CLOCK
12
COMP
20k
REF IN
5k
BIP OFF
20V
IN
10VIN
SAR
12
10k
10k
5k
DAC
IDAC
2.5k
2.5k
5k
SHA
FEATURES
Complete Monolithic 12-Bit 10 ms Sampling ADC
On-Board Sample-and-Hold Amplifier
Industry Standard Pinout
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
65 V, 610 V, 0 V10 V, 0 V20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 and SMD Compliant Versions Available
12
STS
DB11 (MSB)
DB0 (LSB)
AD1674
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD1674 is a complete, multipurpose, 12-bit analog-todigital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD1674SPECIFICATIONS
(TMIN to TMAX, VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 15 V 6 10% or
Min
RESOLUTION
12
AD1674J
Typ
Min
AD1674K
Typ
Max
12
12
Unit
Bits
Max
1/2
12
LSB
Bits
LSB
LSB
0.25
% of FSR
+70
0.1
0
0.25
+70
0.1
0
TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2
2
2
6
1
1
3
LSB
LSB
LSB
2
1/2
2
1
1/2
1
LSB
LSB
LSB
+5
+10
+10
+20
Volts
Volts
Volts
Volts
7
14
k
k
+5.5
+16.5
11.4
Volts
Volts
Volts
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE
5
10
0
0
3
6
+4.5
+11.4
16.5
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion
5
10
9.9
+5
+10
+10
+20
5
10
0
0
7
14
3
6
+5.5
+16.5
11.4
+4.5
+11.4
16.5
5
10
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
385
575
385
575
mW
10.0
10.1
2.0
10.0
10.1
2.0
Volts
mA
9.9
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25C value to the value at T MIN or TMAX.
4
Reference should be buffered for 12 V operation.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. C
AD1674
Parameter
Min
RESOLUTION
12
AD1674A
Typ Max
12
0.1
40
AD1674T
Typ Max
Unit
Bits
1/2
1/2
12
Min
12
1
1
TEMPERATURE RANGE
AD1674B
Typ Max
12
Min
1/2
1
12
LSB
LSB
Bits
LSB
LSB
0.125
% of FSR
+125
0.25
+85
0.1
40
0.125
+85
0.1
55
TEMPERATURE DRIFT 3
Unipolar Offset2
Bipolar Offset2
Full-Scale Error2
2
2
8
1
1
5
1
2
7
LSB
LSB
LSB
2
1/2
2
1
1/2
1
1
1/2
1
LSB
LSB
LSB
+5
+10
+10
+20
Volts
Volts
Volts
Volts
5
10
7
14
k
k
+5.5
+16.5
11.4
Volts
Volts
Volts
ANALOG INPUT
Input Ranges
Bipolar
Unipolar
Input Impedance
10 Volt Span
20 Volt Span
POWER SUPPLIES
Operating Voltages
VLOGIC
VCC
VEE
Operating Current
ILOGIC
ICC
IEE
5
10
0
0
3
6
+4.5
+11.4
16.5
POWER DISSIPATION
INTERNAL REFERENCE VOLTAGE
Output Current (Available for External Loads) 4
(External Load Should Not Change During Conversion
REV. C
5
10
9.9
+5
+10
+10
+20
5
10
0
0
7
14
3
6
5
10
+5.5 +4.5
+16.5 +11.4
11.4 16.5
+5
+10
+10
+20
5
10
0
7
14
3
6
+5.5 +4.5
+16.5 +11.4
11.4 16.5
5
10
14
8
14
18
5
10
14
8
14
18
5
10
14
8
14
18
mA
mA
mA
385
575
385
575
385
575
mW
10.0
10.1
2.0
10.0
10.1
2.0
10.0
10.1
2.0
Volts
mA
9.9
9.9
AD1674SPECIFICATIONS
AC SPECIFICATIONS
(TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%, VEE = 15 V 610% or
12 V 6 5%, fSAMPLE = 100 kSPS, fIN = 10 kHz, stand-alone mode unless otherwise noted)1
Parameter
Min
AD1674J/A
Typ
Max
69
70
Min
AD1674K/B/T
Typ
Max
70
Units
71
dB
90
82
0.008
90
82
0.008
dB
%
92
82
92
82
dB
1
500
90
90
50
250
1
1
500
MHz
kHz
80
80
90
90
80
80
dB
dB
50
250
1
ns
ps
s
(for all grades TMIN to TMAX, with VCC = +15 V 6 10% or +12 V 6 5%, VLOGIC = +5 V 6 10%,
EE = 15 V 6 10% or 12 V 6 5%)
DIGITAL SPECIFICATIONS V
Parameter
LOGIC INPUTS
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIH
High Level Input Current (VIN = 5 V)
IIL
Low Level Input Current (VIN = 0 V)
CIN
Input Capacitance
LOGIC OUTPUTS
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
IOZ
High-Z Leakage Current
COZ
High-Z Output Capacitance
Test Conditions
Min
Max
Units
VIN = VLOGIC
VIN = 0 V
+2.0
0.5
10
10
VLOGIC +0.5 V
+0.8
+10
+10
10
V
V
A
A
pF
+0.4
+10
10
V
V
A
pF
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
+2.4
10
NOTES
1
fIN amplitude = 0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to 0 dB (9.997 V p-p) input signal unless
otherwise noted.
2
Specified at worst case temperatures and supplies after one minute warm-up.
3
See Figures 12 and 13 for other input frequencies and amplitudes.
4
See Figure 11.
5
fa = 9.08 kHz, fb = 9.58 kHz with f SAMPLE = 100 kHz. See Definition of Specifications section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. C
AD1674
SWITCHING SPECIFICATIONS
(for all grades TMIN to TMAX with VCC = +15 V 6 10% or +12 V 6 5%,
VLOGIC = +5 V 610%, VEE = 15 V 6 10% or 12 V 6 5%; VIL = 0.4 V,
VIH = 2.4 V unless otherwise noted)
J, K, A, B, Grades T Grade
Symbol Min Typ Max Min Typ Max Units
tC
tC
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
7
9
8
10
200
50
50
50
50
50
0
50
7
9
50
50
50
50
50
0
50
tHEC
CE
__
CS
8
s
10 s
225 ns
ns
ns
ns
ns
ns
ns
ns
tHSC
tSSC
_
R/C
tSRC
tSAC
A0
tHRC
tHAC
tC
STS
J, K, A, B, Grades
T Grade
Symbol Min Typ Max Min Typ Max Units
Access Time
Data Valid After CE Low
tDD1
tHD
tHL5
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
75
150
252
203
75
252
154
150
50
0
50
0
0
50
50
0
50
0
0
50
tDSC
DB11 DB0
HIGH IMPEDANCE
150 ns
ns
ns
150 ns
ns
ns
ns
ns
ns
ns
CE
__
CS
tHSR
tSSR
_
R/C
tSSR
A0
NOTES
1
tDD is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0C to TMAX.
3
At 40C.
4
At 55C.
5
tHL is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
tHRR
tSAR
tHAR
tHS
STS
tHD
DB11 DB0
HIGH
HIGH
DATA
VALID
IMPEDANCE
tDD
IMP.
tHL
Test
VCP
COUT
5V
0V
0V
5V
100 pF
10 pF
100 pF
10 pF
IOL
DOUT
VCP
COUT
IOH
REV. C
AD1674
TIMINGSTAND-ALONE MODE (Figures 4a and 4b)
Parameter
Symbol
tDDR
tHRL
tDS
tHDR
tHS
tHRH
Min
J, K, A, B Grades
Typ
Max
T Grade
Typ
Min
150
50
Units
150
ns
ns
ns
ns
s
ns
50
200
25
0.6
150
Max
0.8
225
25
0.6
150
1.2
0.8
1.2
NOTE
All min and max specifications are guaranteed.
Specifications subject to change without notice.
tHRL
_
R/C
_
R/C
tDS
tHRH
tDS
STS
STS
tDDR
tC
tHS
tHDR
DB11 DB0
DATA
VALID
DB11 DB0
HIGH-Z
HIGH-Z
tC
tHDR
HIGH-Z
DATA
VALID
DATA VALID
tHL
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1674 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model1
Temperature Range
INL
(TMIN to TMAX)
S/(N+D)
(TMIN to TMAX)
Package
Description
Package
Option2
AD1674JN
AD1674KN
AD1674JR
AD1674KR
AD1674AR
AD1674BR
AD1674AD
AD1674BD
AD1674TD
0C to +70C
0C to +70C
0C to +70C
0C to +70C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
55C to +125C
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
69 dB
70 dB
70 dB
Plastic DIP
Plastic DIP
Plastic SOIC
Plastic SOIC
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
N-28
N-28
R-28
R-28
R-28
R-28
D-28
D-28
D-28
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current
AD1674/883B data sheet. SMD is also available.
2
N = Plastic DIP; D = Hermetic Ceramic DIP; R = Plastic SOIC.
REV. C
AD1674
PIN DESCRIPTION
Symbol
AGND
A0
9
4
P
DI
BIP OFF
12
AI
CE
CS
DB11DB8
6
3
2724
DI
DI
DO
DB7DB4
2320
DO
DB3DB0
1916
DO
DGND
REF OUT
R/C
15
8
5
P
AO
DI
REF IN
STS
10
28
AI
DO
VCC
VEE
VLOGIC
10 VIN
7
11
1
13
P
P
P
AI
20 VIN
14
AI
12/8
DI
AI
AO
DI
DO
P
=
=
=
=
=
Analog Input
Analog Output
Digital Input
Digital Output
Power
AGND
A
AA
AA
AA
A
AA
AAAAAA
AA
CONTROL
10V
REF
CLOCK
12
COMP
20k
REF IN
5k
BIP OFF
20V
IN
10VIN
12
10k
10k
5k
DAC
IDAC
2.5k
2.5k
REV. C
SAR
5k
SHA
AD1674
TYPE:
12
PIN CONFIGURATION
STS
DB11 (MSB)
DB0 (LSB)
VLOGIC
28
STS
12/8
27
DB11(MSB)
CS
26 DB10
A0
25
DB9
R/C
24
DB8
CE
23
DB7
VCC
22
DB6
REF OUT
21
DB5
AGND
20
DB4
REF IN
10
19
DB3
VEE 11
18
DB2
BIP OFF
12
17
DB1
10VIN
13
16
DB0(LSB)
20VIN
14
15
DGND
AD1674
TOP VIEW
(Not to Scale)
AD1674
DEFINITION OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
The first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the
actual transition from that point at 25C. This offset can be
adjusted as shown in Figure 11.
BIPOLAR OFFSET
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error specifies the
deviation of the actual transition from that point at 25C. This
offset can be adjusted as shown in Figure 12.
FULL-SCALE ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10 volts full scale). The full-scale
error is the deviation of the actual level of the last transition
from the ideal level at 25C. The full-scale error can be adjusted
to zero as shown in Figures 11 and 12.
S/(N+D) is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of a full-scale input signal and is expressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
INTERMODULATION DISTORTION (IMD)
TEMPERATURE DRIFT
FULL-LINEAR BANDWIDTH
REV. C
AAAA
AAAA
AAA
AAA
80
fSAMPLE = 100kSPS
AMPLITUDE dB
20
60
20dB INPUT
S/(N+D) dB
THD
40
60
80
10
100
1000
40
30
60dB INPUT
10
2NDHARMONIC
120
50
20
3RD
HARMONIC
100
0dB INPUT
70
FULL-SCALE = +10V
10000
100
10
1000
10000
10
20
30
40
AMPLITUDE dB
AMPLITUDE dB
20
60
80
100
40
50
60
70
80
90
100
120
110
120
140
0
10
15
20
25
30
35
40
45
FREQUENCY kHz
50
130
0
10
30
20
25
FREQUENCY kHz
35
40
45
50
Figure 9. IMD Plot for fIN = 9.08 kHz (fa), 9.58 kHz (fb)
DAC current sum to be greater than or less than the input current. If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a 12-bit
binary code which accurately represents the input signal to
within 1/2 LSB.
The AD1674 is a complete 12-bit, 10 s sampling analog-todigital converter. A block diagram of the AD1674 is shown on
page 7.
When the control section is commanded to initiate a conversion
(as described later), it places the sample-and-hold amplifier
(SHA) in the hold mode, enables the clock, and resets the successive approximation register (SAR). Once a conversion cycle
has begun, it cannot be stopped or restarted and data is not
available from the output buffers. The SAR, timed by the internal clock, will sequence through the conversion cycle and return
an end-of-convert flag to the control section when the conversion has been completed. The control section will then disable
the clock, switch the SHA to sample mode, and delay the STS
LOW going edge to allow for acquisition to 12-bit accuracy.
The control section will allow data read functions by external
command anytime during the SHA acquisition interval.
CONTROL LOGIC
The AD1674 may be operated in one of two modes, the fullcontrol mode and the stand-alone mode. The full-control mode
utilizes all the AD1674 control signals and is useful in systems
that address decode multiple devices on a single data bus. The
stand-alone mode is useful in systems with dedicated input ports
available and thus not requiring full bus interface capability.
Table I is a truth table for the AD1674, and Figure 10 illustrates the internal logic circuitry.
Table I. AD1674A Truth Table
15
CE CS
R/C
12/8 A0 Operation
0
X
X
1
X
X
X
X
X
X
None
None
1
1
0
0
0
0
X
X
0
1
1
1
0
0
1
1
0
0
0
1
AD1674
VALUE OF A AT LAST
0
CONVERT COMMAND
D
Q
EN
Q
QB
EN
EOC 12
EOC 8
S
S
SAR RESET
R QB
1s DELAY-HOLD SETTLING
CE
CLK ENABLE
CS
STATUS
R/C
1s DELAY-ACQUISITION
HOLD/SAMPLE
A0
12/8
NYBBLE A
READ
NYBBLE B
NYBBLE C
TO OUTPUT
BUFFERS
NYBBLE B = 0
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS) and Read/ Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
STAND-ALONE MODE
REV. C
AD1674
R1
100k
+15V
15V
100k
R2
100
100
12/8
3
4
CS
A
5
6
10
8
12
R/C
CE
REF IN
REF OUT
BIP OFF
REFERENCE DECOUPLING
STS 28
HIGH BITS
24-27
It is recommended that a 10 F tantalum capacitor be connected between REF IN (Pin 10) and ground. This has the
effect of improving the S/(N+D) ratio through filtering possible
broad-band noise contributions from the voltage reference.
MIDDLE BITS
20-23
LOW BITS
16-19
BOARD LAYOUT
AD1674
0 TO +10V
ANALOG
INPUTS
0 TO +20V
13 10VIN
14 20VIN
9 ANA COM
+5V 1
+15V 7
15V 11
DIG COM 15
R2
100
5V
ANALOG
INPUTS
10V
R1
100
12/8
CS
A0
R/C
CE
REF IN
REF OUT
BIP OFF
IN
14 20VIN
9 ANA COM
SUPPLY DECOUPLING
The AD1674 power supplies should be well filtered, well regulated, and free from high frequency noise. Switching power supplies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout proximity between all power supply pins and ground. A 10 F tantalum capacitor in parallel with a 0.1 F disc ceramic capacitor
provides adequate decoupling over a wide range of frequencies.
STS 28
HIGH BITS
24-27
MIDDLE BITS
20-23
LOW BITS
16-19
AD1674
13 10V
The AD1674 incorporates several features to help the users layout. Analog pins are adjacent to help isolate analog from digital
signals. Ground currents have been minimized by careful circuit
architecture. Current through AGND is 2.2 mA, with little
code-dependent variation. The current through DGND is dominated by the return current for DB11DB0.
+5V 1
+15V 7
15V 11
DIG COM 15
REV. C
11
AD1674
GROUNDING
PACKAGE INFORMATION
0.505 (12.83)
28
15
0.59 0.01
(14.98 0.254)
PIN 1
14
0.050 0.010
(1.27 0.254)
1.42 (36.07)
1.40 (35.56)
A typical A/D converter interface routine involves several operations. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to complete, since most ADCs take longer than one instruction cycle to
complete a conversion. Valid data can, of course, only be read
after the conversion is complete. The AD1674 provides an output signal (STS) which indicates when a conversion is in
progress. This signal can be polled by the processor by reading
it through an external three-state buffer (or other input port).
The STS signal can also be used to generate an interrupt upon
completion of a conversion, if the system timing requirements
are critical (bear in mind that the maximum conversion time of
the AD1674 is only 10 microseconds) and the processor has
other tasks to perform during the ADC conversion cycle. Another possible time-out method is to assume that the ADC will
take 10 microseconds to convert, and insert a sufficient number
of no-op instructions to ensure that 10 microseconds of processor time is consumed.
0.095
(2.41)
0.145 0.02
(3.68 0.51)
0.125
(3.17)
MIN
0.010 0.002
(0.254 0.05)
0.085
(2.16)
0.017 0.003
(0.43 0.076)
0.047 0.007
(1.19 0.178)
0.1 (2.54)
0.6 (15.24)
SEATING
PLANE
15
28
0.550 (13.97)
0.530 (13.462)
PIN 1
1
14
1.450 (38.83)
1.440 (35.576)
0.160 (4.06)
0.140 (3.56)
0.200
(5.080)
MAX
0.175 (4.45)
0.120 (3.05)
0.020 (0.508)
0.015 (0.381)
0.105 (2.67)
0.095 (2.41)
0.606 (15.39)
0.594 (15.09)
15
0
0.065 (1.65)
0.045 (1.14) SEATING
PLANE
0.012 (0.305)
0.008 (0.203)
15
28
0.2992 (7.60)
0.2914 (7.40)
PIN 1
14
0.1043 (2.65)
0.0926 (2.35)
0.7125 (18.10)
0.6969 (17.70)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
BSC
0.4193 (10.65)
0.3937 (10.00)
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
0.0291 (0.74)
x 45
0.0098 (0.25)
8
0
0.0500 (1.27)
0.0157 (0.40)
12
REV. C
PRINTED IN U.S.A.
C1425b103/94