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Digital Two-Loop Controller Design For Fourth Order Split-Inductor Converter
Digital Two-Loop Controller Design For Fourth Order Split-Inductor Converter
Digital Two-Loop Controller Design For Fourth Order Split-Inductor Converter
(2)
where [A
j
]- state matrix, [B
j
]- input matrix, [E
j
]- output
matrix, and [x]- state vector, [y]- output vector, [u]- forcing
function vector.
1 1
1 3 3
1
2
1 2
/ 0 0 0
0 / 1/ 0
;
0 1/ 0 0
0 0 0 1/ ( ( ))
c
c
r L
r L L
A
C
C R r
=
+
2
3 3 3 3 3
2
1
2 2 2 2
[ ] / / 1/ / ( * )
/ [ ] / 0 / ( * )
;
1/ 0 0 0 0
/ ( ) / ( ) 0 1/ ( ( ))
e c
c c
c
a r L a L L a r L
a L a r L a r L
A
C
R C R R C R C R r
+
+
=
+
[ ]
2 1
1/ 0 0 0 ;
T
B L = [ ]
2
1/ 0 0 0
T
B L =
C3
1 2
C3 C3
Rr R
E =E = 0 0 0
(R+r ) (R+r )
The above matrices gives an idea of the system that they are
linear in each mode of operation, and the circuit behavior can
easily be obtained by the discrete-time state- model [4] given
by eqns. (3) and (4).
^ ^ ^
[ ] [ 1] [ 1] x n x n d n = + ; (3)
0 k
v = E x ; (4)
s d d 1 2 1
DT -t ) T A ( A A D Ts
=e e e ;
s d 2 1
DT -t ) A A ( D Ts
s
=KT e e
where
[ ]
T
L1 L3 c1 c0
x = i i v v ,
g
u=[V ]. Detailed discrete-
time formulations are reported in ref[4] are used and they are
listed here, eqns. (5)-(9), for ready reference.
-1
vg
G ( ) E (z- ) +F z =
(5)
-1
vd
G ( ) E (z- ) z = (6)
-1
( ) P [(ZI- ) ]
in
Z z = (7)
-1
( ) [E (zI- ) +J ]
o
Z z = (8)
3 2
3 2 1 o
vd
4 3 2
4 3 2 1 o
p z +p z +p z+a
G (z)=
[q z +q z +q +q z+q ] z
(9a)
Substituting the converter parameters, given in Section IV,
results in the following control-to-output transfer function.
3 2
vd
4 3 2
12.68z -31.85z +28.66z-8.982
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z
(9b)
3 2
id
4 3 2
6.632z -16.83z +15.64z-5.383
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z
(9c)
TABLE II. FOURTH ORDER SPLIT-INDUCTOR CONVERTER PARAMETERS
Parameter Value
Vg 15 V 20%
Vo 36 V
R 26 50%
L1, r1 100 H, 0.08
L2, r2 100 H, 0.05
L3, r3 200 H, 0.07
C1, rc1 50 F, 0.14
C0, rc0 100 F, 0.22
fs 50 kHz
III. DIGITAL CONTROLLER DESIGN GUIDELINES
Once the power stage transfer functions are known, then
the digital controller can easily be designed to obtain the
desired closed-loop dynamical performance. Several
compensator design approaches [5]-[10] have been reported
in the literature for the analogue controllers. However, there
are two different approaches can be used while designing the
digital compensator, which are: (i) digital redesign approach,
(ii) digital direct design approach (DDDA). The detailed
discussion about these methods have been given in Ref[7].
The second method, DDDA, is used in this paper for digital
controller design. Pole-zero placement technique is used
while arriving at suitable digital compensator, and its brief
description for one such compensator, two-zero two-pole
structure, is given in the following steps: (i) to reduce
regulation error of the load voltage, the loop gain crossover
frequency, f
c
, should be as high as possible, (ii) set the loop
gain crossover frequency, f
c
be in the range of 1/20 ~ 1/50
of the switching frequency f
s
, (iii) select f
3
as multiples of
f
c
like (
3
2
c
f f =
), (iv) select the frequencies f
2
and
f
3
such that they are in geometric mean with respect to f
c
i.e.,
1 3 c
f f f =
, (v) place the two compensator zeroes
below the crossover frequency (f
1
< f
2
< fc), f
1
=f
2
/10, f
2
=f
c
/f
3
,
(vi) place the two compensator poles above the cross over
frequency (f
c
< f
3
< f
4
), f
4
=10f
3
. These design steps have been
taken into consideration while designing the digital
compensator. However, fine tuning of these locations is
needed depending on the nature of converter transfer
functions. The closed-loop block diagram is shown in Fig. 2.
Use of this approach allows the designer to incorporate the
inherent digital delays present in the actual system. By using
above steps the compensator design can be carried out with
the help of any software program. However, MATLAB [11]
platform is the good choice for compensator design as it is
having all the control related functions. Check all the closed-
loop converter performance specifications, and if the design
is not fulfilling the requirements repeat the process by
1139
changing the crossover frequency, location of pole-zeros and
controller gain. By embedding the closed-loop converter into
any of the power electronic simulators it is easy to verify the
time domain responses through simulations. The overall loop
gain of the closed loop system, including inner current-loop
and outer voltage loop, is in the form given in eqn. 10.
( )
i v
T z T T = +
(10)
( ) ( ) ( ) ( ) ,
( ) ( ) ( ) ( ) ,
i c i d p
v c v d p
T z G z G z G z
T z G z G z G z
=
=
(11)
1 2
3
1
( )( )
( )
( 1)( )
( )
( )
( 1)
v
cv
i
ci
k z a z a
G z
z z a
k z b
G z
z
=
(12)
Among all the above equations the control-to-output
transfer function, G
vd
(z), and control-to-inductor current,
G
id
(z), given by eqn. 9, is required while designing the outer
voltage-loop and inner current-loop controllers. After
substituting the required matrices in the mathematical
identities the resulting transfer function is given by (9). Once
having these transfer functions the individual loop design can
easily be carried out and the corresponding steps explained
above the compensator is designed with the help of
MATLAB [8] platform, wherein almost all linear system
theory related functions are readily available. Check all the
closed-loop converter performance specifications, gain
margin (GM) at least 6 dB and phase margin (PM) in between
30
0
~ 75
0
, and if the design is not fulfilling the requirements
repeat the process by changing the crossover frequency,
locations of poles/zeros.
IV. DISCUSSIONS ON THE SIMULATION AND
EXPERIMENTAL RESULTS
In order to demonstrate the proposed converter salient
features and its controlling capability a 25 W, 15 to- 36 V
FSC is considered here and its parameters are listed in Table
II. State-space models, derived in Section II, have been used
and then important small-signal frequency response
characteristics have been obtained, using MATLAB. For
illustration, the overall loop design frequency response bode
plot is shown in Fig. 3. In order to stabilize the two-loop
system, the overall loopgain should follow the T
v
in the low
frequency region and T
i
in the high frequency region. To
achieve this, a two pole two zero compensators in outer loop
and one pole-zero in the inner loop is now included and the
corresponding loopgain frequency response plot is also
shown in Fig. 3. The digital controllers, G
cv
(z) and G
ci
(z),
parameters are: k
v
=0.9123, a
1
=0.941, a
2
=0.704, a
3
=0.849,
k
i
=0.5623, b
1
=0.941. This overall loopgain plot is exhibiting
a GM= 6.11 dB, PM=61
0
which are within the acceptable
stability limits.
To test the designed controller performance several
simulations, using PSIM simulator [12], have been performed
and then found that load regulation together with faster
dynamic response achieved in each case. Detailed simulation
results will be given in the final paper. The steady-state
voltage gain of the FSC has been verified by varying the duty
ratio, and found that the gain is increasing with increased
duty ratios. In order to validate the mathematical analysis and
simulation results a 25 Watts laboratory prototype FSC is
built and tested for its steady-state and dynamic performance.
To validate the developed theoretical analysis and
simulation results, a laboratory prototype closed-loop
converter has been built and then tested for its load voltage
regulation feature against source and load perturbations. The
digital control algorithm has been implemented using a
AMDC401digital signal processor (DSP) [10]. The devices
used in the prototype converter circuits are: Switch IRF540,
Diode MUR860, Driver circuit IR2110, Opto-coupler 6N137.
The load voltage is sensed and is brought down into the range
(0~1 V), which is passed on to the onboard ADC of the DSP.
The digital controller, given by eqn. 12, has been transformed
into a discrete-time control law given by:
( ) 1.849 ( 1) 0.849 ( 2) 0.9123 ( )
1.5 ( 1) 0.6044 ( 2)
v v v v
v v
d n d n d n e n
e n e n
= +
+
( ) ( 1) 0.5623 ( ) 0.5297 ( 1)
i i i i
d n d n e n e n = +
where d(n), d(n-1) and d(n-2) are the new, one-cycle-before
and two-cycles-before duty ratios, respectively; while e(n),
e(n-1) and e(n-2) are the new, one-cycle-before and two-
cycles-before error signals, respectively.
For demonstration of the principle sample experimentally
measured load voltage dynamic response characteristics for
the following cases: (i) load disturbance from 52 26
(50% variation), (ii) supply voltage change from 15 19 V
(20% variation). These measured results, Fig. 5, clearly
indicate that the designed digital controllers are regulating the
load voltage to the reference value of 36 V and exhibiting
faster dynamics response against source and load
disturbances.
-50
0
50
100
M
a
g
n
i
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
10
5
-270
-180
-90
0
90
P
h
a
s
e
(
d
e
g
)
Bode Diagram
Frequency (Hz)
Ti
Tv
T1
Fig. 3. Frequency response bode plot of Ti, Tv, overall loopgain T transfer
functions.
1140
(a) Load perturbation (R: 52 26 )
(b) Source perturbation (Vg: 15 19 V)
Fig. 4. Simulated dynamic response of the load voltage.
(a) Load resistance perturbation (R: 52 26 )
(b) Source voltage perturbation (Vg: 15 19 V)
Fig. 5. Measured dynamic response of the load voltage.
V. CONCLUSION
Digital two-loop controller was designed for fourth order
split inductor converter. The comparative study shown that
the proposed converter has resulted in better performance
over the conventional SEPIC converter. Digital two-loop
controller, with inner current-loop and outer voltage-loop has
resulted better dynamic response against the source and load
perturbations. Simulation and experimental were in close
agreement with each other and thus validating the controller
design.
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1141
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