This document provides step-by-step instructions for using the Pyxis tools to design a schematic, generate a layout, run simulations and extract parasitics. It describes how to:
1. Create a new project and schematic using the esign manager. Components are instantiated from libraries and ports are added.
2. Generate a symbol for the schematic and add input/output ports.
3. Create a testbench schematic to provide stimulus, instantiate the design symbol, and add voltage sources for testing.
4. Generate a layout from the schematic using auto placement, manually add wells and routes, and place ports. Design rule and layout vs schematic checks are run.
This document provides step-by-step instructions for using the Pyxis tools to design a schematic, generate a layout, run simulations and extract parasitics. It describes how to:
1. Create a new project and schematic using the esign manager. Components are instantiated from libraries and ports are added.
2. Generate a symbol for the schematic and add input/output ports.
3. Create a testbench schematic to provide stimulus, instantiate the design symbol, and add voltage sources for testing.
4. Generate a layout from the schematic using auto placement, manually add wells and routes, and place ports. Design rule and layout vs schematic checks are run.
This document provides step-by-step instructions for using the Pyxis tools to design a schematic, generate a layout, run simulations and extract parasitics. It describes how to:
1. Create a new project and schematic using the esign manager. Components are instantiated from libraries and ports are added.
2. Generate a symbol for the schematic and add input/output ports.
3. Create a testbench schematic to provide stimulus, instantiate the design symbol, and add voltage sources for testing.
4. Generate a layout from the schematic using auto placement, manually add wells and routes, and place ports. Design rule and layout vs schematic checks are run.
This document provides step-by-step instructions for using the Pyxis tools to design a schematic, generate a layout, run simulations and extract parasitics. It describes how to:
1. Create a new project and schematic using the esign manager. Components are instantiated from libraries and ports are added.
2. Generate a symbol for the schematic and add input/output ports.
3. Create a testbench schematic to provide stimulus, instantiate the design symbol, and add voltage sources for testing.
4. Generate a layout from the schematic using auto placement, manually add wells and routes, and place ports. Design rule and layout vs schematic checks are run.
Applications Accessories Terminal STEP 2: Type Commands for Environment Setup and Tool Invoking on Terminal STEP 3: Creating New Project and Invoking Schematic Window for Schematic Capture in esign !anager" Goto File New Project and press Enter # new Project window $pens % Give Project Name and Location Folder STEP 4: Now In &i'rary Ta' option give path as % /mgc_ins/new_pdk/PDK/generic! #ll the configuration files will 'e invoked Click $( # new Window called "anage #$ternal Li%raries window will 'e invoked Click on #dd Standard &i'raries #ll Standard &i'raries will 'e added Now come to the esign !anager Window )ight Click on the newly created Project % Select &i'rary % *ive &i'rary Name Click $( # &i'rary is Created in the Project +ierarchy &ig't (lick on (reated Li%rar) and *elect New (ell *ive Cell Name )ight Click on Cell Select New *c'ematic *ive Schematic Name % Click $( # Schematic window will invoke Creating a new Deign: *oto the icon shown with #rrow a'ove and start instantiating the sym'ols Pick and place sym'ols from Generic! *)m%ols nmos/pmos *)m%ols Select the sym'ol and place it in workspace" Similarly Place all Components Now goto Generic Li%rar) Add +dd/ Gro,nd *)m%ol #dd Ports for Input and $utput from the Ta' at &eft +and Side ,shown 'elow with an arrow- Check and Save option Now Click on ('eck and *ave Ta% in Tool'ar" .our design will 'e checked and saved" It will look like as shown 'elow till this time/ Generating a S!"#$% &$r t'e S('e"ati( Ne0t we *enerate a sym'ol for the design" *oto Add Generate *)m%ol ,Shown #'ove with an arrow- # new *enerate Sym'ol Window will open up" *im,lation "ode -,tton Select Edit Sym'ol" Press $(" # sym'ol will 'e generated in a new Sym'ol Window" #dd Input and $utput Ports to the sym'ol" Check and Save Sym'ol" Generating ) Tet*en(' )n+ R,nning Si",%ati$n Creating a Test'ench for Providing Stimulus to the esign just made" *oto esign !anager !ake a new cell in the &i'rary .ou are working in" Create a new Schematic Page in the Cell" In the schematic Instantiate the Sym'ol of the design just made ,1y Clicking on I2 Sym'ol- #dd Input and output Ports to the Test'ench" Provide 3oltage sources to the Test'ench for Stimulus" Instantiate the 3oltage Sources" *oto Sources &i'rary in the design manager window % dc4v4source5Pulse4v4source #dd 'oth to the test'ench" Edit properties of the 3oltage sources" Then Click on Check and Save )un Simulation !ode from the green 'utton shown on &eft Side Palette ,shown a'ove with arrow- # new Entering Simulation !ode Window will $pen 6p" 7ust Click $( ,No Changes are to 'e made- The following Simulation Window will get Invoked" *et,p *im,lation Ta% Now click on Setup Simulation Ta' on &eft +and Palette" The Setup Simulation Window will 'e invoked" &,n *im,lation -,tton *elect Anal)sis Tran *ive Start Time 8888 9n Stop Time 8888:999n !a0 Time Step 8888 :9n Click #pply (lick Li%raries #dit *cenario #n Edit !odel Scenario window will open up" *ive a name to the *cenario *elect onl) TT ,nder ".*/ Click $(" Now select the Scenario just created" Se%e(t In(%,+e" Delete t'e window present t'ere" Click $(" Now goto Schematic and slect the Total esign i"e" from input to output; gra<e through the design" #gain goto *et,p *im,lation window .,tp,ts Select the Input Net name5 $utput Net Name Anal)sis 0000 All Task 0000*ave .nl) T)pe 0000 De1a,lt Click #dd Click #pply *oto *et,p *im,lation window "eas,res #s Previous; gra<e through the design from Input to $utput" Select everything that comes in the window" Click #dd Click #pply Close Setup Simulation Window" Now Press )un Simulation 1utton $nce again" # simulation will Start" .ou can see the result in the !essage 1o0 at 1ottom When Simulation Complete &ine is displayed in the window; it means simulation is $ver" Now 3iew Waveforms 'y clicking on +iew 2ave Latest 2D-s from )ight Palette E<wave window will 'e invoked; where you can see your waveforms" L)YO-T Deigning =or esigning the layout of this schematic; close it and go 'ack to design manager" Select the cell in which the schematic is present" )ight Click on the cell; *elect New La)o,t # New &ayout window will pop up; asking for the name of the &ayout" *ive the name of the layout and click $(" The New &ayout Window will get invoked" Click $( after checking the particular parameters in different fields i"e" Component Name; Cell Name; Process etc" The window for &ayout will open with one ta' of a schematic as 'elow/ A,to Pick and Place icon Now Click on the #uto Pick and Place Icon on the tool'ar" ,Shown a'ove with an arrow- The components will get placed on the &ayout workspace as shown 'elow" Now 6se &eft !ouse 1utton 2 CT)& 1utton of (ey 'oard for 'ringing the components closer" Pick 3 place Ports Click on Pick and place Ports" ,Shown a'ove with an #rrow- # window showing ports will open" Select Each port and the associated metal layer for it" Click #pply and $( for Placing Ports on &ayout" Add 4ro,te 4con Add Device icon Now goto Add Device or click on the #dd evice icon on &eft Palette",Shown with arrows- In the $'ject editor #TT)I16TE window; select Device Name g%_p In the P)$PE)T. Window; Select T)pe nwell Place nwell near Pmos; gra<ing through the surface of Pmos" Similarly select T)pe ps,% Place it near Nmos" 4&o,te Click on Iroute Icon in the Tool'ar" ,Shown with an arrow a'ove- Place Te$t 4con Click $n T. Icon ,shown a'ove with an arrow- In The The #ttri'ute window of the $'ject Editor select &ayer Name % !ET:TE>T *ive 3alues as +DD/gro,nd/4n_a/.,t and Place it on the Ports" C'e(/ing DRC *oto Tools (ali%re &,n D&( # window will open for Cali're" Click on )un )C and )C will 'e done" C'e(/ing L0S =or &3S *oto Tools &,n L+* # window for Cali're &3S will open" Click on )un &3S and &3S is performed" R,nning PEX =or PE> *oto Tools &,n P#5 # Cali're window will 'e invoked" In the Inputs Ta' Change/ Select La)o,t Ta% Format 6 GD*44 select #$port 1rom La)o,t +iewer In the $utputs Ta' Change the following/ E0traction !ode/ 0)C In Netlist % =ormat/ SP= 6se Names =rom/ &ayout Click on )un PE> and PE> will 'e performed" # report =ile will open Click on =ile % Save as #nd save the file in 5root *a(/ )nn$tati$n an+ 0eri1i(ati$n =or 1ack #nnotation Close the &ayout Window $poen Schematic Window" Click on *reen Simulation 1utton *oto Tools in !enu 1ar Tools Parasitics Add /#dit D*PF # window will 'e invoked" Click and 'rowse for the path of SP= file saved 'y you" Select SP= in Simulate using devices from" Now Simulate as earlier and 3iew waves in E<wave 3iewer" 1ack #nnotation is done and you have got the )esults in wave format"