CMOS

1. a) In CMOS technology, in digital design, why do we design the size of pmos to be

higher than the nmos. What determines the size of pmos wrt nmos. Though this is a
simple question try to list all the reasons possible?
b) Why PMOS and NMOS are sized equally in a Transmission Gates?
2. What is latch up? What are the ways to prevent it?
3. Explain velocity saturation
4. If given a choice between NAND and NOR gates, which one would you pick? Explain
5. What are the secondary effects in deep submicron technology in CMOS
6. What is Process variation
7. Draw a CMOS inverter. Explain its transfer characteristics
8. What is channel length modulation
9. a) Explain sizing of the inverter
b) What happens to delay if you increase load capacitance?
10. What is fringe capacitance, area capacitance and coupling capacitance?

Programming
1) WAP for Fibonacci series.
F=0,s=1;
For(1=0;i<n;i++)
If(i<=1)
{
Out=I;
Else
Out=f+s;
F=s;
S=out
}
2) WAP to detect a prime number.


Physical Design
1) What do you mean by temperature Inversion?
What happen for process below 65nm technologies or lower, due to temperature
inversion?
2) What is local skew, global skew?
3) (a) What is muticycle path?
(b) What is false path?




a)MULTI CYCLE path: By default, we expect every timing path to meet setup time in a single
clock cycle. However, we can also specify that some data is captured only after a specified
number of clock cycles. Till then, the data at the capturing flop will not be used. Of course
your circuit should be designed in such a way for this kind of behaviour to be valid. This is
usually a large combinational block between two registers. It is important to specify the
multicycle paths to synthesis and place&route tools, as the tools will otherwise try to fix these
paths.

b) A false path, as its name denotes is a timing path not required to meet its timing constraints for
the design to function properly.In general all timing paths those are launched by a valid startpoint
and captured by a valid endpoint impose setup and hold constraints. If the functionality of the
design is such that the timing constraints need not be met on the path, it is a false path.

Every false path needs to be informed to the STA tool. As the STA tool considers every path that
originates at a valid startpoint and ends on a valid endpoint as a valid timing path that needs to be
met.

A situation where the design results in false paths is:
There are two 2 input muxes in a design. Both of which are selected by a common select line.