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Roadmap PDF
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Topics of discussion
Topics of discussion
Discontinuance of PA
Discontinuance of PA
-
-
RISC, Alpha, and the e3000
RISC, Alpha, and the e3000
means HP users will eventually need to migrate to
means HP users will eventually need to migrate to
new systems platform
new systems platform
Summary Observations
Summary Observations
5
Speaker Background
Speaker Background
Computer industry for 26 years Computer industry for 26 years
Sales/marketing/research & analysis Sales/marketing/research & analysis
Technical background Technical background
Systems/OS Systems/OS
Comms Comms/networking /networking
Application development Application development
Migration Migration
Research/analysis Research/analysis
Former VP of Platforms and Services, Aberdeen Group Former VP of Platforms and Services, Aberdeen Group
Now independent Now independent
Author Author
Visualize This (Internet virtualization); Web Services Explained Visualize This (Internet virtualization); Web Services Explained
(Web services applied to business) (Web services applied to business)
New book on making IT systems and infrastructure serve business New book on making IT systems and infrastructure serve business
process flow (adaptive, agile, on process flow (adaptive, agile, on- -demand computing) demand computing)
Philosophy Philosophy
Information systems should serve business process flow Information systems should serve business process flow
6
The Situation
The Situation
HP is discontinuing Alpha and PA
HP is discontinuing Alpha and PA
-
-
RISC
RISC
Alpha Alpha
New generations include Alpha EV7 and EV79 chips through 2005 New generations include Alpha EV7 and EV79 chips through 2005
See Information Week article on the demise of Alpha at: See Information Week article on the demise of Alpha at:
http:// http://www.informationweek.com/story/showArticle.jhtml?articleID www.informationweek.com/story/showArticle.jhtml?articleID=15600236 =15600236
Support planned through 2011 Support planned through 2011
PA PA- -RISC RISC
PA PA- -8800 and PA 8800 and PA- -8900 roadmap through 2005 (or 2006) 8900 roadmap through 2005 (or 2006)
HP users will eventually need to migrate to new systems platform HP users will eventually need to migrate to new systems platforms s
HP would like to see: HP would like to see:
Its Tru64 Unix Alpha customers move to HP Its Tru64 Unix Alpha customers move to HP- -UX on EPIC/Itanium UX on EPIC/Itanium
Its HP Its HP- -UX PA UX PA- -RISC customers move EPIC/Itanium platforms RISC customers move EPIC/Itanium platforms
But moving from RISC architecture to the new EPIC architecture But moving from RISC architecture to the new EPIC architecture
means means adopting a completely new instruction set! adopting a completely new instruction set!
7
The Situation
The Situation
Further
Further
HP discontinued support for the HP e3000 HP discontinued support for the HP e3000
The e3000 line retired on October 31, 2003 The e3000 line retired on October 31, 2003
http://www.hp.com/products1/evolution/e3000/index.html http://www.hp.com/products1/evolution/e3000/index.html
Wants HP e3000 users to move to EPIC/Itanium Wants HP e3000 users to move to EPIC/Itanium
HP would like HP would like NonStopKernel NonStopKernel OS on MIPS and OpenVMS on OS on MIPS and OpenVMS on
Alpha customers to move to Itanium also Alpha customers to move to Itanium also
http://www.gartner.com/gc/webletter/hp/article1/article1.html http://www.gartner.com/gc/webletter/hp/article1/article1.html
HP has not adopted AMD HP has not adopted AMD s Opteron s Opteron
A 64 A 64- -bit Intel bit Intel- -based processor that has an instruction set similar to IA based processor that has an instruction set similar to IA- -
32 rather than a completely new instruction set (as is the case 32 rather than a completely new instruction set (as is the case with with
EPIC) EPIC)
Opteron would be an option for users with existing Intel Opteron would be an option for users with existing Intel- -based based
applications who want application and database consistency when applications who want application and database consistency when
moving from IA moving from IA- -32 to 64 32 to 64- -bit computing bit computing
Means only Windows/Linux 64 Means only Windows/Linux 64- -bit growth path will necessitate bit growth path will necessitate
dealing with the new EPIC/Itanium instruction set dealing with the new EPIC/Itanium instruction set
HP is clearly steering its customers to
HP is clearly steering its customers to
EPIC/Itanium
EPIC/Itanium
8
The Situation
The Situation
Finally
Finally
The migration story does not end with platforms The migration story does not end with platforms
HP has also announce that it is withdrawing its MA8000, EMA HP has also announce that it is withdrawing its MA8000, EMA
12000/16000 (last orders were in August, 2003) storage offerings 12000/16000 (last orders were in August, 2003) storage offerings
HP customers may also need to reevaluate
HP customers may also need to reevaluate
their storage situation.
their storage situation.
9
The Proposition
The Proposition
HP 9000
PA-RISC
HP 9000
PA-RISC
ProLiant
Intel 32-bit
ProLiant
Intel 32-bit
HP e3000
Proprietary 16-bit,
PA-RISC
HP e3000
Proprietary 16-bit,
PA-RISC
HP NonStop
MIPS
HP NonStop
MIPS
AlphaServer
Alpha
AlphaServer
Alpha
MPE/iX
HP-UX
Linux
Windows
Linux
OpenVMS
Tru64
NonStop Kernel
HP-UX, Linux,
Windows,
OpenVMS (future)
NonStop Kernel (future)
Integrity
64-bit
Itanium
10
The Predicament
The Predicament
"It's probably a good idea for developers and software vendors to do
a native port or re-compilation onto Itanium because RISC has no
understanding of some of the architectural constructs within Itanium.
Therefore, the code that was developed for PA-RISC cannot take
advantage of it," says Chris Franklin, enterprise server marketing
manager at HP.
Source: Infoconomy Information Age
July - 2002
11
What
What
Both RISC and EPIC are trying to tackle the same problem Both RISC and EPIC are trying to tackle the same problem
parallelization parallelization
RISC uses a design that allows the microprocessor to take part RISC uses a design that allows the microprocessor to take part
in the decisions regarding how to best process incoming in the decisions regarding how to best process incoming
instructions instructions
RISC supplements compiler optimization with hardware that RISC supplements compiler optimization with hardware that
extracts parallelism and is responsive to execution variability extracts parallelism and is responsive to execution variability
This is especially relevant at runtime (while a program is execu This is especially relevant at runtime (while a program is executing) ting)
because the processor can dynamically reschedule the workload it because the processor can dynamically reschedule the workload it
receives around failures and disruptions that may occur receives around failures and disruptions that may occur
EPIC uses an approach that performs all parallelization at the EPIC uses an approach that performs all parallelization at the
compiler level and then it tells the microprocessor what to do compiler level and then it tells the microprocessor what to do
EPIC attempts to increase performance by speculatively EPIC attempts to increase performance by speculatively
executing instructions and fetching data from memory without executing instructions and fetching data from memory without
knowledge of actual run time conditions knowledge of actual run time conditions
EPIC design uses EPIC design uses predication predication (conditional execution based on a (conditional execution based on a
qualifying circumstance/predicate) to qualifying circumstance/predicate) to avoid some of the delays avoid some of the delays
associated with branches associated with branches
EPIC architecture relies exclusively on compilers to extract EPIC architecture relies exclusively on compilers to extract execution execution
parallelism parallelism
15
A Closer Look at the EPIC Approach
A Closer Look at the EPIC Approach
How EPIC works
How EPIC works
The ramifications of using this predictive approach
The ramifications of using this predictive approach
By using a predictive data and control speculation approach, EPI By using a predictive data and control speculation approach, EPIC architecture allows C architecture allows
the compiler to move load instructions up earlier in program exe the compiler to move load instructions up earlier in program execution order and hence cution order and hence
initiate memory accesses earlier than would otherwise be possibl initiate memory accesses earlier than would otherwise be possible e
Memory latency (wait time) is reduced, resulting in the ability Memory latency (wait time) is reduced, resulting in the ability to execute program more quickly to execute program more quickly
This makes the EPIC/Itanium a real This makes the EPIC/Itanium a real screamer screamer in certain predictable application environments in certain predictable application environments
Outstanding performance in leading benchmarks (predictable test Outstanding performance in leading benchmarks (predictable test environments) environments)
Scientific, research, network edge, security, and high Scientific, research, network edge, security, and high- -performance computing environments performance computing environments
Very large database consolidation environments
Software Compiler Itanium
Programs written
in architecture in-
dependent "High Level
Language (e.g. C++,
Fortran, etc.)
Translates and
parallelizes com-
puting tasks and
presents them to
Itanium
Executes EPIC tasks
using underlying
parallel architecture,
bandwidth, execution
resources, and inte-
grated cache
Error management in hardware, firmware,and O/S
Very large database consolidation environments
This is a very good architecture in predictable,
number-crunching environments
16
A Closer Look at the EPIC Approach
A Closer Look at the EPIC Approach
A Closer Look at the EPIC Approach
A Closer Look at the EPIC Approach
Two drawbacks
Two drawbacks
EPIC intrinsically requires larger caches EPIC intrinsically requires larger caches
"Code Bloat" "Code Bloat"
EPIC instructions are 33% bigger than RISC instructions EPIC instructions are 33% bigger than RISC instructions
Architectural constraints require insertion of "No Architectural constraints require insertion of "No- -Operation" instructions Operation" instructions
The EPIC compiler must generate code to test if a problem was en The EPIC compiler must generate code to test if a problem was encountered and then generate countered and then generate
code to fix the problem code to fix the problem
Data is speculatively brought into cache and not used Data is speculatively brought into cache and not used
EPIC uses a static approach to determine how a workload should b EPIC uses a static approach to determine how a workload should be e
processed processed
Rigid execution schedule prevents EPIC from adjusting to data an Rigid execution schedule prevents EPIC from adjusting to data and control d control
patterns that do not fit assumptions made at compile time patterns that do not fit assumptions made at compile time
Inability to cope with runtime variability Inability to cope with runtime variability makes EPIC architecture makes EPIC architecture less desirable less desirable
than RISC for than RISC for transaction processing environments transaction processing environments
Runtime is when a system is actually executing commands. Failure to
execute properly at runtime means transactions need to be stopped, rolled-
back, restarted with loss of time but hopefully with no loss of data!
Some computer engineers consider this static approach the Some computer engineers consider this static approach the flaw flaw in in
EPIC architecture because EPIC attempts to predetermine how a EPIC architecture because EPIC attempts to predetermine how a
processor will respond in a dynamic, non processor will respond in a dynamic, non- -predictable environment predictable environment
(rather than examining how an application is behaving at run tim (rather than examining how an application is behaving at run time). e).
17
A Comment on Benchmarking
A Comment on Benchmarking
Because of the static scheduling nature of EPIC, Intel and HP Because of the static scheduling nature of EPIC, Intel and HP
encourage the use of a encourage the use of a profiling profiling step. step.
Profiling is an extra procedure after a program is compiled wher Profiling is an extra procedure after a program is compiled where one runs e one runs
the compiled program on sample data to see how it performs the compiled program on sample data to see how it performs -- -- and then and then
feeds the results back to the compiler for a feeds the results back to the compiler for a second compilation second compilation
Means the sample data must be highly representative of the real Means the sample data must be highly representative of the real data data
This is an expensive process that is only as good as the sample This is an expensive process that is only as good as the sample data data
EPIC works well in TPC EPIC works well in TPC- -C benchmarks (and others) because the C benchmarks (and others) because the
test data is known beforehand! test data is known beforehand!
The code can be pre The code can be pre- -profiled with a workload similar to TPC profiled with a workload similar to TPC- -C (or even with C (or even with
TPC TPC- -C itself) C itself)
EPIC can be tuned to the profile of the benchmark itself EPIC can be tuned to the profile of the benchmark itself usually usually
producing outstanding benchmark results. producing outstanding benchmark results.
Remember Remember it it s what happens at runtime in s what happens at runtime in
the real world that is important! the real world that is important!
18
A Closer Look at the RISC Approach
A Closer Look at the RISC Approach
RISC makers believe they can maintain leadership performance gro RISC makers believe they can maintain leadership performance growth without wth without
introducing a completely new architecture introducing a completely new architecture
Systems performance continues to scale with frequency (and RISC Systems performance continues to scale with frequency (and RISC vendors show vendors show
higher frequency roadmaps than Intel with Itanium) higher frequency roadmaps than Intel with Itanium)
Dual cores; Simultaneous Multi Dual cores; Simultaneous Multi- -Threading (SMT); etc. Threading (SMT); etc.
IBMs Approach:
Courtesy: IBM Corporation
19
A Closer Look at the RISC Approach
A Closer Look at the RISC Approach
Sun
Sun
s approach
s approach
Sun is working on a design that would place six to eight Sun is working on a design that would place six to eight
cores on one die, enabling the company to handle up to cores on one die, enabling the company to handle up to
32 threads simultaneously part of Sun 32 threads simultaneously part of Sun s Throughput s Throughput
Computing Initiative Computing Initiative codenamed codenamed Niagra Niagra) )
Called Called chip multi chip multi- -threading threading (CMT) (CMT) Sun expects to Sun expects to
process tens of threads simultaneously by leveraging the process tens of threads simultaneously by leveraging the
increased number of transistors on a microchip increased number of transistors on a microchip
By 2005, Sun expects to increase performance by By 2005, Sun expects to increase performance by
15X 15X
Beyond 2005, Sun expects to increase today Beyond 2005, Sun expects to increase today s s
process performance by a factor of 30X! process performance by a factor of 30X!
http://www.sun.com/processors/whitepapers/through http://www.sun.com/processors/whitepapers/through
put_whitepaper.pdf put_whitepaper.pdf
In other words, expect RISC technology to continue to have the
capacity and capability to deliver against the Moores Law
performance curve for quite some time!
20
A Closer Look at the RISC Approach
A Closer Look at the RISC Approach
Further, RISC makers believe that they have a solid and Further, RISC makers believe that they have a solid and
sustainable lead over Itanium in the areas of reliability, avail sustainable lead over Itanium in the areas of reliability, availability, ability,
and scalability and scalability
Courtesy: IBM Corporation
21
The Primary Issue:
The Primary Issue:
Applications Availability
Applications Availability
Forget about TPC
Forget about TPC
-
-
C, SPECWEB99_SSL, SPEC CPU2000,
C, SPECWEB99_SSL, SPEC CPU2000,
Linpak
Linpak
HPC et al
HPC et al
Hewlett
Hewlett
-
-
Packard is Intel
Packard is Intel
s co
s co
-
-
developer of EPIC
developer of EPIC
HP has bet the farm on EPIC HP has bet the farm on EPIC
Problems with HP approach: Problems with HP approach:
All roads lead to HP All roads lead to HP- -UX on EPIC/Itanium UX on EPIC/Itanium
HP/e3000 to HP HP/e3000 to HP- -UX on EPIC/Itanium migration tools UX on EPIC/Itanium migration tools
and plan and plan
HP Tru64/Alpha to HP HP Tru64/Alpha to HP- -UX on EPIC/Itanium migration UX on EPIC/Itanium migration
tools and plan tools and plan
HP HP HP HP- -UX/PA UX/PA- -RISC to HP RISC to HP- -UX on EPIC/Itanium UX on EPIC/Itanium
(custom engagements) (custom engagements)
What about people who want to go to Linux. Where What about people who want to go to Linux. Where
are the corresponding tools, utilities, and services? are the corresponding tools, utilities, and services?
What about Windows users or Linux users who want What about Windows users or Linux users who want
backward application compatibility with IA backward application compatibility with IA- -32? 32?
Where Where s HP s HP s AMD Opteron support for 64 s AMD Opteron support for 64- -bit bit
compatibility? compatibility?
30
Summary Observations
Summary Observations
re
re
ultimately trying to accomplish (hopefully it
ultimately trying to accomplish (hopefully it
s to
s to
build information systems that help streamline
build information systems that help streamline
business process flow)
business process flow)
Make your choice on whichever architecture and Make your choice on whichever architecture and
approach will help you achieve that objective! approach will help you achieve that objective!
31