Survey of Low Power VLSI Design

Techniques Exploring Sleep Transistors and

Forced Stack

Shiraz Husain
1
, Nilesh Kushwah
2
1,2
M.E, Final Year, VLSI Design. SVCE, Indore (M.P.)
shirazhusain.78678@gmail.com

Abstract- Power consumption is the major factor of
CMOS-VLSI technology. Earlier only Dynamic
power consumption was focused because it
accounted for 90% of the total power consumption.
But as the feature size shrinks down e.g.:-0.09 and
0.065 um; static power (leakage power) has become
a great challenge for current and future
technologies. The main contributors for the leakage
power are the subthreshold leakage power and
gate-oxide leakage power .Since we assume that
high-k dielectric gate insulators may provide a
solution to reduce gate-leakage; so we have focused
on reducing sub-threshold leakage power
consumption by techniques called as Sleepy Stack,
Sleepy Keeper, Dual Sleep and Forced Sleep which
combines the features of sleep transistor and forced
stack technique. These techniques are of great
beneficiary to those designers who require ultra-
low leakage power consumption but with the delay
and area overheads. This is a review paper
discussing the comparison of various techniques
such as forced stack, sleep transistor, sleepy stack,
Dual Sleep, Sleepy Keeper and Forced Sleep in
terms of area, power and delay.

Keywords-Low power VLSI, Sub threshold Leakage,
Stacking.
I. INTRODUCTION
Since the early days of the MOS
transistor, its switching capability has
been exploited by a wide variety of
applications. By applying a high or low
voltage on the gate contact, the current
flow between source and drain can be
switched on or off, respectively. The off-
state current was supposed to be very
small. In fact, early analytical models for
the electrical behavior of MOS
transistors like the low-level SPICE
models were even assuming a zero off-
state current. Commonly used equations
for deriving the drain current were based
on the well-known quadratic transfer
curve of a MOS transistor. Below a
certain gate-source voltage, called
Threshold voltage, the drain current
was supposed to be zero.
Surely, this has been a good
approximation for quite some time when
long channels and high supply voltages
were used. Then the semiconductor
industry started shrinking the devices to
increase their density on a chip leading
to higher power dissipation.
Additionally, the electric fields in the
device were constantly increasing
because the voltage drops over the gate
oxide and the channel stayed the same
while their sizes were reduced, leading
to reliability concerns. Consequently, the
supply voltage was decreased to
overcome these problems, though the
scaling method applied to the supply
voltage has been much more
conservative than the one for the device
geometry. The threshold voltage was
decreased, accordingly, to maintain good
driving capabilities.
As a result, the off-state current
gradually became a limiting factor for
down-scaling the threshold voltage since
it determines the power consumption of
a chip in its idle state. Basically, three
different regimes can be defined for the
operation of a MOS transistor. Based on
the inversion condition of the channel,
these regimes are called weak inversion,
moderate inversion, and strong
inversion.
In general, two mechanisms are
responsible for the current flow: drift
and diffusion. Under weak inversion the
channel surface potential is almost
constant across the channel and the
current flow is determined by diffusion
of minority carriers due to a lateral
concentration gradient. Under strong
inversion there exists a thin layer of
minority carriers at the channel surface
and a lateral electric field which causes a
drift current. The moderate inversion
regime is considered a transition region
between weak and strong inversion
where both current flow mechanisms
coincidently exist.
The subthreshold leakage current can be
expressed as follows:
I
sub
= K
1
We
Vth/nV
(1 e
V/N
)
where K1 and n are experimental values,
W is the width of the transistor, V
th
is
the threshold voltage and V

is the
thermal voltage.
Subthreshold leakage power increases
exponentially as threshold voltage
decreases. Furthermore, the structure of
the short channel device decreases the
threshold voltage even lower. In addition
to subthreshold leakage, another
contributor to leakage power is gate-
oxide leakage power due to the tunneling
current through the gate-oxide insulator.
Since gate oxide thickness may reduce
as the channel length decreases, in sub
0.1- m technology, gate-oxide leakage
power may be comparable to
subthreshold leakage power if not
handled properly. However, we assume
other techniques will address gate-oxide
leakage; for example, high- dielectric
gate insulators may provide a solution to
reduce gate-leakage. Therefore, this
paper focuses on reducing subthreshold
leakage power consumption.
II. PREVIOUS METHODS:
Techniques for leakage power reduction
can be grouped into the following two
categories:
1) State-saving techniques where circuit
state (present value) is retained. for
example: forced Stack
2) State-destructive techniques where the
current Boolean output value of the
circuit might be lost. For example: Sleep
Transistor.
Base case: We use the phrase base
case to refer to the conventional CMOS
technique. It consists of a pull-up
network and a pull-down network using
as few transistors as possible to
implement the Boolean logic function
desired.
Sleep Transistor Technique: The sleep
transistor technique shown in Fig 1 uses
sleep transistors between both Vdd and
the pull-up network as well as between
GND and the pulldown network.
Generally, the width/length (W/L) ratio
is sized based on a tradeoff between
area, leakage reduction, and delay. For
simplicity, we size the sleep transistor to
the size of the largest transistor in the
network (pull-up or pull-down)
connected to the sleep transistor. The
pMOS and nMOS sleep transistors in
Fig 1 have W/L=6 and W/L=3
respectively, If dual- values are
available, high-V
TH
transistors are used
for sleep transistors. Which adds high-
V
th
sleep transistors between both Vdd
and pull-up networks and as well as
between pull-down networks and GND.
While logic circuits use low-V
th

transistors in order to maintain fast logic
switching speeds. The sleep transistors
are turned off when the logic circuits are
not in use. By isolating the logic
networks using sleep transistors, the
sleep transistor technique dramatically
reduces leakage power during sleep
mode. However, the additional sleep
transistors increase area and delay.

Fig 1: Sleep Transistor Technique Circuit
Furthermore, during sleep mode, the
pull-up and pull-down networks will
have floating values and thus, will lose
state. These floating values significantly
impact the wake-up time and energy of
the sleep technique due to the
requirement to recharge transistors
which lost state during sleep.
Forced Stack Technique: another
technique to reduce leakage power is
done through transistor stacking.
Transistor stacking exploits the stack
effect; the stack effect results in
substantial subthreshold leakage current
reduction when two or more stacked
transistors are turned off together. As a
variation of the stacking transistors, self-
controlled stacked transistors are
inserted between pull-up and pull-down
networks and reduce leakage power by
increasing internal resistance. Fig 2
shows the forced stack technique which
forces a stack structure by breaking
down an existing transistor into two half
size transistors.

Fig 2: Forced stack Technique circuit structure

III DISCUSSED TECHNIQUES

Sleepy Stack Technique: The sleepy
stack structure has a combined structure
of the forced stack and the sleep
transistor techniques. The sleep
transistors of the sleepy stack operate
similar to the sleep transistors used in
the sleep transistor technique in which
sleep transistors are turned on during
active mode and turned off during sleep
mode.
Fig 3 depicts sleepy stack operation.
During active mode S=0 and S=1, are
asserted. Thus, all sleep transistors are
turned on. This sleepy stack structure
can potentially reduce circuit delay in
two ways. First, since the sleep
transistors are always on during active
mode, the sleepy stack structure achieves
faster switching time than the forced
stack structure; specifically, each sleep
transistor drain, the voltage value
connected to the sleep transistor source
is always ready and available at the sleep
transistor drain, and thus, current flow is
immediately available to the low-Vth
transistors connected to the gate output
regardless of the status of each transistor
in parallel to the sleep transistors.
Furthermore, we can use high-V
th

transistors for the sleep transistors and
the transistors parallel to the sleep
transistors without incurring large (e.g.,
2 or more) delay increase. During sleep
mode S=1 and S=0 are asserted, and so
both of the sleep transistors are turned
off. Although the sleep transistors are
turned off, the sleepy stack structure
maintains exact logic state. The leakage
reduction of the sleepy stack structure
occurs in two ways.
First, high-V
th
transistors, which are
applied to the sleep transistors, suppress
leakage power. Secondly, stacked and
turned off transistors induce the stack
effect, which also suppresses leakage
power consumption. By combining these
two effects, the sleepy stack structure
achieves ultra-low leakage power
consumption during sleep mode while
retaining exact logic state. The price for
this, however, is increased area.
The sleepy stack structure can achieve
more power savings than the forced
stack technique and the self-controlled
stacked transistors (e.g.100x compared
with 10x for the forced stack transistor
or the self-controlled stacked
transistors). Furthermore, the sleepy
stack can save exact logic state unlike
gated-Vdd and gated-GND techniques.
Fig.3 shows the sleepy stack technique
applied to a conventional CMOS design.
When we apply the sleepy stack
technique, we replace each existing
transistor with two half sized transistors
and add one extra sleep transistor as
shown in Fig. 3. If dual-V
TH
values are
available, high-V
TH
transistors are used
for sleep transistors and transistors that
are parallel to the sleep transistors.


Fig 3: Sleepy stack technique circuit structure

Dual Sleep:

In this technique, one sleep transistor
is used to turn on in ON state and the
other one is used to turn on in OFF state.
Again in OFF state a block containing
both PMOS and NMOS transistors are
used in order to reduce the leakage
power. Like the sleep, sleepy stack and
sleepy keeper approaches, dual Vth
technology can be applied in dual sleep
approach to obtain greater leakage
power reduction. Since high Vth results
in less leakage but lowers performance,
high Vth is applied only to leakage
reduction transistors, which are sleep
transistors, and any transistors in parallel
to the sleep transistors.


Fig: Dual Sleep Technique

Sleepy Keeper:

An additional NMOS transistor is added
in parallel to the pull up sleep transistor
connected to Vdd. At sleep mode this
NMOS transistor is the only source of
Vdd to the pull-up network since the sleep
transistor is off. Similarly, to maintain a
0 value, assume that the value is
already calculated. The sleepy keeper
approach uses this output value of 0
and a PMOS transistor maintains the
value during sleep mode. An additional
PMOS transistor is added in parallel to
pull down sleep transistor connected to
GND. At sleep mode this PMOS
transistor is only source of GND the pull
down network since the sleep transistor
is off. The technique is state saving and
has less delay than sleepy stack. The
drawback is increase in area and
dynamic power consumption than sleep
transistor approach.

Forced Sleep:

The forced sleep method has a structure
merging the forced stack technique and
the sleep transistor technique. The forced
sleep inverter in Figure uses W/L = 3
Fig: Sleepy Keeper Technique

for the pmos transistors and W/L = 1.5
for the nmos transistors, while a
conventional inverter with the same
input capacitance would use W/L = 6 for
the pull-up transistor and W/L = 3 for
the pull-down transistor (assuming n =
2p). Then sleep transistors are added in
series to each set of two stacked
transistors. We use two sleep transistors
here, the nmos sleep transistor with Vdd
and the pmos sleep transistor with
ground. Conventionally the nmos
transistor is connected to ground because
it is very efficient passing ground
voltage and the pmos transistor is
connected to Vdd because it is efficient
passing Vdd. In forced sleep method we
just reverse the connection. Thats why
we have some delay penalty in our
method. We use same W/L for all the
pmos and nmos transistors in this
method. However, changing the sleep
transistor width may provide additional
tradeoffs between delay, power and area.
During sleep mode, S = 0 and S =1 are
asserted, and so both of the sleep
transistors are turned off. The leakage
reduction of forced sleep structure
occurs in two ways. First, leakage power
is suppressed by the two sleep transistors
which are not efficient in passing Vdd
(nmos) and ground (pmos) potential.
They will be in pure sleep mode at sleep
Second, two stacked and turned off
transistors induce the stack effect, which
also suppresses leakage power
consumption. By combining these two
effects, the forced sleep technique
achieves ultra-low leakage power
consumption during sleep mode. The
price for this, however, is increased
delay.

Fig: Forced Sleep Technique

III. CONCLUSION

The techniques discussed above
uniquely combines the advantages of
two major prior approaches, the sleep
transistor technique and the forced stack
technique. However, unlike the sleep
transistor technique, the sleepy stack
technique retains the original state;
furthermore, unlike the forced stack
technique, the sleepy stack technique can
utilize high- to achieve up to two orders
of magnitude leakage power reduction
compared to the forced stack.
Unfortunately, all the techniques come
with delay and area overheads.
Therefore, there has to be some trade-off
among the techniques based on the
applications. These techniques provides
new Pareto points to Designers who
require ultra-low leakage power
consumption and are willing to pay some
area and delay cost.
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