Adnan Hamid,

DV Club 2 July 2012

The Graphic Truth about SoC Verification:
Stitch and Ship Doesn't Work
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 2
The Canonical SoC
Testbench/Simulation Environment
BFM
SoC
RTL
CPU MEM
A B C
Fabric
Fabric
BFM
System
Management
If the IPs are well verified, the SoC will work

Since the IPs, fabric and memory subsystem have all
been verified, by induction the entire flow will work

If we know that each IP works, we know software
will be able to stitch them together into use cases

Power and clock management can be tested at the IP
or subsystem level
The Myth
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 3
Bus/fabric is saturated; wait states must be inserted
Bus/fabric bandwidth is much less than predicted
Bus bridge works under normal load, but hangs
under stress
Addressing worked fine for each IP, but concurrent
access reveals address decode bug
Memory breaks on concurrent access to same bank
Producer big-endian and Consumer little-endian
Clocking update during execution hangs the system
The Truth
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The SoC Verification Iceberg
Performance Analysis
System Hookup
IP Integration
Multi-Master Concurrency
Multi-CPU Interactions
Data Ordering
Cache Coherency
Virtual Memory
Clocks and Power
Asynchronous Events
Application Use Cases
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Why not SoC-level UVM?
Virtual sequencer too complex
Full-chip simulation too slow
No testbench-CPU links

Why not hand-written C tests?
No testbench-CPU links
Multi-threaded tests impossible to write by hand

Why not just run production code?
No testbench-CPU links
Full-chip simulation even slower with CPU running code
Production is well-behaved and does not hit corner cases
Production code is rarely available before SoC tape-out

HMS Stitch and Ship
System Hookup
IP Integration
Multi-Master Concurrency
Multi-CPU Interactions
Data Ordering
Cache Coherency
Virtual Memory
Clocks and Power
Asynchronous Events
Application Use Cases
Performance Analysis
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 6
test.c
test.c
test.c
The Solution: Automatic Self-
Verifying C Test Cases
Compiler
test.c
test.c
events.rc
T
r
e
k
B
o
x

TrekSoC
Testbench
BFM
SoC
RTL
CPU MEM
A B C
Fabric
Fabric
BFM
System
Management
mailbox
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 7
C

SoC

B

A

Scenario
Model
TrekSoC generates
automatically from
the scenario models
Well commented
Multi-threaded
Does mean, nasty
things to the SoC
Exercises deep
corner cases
Self-Verifying C Test Case
// System Configuration
void configure_system (void) {
static U32 state = 1;
switch(state) {
case (0x1):
active_threads = 4; // initialize thead counter
WREG8(0x00810003, 0x80); // UART_LCR: BREAK_CONTROL=0 ...
WREG8(0x00810001, 0x00); // UART_DIVISOR_MSB: MSB=0
WREG8(0x00810003, 0x06); // UART_LCR: BREAK_CONTROL=0 ...
WREG8(0x00810001, 0x00); // UART_IER: MODEM_STATUS=0 ...
WREG8(0x00810002, 0x46); // UART_FCR: RX_FIFO_CLR=1 ...
...

// Test Thread A
void test_thread_A (void) {
static U32 state = 0x1;
switch(state) {
case (0x1):
trek_do_expect(6); // Begin Thread A
state++;
trek_do_expect(7); // Waiting for UART0_tx to be idle...
case (0x2):
if ( UART0_tx_busy == 1 ) break;
UART0_tx_busy = 1;
trek_do_expect(9); // Begin UART0 uart_fill_tx
trek_write_fifo_mem8(0x00810000, MADDR(0x00000810), 4);
state++;
trek_do_expect(10); // Poll for UART0.UART_LSR.TX_FIFO_EMPTY
case (0x3):
if (!REGTEST8(0x00810005, 0x20, 0x20)) break;
trek_do_expect(11); // ... got UART0.UART_LSR.TX_FIFO_EMPTY
state++;

2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 8
2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Common Models
across Testbenches
A B C
CPU MEM
BFM BFM BFM
CPU MEM
SoC
C

SoC

B

A

Scenario
Model
TBX
test.c events.rc
A
BFM
BFM
A

Scenario
Model
A B C
MEM
BFM BFM BFM
MEM
SoC
BFM
BFM
C

SoC

B

A

Scenario
Model
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 10
Photo Data Flow Example
Testbench/Simulation Environment
SD Card
SoC
RTL
CPU MEM
Camera
Image
Processor
SD Card
Controller
Fabric
Fabric
CCD
System
Management
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Driver Scenarios
Image
Processor
IP
mode
blocks
few
many
A
B
config
enable
completion
interrupt
poll
check
memory
register
I/O
get_src
Graph-Based Constraints
Image
Processor
IP
mode
blocks
few
many
A
B
config
enable
completion
interrupt
poll
check
memory
register
I/O
get_src
SDIO
IP
mode
blocks
few
many
A
B
config
enable
completion
interrupt
poll
check
memory
register
I/O
get_src
MEM2 MEM1 eMMC
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 12
Powerful constraint solver keeps graph size down
Allows natural mapping of outcomes to input prerequisites
No need to capture detailed protocol rules in graph
Leverage existing testbench components (UVM, OVM, etc.)
Generated test cases are self-verifying
Both checking and coverage are encapsulated
Graphs support verification reuse IP SoC
IP graphs can be merged for subsystems and SoC
Generation capabilities scale to full SoC level

The Graphic Truth
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 13
2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Visualize Your
Verification Space
Pre-Simulation Reachability
Un-Reachable Input Case
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 15
Post-Simulation Coverage
Cases That have Not Yet Been Covered
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 16
Coverage By Construction
Automatically Find Minimal Search
Traversals to Close Coverage Targets
2005 - 2012 Breker Verification Systems, Inc. All rights reserved.
Standalone IP verification is not sufficient for an SoC
Stitch and ship misses critical interactions and corner cases
TrekSoC automatically generates C test cases
Run on the embedded processors and link to testbench
Exercise deep corner cases and measure performance
Scenario models are easy and natural to create
Incremental ROI: basic tests require minimal info
Graphs efficiently capture verification knowledge
Graphs help internal communication and teams
Summary
2005 - 2012 Breker Verification Systems, Inc. All rights reserved. 18