FPGA based measurement of frequency and phase difference 2010

Chapter 1 INTRODUCTION

EW Receivers [1-6]
An EW (electronic warfare system is used to protect military resources from enemy threats! "he
field of EW is reco#ni$ed as ha%in# three components&
Electronic support measure (E'() which collects information on the electronic
en%ironment!
Electronic countermeasures (E*() which +am or disturb enemy systems!
Electronic counter-countermeasures (E**() which protect equipment a#ainst E*(!
EW intercept systems can be di%ided into the followin# fi%e cate#ories&
Acoustic detection systems are used to detect enemy sonar and noise #enerated by ship
mo%ement! "hese systems detect acoustic si#nals and usually operate at frequencies
below ,0 -.$!
*ommunication intercept recei%ers are used to detect enemy communication si#nals!
"hese systems usually operate below 2 G.$) althou#h a hi#her operatin# frequency is
required to intercept satellite communication! "hese recei%ers are desi#ned to recei%e
communication si#nals!
/adar intercept recei%ers are used to detect enemy radar si#nals! "hese systems usually
operate in the ran#e of 2 G.$ to 10 G.$! .owe%er) some researchers intend to co%er the
entire 2 to 100 G.$ ran#e! "hese recei%ers are desi#ned to recei%e pulsed si#nals!
1nfrared intercept recei%ers are used to detect the plume of an attac-in# missile! "hese
systems operate at near throu#h far infrared (wa%elen#ths from , to 12 /mm).
3aser intercept recei%ers are used to detect laser si#nals) which are used to #uide weapon
systems (i!e!) attac- missiles!
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FPGA based measurement of frequency and phase difference 2010
"he intercept recei%ers often operate with EW si#nal processors! "he processors are used to
process the information intercepted by the recei%ers to sort and identify enemy threats! After the
threats are identified) the information is passed to an E*( system! "he E*( system must
determine the most effecti%e way to disturb the enemy operation! A threat radar can obtain the
necessary information and ta-e action a#ainst an airplane or a ship in a few seconds! 1f a missile
#uidance si#nal is detected by an EW recei%er) the impact could be imminent! "hus) an EW
system must respond to the input si#nals as soon as possible! 1f an EW system cannot respond
within some critical time) it is equi%alent to no EW system at all because it cannot protect the
aircraft or ship as desired!
(ost radars #enerate pulsed /F si#nals! 'ome radars #enerate frequency modulated (F( pulsed
si#nals) which are often referred to as chirp si#nals! "he /F ran#es rou#hly from 2 G.$ to 100
G.$) but the most popular frequency ran#e is from 2 to 10 G.$! "he duration of these pulses
may be between tens of nanoseconds and hundreds of microseconds! 'ome radars produce
continuous wa%e (*W si#nals for low altitude sur%eillance or weapon #uidance! "he pulse
repetition frequency (P/F) or its reciprocal pulse repetition inter%al (P/1) is an important
parameter of pulsed radar si#nals! "he P/F ran#es rou#hly from a few hundred hert$ to about
one me#ahert$! (ost of the radars ha%e stable P/F) which means the P/F is a constant! 'ome
radars ha%e sta##ered P/67 that is) a #roup of pulses (i!e!) a few to tens repeat themsel%es at a
certain P/F! 'ome radars e%en #enerate a#ile or random P/67 that is) the P/1 %aries from pulse
to pulse! A#ile P/1 usually means that the P/1 %aries in a certain pattern and random P/1 means
the P/1 does not ha%e any predetermined pattern!
An EW recei%er must be able to obtain all the information from a pulse transmitted by a radar!
Fi#ure 1!1 illustrates a pulse transmitted by a radar! When the pulse reaches the intercept recei%er
at the aircraft) the followin# information can be measured& pulse amplitude (PA) pulse width
(PW) time of arri%al ("8A) carrier frequency (also referred to as the /F) and an#le of arri%al
(A8A!

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Fi#! 1!1 pulse transmitted by a radar
FPGA based measurement of frequency and phase difference 2010
Fi#! 1!1 pulse transmitted by a radar
Digital approach [7-13]
9i#ital circuits ha%e lon# been used in EW recei%er applications) such as di#ital controllin# of the
recei%er operation modes! 1n addition) once the radio frequency (/F input si#nal is con%erted into %ideo
si#nals throu#h crystal detectors) the %ideo si#nals will be further processed di#itally! .owe%er) to date all
the EW recei%ers ha%e crystal %ideo detectors to con%ert /F into %ideo si#nals! "he detector destroys the
carrier frequency and phase information in the si#nal! 1f the detector can be replaced by an analo#4to4
di#ital con%erter (A9*) all the information will be maintained!
"he first de%ice needed to con%ert analo# si#nals into di#ital data is the A9*! 1n order to con%ert si#nals
in a wideband recei%er) the A9* must operate at a %ery hi#h samplin# speed! "o di#iti$e si#nals with less
quanti$ation errors) the A9* must also ha%e a lar#e number of bits! 1t is difficult to achie%e both #oals in
an A9* at the same time) but the ad%ancement in the A9* technolo#y is mo%in# at an astonishin# speed!
1n a di#ital recei%er) the input is down4con%erted into an 1F) which is then di#iti$ed with hi#h speed A9*s
with lar#e number of quanti$ation le%els! 9i#ital si#nal processin# is then used to produce the desired
P9W (fi#ure 1!2!
A di#ital recei%er does not ha%e a crystal %ideo detector! "he output from the A9* is di#ital! 'ome of the
ma+or ad%anta#es are related to di#ital si#nal processin#! 8nce a si#nal is di#iti$ed) the followin#
processin# will all be di#ital! 9i#ital si#nal processin# is more robust because there is no temperature
driftin#) #ain %ariation) or dc le%el shiftin# as in analo# circuits! "herefore) less calibration is required!
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FPGA based measurement of frequency and phase difference 2010
"he frequency resolution can be %ery fine if hi#h4resolution spectrum estimation techniques can be
applied! 1n many spectrum estimation schemes) the results are comparable with the *ramer4/ao bound at
hi#h si#nal4to4noise ratios) which analo# recei%er cannot achie%e!
Fi#! 1!2 a con%entional di#ital recei%er
!lti"it vs# o$o"it receivers
As mentioned abo%e) the (ultibit A9*:s reduce quanti$ation errors but at the cost of speed! "his
led to the de%elopment of monobit recei%ers) wherein the si#nal information at each samplin#
point is e;pressed in a sin#le bit or 2 to , bits! "he monobit recei%ers ha%e become widely
famous!
1#1 O"%ective a$& goal o' pro%ect
8ut of all the parameters) this pro+ect aims at obtainin# frequency and phase information that
forms the 91F( module) or the di#ital instantaneous frequency measurement module of a
monobit recei%er! "his pro+ect pro%ides with another method other than the con%entional di#ital
monobit recei%ers!
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FPGA based measurement of frequency and phase difference 2010
1#( )iterat!re *!rve+
1#(#1 ONO,IT RECEI-ER*
INTRODUCTION
"he technique of monobit recei%er can be considered as a di#ital channeli$ed approach! "he fast
Fourier transform (FF" is %ery simple and can be built on one chip! A simple frequency encoder
is used after the FF" outputs to determine the number of input si#nals and their frequencies! "he
encoder and the FF" can be built on one chip! "he chip has been fabricated and the monobit
recei%er concept has been %alidated successfully in the laboratory!
"he monobit recei%er concept is inspired by commercial Global Positionin# 'ystem (GP'
recei%er desi#ns! =sually) the analo#4to4di#ital con%erter (A9* in a commercial GP' recei%er
has only 1 or 2 bits) and the GP' si#nal is more complicated than a pulsed radio frequency (/F!
"his idea is adopted in wideband recei%er applications and the name monobit recei%er is used!
"his technique can be used to reduce to a minimum the hardware required for a #i%en recei%er
function) with only a sli#ht reduction in performance! >ecause the A9* used in the monobit
recei%er has %ery few bits) the system is basically nonlinear! A nonlinear system is difficult to
analy$e theoretically! "hus) in desi#nin# the recei%er one uses data collected from a data
collection system! "he collected data are processed in a computer to e%aluate the performance! 1n
order to determine the number of input si#nals) thresholds must be incorporated in the chip
desi#n! "hese threshold %alues are based on computer simulation results! "he ma+or ad%anta#e of
the monobit recei%er is its simplicity!
ORI.IN/) CONCE0T O1 T2E ONO,IT RECEI-ER
"he ori#inal idea of the monobit recei%er is to reduce the FF" comple;ity by eliminatin# the
multiplication in the FF" operation! 8ne simple way to eliminate multiplication is to use a 14bit
A9*! 8ne bit #enerates ?1 as output) and this is the input to the FF" operation!
"he discrete Fourier transform (9F" can be written as&

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FPGA based measurement of frequency and phase difference 2010
where x (n) is the input data and e~j27rkn/N is the @ernel function! 1f the input x(n) is ?1) no
multiplication is needed with the @ernel function! >ecause the FF" only requires addition and
subtraction) the chip desi#n can be %ery simple! "he ne;t step is to manipulate the @ernel
function! 1n the computer a lar#e number of bits are used to represent the %alue of the @ernel
function! >ecause the operation will be built in hardware) the number of bits is important and
should be minimi$ed! >ecause the input only has 1 bit) a low number of bits in the @ernel
function do not de#rade the output in the frequency domain si#nificantly! An optimum
combination of si#nal bits and @ernel function bits can be determined e;perimentally by
obser%in# the FF" outputs in the frequency domain!
RECEI-ER CO0ONENT*
Fi#1!, "he fi%e main components of monobit recei%er
"he monobit recei%er can be di%ided into fi%e ma+or portions& the /F chain) the A9*) the
demultiple;er) the FF") and the frequency encoder! "he A9* operates at 2!2 G.$ with only 2
bits! "he demultiple;er is 1 to 1A) which connects the input to 1A parallel outputs! Each data
point contains 2 bits and each bit needs a demultiple;er! "he FF" operation uses 22A data points
and it ta-es 1A parallel input data e%ery A!< ns (1A ; 0!<! 1t ta-es total 1A cycles or 102!< ns (1A
; A!< to collect all the data! "he FF" operation is performed e%ery 102!< ns! "he encoder
determines the number of input si#nals and their frequencies7 thus) it is referred to as a frequency
encoder! A #eneral encoder usually pro%ides frequency) pulse amplitude) pulse width) and time of
arri%al ("8A information!
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FPGA based measurement of frequency and phase difference 2010
1#(#( -2D)
5.93 is the 5.'1* .ardware 9escription 3an#ua#e! 5.'1* is an abbre%iation for 5ery .i#h
'peed 1nte#rated *ircuit! 1t can describe the beha%iour and structure of electronic systems) but is
particularly suited as a lan#ua#e to describe the structure and beha%iour of di#ital electronic
hardware desi#ns) such as A'1*s and FPGAs as well as con%entional di#ital circuits!
5.93 is a notation) and is precisely and completely defined by the 3an#ua#e /eference (anual
(3/(! "his sets 5.93 apart from other hardware description lan#ua#es) which are to some
e;tent defined in an ad hoc way by the beha%iour of tools that use them! 5.93 is an
international standard) re#ulated by 1EEE! "he definition of the lan#ua#e is non4proprietary!
5.93 is not an information model) a database scheme) a simulator) a toolset or a methodolo#y!
.owe%er) a methodolo#y and a toolset are essential for the effecti%e use of 5.93!
'imulation and synthesis are two main -inds of tools which operate on the 5.93 lan#ua#e! "he
3/( does not define a simulator) but unambi#uously defines what simulator must do with each
part of the lan#ua#e!
5.93 does not constrain the user to one style of description! 5.93 allows desi#ns to be
described usin# any methodolo#y4 top down) bottom up or middle out! 5.93 can be used to
describe hardware at the #ate le%el or in a more abstract way! 'uccessful hi#h le%el desi#n
requires a lan#ua#e) a tool set and a suitable methodolo#y!
5.93 is fairly a #eneral purpose lan#ua#e) and it does not require a simulator on which to run
the code! "here are a lot of 5.93 compilers) which build e;ecutable binaries! 1t can read and
write files on the host computer) so a 5.93 pro#ram can be written that #enerates another
5.93 pro#ram to be incorporated in the desi#n bein# de%eloped! >ecause of this #eneral
purpose nature) it is possible to use 5.93 to write a testbench that %erifies the functionality of
the desi#n usin# files on the host computer to define stimuli interacts with the user and compares
results with those e;pected!
5.93 is not a case sensiti%e lan#ua#e! 8ne can desi#n hardware in a 5.93 19E (such as
3ili$4 to produce the /"3 schematic of the desired circuit! After that) the #enerated schematic
can be %erified usin# simulation software (such as o&el*i5 which shows the wa%eforms of
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FPGA based measurement of frequency and phase difference 2010
inputs and outputs of the circuit after #eneratin# the appropriate testbench! "o #enerate an
appropriate testbench for a particular circuit or 5.93 code) the inputs ha%e to be defined
correctly!
"he -ey ad%anta#e of 5.93 when used for systems desi#n is that it allows the beha%iour of the
required system to be described (modeled and %erified (simulated before synthesis tools
translate the desi#n into real hardware (#ates and wires! Another benefit is that 5.93 allows
the description of a concurrent system (many parts) each with its own sub beha%iour) wor-in#
to#ether at the same time! 5.93 is a dataflow lan#ua#e unli-e procedural computin# lan#ua#es
such as >A'1*) *) and assembly code) which all run sequentially) one instruction at a time!
When a 5.93 model is translated into the #ates that are mapped onto a pro#rammable lo#ic
de%ice such as *P39 or FPGA) then it is the actual hardware bein# confi#ured) rather than the
5.93 code bein# e;ecuted!
Desig$i$g i$ -2D)6
1! 9efinin# the desi#n requirements li-e timin# constraints) frequency of operation) area etc!
2! *odin# the desi#n!
,! 'imulatin# the code4 chec-in# whether the code #i%es the desired output!
<! 'ynthesis &
a *hec- for synta; and semantic errors!
b *on%ert the desi#n to /"3 (/esistor "ransistor 3o#ic schematic) describin# re#isters
and interconnections of re#isters with combination circuit and constraints!
c "ranslate to >oolean e;pressions!
d 8ptimi$e the >oolean e;pressions!
e (appin#!
f Place and route!
2! 9ownload the file on FPGA!
1#(#3 10./
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FPGA based measurement of frequency and phase difference 2010
A field pro#rammable #ate array (FPGA is a semiconductor de%ice that can be confi#ured by
the customer or desi#ner after manufacturin# C hence the name field C pro#rammable! FPGAs
are pro#rammed usin# a lo#ic circuit dia#ram or a source code in a hardware description
lan#ua#e (.93 to specify how the chip will wor-! "hey can be used to implement any lo#ical
function that an application specific inte#rated circuit (A'1* could perform) but the ability to
update the functionality after shippin# offers ad%anta#es for many applications!
FPGAs contain pro#rammable lo#ic components called lo#ic bloc-s) and a hierarchy of
reconfi#urable interconnects that allow the bloc-s to be wired to#ether C somewhat li-e a one
chip pro#rammable breadboard! 3o#ic bloc-s can be confi#ured to perform comple;
combinational functions) or merely simple lo#ic #ates li-e AD9 and E8/! 1n most FPGAs) the
lo#ic bloc-s also include memory elements) which may be simple flip4flops or more complete
bloc-s of memory!
"o define the beha%iour of the FPGA) the user pro%ides a hardware description lan#ua#e (.93
or a schematic desi#n! "he .93 form mi#ht be easier to wor- with when handlin# lar#e
structures because it:s possible to +ust specify them numerically rather than ha%in# to draw e%ery
piece by hand! 8n the other hand) schematic entry can allow for easier %isuali$ation of a desi#n!
"o simplify the desi#n of comple; systems in FPGAs) there e;ist libraries of predefined comple;
functions and circuits that ha%e been tested and optimi$ed to speed up the desi#n process! "hese
predefined circuits are commonly called 1P cores) and are a%ailable from FPGA %endors and
third party 1P suppliers! 8ther predefined circuits are a%ailable from de%eloper communities such
as 8pen *ores!
1#(#7 ORC/D
8/*A9 is a proprietary software tool suite used primarily for electronic desi#n automation! "he
software is used mainly to create electronic prints for manufacturin# of printed circuit boards) by
electronic desi#n en#ineers and electronic technicians to manufacture electronic schematics and
dia#rams) and for their simulation!
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FPGA based measurement of frequency and phase difference 2010
"he name 8/*A9 is a portmanteau) reflectin# the softwareGs ori#ins& 8r e#on H *A9! 8/*A9
is a schematic editor! 1n other words) it is a pro#ram that allows us to draw circuit schematics! 1t
comes with a nice collection of parts libraries with parts that can be use in ma-in# any circuit!
1#(#8 -IEW/TE
5iewmate is a proprietary software tool suite used primarily for %iewin# GE/>E/ files! A
GE/>E/ file #i%es layer by layer detailed %iew of a P*>!
.ER,ER 'iles
A Gerber File is a file format used by printed circuit board (P*> manufacturin# machines to lay
out electrical connections such as traces) %ias) and pads (the component IfootprintsI on the
P*>! A Gerber file can also contain information for drillin# and millin# the circuit board! "hese
files are #enerated by P*> *A9 software) and are sent to manufacturers where they are loaded
into a *A( system to prepare data for each step of the P*> production process!
When an electronics desi#n en#ineer has completed their circuit desi#n for an application) the
ne;t step towards completin# the product desi#n is to enter the schematic details into a computer
based schematic capture pro#ram! "he schematic capture pro#ram) which is usually part of an
Electronic 9esi#n Automation) E9A or *omputer Automated 9esi#n) P*> *A9) software
desi#n pac-a#e) will create a net list from the completed schematic that details e%ery electrical
connection between each electronic component! "his net list is used by the printed circuit board
or P*> desi#ner in the process of desi#nin# the printed circuit board with the E9A or P*> *A9
software! "he finished printed circuit board will pro%ide the physical assembly and
interconnection platform for the %arious electronic components required by the schematic!
"he printed circuit board is made up of one or more conducti%e layers of copper platin# that is
etched to form the component pads and interconnection traces and one or more layers of
insulatin# material such as epo;y4filled fiber#lass to separate the conducti%e copper layers and to
pro%ide the mechanical stren#th for the board! A sin#le layer board would ha%e components on
the top side of the board and connectin# traces on the bottom side of the board! A double layer
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FPGA based measurement of frequency and phase difference 2010
board could ha%e components on the top side only or ha%e components on both the top and
bottom sides of the board alon# with connectin# traces on both sides of the board! A multilayer
board would ha%e both top and bottom sides with components and traces alon# with a number of
internal layers used for interconnections and for %olta#e and #round plane layers!
"he E9A or P*> *A9 pro#ram pro%ides the detailed information about the completed board
desi#n in a series of data files for each conducti%e layer) such as top) bottom) and any internal
layers! "he ori#inal Gerber format conformed to the E1A /'42B<9 standard and consisted of a
command file for each conducti%e layer and a tool description file! "he command file consisted
of a series of short commands) each followed by a set of E and J coordinates) which would
pro%ide a photo plotter with the information to create a #raphic representation! "hese command
files became -nown as the Gerber files! "he tool description file) or aperture file) defined the
trace line widths and dimensional data for all of the pads and #eometric shapes on the layer!
"hese data files of computer #enerated information for the printed circuit board desi#n are then
sent to a printed circuit board fabrication company to ha%e the physical boards manufactured!
"he Gerber files contain all of the information necessary for the computer controlled machines at
the printed circuit board) P*>) fabrication houses to etch the copper layers to create the
component pads and connection traces) drill all required holes) and cut the board to the required
si$e!
"he newer Gerber format conforms to E1A /'42B<E and this format includes the aperture
information in the file headers as embedded information for each command or Gerber file! "his
newer format is often called E4Gerber! With the entire aperture information included within the
header for the file) each E4Gerber file pro%ides all of the information required to fabricate the
related portion of a P*> layer!
"he file names for the Gerber files should be descripti%e enou#h for the P*> fabricator to
understand which board and board layer that each file applies to) such as membdtop!#br as a file
name! "he standard process is to include with each set of files for a board desi#n a special
readme!t;t type te;t file that defines each file name and its application for the board desi#n! "he
board %endor will use this readme!t;t te;t file as the startin# point for the board manufacturin#
process! Gerber file e;tensions are often !G>/) !G>E) or !A/"! 'ometimes e;tensions such
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FPGA based measurement of frequency and phase difference 2010
as !"8P and !>8" or !'(" and !'(> are used instead of the !G>K type e;tensions! 8ften the
file e;tension for a type of file) top) bottom) sil-screen) paste) inner layer) is controlled by the
E9A or P*> *A9 software pac-a#e or is selectable within the pac-a#e! "his %ariation in the
e;tensions ma-es the inclusion of the readme!t;t file as a requirement in the o%erall file pac-a#e
for the board %endor! "he list of files for a board desi#n will include the sil-screen for the top
and sometimes the bottom layers if components are mounted on both sides) component
placements for the top and sometimes the bottom layers) solder screen paste files for surface
mount applications) drill drawin#s) solder mas- files) panel drawin#s) pad master top and pad
master bottom) etc!
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FPGA based measurement of frequency and phase difference 2010
Chapter 2 UNDER)9IN. T2EOR9
(#1 Co5parators
A co5parator is a de%ice which compares two %olta#es or currents and switches its output to
indicate which is lar#er! "he output is a binary state often used to interface real world si#nals to
di#ital circuitry! A comparator normally chan#es its output state when the %olta#e between its
inputs crosses throu#h appro;imately $ero %olts! >ecause comparators ha%e only two output
states) their outputs are near $ero (binary : or near the supply %olta#e (binary 1!
When a comparator performs the function of tellin# if an input %olta#e is abo%e or below a #i%en
threshold) it is essentially performin# a 14bit quanti$ation! "his function is used in nearly all
analo# to di#ital con%erters!
Fi#! 2!1 comparator wa%eforms
'E3E*"451" 1,
:
-p
p
--p
I$p!t
a$alog
sig$al
O!tp!t
&igital
sig$al
1
:
FPGA based measurement of frequency and phase difference 2010
(#( Correlatio$ 1!$ctio$
*orrelation is a mathematical operation that is %ery similar to con%olution! 6ust as with
con%olution) correlation uses two si#nals to produce a third si#nal! "his third si#nal is called the
cross-correlatio$ of the two input si#nals! 1f a si#nal is correlated with itself) the resultin# si#nal
is instead called the a!tocorrelatio$
A correlatio$ '!$ctio$ is the correlation between random %ariables at two different points in
space or time) usually as a function of the spatial or temporal distance between the points! 1f one
considers the correlation function between random %ariables representin# the same quantity
measured at two different points then this is often referred to as an autocorrelation function bein#
made up of autocorrelations! *orrelation functions of different random %ariables are sometimes
called cross correlation functions to emphasi$e that different %ariables are bein# considered and
because they are made up of cross correlations!
*orrelation functions are a useful indicator of dependencies as a function of distance in time or
space) and they can be used to assess the distance required between sample points for the %alues
to be effecti%ely uncorrelated! 1n addition) they can form the basis of rules for interpolatin#
%alues at points for which there are obser%ations!
(#(#1 Cross correlatio$
*ross4correlation is a measure of similarity of two wa%eforms as a function of a time4la# applied
to one of them! "he cross4correlation is similar in nature to the con%olution of two functions!
Whereas con%olution in%ol%es re%ersin# a si#nal) then shiftin# it and multiplyin# by another
si#nal) correlation only in%ol%es shiftin# it and multiplyin# (no re%ersin#!
For e;ample)
C (t) (f ! ") (t)
#
$ f (t)! " (t- %) &%
*onsider two real %alued functions f and " that differ only by a shift alon# the ;4a;is! 8ne can
calculate the cross4correlation to fi#ure out how much " must be shifted alon# the ;4a;is to ma-e
it identical to f! "he formula essentially slides the " function alon# the ;4a;is) calculatin# the
'E3E*"451" 1<
FPGA based measurement of frequency and phase difference 2010
inte#ral of their product for each possible amount of slidin#! When the functions match) the %alue
of f ! " is ma;imi$ed! "he reason for this is that when lumps (positi%es areas are ali#ned) they
contribute to ma-in# the inte#ral lar#er! Also) when the trou#hs (ne#ati%e areas ali#n) they also
ma-e a positi%e contribution to the inte#ral because the product of two ne#ati%e numbers is
positi%e!
(#(#( /!to correlatio$
Autocorrelation is the cross4correlation of a si#nal with itself! 1nformally) it is the similarity
between obser%ations as a function of the time separation between them! 1t is a mathematical tool
for findin# repeatin# patterns) such as the presence of a periodic si#nal which has been buried
under noise) or identifyin# the missin# fundamental frequency in a si#nal implied by its
harmonic frequencies! 1t is often used in si#nal processin# for analy$in# functions or series of
%alues) such as time domain si#nals!
(athematically) auto4correlation is described as)
C (t) (f ! f) (t)
#
$ f (t)! f (t- %) &%
(#3 1re;!e$c+ 5eas!re5e$t
3et the input si#nal be)
'cos (2(ft)
Where) f is the frequency of the input sinusoidal si#nal and)
f1/) * ) is the period of the si#nal!
3et us find out the auto correlation of this si#nal and the same si#nal delayed in time by 0 to "s
time) where "s is the samplin# time and is less than or equal to "L2!
)
s
+ )/2) since ,
s
- 2f (by nyquist theorem
3et the si#nal delayed by 1"s be defined as '
& !"herefore)
'E3E*"451" 12
FPGA based measurement of frequency and phase difference 2010
'
&
cos (2(f (t.)
s
))
cos (2(ft.2(f/,
s
))
Dow) for the two si#nals to be ma;imally correlated) the shift in the delayed si#nal should be
$ero ("s M 0!
8r) 2(f/,
s
/
i!e! f /. (1)
'imilarly) for the two si#nals to be minimally correlated) the shift in the delayed si#nal should be
equal to N ("sM"L2!
8r) 2(f/,
s
N
i!e! f ,
s
/2. (2)
As discussed in section 2!2!1) we -now that when lumps (positi%es areas are ali#ned) they
contribute to ma-in# the inte#ral lar#er and when the trou#hs (ne#ati%e areas ali#n) they also
ma-e a positi%e contribution to the inte#ral because the product of two ne#ati%e numbers is
positi%e! "hat is)
9 9& O!tp!t C
< < <
< = =
= < =
= = <
"able 2!1
'E3E*"451" 1A
FPGA based measurement of frequency and phase difference 2010
When we di#iti$e the analo# si#nal by 1 bit quanti$ation) the positi%e samples are represented by
a 1 and the ne#ati%e samples are represented by a :! "herefore the table can be rewritten as)
9 9& O!tp!t C
1 1 1
1 0 0
0 1 0
0 0 1
"able 2!2
When obser%ed carefully) we see that output * is an ED8/ function of the si#nal J and Jd! "hus
if we perform ED8/ function on the input bit stream and the delayed bit stream) we #et the
correlation output *! =pon al#ebraic summation of the result we #et the correlation coefficient
*- where - M no of bits by which the input bit stream has been delayed!
(1 bit delay is equi%alent to delay by 1 "s
"hus we can plot the C1 %ersus f #raph for k1
Fi#! 2!2 C1 %ersus f
*- M D (DM no! of bits in the bit stream J! 1t is the ma;imum %alue of the output when J and Jd
are ED8/ed when fM0 referrin# to ma;imum correlation! (>y 1
'E3E*"451" 1B
C1
:
N
1s>( f
FPGA based measurement of frequency and phase difference 2010
And *- M 0 when fM FsL2 (>y 2
1nstead of ED8/in#) if we E8/ the results the plot would chan#e to)

Fi#! 2!, #raph obtained by usin# E8/ in place of ED8/
"he reason we opt for E8/ operation is that it utili$es less no of #ates and hence less no of
resources in the FPGA chip!
'imilarly we can obtain a #raph between *2 and f) where *2 is the correlation coefficient for the
si#nal ' and the same si#nal delayed by 2 bits) i!e! k2.
'
&
cos (2(f (t.2)
s
))
cos (2(ft.0(f/,
s
))
Dow) for the two si#nals to be ma;imally correlated) the shift in the delayed si#nal should be
$ero ("s M 0) "!
8r) 0(f/,
s
/* 2(
i!e! f /* ,
s
/2 (1)
'imilarly) for the two si#nals to be minimally correlated) the shift in the delayed si#nal should be
equal to N ("sM"L2!
8r) 0(f/,
s
N
'E3E*"451" 10
C1
f
N
: 1s>(
FPGA based measurement of frequency and phase difference 2010
i!e! f ,
s
/0. (0)
=sin# E8/ operation instead of ED8/) the #raph can be plotted as)

Fi# 2!< -M2
"a-in# the delay as ,"s) <"s) 2"s and so on we can obtain the #raphs for *,)*<)*2 and so on till
-MD! Graphs for -M,)< and D are shown below!
Fi# 2!2 -M,
'E3E*"451" 1F
C2
1s>( :
N
f
1s>3
C3
f
:
N
1s>( 1s>6
1s>7
C4
CN
FPGA based measurement of frequency and phase difference 2010
Fi# 2!A -M<
Fi# 2!B #eneral Ck %s! f #raph
=sin# strai#ht line equations) the followin# formulae can be deri%ed&
For -M1) (see fi# 2!2
C1 2Nf/,
s
(2)
For -M2) (see fi# 2!<
'E3E*"451" 20
: 1s>(
f
N
31s>? 1s>7 1s>?
N
:
1s>(@ 1s>( A@-1B1s>(@ (1s>@ 31s>(@
(
1s>@
FPGA based measurement of frequency and phase difference 2010
C2 0Nf/ ,
s
3 /+ f 4 ,
s
/0
2N 5 0Nf/ ,
s
3 ,
s
/0 + f 4 ,
s
/2 (7)
For -M,) (see fi# 2!2
C1 2Nf/ ,
s
3 /+ f 4 ,
s
/2
2N 5 2Nf/ ,
s
3 ,
s
/2 + f 4 ,
s
/1
2Nf/ ,
s
5 2N 3 ,
s
/1 + f 4 ,
s
/2 (6)
For -M<) (see fi# 2!A
C0 6Nf/ ,
s
3 /+ f 4 ,
s
/6
2N 5 6Nf/ ,
s
3 ,
s
/6 + f 4 ,
s
/0
6Nf/ ,
s
5 2N 3 ,
s
/0 + f4 1 ,
s
/6
0N 5 6Nf/ ,
s
3 1 ,
s
/6 + f4 ,
s
/2 (7)
And so on till -MD!
=sin# these equations we can calculate the fre8uenc9 f of an input si#nal if we -now the other
parameters such as Ck) N and ,s!
1n this pro+ect we ha%e ta-en) DM22A and ha%e fi;ed the samplin# frequency Fs as <00 (.$!
"hus if we are able to determine the correlation coefficient *-) we can easily find out the
frequency f.
(#7 0hase 5eas!re5e$t
"here are two pairs of antennas on an aircraft out of which any one pair is recei%in# si#nals at a
time! E( si#nal recei%ed from an antenna pair will be fed to the inputs of two en%elope detector
'E3E*"451" 21
FPGA based measurement of frequency and phase difference 2010
1*s! 'ince path difference between recei%in# antenna and the tar#et is not same for the two
antennas in a pair) for same /F frequency si#nal there will be some phase difference between the
2 si#nals fed to 2 different En%elope detectors!
J
1
(t Mcos (2NftHO
1

J
2
(t Mcos (2NftHO
2

Phase difference M P O M O
2
4 O
1
M (2NLQ P;
Where P; is the path difference
Fi# 2!0 path difference
'E3E*"451" 22
Antenna 1 Antenna 2
Frequency and phase measurement
P;
"ar#et
FPGA based measurement of frequency and phase difference 2010
J1 (t
J2 (t
Fi# 2!F phase difference between the same /F si#nal recei%ed by the 2 antennas
For calculation of phase we use the concept of auto correlation between the two inputs to the
en%elope detectors4 J1 (t and J2 (t!
'
1
(t) cos (2(ft.:
1
)
'
2
(t) cos (2(ft.:
2
)
Phase difference M ; : M :
2
- :
1
Dow) for correlation to be ma;imum between these two si#nals) ; : should be either 0 or 2N!
'imilarly for minimum correlation it should be equal to N
i!e!
'E3E*"451" 2,
C
N
C :
C
N : C
FPGA based measurement of frequency and phase difference 2010
Fi# 2!10
A#ain usin# E8/ instead of ED8/ in di#ital domain) as discussed in the pre%ious section) we
will #et the re%ersed plot!
Fi# 2!11
=sin# strai#ht line equation we can deri%e the formulae for calculatin# PO)
;: C(/N 3 / + ;: + (
'E3E*"451" 2<
D E
(C
(C
FPGA based measurement of frequency and phase difference 2010
;: 2( - C(/N 3 ( + ;: + 2( (1/)
"hus if we -now correlation coefficient * and D) we can calculate the phase difference PO!
Chapter 1 I0)EENT/TION
'E3E*"451" 22
FPGA based measurement of frequency and phase difference 2010
3#1 /rchitect!re OvervieF
Fi# ,!1 architecture o%er%iew of the frequency and phase measurement module
3#( Wor@i$g 0ri$ciple
'E3E*"451" 2A
FPGA based measurement of frequency and phase difference 2010
"he two A900<2 chips are basically unity #ain amplifiers that act as analo# buffers between the
connectors recei%in# /F input and the comparator 1*s C (AEFA,E'9! "hey can also be called
A9* dri%ers here! "he (AEFA,E'9 is an 1* that houses two comparators on the same chip!
Each comparator has a differential output which is latch enabled!
Each of the two A9* dri%ers is connected to two of the (AEFA,E'9 1*s! "herefore the four
comparators connected an A9* dri%er #i%e the same output but at < different times! "his is done
so by supplyin# four different cloc- si#nals to the latch enable pins of these four comparators!
"hese four cloc-s are #enerated by the FPGA chip and are F0 de#rees out of phase with each
other! "hat is the 2
nd
cloc- is F0 de#rees out of phase with the 1
st
cloc-) ,
rd
cloc- is F0 de#ree out
of phase with the 2
nd
cloc- ma-in# it 100 de#rees out of phase with the 1
st
cloc- and so on! "he
four comparators latch their output at e%ery risin# ed#e of the cloc-s fed to them and thus data is
fed latched < times faster! 'ay) for our desi#n the FPGA #enerates four 100 (.$ cloc-s F0
de#rees out of phase and effecti%ely data is bein# latched at <00 (.$ rate as e;plained in fi# ,!2
Fi# ,!2 data is recei%ed at < times faster rate!
'E3E*"451" 2B
FPGA based measurement of frequency and phase difference 2010
"his latched data is then processed for measurin# the frequency and the phase difference! After
calculation of frequency and phase the FPGA communicates with the P* throu#h the =A/" to
display the results on the hyper terminal!"he al#orithms for the same are discussed in the ne;t
chapter!
"he two %olta#e re#ulators are to obtain ,!, and 1!0 %olts that the supply %olta#es the FPGA can
ta-e!
3#3 I$si&e the 10./
Fi# ,!, processes inside an FPGA
"he FPGA *hip contains the firmware for frequency and phase difference calculation as well as
for the =A/" that interfaces the chip and the computer hyper terminal! "he FPGA is fed with a
100 (.$ cloc- by the crystal! "he 933 or 9elay 3oc-ed 3oop module inside the FPGA
#enerates the four cloc-s mentioned in section ,!2
'E3E*"451" 20
FPGA based measurement of frequency and phase difference 2010
Chapter 0 0RO.R/IN.
ET2ODO)O.IE*
7#1 1re;!e$c+ a$& 0hase Calc!latio$
"here are , processes runnin# parallel within the FPGA! 1n one process the recei%ed < bit data is
latched in a 22A bit data re#ister in the FPGA while the vali&=&ata fla# is set! After 22A bits are
recei%ed (after A< cloc-s) an enablin# pulse (10=EN is #enerated and this data is passed to
another parallel runnin# process where it is used for measurin# the frequency and phase!
'imultaneously in the 1
st
process) the re#ister is cleared and it a#ain starts latchin# data < bits at a
time! When the frequency and phase calculation is complete) UDT=EN fla# will be set and the
measured frequency and phase %alue will be transferred to the ,
rd
process where data will be
transmitted serially to the P* on .yper "erminal!
'E3E*"451" 2F
FPGA based measurement of frequency and phase difference 2010
7#1#1 0rocess 1 - 1loF Chart
'E3E*"451" ,0
'tart
'tart
/E'E" 'tate
*ountM0) FP(KEDM0
1s
%alidKdata M 1R
1s
%alidKdata M 1R
3atch 22A bit data
*ountM countH1
Do
Jes
1s
*ount M A<R
1s
*ount M A<R
Do
FP(KEDM1
Jes
FPGA based measurement of frequency and phase difference 2010
7#1#( 0rocess ( - 1loF Chart
'E3E*"451" ,1
Jes
'tart
'tart
Reset state
=9"KEDM0
1s
FP(KEDM1R
M1R
1s
FP(KEDM1R
M1R
Do
*alculate shifted data for findin# auto and
cross correlation coefficients!
Cal=C state
*alculation of cross correlation
coefficients (*1) *2 S*10 and auto
correlation coefficients (*0) *0p) *0n
Rea& =&ata state
*alculation of frequency word
correspondin# to *
*tate *:-*1:
/esol%in# Ambi#uity in frequency and
phase measurement
Z
Z
FPGA based measurement of frequency and phase difference 2010
'E3E*"451" ,2
Z
Z
Read data 1i$al=state
8btain frequency and phase output %alues
1s
=9"KEDM1R
1s
=9"KEDM1R
Enable =A/"
Jes
Do
FPGA based measurement of frequency and phase difference 2010
7#1#3 0rocess 3 - 1loF Chart
'E3E*"451" ,,
'tart
'tart
/eset state
=9"KEDM0
1s
=9"KEDM1R
R
1s
=9"KEDM1R
R
Write data to F1F8
"ransfer 0 bit data serially
WriteKdataKcountMWriteKdataKcount 41
Do
Jes
1s
WriteKdataKcountM0
R
1s
WriteKdataKcountM0
R
Jes
Do
1s
";KdataKreadyM1R
R
1s
";KdataKreadyM1R
R
Jes
FPGA based measurement of frequency and phase difference 2010
7#( Test Cases a$& -eri'icatio$ "+ *i5!latio$
7#(#1 Test case16
1nput 1& freq C <2 (.$) phase C ,0 de#rees
1nput 2& freq C <2 (.$) phase C 110 de#rees
'E3E*"451" ,<
FPGA based measurement of frequency and phase difference 2010
7#(#( Test case(6
1nput 1& freq C 20 (.$) phase C ,0 de#rees
1nput 2& freq C 20 (.$) phase C 120 de#rees
'E3E*"451" ,2
FPGA based measurement of frequency and phase difference 2010
7#(#( Test case36
1nput 1& freq C 100 (.$) phase C <2 de#rees
1nput 2& freq C 100 (.$) phase C ,12 de#rees
'E3E*"451" ,A
FPGA based measurement of frequency and phase difference 2010
Chapter < RE*U)T /N/)9*I*
'E3E*"451" ,B
FPGA based measurement of frequency and phase difference 2010
Chapter 2 CONC)U*ION
FPGA based measurement of frequency and phase difference was successfully implemented
usin# 5.93! "he frequency and phase difference of and for an input si#nal were measured
accurately with a tolerance of less than ?1 (.$ and ? 2 de#rees respecti%ely!
5erification of the code was done usin# simulated test benches! A * code was written and used
for #eneratin# 22A bit data streams for any #i%en frequency and phase to be used in the test
benches! "he results obtained were coherent with theoretical calculations!
"he P*> was desi#ned and fabricated successfully! "he schematics for the desi#n alon# with the
"op placement and >ottom placement GE/>E/ files are attached alon# with this pro+ect!
*cope 'or '!t!re For@
Wor- can be done in enhancin# its capability to measure %ery hi#h frequencies to the tune
of 2 to10 G.$ and abo%e!
"he accuracy of the output can be increased by utili$in# more number of bits to describe
the frequency and phase %alues!
"he architecture can be pipelined to reduce the number of cloc-s it ta-es to measure the
frequency and phase once the 22A bit data is ready for processin#!
'E3E*"451" ,0
FPGA based measurement of frequency and phase difference 2010
RE1ERENCE*
T1U >oyd) 6!A!) .arris) 9!>!) @in#) 9!9!) and Welch) .!W!) 6r!) Editors! Electronic
Countermeasures* 3os Altos) *A& Peninsula Publishin#) 1FB0!
T2U Fitts) /! E!) Editor! )he =trate"9 of Electroma"netic Conflict* 3os Altos) *A& Peninsula
Publishin#) 1F00!
T,U Price) A! I"he .istory of =!'! Electronic Warfare)I )he >ssociation of ?l& Cro@s*
Ale;andria) 5A) 1F0<!
T<U 9a%ies) *! 3!) and .ollands) P! IAutomatic Processin# for E'()I AEEE Broc* 5ol! 12F) 6une
1F02) pp! 1A<41B1!
T2U .o%anessian) '! A! IDoise 6ammers as Electronic *ountermeasures)I Cicro@aDe Eournal*
'ept! 1F02) p! 11,!
TAU (ardia) .! @! IDew "echniques for the 9einterlea%in# of /epetiti%e 'equence)I AEE Broc.-,*
5ol! 1,A) pp! 1<F412<) Au#! 1F0F
TBU Walden) /! .u#hes /esearch 3aboratories) (alibu) *A) Pri%ate communication!
T0U Wan#) @! *! 'cience *enter) /oc-well 1nternational) "housand 8a-s) *A) Pri%ate
communication!
TFU 'paanenbur#) .! .oneywell 1nc!) >loomin#ton) (D) Pri%ate communication!
T10U 3emnios) V! Ad%anced /esearch Pro+ects A#ency) Arlin#ton) 5A) Pri%ate communication!
T11U 3ennen) G! /!) and 9aly) P! IA DA5'"A/ GP' *LA *ode 9i#ital /ecei%er)I NaDi"ationF
Eournal of the Anstitute of NaDi"ation* 5ol! ,A) Do! 1) 'prin# 1F0F) pp! 112412A!
T12U >rown) A!) and Wo1t) >! I9i#ital 34>And /ecei%er Architecture with 9irect /F 'amplin#)I
AEEE Bosition Gocation an& NaDi"ation =9mposium* pp! 20F421A) 3as 5e#as) April 1FF<!
T1,U 'harpin) 9! Wri#ht 3aboratory) 9ayton) 8.) Pri%ate communication!
'E3E*"451" ,F
FPGA based measurement of frequency and phase difference 2010
/00ENDI3
A. >H6/0<
1E/TURE*
UltraloF &istortio$
)oF $oise
3 $->G2H
3 p/>G2H
2igh spee&
1 .2HI J3 &, "a$&Fi&th A. K <1B
138: ->Ls sleF rate
7#8 $s settli$g ti5e to :#1M
*ta$&ar& a$& loF &istortio$ pi$o!t
*!ppl+ c!rre$t6 18 5/
O''set voltage6 1#: 5- 5a4
Wi&e s!ppl+ voltage ra$ge6 3#3 - to 1( -
0IN CON1I.UR/TION /ND DE*CRI0TION
Fi# A!1!1'81* Pin *onfi#uration!
'E3E*"451" <0
FPGA based measurement of frequency and phase difference 2010
"able A!1!1'81* Pin description
/00)IC/TION*
.i#h speed A9* dri%er!
F0 (.$ acti%e low4pass filter!
'E3E*"451" <1
FPGA based measurement of frequency and phase difference 2010
AA. C>I721E=H
1E/TURE*
Ultra-1astI 7#8$s 0ropagatio$ Dela+
I&eal 'or <3- a$& <8- *i$gle-*!ppl+ /pplicatio$s
,e+o$&-the-Rails I$p!t -oltage Ra$ge
)oFI 85/ *!ppl+ C!rre$t A/3NN7>/3NNNB
3#85- I$ter$al 2+steresis 'or Clea$ *Fitchi$g
O!tp!t )atch A/3N61>/3N63B
TT)>CO*-Co5pati"le O!tp!ts
(7:L/ *h!t&oF$ C!rre$t per Co5parator
/00)IC/TION*
'in#le ,5L25 'ystems
PortableL>attery4Powered 'ystems
"hreshold 9etectorsL9iscriminators
GP' /ecei%ers
3ine /ecei%ers
Vero4*rossin# 9etectors
.i#h4'peed 'amplin# *ircuits
'E3E*"451" <2
FPGA based measurement of frequency and phase difference 2010
0IN CON1I.UR/TION /ND DE*CRI0TION
Fi#! A!2!1 P1D *onfi#uration
'E3E*"451" <,
N/E 1UNCTION
1DA4 *omparator A 1n%ertin# 1nput
1D>4 *omparator > 1n%ertin# 1nput
1DAH *omparator A Don41n%ertin# 1nput
1D>H *omparator > Don4 1n%ertin# 1nput
3EA *omparator A 3atch Enable 1nput
3E> *omparator > 3atch Enable 1nput
WA *omparator A 8utput
W> *omparator > 8utput
WA bar *omparator A *omplementary 8utput
W> bar *omparator > *omplementary 8utput
FPGA based measurement of frequency and phase difference 2010
"able A!2!1 pin description
AAA. ICJ2//E-2KL012
1E/TURE*
*+ste5 gates6 N?8I??(
)ogic gates6 1?6I6(7
C), /rra+6 7? 4 7(
)ogic Cells6 18I88(
Di''ere$tial I>O 0airs6 (77
User I>Os6 81(
,loc@ R/ "its6 (N7IN1(
Distri"!te& R/ "its6 ((1I1?7
Device t+pe6 3C-6::E
*pee& gra&e6 -6
0ac@age t+pe6 ,all .ri& /rra+ A,.B
No# o' pi$s6 73(
Co$'ig!ratio$ "its6 3IN61I63(
'E3E*"451" <<
FPGA based measurement of frequency and phase difference 2010
AJ. 12-KA) 2.<-J )? 1.1-J/1.1-J )? <-J
GEJEG-=MA,)ANL )N>N=CEAJEN
OA)M 1-=)>)E ?P)BP)=
1E/TURE*
e5"er o' the Te4as I$str!5e$ts Wi&e"!sO 1a5il+
a4 tp& o' 8#? $s at 3#3 -
P(7-5/ O!tp!t Drive at 3#3 -
Co$trol I$p!ts -I2>-I) )evels /re Re'ere$ce& to -CC/ -oltage
)atch-Up 0er'or5a$ce E4cee&s (8: 5/ 0er QE*D 17
0IN CON1I.UR/TION /ND DE*CRI0TION


'E3E*"451" <2
FPGA based measurement of frequency and phase difference 2010
Fi#! A!<!1 pin details
J. G)C1110AL - =ANLGE <J N=212/N =06<
CPG)ABN?)?C?G )N>N=CEAJEN
1E/TURE*
1o!r R*(3( Tra$sceivers or TFo R*7?8 Tra$sceivers o$ O$e Chip
Operates 'ro5 a *i$gle 8- *!ppl+
Withsta$&s Repeate& P1:@- E*D 0!lses
Uses *5all Charge 0!5p Capacitors6 :#151
)oF *!ppl+ C!rre$t6 ?5/ T+pical
1:5/ *!ppl+ C!rre$t i$ *h!t&oF$
*el'-Testi$g Capa"ilit+ i$ )oop"ac@ o&e
0oFer-Up>DoF$ .litch-1ree O!tp!ts
Driver ai$tai$s 2igh I5pe&a$ce i$ Three-*tateI
*h!t&oF$ or Fith 0oFer O''
Ther5al *h!t&oF$ 0rotectio$
Receiver I$p!ts Ca$ Withsta$& P(8-
0IN CON1I.UR/TION /ND DE*CRI0TION
C1< A0i$ 1B6 *ommutatin# *apacitor *1 Positi%e "erminal! 1t requires 0!1mF e;ternal capacitor
between Pins 1 and 2!
C1R A0i$ (B6 *ommutatin# *apacitor *1 De#ati%e "erminal!
-DD A0i$ 3B6 Positi%e 'upply 8utput for /'2,2 9ri%ers! 1t requires an e;ternal 0!1mF capacitor
to #round!
/1 A0i$ 7B6 /ecei%er 1nput!
,1 A0i$ 8B6 /ecei%er 1nput!
'E3E*"451" <A
FPGA based measurement of frequency and phase difference 2010
91 A0i$ 6B6 9ri%er 8utput!
S1 A0i$ 7B6 9ri%er 8utput!
*E)1 A0i$ ?B6 1nterface (ode 'elect 1nput!
*E)( A0i$ NB6 1nterface (ode 'elect 1nput!

Fi#! A!2!1 Pin details
S( A0i$ 1:B& 9ri%er 8utput!
9( A0i$ 11B6 9ri%er 8utput!
,( A0i$ 1(B6 /ecei%er 1nput!
/( A0i$ 13B6 /ecei%er 1nput!
.ND A0i$ 17B6 Ground!
-EE A0i$ 18B6 De#ati%e 'upply 8utput! /equires an e;ternal 0!1mF capacitor to #round!
R,( A0i$ 16B6 /ecei%er 8utput!
'E3E*"451" <B
FPGA based measurement of frequency and phase difference 2010
R/( A0i$ 17B6 /ecei%er 8utput!
DS(>DE( A0i$ 1?B6 /'2,2 9ri%er 1nput in /'2,2 (ode! /'<02 9ri%er Enable with internal
pull4up in /'<02 mode!
D9( A0i$ 1NB6 9ri%er 1nput!
ON>O11 A0i$ (:B6 A hi#h lo#ic input enables the transcei%ers! A low puts the de%ice into
shutdown mode and reduces 1** to 10mA! "his pin has an internal pull4up!
), A0i$ (1B6 3oopbac- *ontrol 1nput! A low lo#ic le%el enables internal loopbac- connections!
"his pin has an internal pull4up!
D91 A0i$ ((B6 9ri%er 1nput!
DS1>DE1 A0i$ (3B6 /'2,2 9ri%er 1nput in /'2,2 (ode! /'<02 9ri%er Enable with internal
pull4up in /'<02 mode!
R/1 A0i$ (7B6 /ecei%er 8utput!
R,1 A0i$ (8B6 /ecei%er 8utput!
-CC A0i$ (6B6 Positi%e 'upply7 <!B25 X 5** X 2!225
C(R A0i$ (7B6 *ommutatin# *apacitor *2 De#ati%e "erminal! /equires 0!1mF e;ternal capacitor
between Pins 2B and 20!
C(< A0i$ (?B6 *ommutatin# *apacitor *2 Positi%e "erminal!
/00)IC/TION*
3ow Power /'<02L/'<22L/'2,2LE1A2A2 1nterface
'oftware4'electable (ultiprotocol 1nterface Port
*able /epeaters
3e%el "ranslators
'E3E*"451" <0
FPGA based measurement of frequency and phase difference 2010
JA. IC16J/0-BGCC00-BN?C
1E/TURE*
Y I$-s+ste5 progra55a"le 3#3- 0ROs 'or co$'ig!ratio$ o' 3ili$4 10./s
4 E$&!ra$ce o' (:I::: progra5>erase c+cles
4 0rogra5>erase over '!ll co55ercial>i$&!strial voltage a$& te5perat!re
ra$ge AR7:TC to <?8TCB
Y IEEE *t& 117N#1 "o!$&ar+-sca$ AQT/.B s!pport
Y *i5ple i$ter'ace to the 10./
Y Casca&a"le 'or stori$g lo$ger or 5!ltiple "it strea5s
Y )oF-poFer a&va$ce& CO* 1)/*2 process
Y D!al co$'ig!ratio$ 5o&es
4 *erial *loF>1ast co$'ig!ratio$ A!p to 33 2HB
4 0arallel A!p to (67 ">s at 33 2HB
Y 8- tolera$t I>O pi$s accept 8-I 3#3- a$& (#8- sig$als
Y 3#3- or (#8- o!tp!t capa"ilit+
Y /vaila"le i$ 0C(:I *O(:I 0C77I a$& -U77 pac@ages
Y Desig$ s!pport !si$g the 3ili$4 I*E /llia$ce *eriesO a$& 3ili$4 I*E 1o!$&atio$O
*eries so'tFare pac@ages
Y QT/. co55a$& i$itiatio$ o' sta$&ar& 10./ co$'ig!ratio$
'E3E*"451" <F
FPGA based measurement of frequency and phase difference 2010
0IN CON1I.UR/TION /ND DE*CRI0TION
Fi#! A!A!1 pin out dia#ram of P*<< P/8(
"able A!A!1 pin description
P1D DA(E P1D 9E'*/1P"18D
90
90 is the 9A"A output pin to pro%ide data for confi#urin# an FPGA in
serial mode!
91)92)9,)9<)
92)9A)9B
9049B is the output pins to pro%ide parallel data for confi#urin# a Eilin;
FPGA in 'la%e ParallelL'elect (AP mode!
9149B remain in hi#h4V state when the P/8( operates in serial mode!
9149B can be left unconnected when the P/8( is used in serial mode!
*3@ Each risin# ed#e on the *3@ input increments the internal address counter
if both *E is 3ow and 8EL/E'E" is .i#h!
8EL
/E'E"
When 3ow) this input holds the address counter reset and the 9A"A output
is in a hi#h4V state! "his is a bidirectional open4drain pin that is held 3ow
'E3E*"451" 20
FPGA based measurement of frequency and phase difference 2010
while the P/8( is reset! Polarity is D8" pro#rammable
*E When *E is .i#h) the de%ice is put into low4power standby mode) the
address counter is reset) and the 9A"A pins are put in a hi#h4V state!
*F Allows 6"AG *8DF1G instruction to initiate FPGA confi#uration without
powerin# down FPGA! "his is an open4drain output that is pulsed 3ow by
the 6"AG *8DF1G command!
*E8 *hip Enable 8utput (*E8 is connected to the *E input of the ne;t P/8(
in the chain! "his output is 3ow when *E is 3ow and 8EL/E'E" input is
.i#h) AD9 the internal address counter has been incremented beyond its
"erminal *ount ("* %alue! *E8 returns to .i#h when 8EL/E'E" #oes
3ow or *E #oes .i#h!
"(' (89E 'E3E*"
"he state of "(' on the risin# ed#e of "*@ determines the state
transitions at the "est Access Port ("AP controller! "(' has an internal 20
-Z resisti%e pull4up to pro%ide lo#ic 1 to the de%ice if the pin is not dri%en!
"*@ *38*@
"his pin is the 6"AG test cloc-! 1t sequences the "AP controller and all
the 6"AG test and pro#rammin# electronics
"91 9A"A 1D!
"his pin is the serial input to all 6"AG instruction and data re#isters! "91
has an internal 20 -Z resisti%e pull4up to pro%ide lo#ic 1 to the de%ice if the
pin is not dri%en!
"98 9A"A 8="!
"his pin is the serial output for all 6"AG instruction and data re#isters!
"98 has an internal 20 -Z resisti%e pull4up to pro%ide a lo#ic 1 to the
system if the pin is not dri%en
5**1D" Positi%e ,!,5 supply %olta#e for internal lo#ic
5**8 Positi%e ,!,5 or 2!25 supply %olta#e connected to the input buffers (2 and
output %olta#e dri%ers!
D* Do connects!
GD9 GD9 is the #round connection
'E3E*"451" 21
FPGA based measurement of frequency and phase difference 2010
JAA. C>I1771EPE-Ne"ulator
1E/TURE*
.!ara$tee& 1/ O!tp!t C!rre$t
)oF (1:5- Dropo!t at 1/
Up to P1M O!tp!t -oltage /cc!rac+
0reset at 1#8-I 1#?-I (#:-I (#8-I 3#3- or 8#:-
/&%!sta"le 'ro5 1#(8- to 8#:-
Reset O!tp!t A75s &ela+B
)oF 1(8L/ .ro!$& C!rre$t
:#1L/ *h!t&oF$
)oF 118L-R* O!tp!t Noise
Ther5al Overloa& 0rotectio$
O!tp!t C!rre$t )i5it
Ti$+ T**O0 0oFer 0ac@age A1#8WB
3:M *5aller tha$ *OT((3 Ao$l+ 1#155 highB
0IN CON1I.UR/TION


Fi# A!B!1& (AE 1BF, E=E pin confi#uration
0IN DE*CRI0TION
'E3E*"451" 22
FPGA based measurement of frequency and phase difference 2010
0IN N/E 1UNCTION
1) 0) F)
1A
D!*! Do *onnection! Dot internally connected!
2) ,) <)
2
1D /e#ulator 1nput! 'upply %olta#e ran#es from H2!25 to H2!25!
>ypass with a <!B[F capacitor to GD9! "hese inputs are
internally connected) but they also must be e;ternally
*onnected for proper operation!
A /'" /eset 8utput! 8pen4drain output is low when 58=" is A\
below its nominal %alue! /'" remains low while the output
%olta#e (58=" is below the reset threshold and for at least
<ms after 58=" rises abo%e the reset threshold! *onnect a
100-Z pull4up resistor to 8=" to obtain an output %olta#e!
B '.9D Acti%e43ow 'hutdown 1nput! A lo#ic low disables the output
and reduces the supply current to 0!1[A! 1n shutdown) the
/'" output is low and 8=" is pulled low throu#h an internal
2-Z resistance! *onnect '.9D to 1D for normal operation!
10 GD9 Ground! "his pin and the e;posed pad also function as a heat
sin-! 'older both to a lar#e pad and to the circuit4board
#round plane to ma;imi$e power dissipation!
11 'E" 5olta#e4'ettin# 1nput! *onnect to GD9 to select the factory4
preset output %olta#e! *onnect 'E" to an e;ternal resistor4
di%ider for ad+ustable4output operation!
12) 1,)
1<) 12
8=" /e#ulator 8utput! >ypass with a A!0[F low4E'/ capacitor to
GD9! *onnect all 8=" pins to#ether at the 1*!
JAAA. BQ/7/IM/2R-Ne"ulator
1E/TURE*
)oF voltage operatio$ Ai$i5!5 operati$g voltage6 (#38-B
'E3E*"451" 2,
FPGA based measurement of frequency and phase difference 2010
(#8- i$p!t V availa"le 1#8 to 1#?- o!tp!t
)arge o!tp!t c!rre$t t+pe AIO6 (/B
)oF &issipatio$ c!rre$t
AU!iesce$t c!rre$t6 /3# (5/
O!tp!t O11-state &issipatio$ c!rre$t6 /3# 8L/B
)oF poFer-loss
,!ilt-i$ over c!rre$t a$& overheat protectio$ '!$ctio$s
TO-(63 s!r'ace 5o!$t pac@age
0INOUT DI/.R/ /ND 0IN DE*CRI0TION
P1D14 5in P1D<4 5ad+ (8utput 5olta#e
Ad+ustment
P1D24 8DL8FF
*ontrol P1D24GD9
P1D,4 9* output P1DA4 5o( 9* 8utput 5olta#e

Fi# A!0!1 pin out dia#ram
/00)IC/TION*
Personal computers and peripheral equipment
Power supplies for %arious di#ital electronic equipment such as 959 player or '">
Power supplies for automoti%e equipment such as car na%i#ation system!
'E3E*"451" 2<
0U:7:32:(S
*ERIE*
RE.U)/TOR
FPGA based measurement of frequency and phase difference 2010
'E3E*"451" 22