EE367 VHDL Guide Book

Spring 2005

VHDL Entity/Architecture
Entity:
entity entity_name is
port ( signal_names : mode signal_type;
signal_names : mode signal_type;
. . .
signal_names : mode signal_type);
end entity_name;


Architecture:
architecture architecture_name of entity_name is
type declarations
signal declarations
constant declarations
function definitions
procedure definitions
component declarations
begin
concurrent_statement;
. . .
concurrent_statement;
end architecture_name;

VHDL Concurrent Signal Assignments:

Simple Signal Assignment:
signal_name <= expression;

Conditional Signal Assignment:
signal_name <= expression when boolean_expression else
expression when boolean_expression else
. . .
expression when boolean_expression else
expression;

Selected Signal Assignment:
with expression select
signal_name <= signal_value when choices,
signal_value when choices,
. . .
signal_value when others;

Process:
process ( signal_name, . . ., signal_name )
begin
...
end process;

VHDL Predefined Types:
bit character severity_level
bit_vector integer string
boolean real time




VHDL Operators:
arithmetic: +, -, *, /
logical: and, or, xor, nand, nor, xnor, not
relational: =, /=, <, <=, >, >=
shift left/right logical: sll, srl
shift left/right arithmetic: sla, sra
rotate left/right logical: rol, ror
other: concatenation: &
exponentiation: **
remainder: rem
division modulo: mod




VHDL Process:
process ( signal_name, . . ., signal_name )
type declarations
variable declarations
constant declarations
function definitions
procedure definitions
begin
sequential_statement
. . .
sequential_statement
end process;

VHDL Array Declarations:
type type_name is array (start to end) of element_type;
type type_name is array (start downto end)of element_type;
type type_name is array (range_type) of element_type;
type type_name is array (range_type range start to end) of
element_type;
type type_name is array (range_type range start downto end)
of element_type;

VHDL CONSTANT Declaration:
CONSTANT const_name : signal_type := expression;


VHDL Component Declaration:
component component_name
port ( signal_names : mode signal_type;
signal_names : mode signal_type);
end component;
VHDL Component Instantiation:
label: component_name port map (port_signal_name_1 =>
signal_1, port_signal_name_2 => signal_2, . . . ,
port_signal_name_n => signal_n );

VHDL Sequential Statements:

Simple Signal Assignment:
signal_name <= expression;

VHDL if Statement:
if boolean_expression then sequential_statement
end if;
if boolean_expression then sequential_statement
else sequential_statement
end if;
if boolean_expression then sequential_statement
elsif boolean_expression then sequential_statement
. . .
elsif boolean_expression then sequential_statement
end if;
if boolean_expression then sequential_statement
elsif boolean_expression then sequential_statement
. . .
elsif boolean_expression then sequential_statement
else sequential_statement
end if;

VHDL Case Statement:
case expression is
when choices => sequential_statements
. . .
when choices => sequential_statements
end case;


VHDL Loop Statements:

Loop:
loop
sequential_statement
. . .
sequential_statement
end loop;

for loop:
for identifier in range loop
sequential_statement
. . .
sequential_statement
end loop;

while loop:
while boolean_expression loop
sequential_statement
. . .
sequential_statement
end loop;


VHDL Entity with Generic:
entity entity_name is
generic ( constant_names : constant_type;
. . .
constant_names : constant_type);
port ( signal_names : mode signal_type;
signal_names : mode signal_type;
. . .
signal_names : mode signal_type);
end entity_name;

VHDL Package Definition:
package package_name is
type declarations
signal declarations
constant declarations
function definitions
procedure definitions
component declarations
end package_name;

package body package_name is
type declarations
constant declarations
function definitions
procedure definitions
end package_name;


VHDL Signal Assignment Statements

The architecture body has concurrent_statements within the begin and end. Concurrent statements are:

Simple Signal Assignment:
signal_name <=expression;

Conditional Signal Assignment:
signal_name <=expression when boolean_expression else
expression when boolean_expression else
. . .
expression when boolean_expression else
expression;

Selected Signal Assignment:
with expression select
signal_name <=signal_value when choices,
signal_value when choices,
. . .
signal_value when choices;

Process:
A process with it =s begin and end is considered to be a concurrent statement in the architecture body.
The process body between it =s begin and end must have sequential_statements.

Sequential statements are:

Simple Signal Assignment:
signal_name <=expression;

IF statement:
if boolean_expression then sequential_statement
end if;

if boolean_expression then sequential_statement
else sequential_statement
end if;

if boolean_expression then sequential_statement
elsif boolean_expression then sequential_statement
. . .
elsif boolean_expression then sequential_statement
end if;

if boolean_expression then sequential_statement
elsif boolean_expression then sequential_statement
. . .
elsif boolean_expression then sequential_statement
else sequential_statement
end if;

CASE Statement:
case expression is
when choices => sequential_statements
. . .
when choices =>sequential_statements
end case;
You may NOT use conditional signal assignments or selected signal assignments within a process as they are not sequential
statements.

Other Miscellaneous Stuff about VHDL


You can specify bit strings in hex: x"ab" is equivalent to "10101011"

You can carve out a slice of bits from a logic vector:
Data1 : in STD_LOGIC_VECTOR(15 downto 0);
Data2 : out STD_LOGIC_VECTOR(7 downto 0);

You can specify individual bits in a vector:
Bit_1 : STD_LOGIC:
Bit_1 <= Data1(1);

You can assign the high byte of Data1 to Data2 by:
Data2(7 downto 0) <= Data1(15 downto 8);

Type conversion between STD_LOGIC_VECTOR and INTEGERS and Arithmetic Operations on STD_LOGIC_VECTORS:

You have two choices to do arithmetic when your signals are STD_LOGIC_VECTOR type (recommended for the entity inputs and
outputs.)
You can:
a. Convert input data to integers, perform all required operations on integers and convert the results to
STD_LOGIC_VECTOR.
b. Attach a package containing definitions of arithmetic and relational operators that allow arithmetic using
STD_LOGIC_VECTOR.

The most frequently used packages that contain both conversion functions and definitions of popular operators for logic vector
arguments are:
C STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED. These define exactly the same set of objects, but the first
interprets logic vectors as numbers with sign and the second as unsigned numbers.
C STD_LOGIC_ARITH. This declares special types SIGNED and UNSIGNED and a full set of operations on
arguments of those types.


Package

Arithmetic Operations

Conversion to Integer

Conversion to
STD_LOGIC_VECTOR

STD_LOGIC_SIGNED and
STD_LOGIC_UNSIGNED

A+B

conv_integer(A)

none

STD_LOGIC_ARITH

signed(A) + signed(B)
or
unsigned(A)+unsigned(B)

conv_integer(signed(A))
or
conv_integer(unsigned(A)
)

conv_std_logic_vector(Int,nb
)

A, B: std_logic_vector
Int: Integer
nb: number of bits required in the resulting vector
signed, unsigned: casting a vector to a signed or unsigned number

You use these packages by declaring them before the entity:
library IEEE;
use IEEE.STD_LOGIC_1164.all; ` -- Uses the STD_LOGIC_VECTOR defintions
use IEEE.STD_LOGIC_ARITH.all; -- Use the STD_LOGIC_ARITH functions



G:\1wpdocs\univ\dept\courses\Ee367\VHDL Guide Book_05a.doc

EE367 VHDL
Guide Book and Cheat Sheets

ECE Department
Montana State University
Spring 2005