Intel(R) Core(TM) i3 CPU

M 330 @ 2.13GHz
Intel64 Family 6 Model 37 Stepping 2, GenuineIntel
HTT
*
Hyperthreading enabled
HYPERVISOR
Hypervisor is present
VMX
*
Supports Intel hardware-assisted virtualization
SVM
Supports AMD hardware-assisted virtualization
EM64T
*
Supports 64-bit mode
SMX
SKINIT

Supports Intel trusted execution

Supports AMD SKINIT

NX
SMEP
SMAP
PAGE1GB
PAE
PAT
PSE
PSE36
PGE
SS
VME
RDWRFSGSBASE

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*
*
*
*
*
*
*
-

Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports

FPU
MMX
MMXEXT
3DNOW
3DNOWEXT
SSE
SSE2
SSE3
SSSE3
SSE4.1
SSE4.2

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*
*
*
*
*
*
*

Implements i387 floating point instructions

Supports MMX instruction set
Implements AMD MMX extensions
Supports 3DNow! instructions
Supports 3DNow! extension instructions
Supports Streaming SIMD Extensions
Supports Streaming SIMD Extensions 2
Supports Streaming SIMD Extensions 3
Supports Supplemental SIMD Extensions 3
Supports Streaming SIMD Extensions 4.1
Supports Streaming SIMD Extensions 4.2

AES
AVX
FMA
MSR
MTRR
XSAVE
OSXSAVE
RDRAND
RDSEED

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*
-

Supports AES extensions

Supports AVX intruction extensions
Supports FMA extensions using YMM state
Implements RDMSR/WRMSR instructions
Supports Memory Type Range Registers
Supports XSAVE/XRSTOR instructions
Supports XSETBV/XGETBV instructions
Supports RDRAND instruction
Supports RDSEED instruction

CMOV
CLFSH
CX8
CX16
BMI1
BMI2
ADX
DCA
F16C
FXSR
FFXSR
MONITOR
MOVBE

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*
*
*
*
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Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports
Supports

no-execute page protection

Supervisor Mode Execution Prevention
Supervisor Mode Access Prevention
1 GB large pages
> 32-bit physical addresses
Page Attribute Table
4 MB pages
> 32-bit address 4 MB pages
global bit in page tables
bus snooping for cache operations
Virtual-8086 mode
direct GS/FS base access

CMOVcc instruction
CLFLUSH instruction
compare and exchange 8-byte instructions
CMPXCHG16B instruction
bit manipulation extensions 1
bit maniuplation extensions 2
ADCX/ADOX instructions
prefetch from memory-mapped device
half-precision instruction
FXSAVE/FXSTOR instructions
optimized FXSAVE/FSRSTOR instruction
MONITOR and MWAIT instructions
MOVBE instruction

ERMSB
PCLULDQ
POPCNT
SEP
LAHF-SAHF
HLE
RTM

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*
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Supports
Supports
Supports
Supports
Supports
Supports
Supports

Enhanced REP MOVSB/STOSB

PCLMULDQ instruction
POPCNT instruction
fast system call instructions
LAHF/SAHF instructions in 64-bit mode
Hardware Lock Elision instructions
Restricted Transactional Memory instructions

DE
DTES64
DS
DS-CPL
PCID
INVPCID
PDCM
RDTSCP
TSC
TSC-DEADLINE
TSC-INVARIANT
xTPR

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*
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*

Supports I/O breakpoints including CR4.DE

Can write history of 64-bit branch addresses
Implements memory-resident debug buffer
Supports Debug Store feature with CPL
Supports PCIDs and settable CR4.PCIDE
Supports INVPCID instruction
Supports Performance Capabilities MSR
Supports RDTSCP instruction
Supports RDTSC instruction
Local APIC supports one-shot deadline timer
TSC runs at constant rate
Supports disabling task priority messages

EIST
ACPI
TM
TM2
APIC
x2APIC

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*
*
*
*
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Supports Enhanced Intel Speedstep

Implements MSR for power management
Implements thermal monitor circuitry
Implements Thermal Monitor 2 control
Implements software-accessible local APIC
Supports x2APIC

CNXT-ID

L1 data cache mode adaptive or BIOS

MCE
MCA
PBE

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*
*

Supports Machine Check, INT18 and CR4.MCE

Implements Machine Check Architecture
Supports use of FERR#/PBE# pin

PSN

Implements 96-bit processor serial number

PREFETCHW

Supports PREFETCHW instruction

Logical to Physical Processor Map:

**-- Physical Processor 0 (Hyperthreaded)
--** Physical Processor 1 (Hyperthreaded)
Logical Processor to Socket Map:
**** Socket 0
Logical Processor to NUMA Node Map:
**** NUMA Node 0
Logical Processor to Cache Map:
**-- Data Cache
0, Level
**-- Instruction Cache 0, Level
**-- Unified Cache
0, Level
--** Data Cache
1, Level
--** Instruction Cache 1, Level
--** Unified Cache
1, Level
**** Unified Cache
2, Level
Logical Processor to Group Map:
**** Group 0

1, 32 KB, Assoc 8,
1, 32 KB, Assoc 4,
2, 256 KB, Assoc 8,
1, 32 KB, Assoc 8,
1, 32 KB, Assoc 4,
2, 256 KB, Assoc 8,
3,
3 MB, Assoc 12,

LineSize
LineSize
LineSize
LineSize
LineSize
LineSize
LineSize

64
64
64
64
64
64
64