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ADC - A 10 Bit 100 MHZ Pipeline ADC
ADC - A 10 Bit 100 MHZ Pipeline ADC
I. INTRODUCTION
A. Performance limits.
The accuracy limitation of most ADC architectures is a
function of various forms of comparator offset errors, which
2
capacitor would be in danger of being swamped by parasitic
capacitances.
In this implementation, the scheme was used for the first three
stages. The net result of this is that the capacitance that the first
and second stages need to drive is divided by half compared
with the conventional scheme. This has the potential to half the
power requirements for charging and discharging of the
capacitors (not including the comparator capacitors). A demerit
of this scheme is that 2 separate capacitor sets need to be used,
in every second sample phase of the first stage. Mismatch
between the 2 sets may cause additional INL errors. However,
as already discussed, capacitor mismatch errors by their nature
lend easily to calibration methods. Amplifier errors, on the other
hand, do not, so this scheme not also saves power, but reduce
the speed requirements of the amplifier, as it is easier to achieve
complete settling.
B. Error cancellation scheme.
Next, the focus shifts to reducing the effects of the amplifier
errors. Consider the standard amplification phase as seen in
Figure 2.
3
referred offset errors, finite gain errors) two 40mV, 10MHz,
sinusoidal sources were placed in series with the negative
terminal of the first two amplifiers. Figure 7 shows the results of
a simulation where the input is ramped from 0 to full scale in a
transient simulation.
Figure 7 shows the input, the output for the non corrected case,
and the output for the corrected case. As can be seen, the
non-corrected case contains all of the amplifier errors
superimposed onto the original signal, which can only be
removed by ensuring the amplifier is of high enough quality to
keep that the errors small. On the other hand the simulation of
our scheme (The second output shown), which contains all of
the same error sources, produces and output which tracks the
original signal, with all of the errors successfully removed. In
conclusion, this demonstrates that our scheme has been
effective in removing these errors.
III. IMPLEMENTATION DETAILS.
A. Switch.
The first real circuit to be considered is the switch.
Figure 7: Plot showing the AHDL simulation results, for normal case and error
corrected case.
the two inputs are balance. Current Ib flows in each of the two
input devices, however current Ix is subtracted from Ib before it
is mirrored to the output. Therefore the static current flowing in
the output leg is
(3)
I static =( I b I x )n
If Ib is made similar to Ix, then the static current in the output
leg can be made close to zero, although for practical purposes,
more than 50uA of current will always flow in the output leg so
as to keep the common mode feedback amplifier alive, and to
keep all devices turned on. The static current in one of the input
current legs is Ib, but if n is large, then this can represent small
fraction of the overall power. Next, consider what happens if
there is a large input signal, and all of the current is flowing in
one of the input devices. In that case the current in the output
can be shown to be
(4)
I
=( 2 I I )n .
out max
5
Coherence test: M=5, 256 bins, Fs=100MHz => Fin=1.953125MHz
AHDL model
Figure 12: The switched capacitor comparator scheme, with timimg diagram.
IV. RESULTS
The top-level was verified under two conditions; 1 the
sub-blocks were modeled as AHDL, 2 the first three stages were
simulated as transistor level, including the amplifiers, switches,
comparators, and most digital blocks. A full transistor level
simulation was not completed. In Figure 13, the INL, and DNL
plots are shown for a sample selection of codes, with the DNL
and INL measured as less than 0.25 of an LSB for all cases. In
Figure 14, the results from a coherent test are shown.
AHDL model
V. CONCLUSIONS.
In this paper, a 10bit 100MHz amplifier has been proposed,
and the performance verified in AHDL simulations, and partial
transistor level simulations. In addition, 3 novel new design
techniques have been introduced to attempt to deal with some of
the limitations of a conventional pipeline ADC. Firstly the
amount of capacitance the amplifier is required to drive has
been halved. Secondly, the settling requirement of the first 2
amplifiers has been removed, resulting in the overall
performance of the ADC being desensitized to the limits of the
first 2 amplifiers. Thirdly, amplifier architecture has been
proposed which breaks the link between the required standing
current, and the maximum output current by using a class AB
output.
REFERENCES
APPENDIX
The simulation files are stored in the directory and library
/afs/engin.umich.edu/class/w04/eecs598/students/mferriss/ADC/.
The top cellview name is toplevel1 for first three stage transistor model, and
toplevel1_behav cellview is AHDL model.