Micro 333 Questions 4

1. How does the below code change the registers?

mov
orr
orr

r0,
r0,

r0,
r0,
r0,

#0x 00 00 03 FC
#0x 00 0A 70 00
#0x 2D C0 00 00

5. How can the following 32 bit values be ANDed with

the contents of the register r0.
0x 3F FF FF FF,
ANS:

ANS:

After 1st instruction, r0 = 0x 00 00 03 FC

After 2nd instruction, r0 = 0x 00 0A 73 FC

After 3rd instruction, r0 = 0x 2D CA 73 FC

These immediate values are not sparse but their

ones complements are.
not

0x 3F FF FF FF 0x C0 00 00 00
not
0x 7F FF FF FF 0x 80 00 00 00
Thus, AND NOT is performed instead of AND.

2. How does the below code change the registers?

mov
mvn
mov
mvn
ANS:

r0,
r1,
r2,
r3,

#0x
#0x
#0x
#0x

00
00
00
00

00
00
00
00

00
00
00
00

01
00
02
01

After 1st instruction, r0 = 0x 00 00 00 01

After 2nd instruction, r1 = 0x FF FF FF FF

After 3rd instruction, r2 = 0x 00 00 00 02

After 4th instruction, r3 = 0x FF FF FF FE

bic
bic

orr
bic
ANS:

r0,

mvn

r1,

mvn

r2,

#0x 00 00 00 00 (or just #0)

#0x 00 00 00 01 (or just #1)

#0x 00 00 00 02 (or just #2)

ANS:

+255 = 0x 00 00 00 FF

not
255 = 0x FF FF FF 01 0x 00 00 00 FE

+254 = 0x 00 00 00 FE

mov

r0,

mvn

r1,

mov

r2,

r1,
r2,

r0,
r0,

#(3<<17)
#(7<<17)

Shifted values correspond the immediate values.

sets the bits of r2 where 2nd

immediate is one. Thus,

bit bit bit bit

19 18 17 16

0x6 = 0 1 1 0
0xE = 1 1 1 0

r1 = b31 . . . b20

b19 1 1 b16

b15 . . . b0

r2 = b31 . . . b20

0 0 0 b16

b15 . . . b0

7. Let the register r0 = 0x C2 5A E3 5B. How do

the registers r1, r2, and r3 change after the following instructions?
orr
orr
bic
ANS:

r1,
r2,
r3,

r0,
r0,
r0,

#0x 00 00 FF 00
#0x 00 FF 00 00
#0x 00 00 00 FF

r1 = 0x C2 5A FF 5B. Byte 1 of r1 is set.

r2 = 0x C2 FF E3 5B. Byte 2 of r2 is set.

4. Write three lines of ARM code so that

r0 = +255 after 1st instruction,
r1 = -255 after 2nd instruction, and
r2 = +254 after 3rd instruction.

#0x C0 00 00 00
#0x 80 00 00 00

orr sets the bits of r1 where

1st immediate is one. bic re-

not

mvn

r0,
r0,

(3<<17) ( 6<<16) 0x 00 06 00 00
(7<<17) (14<<16) 0x 00 0E 00 00

r0 = -1 after 1st instruction,

r1 = -2 after 2nd instruction, and
r2 = -3 after 3rd instruction.
1 = 0x FF FF FF FF 0x 00 00 00 00

not
2 = 0x FF FF FF FE 0x 00 00 00 01

not
3 = 0x FF FF FF FD 0x 00 00 00 02

r0,
r0,

6. Let the 32 bit r0 = b31 b30 . . . . . . b1 b0 . How do

the registers r1 and r2 change by the code below?

3. Write three lines of ARM code so that

ANS:

0x 7F FF FF FF

r3 = 0x C2 5A E3 00. Byte 0 of r3 is reset.

8. How do the registers r1 and r2 change by the
following code?
orr
bic
ANS:

r0,
r0,

#(1<<31)+(1<<29)+(1<<28)
#(1<<31)+(1<<29)+(1<<28)

After the code, r1=r0 and r2=r0. Except,

orr

#0x 00 00 00 FF (or just #0xFF)

#0x 00 00 00 FE (or just #0xFE)

#0x 00 00 00 FE (or just #0xFE)

r1,
r2,

sets the bits 31, 29, 28 in r1.

bic resets the bits 31, 29, 28 in r2.

Shifted value corresponds the immediate value
(1 31) + (1 29) + (1 28) = 0x B0 00 00 00
1

9. Let the 32 bit r0 = b31 b30 . . . . . . b1 b0 . How do

the registers r1 and r2 change by the code below?
and
eor
ANS:

r1,
r2,

r0,
r0,

13. Write an instruction to perform each of the following tasks.

a) r0 = NOT(r0)
c) r0 = r0 - 5

#(3<<17)
#(7<<17)

Shifted values correspond the immediate values.

ANS:

bit bit bit bit

19 18 17 16

0x6 = 0 1 1 0

the bits of r2 where 2nd immediate is one. Thus,

0xE = 1 1 1 0

r1 = 0 . . . 0

0 b18 b17 0

0 ... 0

r2 = b31 . . . b20

b19 b18 b17 b16

b15 . . . b0

10. Let the register r0 = 0x C2 5A E3 5B. How do

the registers r1, r2, and r3 change after the following instructions?
and
and
eor
ANS:

r1,
r2,
r3,

r0,
r0,
r0,

ANS:

r3 = 0x C2 5A E3 A4. Byte 0 is toggled.

11. Let the register r0 = 0x C2 5A E3 5B. How do
the registers r1 and r2 change by the code below?
r1,
r2,

r0,
r0,

The registers are added and the sum is stored in

r4. Then, the sum in r4 is shifted right by 2 bits.
add
add
add
mov

#0x 00 00 FF 00
#0x 00 FF 00 00
#0x 00 00 00 FF

r2 = 0x 00 5A 00 00. Only byte 2 is nozero.

ANS:

14. Write an ARM code taking the average of the 32

bit integers in the registers r0, r1, r2, and r3.
The average must be stored in the register r4.
Assume that the integers are unsigned.

#(1<<31)+(1<<29)+(1<<28)
#(1<<31)+(1<<29)+(1<<28)

ANS:

0x C2 5A E3 5B
XOR 0x B0 00 00 00
r1 = 0x 70 00 00 00

AND

XOR

0xC = (1100)2
0xB = (1011)2
0x7 = (0111)2

12. Write a code to perform the following logic operations on the registers (at most 4 instructions).

add
add
add
mov

r4,
r4,
r4,

r0,
r2,
r4,

r0,
r4,
r4,
r4,

r1
r2
r3
r4, ASR #2

16. How can the following 32 bit values be added with

the contents of the register r0.
0x 3F FF FF FF,
ANS:

0x 7F FF FF FF

These immediate values are not sparse but their

twos complements are.
negate

0x 3F FF FF FF 0x C0 00 00 01
negate
0x 7F FF FF FF 0x 80 00 00 01
Thus, subtraction is used instead of addition.

The code is as follows

eor
bic
and

r4,
r4,
r4,
r4,

Shifting right by 2 bits means division by 22 .

Thus, r4 is equal to the average after the shift.

r4 = NOT(r0 XOR r1) AND r2 AND r3

ANS:

r1
r2
r3
r4, LSR #2

The registers are added and the sum is stored in

r4. Then, the sum in r4 is shifted right by 2 bits.

(1 31) + (1 29) + (1 28) = 0x B0 00 00 00

0xC = (1100)2
0xB = (1011)2
0x8 = (1000)2

r0,
r4,
r4,
r4,

15. Write an ARM code taking the average of the 32

bit integers in the registers r0, r1, r2, and r3.
The average must be stored in the register r4.
Assume that the integers are signed.

Shifted value corresponds the immediate value

0x C2 5A E3 5B
AND 0x B0 00 00 00
r1 = 0x 80 00 00 00

r4,
r4,
r4,
r4,

Shifting right by 2 bits means division by 22 .

Thus, r4 is equal to the average after the shift.

r1 = 0x 00 00 E3 00. Only byte 1 is nozero.

and
eor

a) mvn r0, r0 (ones complementing)

b) rsb r0, r0, #0 (twos complementing)
rsb (reverse subtract) performs r0 = 0 r0
instead of r0 = r0 0
c) sub r0, r0, #5
d) rsb r0, r0, #5

(3<<17) ( 6<<16) 0x 00 06 00 00
(7<<17) (14<<16) 0x 00 0E 00 00
and resets the bits of r1 where
1st immediate is zero. eor flips

b) r0 = NEGATE(r0)
d) r0 = 5 - r0

r1
r4
r3

sub
sub

r0,
r0,

r0,
r0,

#0x C0 00 00 01
#0x 80 00 00 01

17. Let the register r0 = 0x C2 5A E3 5B. How do

the registers change by the instructions?
mov r1, r0, LSL # 4

mov r2, r0, ROR #20

mov r3, r0, LSR #16

mov r4, r0, ASR #16

ANS: r1: 1 hexdigit left.

r3: 4 hexdigit right.

r2: 5 hexdigit rotate right.

r4: 4 hexdigit right (signed).

r1

25

AE

35

B0

r2

AE

35

BC

25

r3

00

00

C2

5A

r4

FF

FF

C2

5A

0xC2 = 1100 0010 is a negative number. Thus, r4 is filled with ones.

18. Let the register r0 = 0x 42 5A E3 5B. How do

the registers change by the instructions?
mov r1, r0, LSL # 4

mov r2, r0, ROR #20

mov r3, r0, LSR #16

mov r4, r0, ASR #16

ANS: r1: 1 hexdigit left.

r3: 4 hexdigit right.

r2: 5 hexdigit rotate right.

r4: 4 hexdigit right (signed).

r1

25

AE

35

B0

r2

AE

35

B4

25

r3

00

00

42

5A

r4

00

00

42

5A

0x42 = 0100 0010 is a positive number. Thus, r4 is filled with zeros.

19. Let the register r0 = 0x C2 5A E3 5B. How do

the registers change by the code below?
and
and
mov
mov
and
mov

r1,
r2,
r2,
r3,
r3,
r4,

r0,
r0,

r3,

#0x
#0x
r2,
r0,
#0x
r0,

00 00 00 FF extract byte0
00 00 FF 00 extract byte1
LSR # 8 make byte1 least significant
LSR #16 make byte2 least significant
00 00 00 FF extract byte2
LSR #24
extract byte3

ANS: The bytes of r0 are extracted with ANDing and shifting.

The bytes are assumed unsigned, thus zero extended.

r1

00

00

00

5B

r2

00

00

00

E3

r3

00

00

00

5A

r4

00

00

00

C2

20. Let the register r0 = 0x C2 5A E3 5B. How do

the registers change by the code below?
mov
mov
mov
mov
mov
mov
mov

r1,
r1,
r2,
r2,
r3,
r3,
r4,

r0,
r1,
r0,
r2,
r0,
r3,
r0,

LSL #24
ASR #24
LSL #16
ASR #24
LSL # 8
ASR #24
ASR #24

make byte 0 most significant

sign extend byte 0 with ASR
make byte 1 most significant
sign extend byte 1 with ASR
make byte 2 most significant
sign extend byte 2 with ASR
sign extend byte 3 with ASR

ANS: The bytes of r0 are extracted with ANDing and shifting.

The bytes are assumed signed, thus sign extended.

r1

00

00

00

5B

r2

FF

FF

FF

E3

r3

00

00

00

5A

r4

FF

FF

FF

C2