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THAT 4301 Datasheet
THAT 4301 Datasheet
THAT 4301 Datasheet
IC Dynamics Processor
THAT 4301
FEATURES
APPLICATIONS
High-Performance Blackmer
Voltage Controlled Amplifier
Compressors
Limiters
High-Performance RMS-Level
Detector
Gates
Expanders
De-Essers
Duckers
Low Cost
Description
THAT 4301 Dynamics Processor, dubbed
THAT Analog Engine, combines in a single IC
all the active circuitry needed to construct a wide
range of dynamics processors. The 4301 includes
a high-performance, exponentially-controlled
VCA, a log-responding RMS-level sensor and
three general- purpose opamps.
The VCA provides two opposing-polarity,
voltage-sensitive control ports. Dynamic range
exceeds 115 dB, and THD is typically 0.003% at
0 dB gain. The RMS detector provides accurate
rms-to-dc conversion over an 80 dB dynamic
range for signals with crest factors up to 10. One
opamp is dedicated as a current-to-voltage
18
19
17
11
14
VCC
OA1
20
Model
20 pin
DIP
Package
20 pin
SO
Package
4301
4301P20-U
4301W20-U
OA3
EC+
EC-
12
13
SYM
VCA OUT
IN
15
THAT4301
1
RMS
IN
16
IT
OUT
CT
OA2
GND VEE
4
10
Page 2 of 12
THAT4301Analog Engine
IC Dynamics Processor
SPECIFICATIONS 1,2
Absolute Maximum Ratings (T A =25C) 3
Positive Supply Voltage (VCC)
Negative Supply Voltage (VEE)
Supply Current (ICC)
+18 V
-18 V
20 mA
700 mW
0 to +70 C
-40 to +125 C
Symbol
Conditions
Min
Typ
Max
Units
VCC
+7
+15
VEE
-7
-15
ICC
12
18
mA
IEE
-12
-18
mA
Symbol
Conditions
Min
Typ
Max
Units
IB(VCA)
No Signal
30
400
pA
VOFF(VCA In)
No Signal
15
mV
IIN(VCA) or IOUT(VCA)
175
750
Arms
Gain at 0V Control
G0
EC+ = EC = 0.000V
-0.4
0.0
+0.4
dB
EC+/Gain (dB)
EC-/Gain (dB)
6.4
-6.4
6.5
-6.5
6.6
-6.6
mV/dB
mV/dB
EC / TCHIP
+0.33
%/C
0.5
110
115
dB
1
2
5
3
10
25
mV
mV
mV
20
20 Hz-20 kHz
Rout = 20k
0 dB gain
+15 dB gain
-96
-85
-94
-83
dBV
dBV
0.003
0.007
Gain-Control Constant
Gain-Control TempCo
Gain-Control Linearity
Off Isolation
Output Offset Voltage Change
EC+=SYM=-375mV, EC-=+375mV
VOFF(OUT)
Rout = 20k
0 dB gain
+15 dB gain
+30 dB gain
IIDLE
en(OUT)
THD
Page 3 of 12
Symbol
VSYM
Conditions
VIN = +10 dBV, 1 kHz
0 dB gain
15 dB gain
VOUT= +10 dBV, 1 kHz
+15 dB gain
minimum THD
Min
Typ
Max
Units
0.03
0.035
0.07
0.09
%
%
0.035
0.09
-2.5
+2.5
mV
Symbol
Conditions
Min
Typ
Max
Units
IB (RMS)
No Signal
30
400
pA
VOFF(RMS In)
No Signal
15
mV
IIN(RMS)
175
750
Iin0
IT= 7.5 A
8.5
12
EO / 20log(Iin/Iin0)
6.4
6.5
6.6
mV/dB
.985
1.015
fIN = 1kHz
1A < Iin< 100A
100nA < Iin< 316A
31.6nA < Iin< 1mA
0.1
0.5
1.5
dB
dB
dB
20
20
3.5
5
10
Iin 10mA
Iin 3mA
Iin 300nA
100
45
7
kHz
kHz
kHz
1.5
7.5
15
IT = 7.5 A
-10
+20
+50
mV
ICT/IT
IT = 7.5 A
0.90
1.1
1.30
TCHIP = 55C
Eo / TCHIP
0.33
%/C
IOUT
90
100
Output Linearity
Rectifier Balance
Crest Factor
IT
Voltage at IT Pin
Timing Current Accuracy
Filtering Time Constant
Output Temp. Coefficient
Output Current
(0.026 ) CI TT
Page 4 of 12
THAT4301Analog Engine
IC Dynamics Processor
Symbol
Conditions
Min
OA1
Typ Max
Min
OA2
Typ Max
Min
OA3
Typ Max
Units
VOS
0.5
0.5
0.5
mV
IB
150
500
150
500
150
500
nA
IOS
15
50
15
50
N/A
nA
IVR
13.5
13.5
N/A
RS<10k
100
100
N/A
PSRR
VS=7V to 15V
100
100
100
GBW
(@50kHz)
AVO
RL=10k
RL=2k
115
N/A
110
N/A
125
120
13
N/A
13
N/A
14
13
V
V
12
mA
V/s
VO@RL=5k
VO@RL=2k
SR
THD
0.0007 0.003
N/A
0.0007 0.003
N/A
0.0007 0.003
0.0007 0.003
fO=1kHz
6.5
10
7.5
12
7.5
12
fO=1kHz
0.3
0.3
0.3
6. Test circuit for opamps is a unity-gain follower configuration with loaded resistor R L as specified.3
+15V
R5
VCA SYM
50K
-15V
SIGNAL
IN
C1
C2
R1
47pF
R4
300K
20K0 1%
47uF
R3
R2
51
20K0 1%
+15V
C7
SYM
OA1
VCC
C8
C3
47uF
IN
100n
VCA
OUT
EC+
EC-
SIGNAL
OUT
OA3
THAT4301
VEE
100n
-15V
R6
RMS
IN
+
OA2
OUT
Ct
It
GND
10K0 1%
C6
R7
2M00
1%
22uF
C4
10uF
RMS
OUT
Ec-
-15V
MHz
%
%
Page 5 of 12
REPRESENTATIVE DATA
dB
GAIN
10
%THD+N
20
0
-20
0.1
-40
-60
0.01
-80
-100
-200
mV
600
400
200
0.001
0.5
%THD+N
10
0.1
0.1
0.01
0.01
Vin
rms
0.001
0.1
%THD+N
0.001
0.5
Vin
rms
10
1.0
Vin
rms
10
1.0
%THD+N
mV Out
300
Note: 0 dBr = 85 m Vrms
200
0.1
100
0
-100
0.01
-200
1kHz
-300
0.001
20
100
1k
10k
Hz
20k
mV Error
-40
20
40
mV Out
+40 dBr
+30 dBr
200
20
dBr
In
-20
10kHz
-400
-60
+20 dBr
100
+10 dBr
10
0 dBr
-10 dBr
0
-100
-20 dBr
-30 dBr
-10
-200
-40 dBr
-20
-60
dBr
In
-40
-20
20
40
-300
20
100
1k
10k
Hz
20k
Page 6 of 12
THAT4301Analog Engine
IC Dynamics Processor
Theory of Operation
THAT 4301 Dynamics Processor combines THAT
Corporations proven Voltage-Controlled Amplifier
(VCA) and RMS-Level Detector designs with three
general-purpose opamps to produce an Analog
Engine useful in a variety of dynamics processor
applications. For details of the theory of operation of
the VCA and RMS-Detector building blocks, the interested reader is referred to THAT Corporations data
sheets on the 2180 Series VCAs and the 2252 RMSLevel Detector. Theory of the interconnection of
exponentially-controlled VCAs and log-responding
level detectors is covered in THAT Corporations
application note AN101, The Mathematics of LogBased Dynamic Processors.
needed to drive the positive VCA control port; circuitry associated with OA1, OA2 and the RMS detector has been omitted.
R5
50K
Positive Control In
C1
C2 47pF
R1
Signal In
47uF
VCA SYM
20K0 1%
R3
R4
300K
OA1
+
IN
VCA
EC-
R2
20K0 1%
51
SYM
OUT
EC+
OA3
+
Signal
Out
THAT4301
VCC
VEE
IN
It
RMS
OUT
Ct
GND
+
OA2
-
Figure 11. Driving the VCA via the Positive Control Port
The 4301s detector computes rms level by rectifying input current signals, converting the rectified
current to a logarithmic voltage, and applying that
voltage to a log-domain filter. The output signal is a
dc voltage proportional to the decibel-level of the rms
value of the input signal current. Some ac component
(at twice the input frequency) remains superimposed
on the dc output. The ac signal is attenuated by a logdomain filter, which constitutes a single-pole rolloff
with cutoff determined by an external capacitor and a
programmable dc current.
Page 7 of 12
Page 8 of 12
THAT4301Analog Engine
IC Dynamics Processor
Applications
The circuit of Figure 12 shows a typical application for THAT 4301. This simple compressor/
limiter design features adjustable hard-knee
threshold, compression ratio, and static gain1.
The applications discussion in this data sheet will
center on this circuit for the purpose of illustrating important design issues. However, it is posslble to configure many other types of dynamics
processors with THAT 4301. Hopefully, the following discussion will imply some of these
possibilities.
Signal Path
As mentioned in the section on theory, the VCA
input pin is a virtual ground with negative feedback provided internally. An input resistor (R1,
20k) is required to convert the ac input voltage
to a current within the linear range of the 4301.
(Peak VCA input currents should be kept under
1 mA for best distortion performance.) The coupling capacitor (C1, 47 f) is strongly recommended to block dc current from preceding stages
(and from offset voltage at the input of the VCA).
Any dc current into the VCA will be modulated by
varying gain in the VCA, showing up in the output
VCA SYM
C1
R1
47uF
20K0 1%
+15
CCW
R5
50K
R9
THRESHOLD
R11
R12
10K
383K 1%
R10
CW
-15
10K0 1%
C9
+15
22p
R4
300K
CR2
R2
51
CR1
20K0 1%
2M00 1%
-15
R8
C7
4k99 1%
+15
100n
C8
100n
IN
C3
CW
IN
EC-
SYM
VCA OUT
EC+
-15 R6
IN
IT
RMS OUT
CT
10K0 1%
R14
1K43
1%
22uF
GND
OUT
+
OA2
R16
R7
2M00
1%
4k99 1%
C4
10uF
C5
100N
-15
R17
R15
CCW
OA3
+
THAT4301
VCC
C6
R13
10K
OA1
+
VEE
47uF
COMPRESSION
47pF
C2
R3
10K0
1%
590K
1%
+15
GAIN
CW
R18
10K
CCW
-15
Page 9 of 12
RMS-Level Detector
The RMS detectors input is similar to that of the
VCA. An input resistor (R6, 10 k) converts the ac
input voltage to a current within the linear range of
the 4301. (Peak detector input currents should be
kept under 1 mA for best linearity.) The coupling
capacitor (C3, 47 f) is recommended to block dc
current from preceeding stages (and from offset voltage at the input of the detector). Any dc current into
the detector will limit the low-level resolution of the
detector, and will upset the rectifier balance at low
levels. Note that, as with the VCA input circuitry, C3
in conjunction with R6 will set the lower frequency
limit of the detector.
The time response of the RMS detector is determined by the capacitor attached to CT (C4, 10 f) and
the size of the current in pin IT (determined by R7,
2 M and the negative power supply, 15V). Since
the voltage at IT is approximately 0 V, the circuit of
Figure 12 produces 7.5 A in IT. The current in IT is
mirrored with a gain of 1.1 to the CT pin, where it is
available to discharge the timing capacitor (C4). The
combination produces a log filter with time constant
equal to approximately 0.026 CT/IT (~35 ms in the
circuit shown).
The waveform at CT will follow the logged
(decibel) value of the input signal envelope, plus a dc
offset of about 1.3 V (2 VBE). This allows a polarized
capacitor to be used for the timing capacitor, usually
an electrolytic. The capacitor used should be a lowleakage type in order not to add significantly to the
timing current.
The output stage of the RMS detector serves to
buffer the voltage at CT and remove the 1.3 V dc offset, resulting in an output centered around 0 V for
input signals of about 85 mV. The output voltage
increases 6.5 mV for every 1 dB increase in input signal level. This relationship holds over more than a
60 dB range in input currents.
Control Path
A compressor/limiter is intended to reduce its
gain as signals rise above a threshold. The output of
the RMS detector represents the input signal level
over a wide range of levels, but compression only
occurs when the level is above the threshold. OA1 is
configured as a variable threshold detector to block
envelope information for low-level signals, passing
only information for signals above threshold.
OA1 is an inverting stage with gain of 2 above
threshold and 0 below threshold. Neglecting the
action of the THRESHOLD control (R12) and its associated resistors (R11 and R10), positive signals from
the RMS detector output drive the output of OA1
negative. This forward biases CR2, closing the feedback loop such that the junction of R9 and CR2 (the
R 16
Page 10 of 12
R 16
Overall Result
The resulting compressor circuit provides hardknee compression above threshold with three essential user-adjustable controls. The threshold of
compression may be varied over a 30 dB range
from about 46 dBV to +14 dBV. The compression
ratio may be varied from 1:1 (no compression) to
THAT4301Analog Engine
IC Dynamics Processor
Page 11 of 12
Package Characteristics
Parameter
Symbol
JA
Thermal Resistance
Conditions
Typ
20 pin DIP
65
C/W
JA
Thermal Resistance
Units
20 pin SO
70
C/W
MSL
20
11
C
1
10
E1
A
D
O
G
c
A2
SEATING
PLANE
L1
A1
b x 20
SYM
A
B
C
D
E
F
G
H
J
L
N
O
P
Inches
MM
Min
Max
1.025
1.035
0.300 BSC
0.245
0.255
0.300
0.325
0.100 BSC
0.014
0.022
0.005
0.045
0.070
0.320
0.380
0.125
0.135
0.015
0.025
0.115
0.150
0.008
0.012
Min
Max
26.04
26.29
7.62 BSC
6.23
6.48
7.62
8.26
2.54 BSC
0.36
0.56
0.12
1.14
1.78
8.12
9.64
3.18
3.43
0.38
0.64
2.92
3.81
0.20
0.30
Pin Name
RMS IN
IT
No Internal Connection
RMS OUT
CT
OA2 -IN
OA2 OUT
OA2 +IN
GND
VEE
Pin Number
1
2
3
4
5
6
7
8
9
10
SYM
A
A1
A2
b
c
D
E1
E
e
L
L1
Inches
Min
Max
0.096
0.104
0.005
0.012
0.089
0.096
0.012
0.020
0.008
0.030
0.502
0.510
0.291
0.299
0.396
0.416
0.050 TYP
0.016
0.050
0.051
0.059
0
8
MM
Min
Max
2.43
2.64
0.13
0.30
2.26
2.44
0.30
0.50
0.20
0.76
12.75
12.95
7.39
7.60
10.05
10.57
1.27 TYP
0.41
1.27
1.29
1.50
0
8
Pin Name
OA1 +IN
OA1 -IN
OA1 OUT
VCA IN
ECEC+
SYM
VCA OUT
OA3 OUT
VCC
Pin Number
20
19
18
17
16
15
14
13
12
11
Page 12 of 12
THAT4301Analog Engine
IC Dynamics Processor
Revision History
Revision
ECO
Date
Changes
00
6/24/1999
01
7/5/2006
02
8/24/2007
03
1/26/2009
04
2748
12/10/2012
05
2849
1/28/2014
06
2855
3/10/2014
11
07
2866
3/31/2014
08
2867
4/1/2014
Removed 'A' version, Chg'd lead finish, added 20p SO Wide pkg
Initial release.
Added C9 to Figure 14; Moved order information chart.
Page
1, 9
2, 3, 5
1, 5, 11