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Lec31 LogicGateCMOS
Lec31 LogicGateCMOS
SYSTEMS
Electronic & Communication Engineering
Danang University of Technology
Voltage Levels
Voltage
VDD
Logic value 1
V1,min
Undefined
V 0,max
Logic value 0
V SS (Gnd)
- Positive/Negative logic
system
-V0,max: max. voltage level that
a logic circuit recognizes as low
- V1,min: min. voltage level that a
logic circuit recognizes as high
- Exact V0,max ,V1,min values
depend on used technology,
normally 40% VDD and 60% VDD
x = "low"
x = "high"
Gate
Source
Drain
Substrate (Body)
VS
VD
NMOS
- Most popular used transistor
is MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to Gnd for NMOS
- No physical difference
between source and drain
terminals
- By convention, the source
terminal is the node with lower
voltage for NMOS
Remarks
- Silicon is an electrical semiconductor.
- A transistor is fabricated by creating areas in the silicon
substrate that have an excess of either positive or negative
electrical charge.
- The gate terminal is made of poly-silicon which is
preferable to metal as it can be fabricated with extremely
small dimensions.
- The gate is electrically isolated from the rest of transistor by
a layer of SiO2.
- Transistors operation is governed by electrical fields caused
by voltages applied to its terminal
NMOS off
V
= 0V
SiO 2
= 0V
V
++++++ ++++
++++++
++++++
+++++++++
++++++
++++++
++++++
++++++
++++++
++++++
+++++++++++
+++++++++++
+++++++++ Substrate (type p) +++++++++
Source (type n)
Drain (type n)
VDD
NMOS on
VG = 5 V
SiO2
VS = 0 V
VD = 0 V
++++++ ++++
+++ ++++++
++++++
++++++
+++++++++++ +++++++++++++++++
+++++++++ ++ +++++++ ++++++++++
Channel (type n)
(b) When VGS = 5 V, the transistor is on
Channel
-The positive voltage on the gate attracts free electrons
existing in the type-n source and drain terminals & other
areas of the transistor towards the gate. Because of SiO2
layer, electrons gather in region of the substrate between
source & drain terminals, which results into channel
connecting source & drain.
+
W1
W2
L
L
(a) Small transistor
x = "high"
x = "low"
Gate
Drain
Source
Substrate (Body)
VDD
VG
VS
VD
PMOS
- Most popular used transistor
is MOSFET: NMOS & PMOS
- 4 electrical terminals. In logic
circuits the substrate terminal is
connected to to VDD for PMOS
- No physical difference
between source and drain
terminals
- By convention, the source
terminal is the node with higher
voltage for PMOS
VD
VD = 0 V
Operations
VD
VG
VS = 0 V
Closed switch
whenVG = VDD
Open switch
whenVG = 0 V
VS = VDD
VDD
VDD
VG
VD
VD
Open switch
whenVG = VDD
VD = VDD
Closed switch
whenVG = 0 V
VDD
5V
NMOS NOT
+
Vf
Vx
Vf
Vx
VDD
NMOS NAND
- Series connection of NMOS to
create the logic AND function
- VX1= VX2=5V, tr is turned off -> Vf=5V
- When VX=5V, trs are turned
on, their drains are pulled down
to Gnd --> Vf will be closed to
0V
Vf
Vx
Vx
(a) Circuit
x1
x2
x1 x2
0
0
1
1
1
1
1
0
0
1
0
1
x1
x2
V DD
NMOS NOR
x1 x2
Vf
Vx
Vx
0
0
1
1
x2
f
1
0
0
0
(a) Circuit
x1
0
1
0
1
- Parallel connection of
NMOS to create the logic
NOR function
- Either VX1= 5V or VX2=5V,
Vf will be closed to 0V
- If both Vx =0V --> Vf will
be pulled up to 5V
x1
x2
VDD
VDD
NMOS AND
- AND realization by following a
NAND gate with an Inverter
Vf
A
Vx1
Vx2
x2
0
0
1
1
0
0
0
1
0
1
0
1
(a) Circuit
x1
x1 x2
x1
x2
V DD
NMOS OR
VDD
Vf
Vx
Vx
(a) Circuit
x1
x2
x1 x2
0
0
1
1
0
1
1
1
0
1
0
1
- OR realization by
following a NOR gate with
an Inverter
x1
x2
PDN Structure
VDD
Pull-down network
(PDN)
n
PDN-PUN
CMOS NOT
VDD
R
Vf
VDD
Vx
T1
Vx
(a) Circuit
T1 T2
0
1
on off
off on
1
0
Vx
T3
T4
(a) Circuit
x1 x2
T1 T2 T3 T4
0
1
0
1
on on off off
on off off on
off on on off
1
1
1
0
0
0
1
1
off off on on
CMOS NOR
VDD
f = x1 + x2 = x1 x2
Vx
T1
Vx
T2
Vf
T3
! f = x1 + x2
(a) Circuit
T4
x1 x2
T1 T2 T3 T4
0
1
0
1
on on off off
on off off on
off on on off
1
0
0
0
0
0
1
1
off off on on
CMOS AND
V DD
VDD
Vf
Vx
Vx
VDD
Example 3.1
Consider the following function:
f = x1 + x2 x3
Since all variables appear in their
complemented form, we can directly
derive the PUN: 1 PMOS tr. controlled by
x1 in parallel with a series combination of
2 PMOS trs. controlled by x2 & x3
f = x1 + x2 x3 = x1 ( x2 + x3 )
Vf
Vx
Vx
Vx
Example 3.2
f = x1 + x2 + x3 x4
Build a circuit using CMOS to implement this functionality
VDD
Example 3.2
Consider the following function :
f = x1 + x2 + x3 x4
Vf
Vx
Vx
f = x1 + x2 + x3 x4
Vx
Vx
Voltage Levels
V DD
Vf
Vx
Vx
Vx Vx
1
L L
L H
H L
H H
(a) Circuit
Vf
H
H
H
L
x1 x2
0
0
1
1
1
1
1
0
0
1
0
1
Voltage Levels
x1
x2
1
1
0
0
0
0
0
1
1
0
1
0
x1
x2
Circuit Topology
Describes the input and output structure of the device
Three general categories
TTL - Transistor Transistor Logic
Bipolar transistors on input and output
Output section looks like described circuit
Referred to as totem pole output
ECL - Emitter Coupled Logic
Bipolar
Logic done in emitter circuitry rather than
collector
High speed
MOS - Metal Oxide Semiconductors
MOS transistors on input and output
SSI Circuits
Lets look now at some SSI circuits
Referred to as glue logic in todays design
Most designs highly integrated
VLSI
Gate arrays
Array logics
Glue logic provides means of interconnection
SSI circuits fall into 3 general categories
Basic gates
Simple combinations of gates
Buffer and driver gates
Basic Gates
These implement fundamental logic functions
AND OR
NAND NOR
NOT
VDD
Gnd
A 7400-series chip.
DD
7404
7408
7432
x
x2
3
x
f
An implementation of f = x1 x2 + x2 x3
Pin 13
Pin 15
Pin 17
Pin 5
Pin 7
Pin 9
Pin 18
Pin 8
Pin 11
Pin 16
Pin 6
Pin 3
Pin 14
Pin 4
Pin 19
Pin 12
Pin 2
Pin 1
Buffer
VDD
Vx
Vf
f
(b) Graphical symbol
A non-inverting buffer
Inverting Buffer
-Inverting buffer produces the same output as an inverter but
is built with relatively large transistors
- As shown in figure, for large values of n an inverting buffer
could be used for the inverter labeled as N1
N1
x
To inputs of
n other inverters
n
e= 0
x
e
x
e= 1
x
e x
0
0
1
1
Z
Z
0
1
0
1
0
1
(a)
(b)
x
(c)
x
(d)
Multiplexer
From Truth Table, derive canonical SOP form
) (
x1
s
x2
s
(a) Circuit
0
1
Z
x
s= 0
x
e
s
f=Z
s= 1
x
f=x
(c) Equivalent circuit
f
s
(e) Implementation
0
1
Z
x
e x
0
0
1
1
Z
Z
0
1
0
1
0
1
x1
s
x2
XOR Gate
x1
x1 x2
x2
0
0
1
1
f = x1 x2
f = x1 x2
0
1
0
1
Truth table
CMOS implementation
0
1
1
0
x 1 x2
0
0
1
1
0
1
0
1
f = x 1 x2
0
1
1
0
x1
f = x1 x2
x2
x1
x2
f = x1 x2
PLD
x1 x2
x3
NOR plane
VDD
VDD
VDD
f1
f2
S1
VDD
S2
VDD
S3
NOR plane
Inputs
(logic variables)
Logic gates
and
programmable
switches
Outputs
(logic functions)
x1 x2
xn
PLA
-Be realized in Sum-Of-Products form
- Each Pk is configured to implement
any AND function of xi
- Each fm is configured to implement
any OR function of Pk
Input buffers
and
inverters
x1 x1
xn xn
P1
OR plane
AND plane
Pk
f1
fm
x1
x2
x3
f1 = x1 x2 + x1 x3 + x1 x2 x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
f1
f2
x1
x2
x3
OR plane
P1
P2
P3
P4
AND plane
f1
f2
x1
x2
x3
PAL
P1
f1
P2
P3
f2
P4
AND plane
Select
Enable
f1
Flip-flop
D
Clock
To AND plane
PAL-like
block
PAL-like
block
I/O block
I/O block
CPLD
PAL-like
block
PAL-like
block
I/O block
I/O block
Interconnection wires
CPLD Section
PAL-like block (details not shown)
PAL-like block
D Q
D Q
D Q
- A CPLD consists of
many PAL-like blocks
interconnected via
switches
-A commercial CPLD has
2-100 PAL-like blocks
- Each PAL-l.b. has 3
macrocells.
- Each macrocell some
OR gates .
To computer
Printed
circuit board
FPGA
-FPGA differ from CPLD (no
AND OR gates)
- Use logic blocks to
implement required functions
- 3 main resources: logic
blocks, I/O blocks,
interconnect. wires &
switches
- LB: 2-d array
- Interconnection: h. & v.
routing channels
A field-programmable gate array (FPGA).
Gate Multiplexer
From Truth Table, derive canonical SOP form
) (
LUT Multiplexer
x1
0/1
0/1
0/1
0/1
x2
(a) Circuit for a two-input LUT
x1 x2
f1
0
0
1
1
1
0
0
1
0
1
0
1
(b) f 1 = x 1 x 2 + x 1 x 2
x1
1
0
f1
0
1
x2
(c) Storage cell contents in the LUT
Example
x1
x2
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
x3
A three-input LUT.
Out
Flip-flop
In1
In2
LUT
In3
Clock
LUT in FPGA
- Two-input LUTs
- Four wires in each
routing channel
- Fig. shows
programmed states of
the L.Bs. & switches
+ Blue switches: ON
+ Black switches: OFF
x3
x1
x2
x1 0
0
0
x2
1
f1
x2 0
1
0
x3
0
f2
f1 0
1
1
f2
1
f1 = x1 x2
f 2 = x2 x3
f = f1 + f 2
Remarks
- Each logic function must be small enough to fit within a single L.B.
- Users circuit is automatically translated into the required form by
using CAD tools
- When a circuit is implemented in an FPGA, the L.B. are
programmed to realize the necessary functions, and the routing
channels are programmed to make the required interconnections
between L.Bs.
- The storage cells in the LUTs in an FPGA are volatile: they lose their
stored values whenever the power supply for the chip is turned off.
- Instead of being re-programmed every time, a small memory chip
that holds its data permanently, called PROM, is included on the
circuit board that houses the FPGA. The storage contents are
automatically loaded from PROM to FPGA when power is applied to
the chips
Custom Chip
- Provide largest no. of logic gates, highest circuit speed, lowest power
- Whereas a PLD is prefabricated, a custom chip is created from scratch
- The process of defining where trs. & wires are placed on chip is called CHIP LAYOUT
- A typical chip has many long rows of logic gates with a large number of wires between rows
+ Blue wire on one layer/ Black wire on another layer
+ Blue square: hard-wired connection (via) between layers
x1
f2
x2
x3
f1
f1
x1
x2
x3