What is a FET?

The acronym FET stands for field effect transistor. It is a three-terminal unipolar solidstate device in which current is controlled by an electric field inside a semiconductor
material.
In other words;
The current controlled mechanism (drain current) is based on electric field established by the
voltage applied to the control terminal (gate).
Field-effect transistors (FETs) are the simplest form of transistor
widely used in both analogue and digital applications
they are characterised by a very high input resistance and small physical size,
and they can be used to form circuits with a low power consumption
they are widely used in very large-scale integration
Broadly speaking, there are two types of FETs :

JFET
PHYSICAL STRUCTURE OF JFET
As shown in Fig.1, it can be fabricated with either an N-channel or P-channel though Nchannel is generally preferred (commonly used).
Following FET notation is worth remembering:
1. Source. It is the terminal through which majority carriers enter the bar. Since carriers come
from it, it is called the source.

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

2. Drain. It is the terminal through which majority carriers leave the bar i.e. they are drained
out from this terminal. The drain-tosource voltage V DS drives the drain current ID.
3. Gate. These are two internally-connected heavily-doped impurity regions which form two
P-N junctions.
The gate-source voltage VGS reverse biases the gates.
4. Channel. It is the space between two gates through which majority carriers pass from
source-to-drain when VDS is applied.

Fig 1: Physical Structure

JFET OPERATION
While discussing the theory of operation of a JFET, it should be kept in mind that:
1. Gates are always reversed-biased. Hence, gate current IG is practically zero.
2. The source terminal is always connected to that end of the drain supply which
provides the necessary charge carriers. In an N-channel JFET, source terminal S is
connected to the negative end of the drain voltage supply (for obtaining electrons).
Let us now consider an N-channel JFET and discuss its working when either VGS or VDS or
both are changed. REMEMBER ITS VOLTAGE CONTROLLED DEVICE!!!
(i) When VGS = 0 and VDS = 0. (Imagine the circuit diagram)
In this case, drain current ID = 0, because VDS = 0. NO ELECTRIC FIELD!
(ii) When VGS = 0 and VDS is increased from zero. (Imagine the circuit diagram)
For this purpose, the JFET is connected to the VDD supply as shown in Fig. 2

VDS

Fig 2: Configuration/Circuit Diagram

The depletion region/width is increases as electrons from nchannel combine with

holes from p-gate.
Increasing the depletion region, decreases the size of the n-channel which increases
the resistance of the n-channel.
Even though the n-channel resistance is increasing, the current (ID) from drain to
source through the n-channel is increasing. This is because VDS is increasing.

If VDS is further increased to a more positive voltage, then the depletion zone gets so large
that it pinches off the n-channel AT DRAIN. The Pinch off voltage is known as VP. If VDS
continues to increase, the flowing current becomes saturated. Be carefully noted that pinchoff DOES NOT mean current-off . In fact, ID is saturated, denoted as IDSS. Increasing
more in VDS will cause the device damage.
NOTE: Drawing error:
Depletion Width should not
touch each other. If not,
ID=0.It should be narrowed. So
that ID will remain constant.

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

FIG: I-V Drain Characteristics

(iii) When VDS = 0 and VGS is decreased from zero.

(Imagine the circuit diagram)

As VGS is made more and more negative, the gate reverse bias increases which increases the
thickness of the depletion regions. ID decreases till it is reduced to zero for a certain value of
VGS called VGS(off).

A Pchannel JFET operates exactly in the same manner as an N-channel JFET except that
current carriers are holes and polarities of both VDD and VGS are reversed.
(Assigment)

JFET Transfer (Characteristics) Curve

When VGS is set to different values, the relationship between VDS and ID develops a family of
characteristic curves for the device.

Fig. 3.1 Transfer and Output (Drain) Characteristics

Fig. 3.1 shows a family of ID versus VDS curves for different values of VGS. A plot of VGS
to ID is called the transfer curve or transconductance curve. The transfer curve is a plot of the
output current (ID) to the input voltage (VGS). It is seen that as the negative gate bias voltage
is increased pinch off voltage is reached at a lower value of ID than when VGS = 0.

Summary

Drain current in this region is given by Shockley's equation

The JFET

A plot of VGS to ID is called the transfer or transconductance

It is the normal
thethe
JFET
when used
as an amplifier.
urve. The transfer
curveoperating
is a is region
a plotofof
output
current
ID) to the input voltage (VGS).
I
D

he transfer curve is based on the

quation

V
I D I DSS 1 GS
V

GS(off)

IDSS

y substitution, you can find other

oints on the curve for plotting the
niversal curve.

IDSS
2

IDSS
4

VGS

VGS(off)

0.3 VGS(off)
0.5 VGS(off)

Fig 4 : JFET Universal Transfer Characteristic

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

Example:
A certain 2N5458 JFET has IDSS = 6.0 mA and VGS(off) = 3.5 V.
(a) Show the values of the these end points on the transfer curve.
(b) Show the point for the case when ID = 3.0 mA.

Small Signal JFET Parameters

JFET has certain parameters which determine its performance in a circuit. The main
parameters of a JFET are (i) a.c. drain resistance (ii) transconductance (iii) amplification
factor.
(i) AC Drain Resistance, rd
It is the ac resistance between drain and source terminals when JFET is operating in the
pinch-off region. It is given by:

Referring to the Output characteristics of a JFET in Fig 3.1, it is clear that above the pinch off
voltage, the change in ID is small for a change in VDS because the curve is almost flat.
Since rd is usually the output resistance of a JFET, it may also be expressed as an output
admittance yos. Obviously, yos = 1/rd. It has a very high value.

(ii) Transconductance, gm
The relationship of VGS(input) to ID(output) is called transconductance.
It is the ratio of change in drain current ( ID) to the change in gate-source voltage ( VGS)
at constant drain-source voltage i.e.

at constant VDS and the unit is Siemens (S) or A/V.

OR
When plotting, it is simply the slope of transfer characteristic.

The transconductance gm of a JFET is an important parameter because it is a major factor

in determining the voltage gain of JFET amplifiers. However, the transfer characteristic
curve for a JFET is nonlinear so that the value of gm depends upon the location on the curve.
Thus the value of gm at any point in curve will be different. Luckily, there is following
equation to determine the value of gm at a specified value of VGS

Where,
gm = value of transconductance at any
point on the transfer characteristic curve
gmo = value of
transconductance(maximum) at VGS = 0
Vp= VGS(off)

Example:

Answer : i)3.87 A , ii) 5.8mS, iii) 3.87mS

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

JFET BIASING
A JFET may be biased by using either
1. Fixed biased / Biased by DC Source circuit. Less prefer cos batteries are costly and require frequent replacement.
2. Self Biased Circuit
3. Voltage Divider Biased Circuit.
1. Fixed biased / Biased by DC Source circuit.

2. Self Biased Circuit

Example :

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

Example 2

3. Voltage Divider Biased Circuit.

JFET Connections/ Practical JFET Amplifier

Accordingly, a JFET Amplifier can be connected in a circuit in the following three ways :
(i) Common source connection
(ii) Common gate connection
(iii) Common drain connection
(i) Common source connection
The common source connection is the most widely used arrangement. It is because this
connection provides high input impedance, good voltage gain and a moderate output
impedance. However, the circuit produces a phase reversal i.e., output signal is 180 out of
phase with the input signal.

COMMON SOURCE JFET AMPLIFIER (Voltage divider biased circuit)

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP

A simple way to analyse the action of a JFET amplifier is to split the circuit into two parts
1. d.c. equivalent circuit and
2. a.c. equivalent circuit.
1. The d.c. equivalent circuit will determine the operating point (d.c. bias levels) for the
circuit:
Steps
(i) Reduce all a.c. sources to zero.
(ii) Open all the capacitors.

Fig: d.c. Equivalent Circuit of JFET

2. a.c. equivalent circuit determines the output voltage and hence voltage gain of the circuit.
Steps
(i) Reduce all d.c. sources to zero (i.e. VDD = 0).
(ii) Short all the capacitors.

Fig 50: a.c Equivalent Circuit of JFET

Fig. 51: a.c Equivalent Circuit of JFET

The a.c. equivalent circuit of JFET amplifier is redrawn as Fig. 51 for facility of reference.
Note that R1 || R2 and can be replaced by a single resistance RT. Similarly, RD || RL and can be
replaced by a single resistance RAC (= total a.c. drain resistance). The a.c. equivalent circuit
shown in Fig. 50 then reduces to the one shown in Fig. 51
We now find the expression for voltage gain of this amplifier. Referring to Fig. 51
output voltage (vout) is given by ;

vout = id RAC

(i)

Remember that we define gm as :

Source Resistor, (Rs) is bypassed

(neglecting RS) with CS Capacitor
IF the JFET amplifier with source resistor RS is unbypassed (without neglecting RS).This
means that a.c. signal will not be bypassed by the capacitor CS.
And the voltage gain will be:

Steven Taniselass : SEM2 A.S. 2013/14 : School of Microelectronic Eng. UniMAP