Professional Documents
Culture Documents
Features Description: 12-Bit, Multiplying D/A Converter
Features Description: 12-Bit, Multiplying D/A Converter
Features Description: 12-Bit, Multiplying D/A Converter
August 1997
Features
Description
Pretrimmed Gain
Low Gain and Linearity Tempcos
TTL/CMOS Compatible
+5V to +15V Supply Range
20mW Low Power Dissipation
Current Settling Time 1s to 0.01% of FSR
Ordering Information
NONLINEARITY
AD7541JN
0.02% (11-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541KN
0.01% (12-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541LN
0 to 70
18 Ld PDIP
E18.3
PART NUMBER
Pinout
PACKAGE
PKG. NO.
VREF IN
IOUT1 1
18 RFEEDBACK
IOUT2 2
17 VREF IN
GND 3
BIT 1 (MSB) 4
10k
10k
20k
20k
10k
10k
(17)
20k
20k
20k
20k
(3)
16 V+
15 BIT 12 (LSB)
BIT 2 5
14 BIT 11
BIT 3 6
13 BIT 10
BIT 4 7
12 BIT 9
BIT 5 8
11 BIT 8
BIT 6 9
10 BIT 7
SPDT
NMOS
SWITCHES
IOUT2 (2)
IOUT1 (1)
10k
MSB
(4)
BIT 2
(5)
BIT 3
(6)
RFEEDBACK
(18)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
10-9
File Number
3107.1
AD7541
Absolute Maximum Ratings
Thermal Information
Operating Conditions
Temperature Range
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified
TA = 25oC
PARAMETER
TEST CONDITIONS
TA MIN-MAX
MIN
TYP
MAX
MIN
MAX
UNITS
12
12
Bits
0.024
0.024
% of FSR
0.012
0.012
% of FSR
0.012
0.012
% of FSR
SYSTEM PERFORMANCE
Resolution
Nonlinearity
A, S, J
B, T, K
L
Monotonicity
Guaranteed
Gain Error
0.3
0.4
% of FSR
VOUT1 = VOUT2 = 0
50
200
nA
V+ = 14.5V to 15.5V
See Figure 5 (Note 5)
0.005
0.01
% of FSR/% of
V+
To 0.1% of FSR
See Figure 9 (Note 6)
Feedthrough Error
mVP-P
10
20
20
DYNAMIC CHARACTERISTICS
REFERENCE INPUTS
Input Resistance
ANALOG OUTPUT
Voltage Compliance
Output Capacitance
-100mV to V+
-
200
200
pF
60
60
pF
60
60
pF
200
200
pF
See Figure 6
DIGITAL INPUTS
Low State Threshold, VIL
(Notes 2, 6)
10-10
0.8
0.8
2.4
2.4
AD7541
Electrical Specifications
V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, TA = 25oC, Unless Otherwise Specified (Continued)
TA = 25oC
PARAMETER
TEST CONDITIONS
Input Current
VIN = 0V or V+ (Note 6)
Input Coding
Input Capacitance
(Note 6)
TA MIN-MAX
MIN
TYP
MAX
MIN
MAX
UNITS
pF
Binary/Offset Binary
-
+5 to +16
I+
2.0
2.5
mA
20
mW
NOTES:
2. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
3. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and RFEEDBACK .
4.
5.
6.
7.
Full scale range (FSR) is 10V for unipolar and 10V for bipolar modes.
Using internal feedback resistor, RFEEDBACK .
Guaranteed by design or characterization and not production tested.
Accuracy not guaranteed unless outputs at ground potential.
Definition of Terms
Detailed Description
10-11
AD7541
V+
+15V
1 3
4
VREF
10V
TO LADDER
BIT 1 (MSB)
8
TTL/CMOS
INPUT
16 RFEEDBACK
18
IOUT1
5 AD7541 1
CR1
I
15 3
2 OUT2
17
4
DIGITAL
INPUT
BIT 12 (LSB)
IOUT2 IOUT1
6
+
VOUT
A
GND
Typical Applications
General Recommendations
Gain Adjustment
1. Connect all digital inputs to VDD .
2. Monitor VOUT for a -VREF (11/212) reading.
3. To increase VOUT , connect a series resistor, (0 to
250), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT , connect a series resistor, (0 to 250),
between the reference voltage and the VREF terminal.
The V+ (pin 18) power supply should have a low noise level
and should not have any transients exceeding +17V.
Unused digital inputs must be connected to GND or VDD for
proper operation.
A high value resistor (~1M) can be used to prevent static
charge accumulation, when the inputs are open-circuited for
any reason.
When gain adjustment is required, low tempco
(approximately 50ppm/oC) resistors or trim-pots should be
selected.
ANALOG OUTPUT
111111111111
-VREF (1 - 1/212)
100000000001
100000000000
-VREF/2
011111111111
000000000001
-VREF (1/212)
000000000000
10-12
AD7541
A Logic 1 input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A Logic
0 input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at
IOUT1 output sums the two currents. This configuration doubles the output range of the DAC. The difference current
resulting at zero offset binary code, (MSB = Logic 1, All
other bits = Logic 0), is corrected by using an external
resistive divider, from VREF to IOUT2 .
Gain Adjustment
1. Connect all digital inputs to VDD .
2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
3. To increase VOUT , connect a series resistor, (0 to
250), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT , connect a series resistor, (0 to 250),
between the reference voltage and the VREF terminal.
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Set R4 to zero.
3. Connect all digital inputs to Logic 1.
4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V
0.1mV at IOUT2 amplifier output.
ANALOG OUTPUT
111111111111
-VREF (1 - 1/211)
100000000001
-VREF (1/211)
100000000000
011111111111
VREF (1/211)
000000000001
VREF (1 - 1/211)
000000000000
VREF
10V
VREF
+15V
17
BIT 1 (MSB)
16
18
1
IOUT1
6
+
DIGITAL
INPUT
A1
VOUT
AD7541
R1 10K
R2 10K
R5 10K
15
BIT 12 (LSB)
2
IOUT2
6
+
GND
R3
390K
A2
10-13
R4
500
AD7541
Test Circuits
+15V
VREF
17
16
18
BIT 1 (MSB)
12-BIT
BINARY
COUNTER
RFEEDBACK
IOUT1
AD7541
AD7541
15
BIT 12
(LSB)
HA2600
+
10K
0.01%
IOUT2
1M
GND
CLOCK
VREF
HA2600
+
BIT 1
(MSB)
10K 0.01%
LINEARITY
ERROR X 100
14-BIT
REFERENCE
DAC
BIT 12
BIT 13
BIT 14
+15V
UNGROUNDED
SINE WAVE
GENERATION
40Hz 1.0VP-P
VREF
500K
+10V
5K 0.01%
BIT 1 (MSB)
BIT 12
(LSB)
HA2600
+
17
4
16
RFEEDBACK 5K 0.01%
18
IOUT1
5
1
AD7541
HA2600
IOUT2
+
15 3 2
VERROR X 100
GND
100
15F
17
4
5
16
2
AD7541
101ALN
IOUT1
15
F = 1KHz
BW = 1Hz
10K
IOUT2
+
50K
1K
-50V
0.1F
10-14
VOUT
QUAN
TECH
MODEL
134D
WAVE
ANALYZER
AD7541
Test Circuits
(Continued)
+15V
NC
BIT 1 (MSB)
+15V
17
16
18
4
5
AD7541
1
17
BIT 12 (LSB)
+15V
BIT 1 (MSB)
NC
1K
100mVP-P
1MHz
SCOPE
BIT 12 (LSB)
17
16
4
18
5
AD7541
IOUT1 3
1
IOUT2
HA2600
15 3
2
2
6
VOUT
GND
+10V
+15V
VREF
EXTRAPOLATE
BIT 1 (MSB)
+5V
0V
DIGITAL INPUT
17
16
4
5
AD7541
1
15
BIT 12 (LSB)
OSCILLOSCOPE
+100mV
IOUT2
3t: 5% SETTLING
9t: 0.01% SETTLING
100
GND
Dynamic Performance
code. These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.
+15V
VREF +10V
BIT 1 (MSB)
BIT 2
BIT 12 (LSB)
17
16
18
4
5
AD7541
1
15
RFEEDBACK
IOUT1
IOUT2
CC
A
+
VOUT
GND
10-15
AD7541
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
10-16
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029