APPLICATION SEEKING GRANT-IN-AID FROM DRDO FOR ORGANISING

A WORKSHOP EVENT
1. Name and address of Event Organiser (chairman/secretary)
proposing event
1. Dr.T.Ravichandran,
Principal,
Hindusthan Institute of Technology,
Coimbatore-32.

For DRDO use

Date
Received
ER&IPR
File No.

2. Dr.B.Paulchamy,
Prof & Head,
Department of ECE,
Hindusthan Institute of Technology,
Othakkalmandapam (Post),Pollachi Main Road,
Coimbatore-641 032, Tamil Nadu, INDIA.
2. Name of Convenor (1) above
1. Dr.B.Paulchamy,
Prof & Head,
Department of ECE
Hindusthan Institute of Technology,
Othakkalmandapam (Post),
Coimbatore-641 032,
Tamil Nadu, INDIA.
2. Mr.R.Saravanakumar,
AP/ECE,
Department of ECE
Hindusthan Institute of Technology,
Othakkalmandapam (Post),
Coimbatore-641 032,
Tamil Nadu, INDIA.

Email
balurjp@yahoo.co.in

Tel.
Mobile:
+91
9629183233

Email
ssaceet_blossom@yahoo
.co.in

Tel.
Mobile:
+91
9894951308

3. Title of event (attach event circular/brochure)

Two days National Level Workshop on
XILINX SYSTEM GENERATOR FOR DSP APPLICATIONS
(Brochure Attached)
4. Venue of event:
Hindusthan Institute of Technology,
Othakkalmandapam (Post),Pollachi Main Road,
Coimbatore-641 032, Tamil Nadu, INDIA.
Phone : +91 422 - 2610788
Fax
: +91 422 - 2610844
e-mail : hitinfo@hindusthan.net | hit.office@hindusthan.net |
hitoffice2011@gmail.com
5. Duration of event (days)
Two days

6.

Beginning date
Nov 13 & 14 2014

Fax
: +91
422 - 2610844

Fax
: +91
422 - 2610844

7. Topics to be covered during event:

Introduction to reconfigurable hardware platform of Field-programmable gate arrays (FPGA).
Complete introduction on VLSI Design on Field-programmable gate arrays (FPGA) with hands-on
session
Complete introduction on DSP design flow on field programmable gate array with hands-on session
Implementation and verification of designs in VLSI Design by participants on advanced FPGA
boards.
Case studies and interactive discussion on the implementation of Image Processing through FPGA.
8. Relevance of (7) to Armed Services or DRDO:
GOAL: This workshop will provide an introduction to scientists and engineers in VLSI Design. The
goal of the workshop is to take a researcher through the various aspects and steps in their research area.
The workshop will consist of lectures, hands on session and interactive sessions. The workshop mainly
concentrates on the various research methodologies in Field-programmable gate arrays (FPGA).
Participants will work on several exercises individually and in teams. This workshop will provide
platform for initiating the research work in this area
OBJECTIVE: Field-programmable gate arrays (FPGA) is the right choice to design a digital system
design because FPGA gives wide applications in Rresearch and Development phase and rapid prototype
of new design. FPGAs are rapidly becoming an essential flexible integrated circuit building block of
choice for many commercial and defence systems. As their performance, complexity, cost, and capacity
have improved, these devices have begun to challenge the use of Application Specific Integrated Circuits
(ASICs) in many electronic systems. In some applications the ability to incorporate built-in core
functionality such as those of microprocessors or digital signal processing (DSPs) has led to preferred
system level solutions over traditional design approaches. Military systems, however, differ from their
commercial counterparts in terms of their production volume, radiation tolerance, assured secure
functionality, and system lifetimes.
Processor based embedded system is quite effective for small and medium application. For
medium and high- end embedded systems design, FPGAs and ASICs are the right choice. Further FPGA
implementation is cost effective for low volume application. FPGAs are drawing ever increasing interest
from designers of embedded wireless communications systems. In the near future FPGAs may be
expected to be cost effective even for small end applications. The development tools that will convert
ideas into reality of a working system for these categories are Verilog HDL / VHDL compiler, simulation,
synthesis, place & route tools and programmers. .
9. Name DRDO Labs/Estts which will be
actively associated with the event
10. DRDO establishments which have
confirmed participation
11. Estimated number (in words) of
participants
80 Nos (Eighty Numbers)

None
None
National

75 Nos

International
05 Nos

12. Proposed Registration

Fee for each participant

National

(i) Student
(ii) Faculty
(iii) Research Scholars

International

:Rs.250 (Two Hundred and fifty)

:Rs.400 (Four Hundred)
:Rs. 400 (Four Hundred)

$ 100

13. Estimated expenditure on event (Give break-up overleaf)

Rs.
14. Money requested/received from other organizations (Give break-up overleaf)
Rs.
15. Previous conference grant received from
Rupees per grant
DRDO during last 02 years
Thirty Thousand rupees only
YES

1,20,000.00
45,000.00

16. Grant-in-Aid now requested from DRDO: Rupees (in words)

Rs.75,000 (Seventy Five Thousands Only)
17. The Cheque to be issued in favour of :

The Principal,
Hindusthan Institute of Technology,Coimbatore-32
We have read, understood, and shall comply with the Instructions and Conditions overleaf. Certified also
that monies will not be sought from any other DRDO Laboratory/ Project/Research Board.

Date:

Signature of Convenor

Name & Signature of Chairman

of Organising Committee

Send completed form to:

Amount approved
Signature of approving Competent Authority

use OnlyDRDO

Director, Directorate of Extramural Research & Intellectual Property Rights, DRDO, Room No. 348, DRDO Bhawan,
Rajaji Marg, New Delhi 110105.. Fax : 011 23017582 Phone: 23007350 erip_er@hqr.drdo.in

13. Estimated Expenditure

Rupees

14. Funds requested/received from other

organizations named below

(i) Hiring of covered space

NIL

(i)

(ii) Hiring of facilities like

public address system, etc.

NIL

(iii) Travelling charges for local

movement and outstation
experts/invited speakers

Rupees

(ii)
Rs.30,000

(iv) Honoraria

Rs.10,000

(v) Accommodation and

catering

Rs.35,000

(vi) Stationery, folders,

secretarial assistance,
postage, etc.

Rs.15000

(vii) Printing of circulars,

proceedings, abstracts, etc.

Rs.15,000

(viii) Other expenses(TA/DA for

invited Speakers)

Rs.15,000

(iii)
_

Total Rs.1,20,000
Break-up of Columns 13 and 14 overleaf

(iv) Other Sponsors

(i)

By the Management

(ii)

By
Registration(Approximately)

Rs.30,000
Rs.15,000

Total Rs.45,000