OSN 3500 V200R011C03 Hardware Description 03

OptiX OSN 3500 Intelligent Optical Transmission
System
V200R011C03
Hardware Description
Issue
03
Date
2013-02-20
HUAWEI TECHNOLOGIES CO., LTD.
Copyright Huawei Technologies Co., Ltd. 2013. All rights reserved.

No part of this document may be reproduced or transmitted in any form or by any means without prior written
consent of Huawei Technologies Co., Ltd.
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and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd.
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Notice
The purchased products, services and features are stipulated by the contract made between Huawei and the
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The information in this document is subject to change without notice. Every effort has been made in the
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Huawei Technologies Co., Ltd.

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Issue 03 (2013-02-20)
Huawei Proprietary and Confidential

Copyright Huawei Technologies Co., Ltd.
OptiX OSN 3500 Intelligent Optical Transmission System

About This Document
About This Document

Related Versions
The following table lists the product versions related to this document.
Product Name
Version
OptiX OSN 3500
V200R011C03
Intended Audience
This document describes the structure, composition, boards, and cables of the OptiX OSN
equipment.
The readers can have a comprehensive understanding of the hardware of the OptiX OSN
equipment through this document.
This document is intended for:
l
Network design and planning engineers
Hardware installation engineers
Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol
Description
DANGER
WARNING
Issue 03 (2013-02-20)
DANGER indicates a hazard with a high level or medium

level of risk which, if not avoided, could result in death or
serious injury.
WARNING indicates a hazard with a low level of risk which,
if not avoided, could result in minor or moderate injury.

ii

Symbol
About This Document
Description
CAUTION
CAUTION indicates a potentially hazardous situation that,

if not avoided, could result in equipment damage, data loss,
performance deterioration, or unanticipated results.
TIP
Provides a tip that may help you solve a problem or save time.
NOTE
Provides additional information to emphasize or supplement

important points in the main text.
GUI Conventions
The GUI conventions that may be found in this document are defined as follows.
Convention
Description
Boldface
Buttons, menus, parameters, tabs, window, and dialog titles

are in boldface. For example, click OK.
>
Multi-level menus are in boldface and separated by the ">"

signs. For example, choose File > Create > Folder.
Change History
Updates between document issues are cumulative. Therefore, the latest document issue contains
all updates made in previous issues.
Updates in Issue 03 (2013-02-20) Based on Product Version

V200R011C03
This document of the V200R011C03 version is of the third release. Compared with Issue 02,
Issue 03 includes the following updates in V200R011C03SPC200:
l
Information about pluggable optical modules supported by boards is added in topic "SDH
Boards".
In chapter "SDH Boards", the description of PRBS support is optimized for each line board.
In chapter "Cabinet", added the description of DPD100-2-8 PDU and DPD63-8-8 PDU.
Issue 03 (2013-02-20)

iii

About This Document

V200R011C03
This document of the V200R011C03 version is of the second release. Compared with issue 01,
this issue has the following new or optimized contents:
l
In topic "EoS Boards", the description of frame length range is optimized.

V200R011C03
This document of the V200R011C03 version is of the first release. Compared with
V200R011C02, This issue has the following new or optimized contents:
l
In topics "SDH Boards" and "PDH Boards", the version description of each board is
optimized.
In topic "UPM", the description that type-III subracks (2300 W) support EPS75-4815AF
UPMs is added.
In topic "UPM", the front panel diagram and power consumption of the EPS75-4815AF
UPM are modified.

V200R011C02
l
In topic "Packet Interface Boards", the MTU is modified for ports on N1PETF8 and
N1PEFF8 boards.

V200R011C02
V200R011C01, this issue has the following new or optimized contents:
l
The description of the N1SXCSA and N3PSXCSA boards is added to topic "Cross-Connect
Boards and System Control Boards".
The description of the N4SL64 boards is added to topic "SDH Boards".
The description that the N3EGS2 boards support HUB/SPOKE is added to topic "EoS
Boards".
The description of the N1PFL1 boards is added to topic "PDH Boards".
The description of the N1VST4 boards is added to topic "SAN/Video Boards".
The description of the N2EFT8 and N2EFT8A boards is deleted from topic "EoS Boards".
Issue 03 (2013-02-20)

iv

About This Document

V200R011C01
l
The description of the N2EFT8 and N2EFT8A boards is added to topic "EoS Boards".
The description of MTU and inband DCN is added to topics "Packet Processing Boards"
and "Packet Interface Boards".
The sections "Functions and Features" of packet boards and EoS boards are optimized.

V200R011C01
l
The description that the PEG8 supports GE electrical ports is added to the topic "Packet
Processing Boards".
The description of the TN12OBU1 board is added to the topic "Optical Amplifier Boards
and Dispersion Compensation Boards".

V200R011C00
l
The description that the N2PEX1 and N1PEX2 boards support the 0.3 km transmission
distance is deleted from the topic "Functions and Features".
The description that the colored optical transmission distance supported by the PEX1,
PEX2, PEG8, and PEG16 boards is added in the topic "Functions and Features".

V200R011C00
l
The description of the PEX2/PEG8/PEFF8 is added in the topic "Packet Boards".
The description of the EDQ41 is added.
The description of the CQ1/MD12/MD75 is added.
Issue 03 (2013-02-20)


Contents
Contents
About This Document.....................................................................................................................ii
1 Equipment Structure.....................................................................................................................1
2 Cabinet.............................................................................................................................................5
2.1 Types of Cabinets...............................................................................................................................................6
2.2 Configuration of the Cabinet............................................................................................................................13
2.2.1 Indicators.................................................................................................................................................14
2.2.2 DC Power Distribution Unit....................................................................................................................15
2.2.3 Other Configurations...............................................................................................................................21
3 Subrack..........................................................................................................................................22
3.1 Subrack Structure.............................................................................................................................................24
3.2 Slot Allocation..................................................................................................................................................25
3.3 Slot Access Capacity in Packet Mode..............................................................................................................28
3.4 Slot Access Capacity in TDM Mode................................................................................................................29
3.5 Ventilation Mode..............................................................................................................................................30
3.6 Cable Management...........................................................................................................................................31
3.7 Mapping Policies of Power Consumption........................................................................................................32
3.8 Technical Specifications...................................................................................................................................33
4 Overview of Boards.....................................................................................................................36
4.1 Appearances and Dimensions of the Boards....................................................................................................37
4.2 Bar Codes of the Boards...................................................................................................................................39
5 Classification of Boards..............................................................................................................41
6 Cross-Connect Boards and System Control Boards..............................................................53
6.1 SXCSA.............................................................................................................................................................54
6.1.1 Version Description.................................................................................................................................54
6.1.2 Application..............................................................................................................................................54
6.1.3 Functions and Features............................................................................................................................54
6.1.4 Working Principle and Signal Flow........................................................................................................56
6.1.5 Front Panel...............................................................................................................................................58
6.1.6 Jumpers and DIP Switches......................................................................................................................59
6.1.7 Valid Slots...............................................................................................................................................59
6.1.8 Feature Code............................................................................................................................................59
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6.1.9 Configuring and Commissioning the Board............................................................................................59

6.1.10 Parameter Settings.................................................................................................................................60
6.1.11 Maintaining the Board...........................................................................................................................61
6.1.12 List of Alarms........................................................................................................................................62
6.1.12.1 Alarms of N1SXCSA...................................................................................................................62
6.1.13 List of Performance Events...................................................................................................................62
6.1.14 Technical Specifications........................................................................................................................62
6.2 PSXCS(A)........................................................................................................................................................63
6.2.2 Application..............................................................................................................................................64
6.2.5 Front Panel...............................................................................................................................................67
6.2.7 Valid Slots...............................................................................................................................................69
6.2.8 Feature Code............................................................................................................................................69
6.2.12 List of Alarms........................................................................................................................................71
6.2.12.1 Alarms of N1PSCXS(A)..............................................................................................................72
6.3 GSCC................................................................................................................................................................75
6.3.2 Application..............................................................................................................................................75
6.3.5 Front Panel...............................................................................................................................................79
6.3.7 Valid Slots...............................................................................................................................................85
6.3.8 Feature Code............................................................................................................................................86
6.3.12 List of Alarms........................................................................................................................................88
6.3.12.1 Alarms of N4GSCC......................................................................................................................88
6.3.12.2 Alarms of N6GSCC......................................................................................................................89
6.3.13.1 Performance Events of N4GSCC.................................................................................................91
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6.3.13.2 Performance Events of N6GSCC.................................................................................................91

7 Packet Processing Boards...........................................................................................................92

7.1 PEX1.................................................................................................................................................................93
7.1.2 Application..............................................................................................................................................93
7.1.4 Working Principle and Signal Flow......................................................................................................100
7.1.5 Front Panel.............................................................................................................................................102
7.1.6 Jumpers and DIP Switches....................................................................................................................104
7.1.7 Valid Slots.............................................................................................................................................104
7.1.8 Feature Code..........................................................................................................................................105
7.1.9 Configuring and Commissioning the Board..........................................................................................105
7.1.10 Configuring the Board Functions........................................................................................................107
7.1.11 Parameter Settings...............................................................................................................................107
7.1.12 Maintaining the Board.........................................................................................................................108
7.1.13 List of Alarms......................................................................................................................................108
7.1.13.1 Alarms of N1PEX1.....................................................................................................................109
7.1.13.2 Alarms of N2PEX1.....................................................................................................................109
7.1.14 List of Performance Events.................................................................................................................111
7.1.14.1 Performance Events of N1PEX1................................................................................................111
7.1.15 Technical Specifications......................................................................................................................115
7.2 PEX2...............................................................................................................................................................119
7.2.1 Version Description...............................................................................................................................119
7.2.2 Application............................................................................................................................................120
7.2.3 Functions and Features..........................................................................................................................120
7.2.5 Front Panel.............................................................................................................................................127
7.2.7 Valid Slots.............................................................................................................................................129
7.2.8 Feature Code..........................................................................................................................................129
7.2.13 List of Alarms......................................................................................................................................132
7.2.13.1 Alarms of N1PEX2.....................................................................................................................132
7.3 PEG8...............................................................................................................................................................139
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7.3.2 Application............................................................................................................................................139
7.3.5 Front Panel.............................................................................................................................................147
7.3.7 Valid Slots.............................................................................................................................................148
7.3.8 Feature Code..........................................................................................................................................149
7.3.13 List of Alarms......................................................................................................................................152
7.3.13.1 Alarms of N1PEG8.....................................................................................................................152
7.3.14.1 Performance Events of N1PEG8................................................................................................154
7.4 PEG16.............................................................................................................................................................159
7.4.2 Application............................................................................................................................................159
7.4.5 Front Panel.............................................................................................................................................166
7.4.7 Valid Slots.............................................................................................................................................168
7.4.8 Feature Code..........................................................................................................................................168
7.4.13 List of Alarms......................................................................................................................................172
7.4.13.1 Alarms of N1PEG16...................................................................................................................172
7.4.14.1 Performance Events of N1PEG16..............................................................................................173
8 Packet Interface Boards............................................................................................................178

8.1 PETF8.............................................................................................................................................................179
8.1.2 Application............................................................................................................................................179
8.1.5 Front Panel.............................................................................................................................................184
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8.1.7 Valid Slots.............................................................................................................................................186
8.1.8 Feature Code..........................................................................................................................................186
8.1.12 List of Alarms......................................................................................................................................189
8.1.12.1 Alarms of N1PETF8...................................................................................................................189
8.1.13.1 Performance Events of N1PETF8..............................................................................................190
8.2 PEFF8.............................................................................................................................................................193
8.2.2 Application............................................................................................................................................194
8.2.5 Front Panel.............................................................................................................................................199
8.2.6 Valid Slots.............................................................................................................................................201
8.2.7 Feature Code..........................................................................................................................................201
8.2.9 Configuring the Board Functions..........................................................................................................203
8.2.12 List of Alarms......................................................................................................................................204
8.2.12.1 Alarms of N1PEFF8...................................................................................................................204
8.2.13.1 Performance Events of N1PEFF8...............................................................................................206
8.3 CQ1.................................................................................................................................................................209
8.3.2 Application............................................................................................................................................209
8.3.5 Front Panel.............................................................................................................................................213
8.3.7 Valid Slots.............................................................................................................................................215
8.3.8 Feature Code..........................................................................................................................................215
8.3.12 List of Alarms......................................................................................................................................217
8.3.12.1 Alarms of N1CQ1.......................................................................................................................217
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8.3.13.1 Performance Events of N1CQ1..................................................................................................218
8.4 MD12..............................................................................................................................................................220
8.4.2 Application............................................................................................................................................221
8.4.5 Front Panel.............................................................................................................................................226
8.4.7 Valid Slots.............................................................................................................................................229
8.4.8 Feature Code..........................................................................................................................................229
8.4.12 List of Alarms......................................................................................................................................231
8.4.12.1 Alarms of N1MD12....................................................................................................................231
8.4.13.1 Performance Events of N1MD12...............................................................................................232
8.5 MD75..............................................................................................................................................................234
8.5.2 Application............................................................................................................................................234
8.5.5 Front Panel.............................................................................................................................................240
8.5.7 Valid Slots.............................................................................................................................................243
8.5.8 Feature Code..........................................................................................................................................243
8.5.12 List of Alarms......................................................................................................................................245
8.5.12.1 Alarms of N1MD75....................................................................................................................245
8.5.13.1 Performance Events of N1MD75...............................................................................................246
9 EoD Boards................................................................................................................................. 249

9.1 EDQ41............................................................................................................................................................250
9.1.2 Application............................................................................................................................................250
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9.1.5 Front Panel.............................................................................................................................................259
9.1.7 Valid Slots.............................................................................................................................................260
9.1.8 Feature Code..........................................................................................................................................260
9.1.13 List of Alarms......................................................................................................................................265
9.1.13.1 Alarms of N1EDQ41..................................................................................................................265
9.1.14.1 Performance Events of N1EDQ41.............................................................................................267
10 SDH Boards..............................................................................................................................271
10.1 SL1................................................................................................................................................................274
10.1.1 Version Description.............................................................................................................................274
10.1.2 Application..........................................................................................................................................274
10.1.3 Functions and Features........................................................................................................................275
10.1.4 Working Principle and Signal Flow....................................................................................................276
10.1.5 Front Panel...........................................................................................................................................278
10.1.6 Jumpers and DIP Switches..................................................................................................................280
10.1.7 Valid Slots...........................................................................................................................................280
10.1.8 Feature Code........................................................................................................................................280
10.1.9 Configuring and Commissioning the Board........................................................................................281
10.1.10 Parameter Settings.............................................................................................................................282
10.1.11 Maintaining the Board.......................................................................................................................282
10.1.12 List of Alarms....................................................................................................................................284
10.1.12.1 Alarms of N1SL1......................................................................................................................284
10.1.12.2 Alarms of N2SL1......................................................................................................................285
10.1.13 List of Performance Events...............................................................................................................286
10.1.13.1 Performance Events of N1SL1.................................................................................................286
10.1.13.2 Performance Events of N2SL2.................................................................................................286
10.1.14 Technical Specifications....................................................................................................................287
10.2 SL1A.............................................................................................................................................................288
10.2.2 Application..........................................................................................................................................289
10.2.5 Front Panel...........................................................................................................................................292
10.2.6 Valid Slots...........................................................................................................................................294
10.2.7 Feature Code........................................................................................................................................294
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10.3 SLQ1.............................................................................................................................................................296
10.3.2 Application..........................................................................................................................................297
10.3.5 Front Panel...........................................................................................................................................301
10.3.6 Valid Slots...........................................................................................................................................303
10.3.7 Feature Code........................................................................................................................................303
10.4 SLQ1A..........................................................................................................................................................305
10.4.2 Application..........................................................................................................................................305
10.4.5 Front Panel...........................................................................................................................................310
10.4.6 Valid Slots...........................................................................................................................................311
10.4.7 Feature Code........................................................................................................................................311
10.5 SLO1.............................................................................................................................................................313
10.5.2 Application..........................................................................................................................................314
10.5.5 Front Panel...........................................................................................................................................318
10.5.6 Valid Slots...........................................................................................................................................321
10.5.7 Feature Code........................................................................................................................................321
10.6 SLT1.............................................................................................................................................................323
10.6.2 Application..........................................................................................................................................324
10.6.5 Front Panel...........................................................................................................................................327
10.6.6 Valid Slots...........................................................................................................................................329
10.6.7 Feature Code........................................................................................................................................329
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10.7 SLH1.............................................................................................................................................................331
10.7.2 Application..........................................................................................................................................331
10.7.5 Front Panel...........................................................................................................................................336
10.7.7 Valid Slots...........................................................................................................................................338
10.7.8 Board Protection..................................................................................................................................338
10.7.12 List of Alarms....................................................................................................................................343
10.7.12.1 Alarms of N1SLH1(B).............................................................................................................343
10.7.13.1 Performance Events of N1SLH1(B).........................................................................................344
10.8 SEP1.............................................................................................................................................................345
10.8.2 Application..........................................................................................................................................346
10.8.5 Front Panel...........................................................................................................................................352
10.8.7 Valid Slots...........................................................................................................................................353
10.8.9 Feature Code........................................................................................................................................356
10.8.10 Configuring and Commissioning the Board......................................................................................356
10.8.13 List of Alarms....................................................................................................................................359
10.8.13.1 Alarms of N1SEP1...................................................................................................................359
10.8.14.1 Performance Events of N1SEP1...............................................................................................360
10.9 SL4................................................................................................................................................................361
10.9.2 Application..........................................................................................................................................362
10.9.5 Front Panel...........................................................................................................................................366
10.9.6 Valid Slots...........................................................................................................................................367
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10.9.7 Feature Code........................................................................................................................................367

10.10 SL4A...........................................................................................................................................................369
10.10.1 Version Description...........................................................................................................................369
10.10.2 Application........................................................................................................................................370
10.10.3 Functions and Features......................................................................................................................370
10.10.4 Working Principle and Signal Flow..................................................................................................372
10.10.5 Front Panel.........................................................................................................................................374
10.10.6 Valid Slots.........................................................................................................................................375
10.10.7 Feature Code......................................................................................................................................375
10.11 SLD4...........................................................................................................................................................378
10.11.2 Application........................................................................................................................................379
10.11.5 Front Panel.........................................................................................................................................383
10.11.6 Valid Slots.........................................................................................................................................385
10.11.7 Feature Code......................................................................................................................................385
10.12 SLD4A........................................................................................................................................................387
10.12.2 Application........................................................................................................................................387
10.12.5 Front Panel.........................................................................................................................................392
10.12.6 Valid Slots.........................................................................................................................................393
10.12.7 Feature Code......................................................................................................................................393
10.13 SLQ4...........................................................................................................................................................395
10.13.2 Application........................................................................................................................................396
10.13.5 Front Panel.........................................................................................................................................400
10.13.6 Valid Slots.........................................................................................................................................402
10.13.7 Feature Code......................................................................................................................................402
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10.14 SLQ4A........................................................................................................................................................404
10.14.2 Application........................................................................................................................................404
10.14.5 Front Panel.........................................................................................................................................409
10.14.6 Valid Slots.........................................................................................................................................410
10.14.7 Feature Code......................................................................................................................................410
10.15 SL16............................................................................................................................................................412
10.15.2 Application........................................................................................................................................413
10.15.5 Front Panel.........................................................................................................................................417
10.15.6 Valid Slots.........................................................................................................................................419
10.15.7 Feature Code......................................................................................................................................419
10.16 SL16A.........................................................................................................................................................422
10.16.2 Application........................................................................................................................................423
10.16.5 Front Panel.........................................................................................................................................428
10.16.6 Jumpers and DIP Switches................................................................................................................429
10.16.7 Valid Slots.........................................................................................................................................429
10.16.8 Feature Code......................................................................................................................................429
10.16.10 Parameter Settings...........................................................................................................................431
10.16.11 Maintaining the Board.....................................................................................................................432
10.16.12 List of Alarms..................................................................................................................................433
10.16.12.1 Alarms of N1SL16A...............................................................................................................433
10.16.12.2 Alarms of N2SL16A...............................................................................................................434
10.16.12.3 Alarms of N3SL16A...............................................................................................................435
10.16.13 List of Performance Events.............................................................................................................437
10.16.13.1 Performance Events of N1SL16A..........................................................................................437
10.16.14 Technical Specifications..................................................................................................................439
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10.17 SLD16.........................................................................................................................................................442
10.17.2 Application........................................................................................................................................442
10.17.5 Front Panel.........................................................................................................................................446
10.17.7 Valid Slots.........................................................................................................................................448
10.17.8 Feature Code......................................................................................................................................448
10.17.12 List of Alarms..................................................................................................................................452
10.17.12.1 Alarms of N1SLD16...............................................................................................................452
10.17.13.1 Performance Events of N1SLD16..........................................................................................453
10.18 SLQ16.........................................................................................................................................................455
10.18.2 Application........................................................................................................................................456
10.18.5 Front Panel.........................................................................................................................................460
10.18.7 Valid Slots.........................................................................................................................................463
10.18.8 Feature Code......................................................................................................................................463
10.18.12 List of Alarms..................................................................................................................................467
10.18.12.1 Alarms of N1SLQ16...............................................................................................................467
10.18.13.1 Performance Events of N1SLQ16..........................................................................................468
10.19 SLO16.........................................................................................................................................................470
10.19.2 Application........................................................................................................................................470
10.19.5 Front Panel.........................................................................................................................................475
10.19.7 Valid Slots.........................................................................................................................................476
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10.19.8 Feature Code......................................................................................................................................476

10.19.12 List of Alarms..................................................................................................................................480
10.19.12.1 Alarms of N1SLO16...............................................................................................................480
10.19.13.1 Performance Events of N1SLO16..........................................................................................481
10.20 SF16............................................................................................................................................................483
10.20.2 Application........................................................................................................................................483
10.20.5 Front Panel.........................................................................................................................................488
10.20.6 Valid Slots.........................................................................................................................................489
10.20.7 Feature Code......................................................................................................................................489
10.21 SL64............................................................................................................................................................492
10.21.2 Application........................................................................................................................................493
10.21.5 Front Panel.........................................................................................................................................498
10.21.7 Valid Slots.........................................................................................................................................501
10.21.8 Feature Code......................................................................................................................................501
10.21.12 List of Alarms..................................................................................................................................505
10.21.12.1 Alarms of N1SL64..................................................................................................................505
10.21.12.2 Alarms of N2SL64..................................................................................................................506
10.21.12.3 Alarms of N4SL64..................................................................................................................508
10.21.13.1 Performance Events of N1SL64.............................................................................................509
10.22 SLD64.........................................................................................................................................................516
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10.22.2 Application........................................................................................................................................516
10.22.5 Front Panel.........................................................................................................................................520
10.22.7 Valid Slots.........................................................................................................................................522
10.22.8 Feature Code......................................................................................................................................522
10.22.12 List of Alarms..................................................................................................................................526
10.22.12.1 Alarms of N1SLD64...............................................................................................................526
10.22.13.1 Performance Events of N1SLD64..........................................................................................527
10.23 SF64............................................................................................................................................................529
10.23.2 Application........................................................................................................................................529
10.23.5 Front Panel.........................................................................................................................................534
10.23.7 Valid Slots.........................................................................................................................................535
10.23.8 Feature Code......................................................................................................................................535
10.23.12 List of Alarms..................................................................................................................................539
10.23.12.1 Alarms of N1SF64..................................................................................................................539
10.23.13.1 Performance Events of N1SF64.............................................................................................541
10.24 SF64A.........................................................................................................................................................543
10.24.2 Application........................................................................................................................................544
10.24.5 Front Panel.........................................................................................................................................548
10.24.6 Valid Slots.........................................................................................................................................550
10.25 SLQ41.........................................................................................................................................................552
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10.25.2 Application........................................................................................................................................553
10.25.5 Front Panel.........................................................................................................................................557
10.25.7 Valid Slots.........................................................................................................................................559
10.25.8 Feature Code......................................................................................................................................559
10.25.12 List of Alarms..................................................................................................................................563
10.25.12.1 Alarms of N3SLQ41...............................................................................................................563
10.25.13.1 Performance Events of N3SLQ41..........................................................................................564
10.26 SLH41.........................................................................................................................................................569
10.26.2 Application........................................................................................................................................569
10.26.5 Front Panel.........................................................................................................................................573
10.26.7 Valid Slots.........................................................................................................................................576
10.26.8 Feature Code......................................................................................................................................577
10.26.12 List of Alarms..................................................................................................................................580
10.26.12.1 Alarms of N3SLH41...............................................................................................................580
10.26.13.1 Performance Events of N3SLH41..........................................................................................581
10.27 EU04...........................................................................................................................................................585
10.27.2 Application........................................................................................................................................585
10.27.5 Front Panel.........................................................................................................................................586
10.27.6 Valid Slots.........................................................................................................................................588
10.28 EU08...........................................................................................................................................................589
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10.28.2 Application........................................................................................................................................589
10.28.5 Front Panel.........................................................................................................................................590
10.28.6 Valid Slots.........................................................................................................................................592
10.29 OU08..........................................................................................................................................................593
10.29.2 Application........................................................................................................................................594
10.29.5 Front Panel.........................................................................................................................................595
10.29.6 Valid Slots.........................................................................................................................................598
11 PDH Boards..............................................................................................................................601
11.1 PQ1...............................................................................................................................................................603
11.1.2 Application..........................................................................................................................................603
11.1.5 Front Panel...........................................................................................................................................608
11.1.7 Valid Slots...........................................................................................................................................609
11.1.8 Feature Code........................................................................................................................................610
11.1.13 List of Alarms....................................................................................................................................615
11.1.13.1 Alarms of N1PQ1.....................................................................................................................615
11.1.13.2 Alarms of N2PQ1.....................................................................................................................615
11.1.14.1 Performance Events of N1PQ1.................................................................................................616
11.1.14.2 Performance Events of N2PQ1.................................................................................................616
11.2 PQM..............................................................................................................................................................617
11.2.2 Application..........................................................................................................................................617
11.2.5 Front Panel...........................................................................................................................................622
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11.2.7 Valid Slots...........................................................................................................................................623
11.2.8 Feature Code........................................................................................................................................624
11.2.13 List of Alarms....................................................................................................................................628
11.2.13.1 Alarms of N1PQM....................................................................................................................628
11.2.14.1 Performance Events of N1PQM...............................................................................................629
11.3 PFL1.............................................................................................................................................................630
11.3.2 Application..........................................................................................................................................630
11.3.5 Front Panel...........................................................................................................................................633
11.3.7 Valid Slots...........................................................................................................................................634
11.3.8 Feature Code........................................................................................................................................634
11.3.12 List of Alarms....................................................................................................................................637
11.3.12.1 Alarms of N1PFL1...................................................................................................................637
11.3.13.1 Performance Events of N1PFL1...............................................................................................638
11.4 PL3................................................................................................................................................................639
11.4.2 Application..........................................................................................................................................640
11.4.5 Front Panel...........................................................................................................................................644
11.4.7 Valid Slots...........................................................................................................................................645
11.4.8 Feature Code........................................................................................................................................645
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Contents
11.4.13 List of Alarms....................................................................................................................................650

11.4.13.1 Alarms of N1PL3......................................................................................................................651
11.4.13.2 Alarms of N2PL3......................................................................................................................651
11.4.14.1 Performance Events of N1PL3.................................................................................................652
11.4.14.2 Performance Events of N2PL3.................................................................................................652
11.5 PL3A.............................................................................................................................................................653
11.5.2 Application..........................................................................................................................................654
11.5.5 Front Panel...........................................................................................................................................658
11.5.7 Valid Slots...........................................................................................................................................659
11.5.8 Feature Code........................................................................................................................................659
11.5.12 List of Alarms....................................................................................................................................662
11.5.12.1 Alarms of N1PL3A...................................................................................................................662
11.5.12.2 Alarms of N2PL3A...................................................................................................................663
11.5.13.1 Performance Events of N1PL3A..............................................................................................663
11.5.13.2 Performance Events of N2PL3A..............................................................................................664
11.6 PD3...............................................................................................................................................................665
11.6.2 Application..........................................................................................................................................666
11.6.5 Front Panel...........................................................................................................................................670
11.6.6 Valid Slots...........................................................................................................................................671
11.7 PQ3...............................................................................................................................................................674
11.7.2 Application..........................................................................................................................................674
11.7.5 Front Panel...........................................................................................................................................679
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Contents
11.7.6 Valid Slots...........................................................................................................................................680

11.8 DX1..............................................................................................................................................................683
11.8.2 Application..........................................................................................................................................683
11.8.5 Front Panel...........................................................................................................................................686
11.8.7 Valid Slots...........................................................................................................................................688
11.8.8 Feature Code........................................................................................................................................688
11.8.13 List of Alarms....................................................................................................................................693
11.8.13.1 Alarms of N1DX1....................................................................................................................693
11.8.14.1 Performance Events of N1DX1................................................................................................694
11.9 DXA..............................................................................................................................................................695
11.9.2 Application..........................................................................................................................................695
11.9.5 Front Panel...........................................................................................................................................697
11.9.6 Valid Slots...........................................................................................................................................699
11.10 SPQ4...........................................................................................................................................................699
11.10.2 Application........................................................................................................................................700
11.10.5 Front Panel.........................................................................................................................................705
11.10.7 Valid Slots.........................................................................................................................................707
11.10.8 Feature Code......................................................................................................................................707
11.10.9 Board Protection................................................................................................................................707
11.10.10 Configuring and Commissioning the Board....................................................................................710
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Contents

11.10.13 List of Alarms..................................................................................................................................712
11.10.13.1 Alarms of N1SPQ4.................................................................................................................712
11.10.13.2 Alarms of N2SPQ4.................................................................................................................713
11.10.14.1 Performance Events of N1SPQ4............................................................................................714
11.10.14.2 Performance Events of N2SPQ4............................................................................................715
11.11 D12B...........................................................................................................................................................715
11.11.2 Application........................................................................................................................................716
11.11.5 Front Panel.........................................................................................................................................716
11.11.6 Valid Slots.........................................................................................................................................718
11.12 D12S...........................................................................................................................................................720
11.12.2 Application........................................................................................................................................720
11.12.5 Front Panel.........................................................................................................................................721
11.12.6 Valid Slots.........................................................................................................................................723
11.13 D75S...........................................................................................................................................................725
11.13.2 Application........................................................................................................................................725
11.13.5 Front Panel.........................................................................................................................................727
11.13.6 Valid Slots.........................................................................................................................................729
11.14 D34S...........................................................................................................................................................730
11.14.2 Application........................................................................................................................................730
11.14.5 Front Panel.........................................................................................................................................731
11.14.6 Valid Slots.........................................................................................................................................733
11.15 C34S...........................................................................................................................................................734
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Contents

11.15.2 Application........................................................................................................................................734
11.15.5 Front Panel.........................................................................................................................................735
11.15.6 Valid Slots.........................................................................................................................................737
11.16 MU04..........................................................................................................................................................738
11.16.2 Application........................................................................................................................................738
11.16.5 Front Panel.........................................................................................................................................739
11.16.6 Valid Slots.........................................................................................................................................741
11.17 DM12..........................................................................................................................................................742
11.17.2 Application........................................................................................................................................742
11.17.5 Front Panel.........................................................................................................................................743
11.17.6 Valid Slots.........................................................................................................................................746
11.18 TSB4...........................................................................................................................................................748
11.18.2 Application........................................................................................................................................748
11.18.5 Front Panel.........................................................................................................................................749
11.18.6 Valid Slots.........................................................................................................................................750
11.19 TSB8...........................................................................................................................................................751
11.19.2 Application........................................................................................................................................751
11.19.5 Front Panel.........................................................................................................................................753
11.19.6 Valid Slots.........................................................................................................................................753
12 EoS Boards................................................................................................................................758
12.1 EFT8.............................................................................................................................................................760
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Contents
12.1.2 Application..........................................................................................................................................760
12.1.5 Front Panel...........................................................................................................................................766
12.1.7 Valid Slots...........................................................................................................................................769
12.1.8 Feature Code........................................................................................................................................769
12.1.10 Configuring the Board Functions......................................................................................................771
12.1.13 List of Alarms....................................................................................................................................772
12.1.13.1 Alarms of N1EFT8...................................................................................................................772
12.1.14.1 Performance Events of N1EFT8...............................................................................................773
12.2 EFT8A..........................................................................................................................................................779
12.2.2 Application..........................................................................................................................................779
12.2.5 Front Panel...........................................................................................................................................786
12.2.7 Valid Slots...........................................................................................................................................789
12.2.8 Feature Code........................................................................................................................................789
12.2.13 List of Alarms....................................................................................................................................792
12.2.13.1 Alarms of N1EFT8A................................................................................................................792
12.2.14.1 Performance Events of N1EFT8A............................................................................................793
12.3 EGT2............................................................................................................................................................799
12.3.2 Application..........................................................................................................................................800
12.3.5 Front Panel...........................................................................................................................................806
12.3.7 Valid Slots...........................................................................................................................................810
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Contents
12.3.8 Feature Code........................................................................................................................................810

12.3.13 List of Alarms....................................................................................................................................813
12.3.13.1 Alarms of N1EGT2..................................................................................................................813
12.3.13.2 Alarms of N2EGT2..................................................................................................................814
12.3.14.1 Performance Events of N1EGT2..............................................................................................815
12.3.14.2 Performance Events of N2EGT2..............................................................................................816
12.4 EFS0.............................................................................................................................................................827
12.4.2 Application..........................................................................................................................................828
12.4.5 Front Panel...........................................................................................................................................838
12.4.7 Valid Slots...........................................................................................................................................839
12.4.8 Feature Code........................................................................................................................................840
12.4.14 List of Alarms....................................................................................................................................845
12.4.14.1 Alarms of N1EFS0...................................................................................................................845
12.4.14.2 Alarms of N2EFS0...................................................................................................................845
12.4.14.3 Alarms of N4EFS0...................................................................................................................846
12.4.14.4 Alarms of N5EFS0...................................................................................................................847
12.4.15.1 Performance Events of N1EFS0...............................................................................................848
12.5 EFS0A..........................................................................................................................................................862
12.5.2 Application..........................................................................................................................................863
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Contents
12.5.5 Front Panel...........................................................................................................................................871

12.5.7 Valid Slots...........................................................................................................................................872
12.5.8 Feature Code........................................................................................................................................873
12.5.14 List of Alarms....................................................................................................................................878
12.5.14.1 Alarms of N1EFS0A................................................................................................................878
12.5.15.1 Performance Events of N1EFS0A............................................................................................879
12.6 EFS4.............................................................................................................................................................884
12.6.2 Application..........................................................................................................................................885
12.6.5 Front Panel...........................................................................................................................................894
12.6.7 Valid Slots...........................................................................................................................................897
12.6.8 Feature Code........................................................................................................................................897
12.6.13 List of Alarms....................................................................................................................................900
12.6.13.1 Alarms of N1EFS4...................................................................................................................900
12.6.13.2 Alarms of N2EFS4...................................................................................................................901
12.6.13.3 Alarms of N3EFS4...................................................................................................................902
12.7 EGS2.............................................................................................................................................................915
12.7.2 Application..........................................................................................................................................916
12.7.5 Front Panel...........................................................................................................................................925
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Contents

12.7.7 Valid Slots...........................................................................................................................................928
12.7.8 Feature Code........................................................................................................................................928
12.7.13 List of Alarms....................................................................................................................................932
12.7.13.1 Alarms of N2EGS2...................................................................................................................932
12.7.13.2 Alarms of N3EGS2...................................................................................................................933
12.7.14.1 Performance Events of N2EGS2..............................................................................................934
12.7.14.2 Performance Events of N3EGS2..............................................................................................935
12.8 EMS2............................................................................................................................................................946
12.8.2 Application..........................................................................................................................................946
12.8.5 Front Panel...........................................................................................................................................955
12.8.7 Valid Slots...........................................................................................................................................958
12.8.8 Feature Code........................................................................................................................................958
12.8.13 List of Alarms....................................................................................................................................962
12.8.13.1 Alarms of N1EMS2..................................................................................................................962
12.8.14.1 Performance Events of N1EMS2.............................................................................................963
12.9 EMS4............................................................................................................................................................974
12.9.2 Application..........................................................................................................................................974
12.9.5 Front Panel...........................................................................................................................................983
12.9.7 Valid Slots...........................................................................................................................................986
12.9.8 Feature Code........................................................................................................................................987
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12.9.14 List of Alarms....................................................................................................................................994
12.9.14.1 Alarms of N1EMS4..................................................................................................................995
12.9.15.1 Performance Events of N1EMS4.............................................................................................996
12.10 EGS4.........................................................................................................................................................1006
12.10.1 Version Description.........................................................................................................................1006
12.10.2 Application......................................................................................................................................1007
12.10.3 Functions and Features....................................................................................................................1007
12.10.4 Working Principle and Signal Flow................................................................................................1013
12.10.5 Front Panel.......................................................................................................................................1016
12.10.6 Jumpers and DIP Switches..............................................................................................................1019
12.10.7 Valid Slots.......................................................................................................................................1019
12.10.8 Feature Code....................................................................................................................................1019
12.10.9 Board Protection..............................................................................................................................1020
12.10.10 Configuring and Commissioning the Board..................................................................................1023
12.10.11 Configuring the Board Functions..................................................................................................1025
12.10.12 Parameter Settings.........................................................................................................................1025
12.10.13 Maintaining the Board...................................................................................................................1025
12.10.14 List of Alarms................................................................................................................................1026
12.10.14.1 Alarms of N1EGS4...............................................................................................................1027
12.10.14.2 Alarms of N3EGS4...............................................................................................................1028
12.10.14.3 Alarms of N4EGS4...............................................................................................................1029
12.10.15 List of Performance Events...........................................................................................................1030
12.10.15.1 Performance Events of N1EGS4..........................................................................................1030
12.10.16 Technical Specifications................................................................................................................1034
12.11 EAS2.........................................................................................................................................................1044
12.11.2 Application......................................................................................................................................1044
12.11.5 Front Panel.......................................................................................................................................1052
12.11.6 Jumpers and DIP Switches..............................................................................................................1053
12.11.7 Valid Slots.......................................................................................................................................1053
12.11.8 Feature Code....................................................................................................................................1053
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Contents
12.11.10 Configuring the Board Functions..................................................................................................1055

12.11.11 Parameter Settings.........................................................................................................................1055
12.11.12 Maintaining the Board...................................................................................................................1056
12.11.13 List of Alarms................................................................................................................................1057
12.11.13.1 Alarms of N1EAS2...............................................................................................................1057
12.11.14 List of Performance Events...........................................................................................................1057
12.11.14.1 Performance Events of N1EAS2..........................................................................................1058
12.11.15 Technical Specifications................................................................................................................1059
12.12 EFF8.........................................................................................................................................................1063
12.12.2 Application......................................................................................................................................1063
12.12.5 Front Panel.......................................................................................................................................1064
12.12.6 Valid Slots.......................................................................................................................................1065
12.13 EFF8A......................................................................................................................................................1067
12.13.2 Application......................................................................................................................................1067
12.13.5 Front Panel.......................................................................................................................................1068
12.13.6 Valid Slots.......................................................................................................................................1070
12.14 ETF8.........................................................................................................................................................1071
12.14.2 Application......................................................................................................................................1071
12.14.5 Front Panel.......................................................................................................................................1072
12.14.6 Valid Slots.......................................................................................................................................1074
12.15 ETF8A......................................................................................................................................................1076
12.15.2 Application......................................................................................................................................1076
12.15.5 Front Panel.......................................................................................................................................1077
12.15.6 Valid Slots.......................................................................................................................................1078
12.16 ETS8.........................................................................................................................................................1079
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Contents
12.16.2 Application......................................................................................................................................1080
12.16.5 Front Panel.......................................................................................................................................1081
12.16.6 Valid Slots.......................................................................................................................................1082
13 ATM Boards............................................................................................................................1085
13.1 ADL4..........................................................................................................................................................1086
13.1.2 Application........................................................................................................................................1086
13.1.5 Front Panel.........................................................................................................................................1091
13.1.7 Valid Slots.........................................................................................................................................1093
13.1.8 Feature Code......................................................................................................................................1093
13.1.12 List of Alarms..................................................................................................................................1096
13.1.12.1 Alarms of N1ADL4................................................................................................................1096
13.1.13.1 Performance Events of N1ADL4...........................................................................................1097
13.2 ADQ1..........................................................................................................................................................1099
13.2.2 Application........................................................................................................................................1099
13.2.5 Front Panel.........................................................................................................................................1104
13.2.7 Valid Slots.........................................................................................................................................1106
13.2.8 Feature Code......................................................................................................................................1106
13.2.12 List of Alarms..................................................................................................................................1109
13.2.12.1 Alarms of N1ADQ1................................................................................................................1109
13.2.13.1 Performance Events of N1ADQ1...........................................................................................1110
13.3 IDL4............................................................................................................................................................1112
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Contents

13.3.2 Application........................................................................................................................................1112
13.3.5 Front Panel.........................................................................................................................................1117
13.3.7 Valid Slots.........................................................................................................................................1118
13.3.8 Feature Code......................................................................................................................................1118
13.3.13 List of Alarms..................................................................................................................................1122
13.3.13.1 Alarms of N1IDL4..................................................................................................................1122
13.3.14.1 Performance Events of N1IDL4.............................................................................................1123
13.4 IDQ1...........................................................................................................................................................1125
13.4.2 Application........................................................................................................................................1125
13.4.5 Front Panel.........................................................................................................................................1130
13.4.7 Valid Slots.........................................................................................................................................1131
13.4.8 Feature Code......................................................................................................................................1131
13.4.13 List of Alarms..................................................................................................................................1135
13.4.13.1 Alarms of N1IDQ1.................................................................................................................1135
13.4.14.1 Performance Events of N1IDQ1.............................................................................................1136
14 RPR Boards.............................................................................................................................1139
14.1 EGR2..........................................................................................................................................................1140
14.1.2 Application........................................................................................................................................1140
14.1.5 Front Panel.........................................................................................................................................1147
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Contents

14.1.7 Valid Slots.........................................................................................................................................1149
14.1.8 Feature Code......................................................................................................................................1149
14.1.10 Configuring the Board Functions....................................................................................................1151
14.1.13 List of Alarms..................................................................................................................................1153
14.1.13.1 Alarms of N2EGR2................................................................................................................1153
14.1.14.1 Performance Events of N2EGR2............................................................................................1154
14.2 EMR0..........................................................................................................................................................1162
14.2.2 Application........................................................................................................................................1163
14.2.5 Front Panel.........................................................................................................................................1169
14.2.7 Valid Slots.........................................................................................................................................1171
14.2.8 Feature Code......................................................................................................................................1172
14.2.10 Configuring the Board Functions....................................................................................................1174
14.2.13 List of Alarms..................................................................................................................................1175
14.2.13.1 Alarms of N2EMR0................................................................................................................1175
14.2.14.1 Performance Events of N2EMR0...........................................................................................1176
15 SAN/Video Boards................................................................................................................1189
15.1 MST4..........................................................................................................................................................1190
15.1.2 Application........................................................................................................................................1190
15.1.5 Front Panel.........................................................................................................................................1194
15.1.7 Valid Slots.........................................................................................................................................1196
15.1.8 Feature Code......................................................................................................................................1196
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Contents

15.1.12 List of Alarms..................................................................................................................................1199
15.1.12.1 Alarms of N1MST4................................................................................................................1199
15.1.13.1 Performance Events of N1MST4...........................................................................................1200
15.2 VST4...........................................................................................................................................................1202
15.2.2 Application........................................................................................................................................1202
15.2.5 Front Panel.........................................................................................................................................1205
15.2.7 Valid Slots.........................................................................................................................................1207
15.2.8 Feature Code......................................................................................................................................1207
15.2.9 Configuring and Commissioning a Board.........................................................................................1207
15.2.12 List of Alarms..................................................................................................................................1209
15.2.12.1 Alarms of N1VST4.................................................................................................................1209
15.2.13.1 Performance Events of N1VST4............................................................................................1210
16 Microwave Boards.................................................................................................................1212
16.1 IFSD1..........................................................................................................................................................1213
16.1.2 Application........................................................................................................................................1213
16.1.5 Front Panel.........................................................................................................................................1216
16.1.7 Valid Slots.........................................................................................................................................1219
16.1.8 Feature Code......................................................................................................................................1219
16.1.13 List of Alarms..................................................................................................................................1223
16.1.13.1 Alarms of N1IFSD1................................................................................................................1223
16.1.14.1 Performance Events of N1IFSD1...........................................................................................1224
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Contents
16.2 RPWR.........................................................................................................................................................1226
16.2.2 Application........................................................................................................................................1226
16.2.5 Front Panel.........................................................................................................................................1228
16.2.6 Valid Slots.........................................................................................................................................1230
16.2.7 Feature Code......................................................................................................................................1230
16.2.10 List of Alarms..................................................................................................................................1232
16.3 ODU............................................................................................................................................................1232
17 WDM Boards..........................................................................................................................1234
17.1 CMR2.........................................................................................................................................................1236
17.1.2 Application........................................................................................................................................1236
17.1.5 Front Panel.........................................................................................................................................1238
17.1.6 Valid Slots.........................................................................................................................................1240
17.1.7 Feature Code......................................................................................................................................1240
17.2 CMR4.........................................................................................................................................................1242
17.2.2 Application........................................................................................................................................1242
17.2.5 Front Panel.........................................................................................................................................1244
17.2.6 Valid Slots.........................................................................................................................................1245
17.2.7 Feature Code......................................................................................................................................1245
17.3 CMD2.........................................................................................................................................................1248
17.3.2 Application........................................................................................................................................1248
17.3.5 Front Panel.........................................................................................................................................1249
17.3.6 Valid Slots.........................................................................................................................................1251
17.3.7 Feature Code......................................................................................................................................1251
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Contents

17.3.11 List of Alarms..................................................................................................................................1253
17.4 MR2............................................................................................................................................................1254
17.4.2 Application........................................................................................................................................1255
17.4.5 Front Panel.........................................................................................................................................1257
17.4.6 Valid Slots.........................................................................................................................................1258
17.4.7 Feature Code......................................................................................................................................1258
17.5 MR2A.........................................................................................................................................................1260
17.5.2 Application........................................................................................................................................1260
17.5.5 Front Panel.........................................................................................................................................1263
17.5.6 Valid Slots.........................................................................................................................................1265
17.6 MR2C.........................................................................................................................................................1266
17.6.2 Application........................................................................................................................................1266
17.6.5 Front Panel.........................................................................................................................................1269
17.6.6 Valid Slots.........................................................................................................................................1271
17.7 MR4............................................................................................................................................................1272
17.7.2 Application........................................................................................................................................1272
17.7.5 Front Panel.........................................................................................................................................1274
17.7.6 Valid Slots.........................................................................................................................................1276
17.7.7 Feature Code......................................................................................................................................1276
17.8 LWX...........................................................................................................................................................1278
17.8.2 Application........................................................................................................................................1278
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Contents

17.8.5 Front Panel.........................................................................................................................................1281
17.8.6 Valid Slots.........................................................................................................................................1283
17.8.7 Feature Code......................................................................................................................................1283
17.9 FIB..............................................................................................................................................................1287
17.9.2 Application........................................................................................................................................1287
17.9.5 Front Panel.........................................................................................................................................1288
17.9.6 Valid Slots.........................................................................................................................................1290
18 Auxiliary Boards....................................................................................................................1292
18.1 AUX............................................................................................................................................................1293
18.1.2 Application........................................................................................................................................1293
18.1.5 Jumpers..............................................................................................................................................1296
18.1.6 Front Panel.........................................................................................................................................1297
18.1.7 Valid Slots.........................................................................................................................................1306
18.2 FAN............................................................................................................................................................1306
18.2.2 Application........................................................................................................................................1307
18.2.5 Front Panel.........................................................................................................................................1308
18.2.6 Valid Slots.........................................................................................................................................1309
19 Optical Amplifier Boards and Dispersion Compensation Boards..............................1311

19.1 BA2.............................................................................................................................................................1312
19.1.2 Application........................................................................................................................................1312
19.1.5 Front Panel.........................................................................................................................................1315
19.1.6 Valid Slots.........................................................................................................................................1318
19.1.7 Feature Code......................................................................................................................................1319
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Contents

19.2 BPA............................................................................................................................................................1320
19.2.2 Application........................................................................................................................................1321
19.2.5 Front Panel.........................................................................................................................................1323
19.2.6 Valid Slots.........................................................................................................................................1325
19.2.7 Feature Code......................................................................................................................................1325
19.3 COA............................................................................................................................................................1327
19.3.2 Application........................................................................................................................................1328
19.3.5 Front Panel.........................................................................................................................................1332
19.3.6 Valid Slots.........................................................................................................................................1336
19.3.7 Feature Code......................................................................................................................................1337
19.4 RPC01.........................................................................................................................................................1339
19.4.2 Application........................................................................................................................................1339
19.4.5 Front Panel.........................................................................................................................................1342
19.4.6 Valid Slots.........................................................................................................................................1343
19.4.8 Feature Code......................................................................................................................................1344
19.5 RPC02.........................................................................................................................................................1346
19.5.2 Application........................................................................................................................................1346
19.5.5 Front Panel.........................................................................................................................................1349
19.5.6 Valid Slots.........................................................................................................................................1350
19.5.8 Feature Code......................................................................................................................................1351
19.6 OBU1..........................................................................................................................................................1353
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Contents

19.6.2 Application........................................................................................................................................1353
19.6.5 Front Panel.........................................................................................................................................1356
19.6.6 Valid Slots.........................................................................................................................................1358
19.6.7 Feature Code......................................................................................................................................1358
19.7 DCU............................................................................................................................................................1361
19.7.2 Application........................................................................................................................................1361
19.7.5 Front Panel.........................................................................................................................................1363
19.7.6 Valid Slots.........................................................................................................................................1365
19.7.7 Feature Code......................................................................................................................................1365
20 Power Boards..........................................................................................................................1368
20.1 UPM............................................................................................................................................................1369
20.1.2 Application........................................................................................................................................1369
20.1.5 Front Panel.........................................................................................................................................1372
20.1.6 Valid Slots.........................................................................................................................................1375
20.2 PIU..............................................................................................................................................................1377
20.2.2 Application........................................................................................................................................1377
20.2.5 Front Panel.........................................................................................................................................1379
20.2.6 Valid Slots.........................................................................................................................................1381
20.3 PIUA...........................................................................................................................................................1381
20.3.2 Application........................................................................................................................................1381
20.3.5 Front Panel.........................................................................................................................................1383
20.3.6 Valid Slots.........................................................................................................................................1385
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Contents

20.4 PIUB...........................................................................................................................................................1385
20.4.1 Version Description........................................................................................................................... 1386
20.4.2 Application........................................................................................................................................1386
20.4.5 Front Panel.........................................................................................................................................1388
20.4.6 Valid Slots.........................................................................................................................................1389
21 Pluggable Optical Module...................................................................................................1391

21.1 Overview....................................................................................................................................................1392
21.2 SFP/eSFP....................................................................................................................................................1393
21.3 XFP............................................................................................................................................................. 1399
21.4 CWDM/DWDM.........................................................................................................................................1400
22 Pluggable Electrical Module...............................................................................................1416

23 Cables.......................................................................................................................................1418
23.1 Fiber Jumper...............................................................................................................................................1419
23.1.1 Categories of the Fiber Jumpers........................................................................................................1419
23.1.2 Connector...........................................................................................................................................1419
23.2 Power Cable and Ground Cable.................................................................................................................1422
23.2.1 Power Cable of the Cabinet...............................................................................................................1422
23.2.2 Ground Cable of the Cabinet Door....................................................................................................1426
23.2.3 Subrack Power Cable.........................................................................................................................1427
23.2.4 COA Power Cable.............................................................................................................................1429
23.2.5 RPC Power Cable..............................................................................................................................1431
23.3 Alarm Cable................................................................................................................................................1432
23.3.1 Cabinet Indicator Cable.....................................................................................................................1432
23.3.2 Indicator Cascading Cable Between Subracks or Alarm Cascading Cable Between the OptiX OSN
Equipment.....................................................................................................................................................1434
23.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment and the Other Huawei Transmission
Equipment.....................................................................................................................................................1435
23.3.4 Alarm Input/Output Cable.................................................................................................................1437
23.4 Management Cable.....................................................................................................................................1438
23.4.1 OAM Serial Cable.............................................................................................................................1439
23.4.2 Serial 1 to 4/F1/F&f Serial Cable......................................................................................................1440
23.4.3 RS-232/RS-422 Serial Cable.............................................................................................................1441
23.4.4 Ordinary Telephone Line...................................................................................................................1443
23.4.5 COA Cascading Cable.......................................................................................................................1444
23.4.6 Straight-Through Cable.....................................................................................................................1445
23.4.7 Crossover Cable.................................................................................................................................1447
23.5 Signal Cable................................................................................................................................................1448
23.5.1 75-ohm 8xE1 Cable...........................................................................................................................1448
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Contents
23.5.2 120-ohm 8xE1 Cable.........................................................................................................................1451

23.5.3 E3/T3/STM-1 Cable..........................................................................................................................1453
23.5.4 Framed E1 Cable...............................................................................................................................1455
23.5.5 Nx64 kbit/s Cable..............................................................................................................................1455
23.6 Clock Cable................................................................................................................................................1473
23.6.1 75-ohm/120-ohm Clock Cable..........................................................................................................1473
23.6.2 One-Channel Clock Transit Cable and Two-Channel Clock Transit Cable......................................1475
24 Indicators.................................................................................................................................1478
24.1 Indicators on the Cabinet............................................................................................................................1479
24.2 Alarm Indicators on the Boards..................................................................................................................1479
25 Labels.......................................................................................................................................1486
25.1 Safety Labels..............................................................................................................................................1487
25.1.1 Label Description..............................................................................................................................1487
25.1.2 Label Position....................................................................................................................................1488
25.2 Engineering Labels.....................................................................................................................................1490
26 Board Information Quick Reference.................................................................................1494

26.1 Board Version Replacement.......................................................................................................................1495
26.2 Quick Reference Table for Optical Interfaces............................................................................................1500
26.2.1 Common Parameters Specified for Optical Interfaces of SDH Boards.............................................1500
26.2.2 Parameters Specified for the Optical Ports of PDH Boards..............................................................1507
26.2.3 Common Parameters Specified for Optical Interfaces of Packet Boards..........................................1507
26.2.4 Common Parameters Specified for Optical Interfaces of Packet Boards..........................................1510
26.2.5 Common Parameters Specified for Optical Interfaces of Data Boards.............................................1511
26.3 Quick Reference of Board Functions.........................................................................................................1514
26.3.1 Information Quick Reference of SDH Boards...................................................................................1514
26.3.2 Information Quick Reference of PDH Boards...................................................................................1517
26.3.3 Information Quick Reference of Data Boards...................................................................................1518
26.3.4 Information Quick Reference of Packet Boards................................................................................1521
26.4 Loopback Capability of the Boards............................................................................................................1525
26.5 Protection Schemes Supported by Each Board..........................................................................................1535
26.6 Quick Reference of Power Consumption and Weight of Each Board........................................................1542
27 Parameter Settings.................................................................................................................1548
27.1 Packet Processing Boards...........................................................................................................................1550
27.1.1 General Attributes..............................................................................................................................1550
27.1.2 Flow Control......................................................................................................................................1551
27.1.3 Layer 2 Attributes..............................................................................................................................1552
27.1.4 Layer 3 Attributes..............................................................................................................................1554
27.1.5 Advanced Attributes..........................................................................................................................1555
27.2 EoD Boards.................................................................................................................................................1557
27.3 Packet Interface Boards..............................................................................................................................1557
27.3.1 SDH Parameters................................................................................................................................1558
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27.3.2 Channelized STM-1 Port...................................................................................................................1559

27.3.3 E1 Port...............................................................................................................................................1563
27.4 Data Boards................................................................................................................................................1566
27.4.1 SDH Parameters................................................................................................................................1566
27.4.2 Ethernet Parameters...........................................................................................................................1568
27.4.2.1 Basic Attributes........................................................................................................................1568
27.4.2.2 Flow Control.............................................................................................................................1569
27.4.2.3 Network Attributes...................................................................................................................1570
27.4.2.4 Advanced Attributes.................................................................................................................1571
27.4.2.5 TAG Attributes.........................................................................................................................1575
27.4.2.6 Encapsulation/Mapping............................................................................................................1576
27.4.2.7 Bound Paths..............................................................................................................................1577
27.4.3 ATM Parameters................................................................................................................................1578
27.5 SDH Processing Boards..............................................................................................................................1579
27.6 PDH Boards................................................................................................................................................1580
27.7 WDM Boards..............................................................................................................................................1582
27.8 Cross-Connect and Timing Units...............................................................................................................1590
27.9 Optical Amplifier Boards...........................................................................................................................1594
28 Task Collection......................................................................................................................1602
28.1 Querying the Protection Subnet..................................................................................................................1604
28.2 Troubleshooting Service Unavailability.....................................................................................................1604
28.3 Troubleshooting the Clock Tracing Failure................................................................................................1605
28.4 Configuring the F&f Debugging Serial Port and OAM NM Port..............................................................1606
28.5 Testing the Frequency Accuracy of the Free-Run Clock...........................................................................1607
28.6 Testing the Clock Holdover Accuracy.......................................................................................................1608
28.7 Checking Board Parameters.......................................................................................................................1609
28.8 Testing the SAN Service Channel..............................................................................................................1613
28.9 Testing the SDI Service Channel................................................................................................................1615
A Glossary....................................................................................................................................1617
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1 Equipment Structure
Equipment Structure
The OptiX OSN 3500 equipment consists of the cabinet, cabinet doors, DC power distribution
unit (PDU), subracks, orderwire phone fixing frame, boards, and cables. The OptiX OSN 3500
subrack can be installed in a 300 mm or 600 mm ETSI cabinet.
Figure 1-1 shows the appearance of the OptiX OSN 3500 that is installed in the 300 mm ETSI
cabinet.
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Figure 1-1 Appearance of the OptiX OSN 3500 that is installed in the 300 mm ETSI cabinet
1
7
7
7
H
D
1. DC PDU
2. Side panel
3. Cable distribution plate
4. Orderwire phone fixing frame
5. Subrack
6. Cabinet
7. Fiber management tray
8. Front door
Figure 1-2 shows the appearance of the general OptiX OSN 3500 subrack and enhanced OptiX
OSN 3500 subrack (1100 W).
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Figure 1-2 Appearance of the general OptiX OSN 3500 subrack and enhanced OptiX OSN 3500
subrack (1100 w)
4
1. Interface board area
2. Fan area
3. Processing board area
4. Cable routing area
Figure 1-3 shows the appearance of the OptiX OSN 3500 type III subrack (2300 W).
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Figure 1-3 Appearance of the OptiX OSN 3500 type III subrack (2300 W)
4
2. Fan area
NOTE
The difference between a general subrack and a type III subrack (2300 W) is with regard to applicable power
boards. With different power boards, the two types of subracks support different maximum power consumption
values.
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Cabinet
About This Chapter

Subracks are installed in a cabinet. OptiX OSN subracks need to be installed in appropriate
cabinets.
2.1 Types of Cabinets
The OptiX OSN 3500 subrack can be installed in the 300 mm or 600 mm ETSI cabinet.2600
mm high T63 cabinets are discontinued. For details, see the released product change notice.
2.2 Configuration of the Cabinet
An ETSI cabinet has indicators and a DC PDU at the top.
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2.1 Types of Cabinets

The OptiX OSN 3500 subrack can be installed in the 300 mm or 600 mm ETSI cabinet.2600
mm high T63 cabinets are discontinued. For details, see the released product change notice.
NOTE
The cabinets described in this topic are provided by Huawei.
The 300 mm ETSI cabinet is available in two types, namely, T63 cabinet and N63E cabinet.
Figure 2-1 shows the appearances of the T63 cabinet and N63E cabinet.
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Figure 2-1 Appearances of the T63 cabinet and N63E cabinet
T63 Cabinet
N63E Cabinet
Comparison Between the Specifications of the T63 Cabinet and the Specifications
of the N63E Cabinet
Table 2-1 describes the comparison between the specifications of the T63 cabinet and the
specifications of the N63E cabinet.
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Table 2-1 Comparison between the specifications of the T63 cabinet and the specifications of
the N63E cabinet
Cabinet
Dimensions (mm)
Weight (kg)
300 mm ETSI cabinet (T63)
600 (W) x 300 (D) x 2000 (H)
58
600 (W) x 300 (D) x 2200 (H)
63
600 (W) x 300 (D) x 2600 (H)
73
600 (W) x 300 (D) x 2000 (H)
41
600 (W) x 300 (D) x 2200 (H)
45
300 mm ETSI cabinet (N63E)
T63 Cabinet
The specifications of the T63 cabinet comply with the ETSI standard. The T63 cabinet is 600
mm wide and 300 mm deep.
There are two ground bolts on the frame at the top of the T63 cabinet. Figure 2-2 shows the
locations of the cable holes at the top of the T63 cabinet. Figure 2-3 shows the locations of the
cable holes at the bottom of the T63 cabinet.
Figure 2-2 Locations of the cable holes at the top of the T63 cabinet
600mm
200mm
106mm
Cabling hole
15mm
160mm
200mm
295mm
106mm
110mm
110mm
Power cable hole Cabniet grounding terminal
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Figure 2-3 Locations of the cable holes at the bottom of the T63 cabinet
600mm
106mm
Cabling hole
15mm
200mm
200mm
160mm
295mm
106mm
Cabniet installtion hole
110mm
Power cable hole
N63E Cabinet
The specifications of the N63E cabinet comply with the ETSI standard. The N63E cabinet is
600 mm wide and 300 mm deep.
There are two ground bolts on the frame at the top of the N63E cabinet. Figure 2-4 shows the
locations of the cable holes at the top of the N63E cabinet. Figure 2-5 shows the locations of
the cable holes at the bottom of the N63E cabinet.
Figure 2-4 Locations of the cable holes at the top of the N63E cabinet
Cable hole Cable hole
Cable hole Cable hole
600mm
143mm
155mm
62mm
81mm
188mm
300mm
66mm
251mm
Fiber hole
Grounding bolt
Fiber hole
Power cable hole
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Figure 2-5 Locations of the cable holes at the bottom of the N63E cabinet
Cable hole
Cable hole
184mm
360mm
Fiber hole
Fiber hole
CAUTION
The difference between the cable routing in the case of the T63 cabinet and the cable routing in
the case of the N63E cabinet is with regard to the cable routing at the top and bottom cable holes.
The cable routing in the T63 cabinet is the same as the cable routing in the N63E cabinet.
The T63 cabinet is approximately 16 mm deeper than the N63E cabinet. When you install the
mounting ears of the components, select proper mounting holes according to the type of cabinet
on site.
Enclosure Frame
Only the 2000 mm and 2200 mm high N63E cabinets are available. If the 2600 mm high N63E
cabinet is required, you need to place a 400 mm high enclosure frame on the top of the 2200
mm high N63E cabinet.
Figure 2-6 shows the picture and dimensions of the enclosure frame.
Figure 2-6 Picture and dimensions of the enclosure frame
60
0m
m
400mm
m
0m
0
3
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N66T Cabinet
The 600 mm ETSI cabinet is called the N66T cabinet. The N66T cabinet uses both the front and
rear columns, and it has a single front door and a single rear door. Figure 2-7 shows the
appearance of the N66T cabinet.
NOTE
The N66T cabinet supports back-to-back installation of one ordinary OptiX OSN 3500 subrack and one
enhanced OptiX OSN 3500 subrack (1,100 W).
Figure 2-7 Appearance of the N66T cabinet
Table 2-2 lists the specifications of the N66T cabinet.
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Table 2-2 Specifications of the N66T cabinet

Cabinet
Dimensions (mm)
Weight (kg)
N66T cabinet
600 (W) x 600 (D) x 2000 (H)
71
600 (W) x 600 (D) x 2200 (H)
76
There are two ground bolts on the frame at the top of the N66T cabinet. Figure 2-8 shows the
locations of the cable holes at the top of the N66T cabinet. Figure 2-9 shows the locations of
the cable holes at the bottom of the N66T cabinet.
Figure 2-8 Locations of the cable holes at the top of the N66T cabinet
600 mm
95 mm
95 mm
95 mm
215 mm
Cabling hole
17.8 mm
600 mm
95 mm
17.8 mm
224 mm
Power cable hole
Cabniet grounding terminal
224 mm
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Figure 2-9 Locations of the cable holes at the bottom of the N66T cabinet
Cabling hole
2.2 Configuration of the Cabinet

An ETSI cabinet has indicators and a DC PDU at the top.
Figure 2-10 shows the positions of the indicators and the DC PDU.
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Figure 2-10 ETSI cabinet

1
2
PowerCritical MajorMinor
Power distribution unit
H
W
1. Indicators
2. DC PDU
2.2.1 Indicators
The ETSI cabinet has one power indicator and three alarm severity indicators.
Table 2-3 describes the meanings of the status of the indicators.
Table 2-3 Meanings of the status of the indicators
Indicator
Status
Meaning
Power indicator - Power (green)
On
Power is supplied to the

equipment.
Off
Power is not supplied to

the equipment.
On
A critical alarm occurs

on the equipment.
Off
No critical alarm
occurs on the
equipment.
On
A major alarm occurs

on the equipment.
Off
No major alarm occurs

on the equipment.
Critical alarm indicator - Critical (red)
Major alarm indicator - Major (orange)
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Indicator
Status
Meaning
Minor alarm indicator - Minor (yellow)
On
A minor alarm occurs

on the equipment.
Off
No minor alarm occurs

on the equipment.
CAUTION
The status of the indicators is controlled by the AUX on the subrack. The indicators work only
after the cables of the indicators are correctly connected and the subrack is powered on.
2.2.2 DC Power Distribution Unit

The DC power distribution unit (PDU) is located on the top of a cabinet and is used to supply
power to the equipment.
DC Power Distribution Unit N1PDU

Figure 2-11 shows the front panel of the general cabinet DC PDU, N1PDU.
Figure 2-11 Front panel of the N1PDU
3
2
OUTPUT
2 3 4 5
ON
3
2
OUTPUT
ON
RTN1(+) RTN2(+) NEG1(-) NEG2(-)
OFF
32A
32A
20A
INPUT
OFF
20A
32A
32A
1. Terminal block (A)
2. Power ground cable RTN1(+)
3. Power ground cable RTN2(+)
4. Power cable NEG1(-)
5. Power cable NEG2(-)
6. Terminal block (B)
7. PGND
8. Power switch
20A
20A
In the case of the OptiX OSN 3500, the output terminal block on side A supplies power to the
power interface board on side A of the subrack, and the output terminal block on side B supplies
power to the power interface board on side B of the subrack. Table 2-4 shows the connections
of the output terminal blocks on side A and side B.
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Table 2-4 Connections of the output terminal blocks on side A and side B
Terminal
Block on
Side A
Corresponding Subrack
and Power Interface
Board
Terminal
Block on
Side B
Corresponding Subrack
and Power Interface
Board
Power interface board on

side A of the first subrack

side B of the first subrack

side A of the second subrack

side B of the second subrack

side A of the third subrack

side B of the third subrack

side A of the fourth subrack

side B of the fourth subrack
NOTE
In the case of an enhanced subrack, the two power inputs work in load-sharing mode (each input carries
16 A). In the telecommunications room, however, the PDU needs to provide power supply of 34 A to an
entire subrack. In the case of a general subrack, the two power inputs work in load-sharing mode (each
input carries 10 A). In the telecommunications room, however, the PDU needs to provide power supply of
20 A to an entire subrack. In this case, power failure will not occur if either of the power inputs fails.
CAUTION
In the case of the OptiX OSN 3500, the first and second terminal blocks are used. The third and
fourth terminal blocks supplies power to other equipment such as case-shaped optical amplifiers.
The number of the subracks increases from the bottom up.
NOTE
The DPD100-2-8 PDU can substitute for the N1PDU.
DC Power Distribution Unit DPD100-2-8 PDU

The DPD100-2-8 is installed at the top of the cabinet, and is divided into two parts, namely, part
A and part B that back up each other. Part A and part B each receive one -48 V power input and
provide four power outputs to subracks inside the cabinet.
Figure 2-12 and Figure 2-13 show the front panel of the DPD100-2-8 PDU.
Figure 2-12 Front panel of the DPD100-2-8 PDU (covered)
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Figure 2-13 Front panel of the DPD100-2-8 PDU (uncovered)
Power output area: On both sides of the DC PDU, there are respectively four output terminal
blocks that are used to connect to the power cables of subracks.
Power input area: INPUT A and INPUT B are each connected to one -48 V DC power cable
and one power ground cable, that is, two -48 V DC power cables and two power ground
cables in total.
Power switch area: On both sides of the DC PDU, there are respectively four power output
switches that correspond to the output terminal blocks. The power output switches control
power supply to the corresponding subracks.
DC Power Distribution Unit TN51PDU

The TN51PDU is installed at the top of the cabinet, and is divided into two parts, namely, part
A and part B that back up each other. Part A and part B respectively access four -48 V power
supplies. Among them:
l
Connections of main power supply: Part A is connected to RTN(+) and NEG(-).
Connections of standby power supply: Part B is connected to RTN(+) and NEG(-).

NOTE
RTN(+)s and NEG(-)s are located at the upper layer and lower layer of the power input area respectively.
The TN51PDU provides eight power output interfaces, supplying power to the subracks inside
the cabinet. Figure 2-14 shows the front panel of the TN51PDU.
Figure 2-14 Front panel of the TN51PDU
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Power input area: The TN51PDU supports corresponding power input capability based on
the power supply capacity of the telecommunications room.
When the telecommunications room provides four power inputs not less than 63 A, part
A and part B can respectively be connected to four -48 V DC power cables and four
power ground cables, that is, eight -48 V DC power cables and eight power ground
cables in total.
When the telecommunications room provides two power inputs not less than 125 A,
part A and part B can respectively be connected to two -48 V DC power cables and two
power ground cables, that is, four-48 V DC power cables and four power ground cables
in total.
DC Power Distribution Unit DPD63-8-8 PDU

The DPD63-8-8 PDU is installed at the top of the cabinet, and is divided into two parts, namely,
part A and part B that back up each other. Part A and part B each receive four -48 V power inputs
and provide four power outputs subracks inside the cabinet.
Figure 2-15 and Figure 2-16 show the front panel of the DPD63-8-8 PDU.
Figure 2-15 Front panel of the DPD63-8-8 PDU (covered)
Figure 2-16 Front panel of the DPD63-8-8 PDU (uncovered)
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Power input area: INPUT A and INPUT B are each connected to four -48 V DC power
cables and four power ground cables, that is, eight -48 V DC power cables and eight power
ground cables in total.
NOTE
Each of part A and part B needs to be connected to only two -48 V DC power cables and two power ground
cables.
The DPD63-8-8 PDU can substitute for the TN51PDU.
By default, one DPD63-8-8 PDU provides eight inputs and eight outputs. It can provide four inputs and
eight outputs with a short-circuiting copper bar installed.
Power Distribution Scheme

The DC PDU provides two groups (left and right) of power output at the same time. Table
2-5 lists the power distribution scheme of the N1PDU. Table 2-6 lists the power distribution
scheme of the TN51PDU. Table 2-7 lists the power distribution scheme of the DPD100-2-8
PDU.Table 2-8 lists the power distribution scheme of the DPD63-8-8 PDU.
Table 2-5 Power distribution scheme of the N1PDU
Input/
Output
Group
No.
Power
Ground
Cable
Remarks
Power input
INPUT
NEG1(-)
RTN1(+)
External power supply 1
NEG2(-)
RTN2(+)
32 A
power
supply
group
1(-)
1(+)
Two outputs, providing 1+1 hot backup

of 32 A power to the subrack
2(-)
2(+)

20 A
power
supply
group
3(-)
3(+)

4(-)
4(+)

Connected to the protection ground of

the cabinet
Power
output
Protection
ground
Table 2-6 Power distribution scheme of the TN51PDU
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Input/Output
Group No.
Remarks
Power input
(short-circuiting
INPUT A
Two 63 A power inputs and two 32 A power inputs

19

2 Cabinet
Input/Output
Group No.
Remarks
copper bar not

installed)
INPUT B
Power input
(short-circuiting
copper bar
installed)
INPUT A
One 125 A power input and two 32 A power inputs
INPUT B
One 125 A power input and two 32 A power inputs
Power output
63 A power
supply group
Four outputs, providing 1+1 hot backup of 63 A power

to the subrack
32 A power
supply group
Four outputs, providing 1+1 hot backup of 32 A power

to the subrack
Connected to the protection ground of the cabinet
Protection
ground
Table 2-7 Power distribution scheme of the DPD100-2-8 PDU

Input/Output
Group No.
Remarks
Power input
INPUT A
One 100 A power input
INPUT B
One 100 A power input
OUTPUT A
Four outputs, providing two 32 A power inputs and two

20 A power inputs to subracks
OUTPUT B
Four outputs, providing 1+1 hot backup for the two 32

A power inputs and two 20 A power inputs to subracks
Power output
Protection
ground
Table 2-8 Power distribution scheme of the DPD63-8-8 PDU
Issue 03 (2013-02-20)
Input/Output
Group No.
Remarks
Power input
(short-circuiting
copper bar not
installed)
INPUT A
INPUT B
Power input
(short-circuiting
copper bar
installed)
INPUT A
One 125 A power input and one 63 A power input
INPUT B
One 125 A power input and one 63 A power input
Power output
OUTPUT A
Four outputs, providing two 63 A power inputs and two

32 A power inputs to subracks

20

Input/Output
Protection
ground
2 Cabinet
Group No.
Remarks
OUTPUT B
Four outputs, providing 1+1 hot backup for the two 63

A power inputs and two 32 A power inputs to subracks
Technical Specifications
Table 2-9 Technical specifications of the PDU
Board
Dimensions
(mm)
Single-Cabinet
Input Voltage
(V)
Single-Cabinet
Output Voltage
(V)
Output
Current (A)
DPD100-2
-8 PDU
442 (W) x 79.6

(D) x 110 (H)
-48 (DC)
-38.4 to -57.6
-60 (DC)
-48 to -72
l 4x32 A
l 4x20 A
N1PDU
530 (W) x 97 (D)

x 133 (H)
-48 (DC)
-38.4 to -57.6
-60 (DC)
-48 to -72
-48 (DC)
-38.4 to -57.6
-60 (DC)
-48 to -72
-48 (DC)
-38.4 to -57.6
-60 (DC)
-48 to -72
DPD63-88 PDU
442 (W) x 79.6

(D) x 110 (H)
TN51PDU
535 (W) x 147

(D) x 133 (H)
l 4x32 A
l 4x20 A
l 4x63 A
l 4x32 A
l 4x63 A
l 4x32 A
NOTE
l Two power inputs that back up each other need to be provided, and they work in load-sharing mode.
l In the telecommunications room, it is required that the PDU needs to provide power supply for an
entire subrack. In this case, normal power supply can be guaranteed when either of the power inputs
fails.
2.2.3 Other Configurations

In addition to subracks, external case-shaped devices can be installed in a cabinet as required.
l
Uninterruptible power module (UPM)
Roman pump amplifiers RPC01 and RPC02
Orderwire phone
Dispersion compensation module (DCM)
Case-shaped optical amplifier (COA)
Fiber management tray
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3 Subrack
Subrack
About This Chapter

This topic describes the structure, capacity, slot layout, and technical specifications of the
subrack.
3.1 Subrack Structure
An OptiX OSN 3500 subrack has a two-layer structure. The subrack consists of a processing
board area, an interface board area, a fan area, and a cable routing area.
3.2 Slot Allocation
An OptiX OSN 3500 subrack consists of an upper layer and a lower layer. The upper layer,
where 19 slots are available, is the slot area for interface boards. The lower layer, where 18 slots
are available, is the slot area for processing boards.
3.3 Slot Access Capacity in Packet Mode
When different cross-connect boards are used, the access capacity of each slot on the equipment
varies.
3.4 Slot Access Capacity in TDM Mode
varies.
3.5 Ventilation Mode
The subrack of the equipment has many minute air vents and houses fans. The air enters from
the front and exits from the back, and the air flows from the bottom to the top. In this manner,
the equipment has good performance in heat dissipation.
3.6 Cable Management
This topic describes the function of the cable distribution plate and fiber spool box and the overall
scheme for cable routing.
3.7 Mapping Policies of Power Consumption
The increasing features supported by the equipment cause higher power consumption. To ensure
the normal operation of the equipment, the internal power supply system provides different
mapping policies of power consumption according to different power consumption
requirements.
3.8 Technical Specifications
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3 Subrack
The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.
Issue 03 (2013-02-20)

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3 Subrack
3.1 Subrack Structure

An OptiX OSN 3500 subrack has a two-layer structure. The subrack consists of a processing
board area, an interface board area, a fan area, and a cable routing area.
Figure 3-1 shows the structure of an OptiX OSN 3500 subrack.
Figure 3-1 Structure of an OptiX OSN 3500 subrack
2
3
5
4
H
W
2. Fan area
5. Mounting ear
The functions of the areas are as follows:

l
Interface board area: This area houses the interface boards of the OptiX OSN 3500.
Fan area: This area houses three fan modules, which dissipate heat generated by the
equipment.
Processing board area: This area houses the processing boards of the OptiX OSN 3500.
Cable routing area: This area houses fiber jumpers in a subrack.
Mounting ear: This mounting ear secures the subrack in a cabinet.

NOTE
An interface board is also called an access board or a transit board. An interface board provides physical
interfaces for optical signals and electrical signals, and transmits the optical signals or electrical signals to
the corresponding processing board.
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3 Subrack
3.2 Slot Allocation

An OptiX OSN 3500 subrack consists of an upper layer and a lower layer. The upper layer,
where 19 slots are available, is the slot area for interface boards. The lower layer, where 18 slots
are available, is the slot area for processing boards.
Figure 3-2 shows the slot layout of an OptiX OSN 3500 subrack.
Figure 3-2 Slot layout of an OptiX OSN 3500 subrack
S
L
O
T
1
9
S
L
O
T
2
0
S
L
O
T
2
1
S
L
O
T
2
2
S
L
O
T
2
3
S
L
O
T
2
4
S
L
O
T
2
5
S
L
O
T
2
6
S
L
O
T
2
7
S
L
O
T
2
8
P
I
U
P
I
U
S S S S
L L L L
O O O O
T T T T
2 3 4 5
S
L
O
T
3
0
S
L
O
T
6
S S
L L
O O
T T
7 8
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
3
7
S
L
O
T
3
6
A
U
X
FAN
SLOT 39
FAN
SLOT 38
S
L
O
T
1
S
L
O
T
2
9
S
L
O
T
9
S
L
O
T
1
0
X
C
S
X
C
S
S
L
O
T
1
1
FAN
SLOT 40
S S S S
L L L L
O O O O
T T T T
1 1 1 1
2 3 4 5
S
L
O
T
1
6
S
L
O
T
1
7
S
L
O
T
1
8
G
S
C
C
G
S
C
C
Fiber routing trough
Figure 3-3 shows the dual-slot layout of an OptiX OSN 3500 subrack.
Issue 03 (2013-02-20)

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3 Subrack
Figure 3-3 Dual-slot layout of an OptiX OSN 3500 subrack
S
L
O
T
1
9
S
L
O
T
2
0
S
L
O
T
2
1
S
L
O
T
2
2
S
L
O
T
2
4
S
L
O
T
2
3
S
L
O
T
2
5
S
L
O
T
2
6
S
L
O
T
2
7
S
L
O
T
2
8
P
I
U
P
I
U
S
L
O
T
3
S
L
O
T
5
S
L
O
T
3
0
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
7
S
L
O
T
3
5
S
L
O
T
3
4
S
L
O
T
3
7
S
L
O
T
3
6
A
U
X
FAN
SLOT 39
FAN
SLOT 38
S
L
O
T
1
S
L
O
T
2
9
S
L
O
T
9
S
L
O
T
1
0
X
C
S
X
C
S
S
L
O
T
1
1
FAN
SLOT 40
S
L
O
T
1
3
S
L
O
T
1
5
S
L
O
T
1
7
S
L
O
T
1
8
G
S
C
C
G
S
C
C
Fiber routing trough
Slot Area for Interface Boards

Slots for service interface boards: slots 19-26 and 29-36
Slot Area for Processing Boards

Slots for service processing boards: slots 1-8 and 11-17
Other Slots
l
Slots for cross-connect and timing boards: slots 9-10
Slots for system control and communication boards: slots 17-18 (slot 17 can also house a
processing board)
Slots for power interface boards: slots 27-28
Slot for an auxiliary interface board: slot 37
Slots for fan boards: slots 38-40
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3 Subrack
NOTE
In an OptiX OSN 3500 subrack, dual-slot boards and single-slot boards cannot be installed at the same
time.
Mapping Between Slots for Interface Boards and Slots for Processing Boards
Table 3-1 lists the mapping between slots for interface boards and slots for processing boards.
Table 3-1 Mapping between slots for interface boards and slots for processing boards
Slot for
Processing
Board
Dual-Slot for
Processing Board
Slot for Corresponding Interface Board
Slot 2
Slots 19 and 20
Slot 3
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slot 5
Slots 25 and 26
Slot 13
Slot 13
Slot 29 and 30
Slot 14
Slot 31 and 32
Slot 15
Slot 15
Slot 33 and 34
Slot 16
Slot 35 and 36
Paired Slots
If overhead bytes pass through the backplane bus between two slots, the two slots are called
paired slots. Paired slots achieves automatic transparent transmission of overhead bytes such as
K bytes, D bytes, and E1 overhead bytes. This improves multiplex section protection (MSP)
switching performance and protects orderwire and DCC communication with other NEs even
after the system control board on the local NE cannot be detected. Table 3-2 lists paired slots.
Table 3-2 Paired slots
Cross-Connect Capacity
Paired Slot
200 Gbit/s
(Slot 2, Slot 17)

(Slot 3, Slot 16)
(Slot 4, Slot 15)
(Slot 5, Slot 14)
(Slot 6, Slot 13)
(Slot 7, Slot 12)
(Slot 8, Slot 11)
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3 Subrack
3.3 Slot Access Capacity in Packet Mode

varies.
When the N1PSXCS board is used, one service processing board occupies two slots. In this case,
adjacent slots can be merged, as shown in Figure 3-4.
Figure 3-4 Slot access capacity of the OptiX OSN 3500 when the N1PSXCS board is used (dualslot)
S
L
O
T
1
3
S
L
O
T
1
5
S S
L L
O O
T T
1 1
7 8
GSCC
S
L
O
T
1
1
GSCC
10Gbit/s
S
L
O
T
1
0
7.5Gbit/s
10Gbit/s
S
L
O
T
9
10Gbit/s
S
L
O
T
7
10Gbit/s
S
L
O
T
5
XCS
S
L
O
T
3
FAN
XCS
S
L
O
T
1
7.5Gbit/s
FAN
5Gbit/s
FAN
Cable routing area
Figure 3-5 shows the slot access capacity of the OptiX OSN 3500 when the N2PSXCSA or
N3PSXCSA board is used.
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3 Subrack
Figure 3-5 Slot access capacity of the OptiX OSN 3500 when the N2PSXCSA/N3PSXCSA
board is used (single slots)
GSCC
GSCC
5Gbit/s
XCS
S S S S
L L L L
O O O O
T T T T
1 1 1 1
5 6 7 8
2.5Gbit/s
20Gbit/s
S
L
O
T
1
4
5Gbit/s
10Gbit/s
S S
L L
O O
T T
1 1
2 3
5Gbit/s
2.5Gbit/s
S
L
O
T
1
1
10Gbit/s
2.5Gbit/s
S
L
O
T
1
0
20Gbit/s
S
L
O
T
9
5Gbit/s
S
L
O
T
8
5Gbit/s
S
L
O
T
7
5Gbit/s
S S S S S
L L L L L
O O O O O
T T T T T
2 3 4 5 6
2.5Gbit/s
S
L
O
T
1
FAN
XCS
FAN
FAN
Cable routing
3.4 Slot Access Capacity in TDM Mode

varies.
Figure 3-6 shows the slot access capacity of the OptiX OSN 3500.
Figure 3-6 Slot access capacity of the OptiX OSN equipment
S
L
O
T
1
0
S
L
O
T
1
1
S S
L L
O O
T T
1 1
2 3
S
L
O
T
1
4
XCS
XCS
20Gbit/s
20Gbit/s
10Gbit/s
5Gbit/s
S S S S
L L L L
O O O O
T T T T
1 1 1 1
5 6 7 8
GSCC
S
L
O
T
9
5Gbit/s or GSCC
S
L
O
T
8
10Gbit/s
S
L
O
T
7
20Gbit/s
FAN
20Gbit/s
10Gbit/s
10Gbit/s
5Gbit/s
5Gbit/s
S S S S S
L L L L L
O O O O O
T T T T T
2 3 4 5 6
5Gbit/s
S
L
O
T
1
5Gbit/s
FAN
5Gbit/s
FAN
Cable routing
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3 Subrack
3.5 Ventilation Mode

The subrack of the equipment has many minute air vents and houses fans. The air enters from
the front and exits from the back, and the air flows from the bottom to the top. In this manner,
the equipment has good performance in heat dissipation.
NOTE
Make smooth ventilation of the air pipe of the cabinet. Do not block the air intake vents and air exhaust
vents of the subrack. Do not place any sundries in the upper part of the subrack to ensure that air can flow
through the subrack.
Figure 3-7 Ventilation mode of the OptiX OSN 3500
AIR OUT
AIR OUT
AIR OUT
AIR IN
NOTE
When the arrow color changes from a cool color to a warm color, air temperature increases.
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30

3 Subrack
3.6 Cable Management

This topic describes the function of the cable distribution plate and fiber spool box and the overall
scheme for cable routing.
Cable Distribution Plate

One subrack needs to have one cable distribution plate installed on its top. Figure 3-8 shows
the appearance of the cable distribution plate. The function of the cable distribution plate is to
fix the equipment cable to avoid the difficulty that the board may not be easily reseated or that
the air vents of the equipment are blocked and therefore the heat dissipation of the equipment
is poor.
Figure 3-8 Appearance of the cable distribution plate
Fiber Spool Box

The fiber spool box is used to coil the redundant optical fibers inside the cabinet, and is installed
under a subrack by default. Figure 3-9 shows the appearance of a fiber spool box.
Figure 3-9 Appearance of a fiber spool box
Cable-through
hole
Fiber spool
box
For the installation position of the fiber spool box and cable distribution plate in the cabinet, see
1 Equipment Structure.
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3 Subrack
Overall Scheme for Fiber Jumper Routing

l
The fiber jumpers of the equipment are routed through the front vertical columns at the two
sides of the cabinet.
The fiber jumpers of the equipment are led out through the fiber hole of the cabinet.
The fiber jumpers between the cabinet and the ODF are protected with a protection pipe.
The two ends of the protective pipe should be extended 10 cm into the cabinet and the ODF.
The fiber jumpers are secured smoothly and interconnected reliably in the ODF. The
redundant fiber jumpers are coiled tidily.
When the internal fiber jumpers are routed, the redundant fibers are coiled tidily in the fiber
spool box.
The routing and connection of the fiber jumpers should be consistent with the design. The
optical attenuators are added according to the requirements of the engineering design.
The bend radius of the fiber jumper must be greater than its minimum curvature radius.
Specifically, the minimum curvature radius for the 2 mm fiber jumper is 40 mm, and that
for the 3 mm fiber jumper is 60 mm.
Overall Scheme for Cable Routing

l
The external power cables and ground cables are arranged separately from the signal cables,
with a space more than 3 cm.
The power cables of the subrack are bundled under the cable distribution plate. The power
cables of the subrack are routed separately towards the back of the two sides of the cabinet,
and are routed along the back of the side panels to reach the power box.
The power cables of the IF board connect the IF power board to the IF board and are routed
through the cable-routing channel. If the IF power cable is redundant in the cable-routing
channel, bundle the redundant part of the power cable on the vertical column or at the cablerouting area on the side of the cabinet.
The method of routing the IF cables is the same as the method of routing the signal cables.
In the case of overhead cabling, the signal cables of the upper subrack are led out from the
cable-through holes in the top middle of the cabinet, and the signal cables of the lower
subrack are led out from the cable-through holes on the two sides of the top of the cabinet.
In the case of underfloor cabling, the signal cables of the upper and lower subracks are led
out from the cable-through holes on the two sides of the bottom of the cabinet.
3.7 Mapping Policies of Power Consumption

The increasing features supported by the equipment cause higher power consumption. To ensure
the normal operation of the equipment, the internal power supply system provides different
mapping policies of power consumption according to different power consumption
requirements.
The internal power supply system consists of PDU and PIU. Table 3-3 shows different mapping
policies of power consumption.
Issue 03 (2013-02-20)

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3 Subrack
Table 3-3 Mapping policies of power consumption on the OptiX OSN 3500
Type of
Subrac
k
Label of Subrack
Mappin
g PDU
Mappi
ng PIU
Mappin
g UPM
Maxim
um
Power
Consu
mption
Fuse
Capacit
y of
Circuit
Breaker
s in a
DC
PDU
Standard
OptiX
OSN
3500
subrack
N1PDU,
DPD100
-2-8
PDU
N1PIU,
N1PIU
A
EPS75-4
815AF
720 W
20 A
Enhance
d OptiX
OSN
3500
subrack
(1100
W)
N1PDU,
DPD100
-2-8
PDU
N1PIU
A
EPS75-4
815AF
1100 W
32 A
OptiX
OSN
3500
type III
subrack
(2300
W)
TN51PD
U,
DPD638-8 PDU
N1PIUB
EPS75-4
815AF
2300 W
63 A
CAUTION
When the type III subrack (2300 W) is configured with N1PDU/DPD100-2-8 PDU, the
maximum power consumption of the equipment is 1100 W. Therefore, it is recommended that
the type III subrack (2300 W) be configured with 51PDU/DPD63-8-8 PDU.
The service boards supported by various subracks are the same. However, for a specific type of
service board, the maximum number of boards that can be configured per subrack is related to
the power consumption of the subrack.
3.8 Technical Specifications

The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.
Table 3-4 lists the technical specifications of the OptiX OSN 3500 subrack.
Issue 03 (2013-02-20)

33

3 Subrack
Table 3-4 Technical specifications of the OptiX OSN 3500 subrack

Dimensions (mm)
Weight (kg)
497 (W) x 295 (D) x 722 (H)
23 (net weight of the subrack that is not

installed with boards or fans)
Table 3-5 lists the maximum power consumption of the OptiX OSN 3500 subrack.
Table 3-5 Maximum power consumption of the OptiX OSN 3500 subrack
Subrack
Type
Maximum
Power
Consumpt
iona
General
720 W
OptiX
OSN 3500
subrack
Fuse
Capaci
ty
Typical Configuration
Typical Power
Consumption
20 A
496 W
l Two N1SLD64 (S-64.2b, LC)

boards
l Two N2SLQ4 (S-4.1, LC)
boards
l Two N1SLQ16 (L-16.2, LC)
boards
l Two N1SLH1 (S-1.1, LC)
boards
l Four N1OU08 boards
l Two N2EGT2 boards
l Two N1PSXCS boards
l One N4GSCC board
l One N1AUX board
l Two N1PIU boards
Enhanced 1100 W
OptiX
OSN 3500
subrack
32 A
534 W
l Two N1SL64 (S-64.2b, LC)

boards
l Two N2SLQ4 (S-4.1, LC)
boards
l One N1SLT1 (S-1.1, LC)
board
l Two N1PEG8 boards
l Two N1PEX2 boards
l Two N1PETF8 boards
l Two N2PSXCSA boards
l One N1AUX board
l Two N1PIUA boards
Issue 03 (2013-02-20)

34

Subrack
Type
Maximum
Power
Consumpt
iona
OptiX
2300 W
OSN 3500
type-III
subrack
3 Subrack
Fuse
Capaci
ty
Typical Power
Consumption
63 A
718 W
l Five N1PEG8 boards

l Two N1PEX2 boards
l Two N2PEX1 boards
l Three N1PETF8 boards
l Two N2PSXCSA boards
l One N1AUX board
l Two N1PIUB boards
a: The maximum power consumption refers to the maximum power consumption

configuration that the subrack can support and the maximum heat dissipation capability of
the subrack. In the actual application, the value is much higher than the power consumption
of the subrack in typical configuration.
NOTE
The default maximum power consumption of the equipment is 1100 W. If the maximum power
consumption of the equipment needs to reach 2300 W, set the maximum power consumption parameter
on the NMS.
When the cabinet is fully loaded, the maximum power consumption is the sum of the maximum power
consumption of all subracks and the maximum power consumption of other configuration.
In the case of transmission equipment, power consumption is generally transformed into heat consumption.
Hence, heat consumption (BTU/h) and power consumption (W) can be converted to each other in the
formula: Heat consumption (BTU/h) = Power consumption (W) / 0.2931 (Wh).
Table 3-6 lists the predicted reliability specifications of the OptiX OSN equipment.
Table 3-6 Equipment predicted reliability
Issue 03 (2013-02-20)
System
Availability
Mean Time to Repair (MTTR)
Mean Time Between Failures

(MTBF)
0.9999964
1 hour
31.83 years

35

4 Overview of Boards
Overview of Boards
About This Chapter

This topic describes the appearances, dimensions, bar codes, and classification of the boards
used on the OptiX OSN systems.
4.1 Appearances and Dimensions of the Boards
Different boards have different appearances and dimensions.
4.2 Bar Codes of the Boards
The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
Issue 03 (2013-02-20)

36

4.1 Appearances and Dimensions of the Boards

Different boards have different appearances and dimensions.
Table 4-1 provides information about the appearances and dimensions of the boards used on
the OptiX OSN 3500.
Table 4-1 Appearances and dimensions of the boards used on the OptiX OSN 3500
Parameter
Appearance and Dimensions
Board
appearance
Board
classificatio
n
Optical interface board

(for example, SL16)
Service processing
board (for example,
PQ1)
Service interface board

(for example, D75S)
Height
(mm)
262.05
262.05
262.05
Depth (mm)
220
220
110
Width (mm)
25.4
25.4
22
Cross-connect and
timing board
System auxiliary
interface board (AUX)
Power interface board

(PIU)
Board
appearance
Board
classificatio
n
Issue 03 (2013-02-20)

37

Parameter
Appearance and Dimensions
Height
(mm)
262.05
262.05
262.05
Depth (mm)
220
110
110
Width (mm)
40
44
44
Board
appearance
Board
classificatio
n
Board that occupies two

slots (such as the
N1PEG16)
Height
(mm)
262.05
Depth (mm)
220
Width (mm)
50.8
Note: The figure in the right cell shows the three dimensions.
"H" and "W" indicate the height and width of the front panel
respectively and "D" indicates the depth of the printed circuit
board (PCB).
H
D
CAUTION
Wear an ESD wrist strap when holding a board. To prevent the static discharge from damaging
the board, ensure that the ESD wrist strap is grounded properly.
DANGER
Do not look directly at the optical interface board or optical interface. The laser beams inside
the fiber can damage your eyes.
Issue 03 (2013-02-20)

38

CAUTION
l A level optical module cannot be directly connected to an optical attenuator. If an optical
attenuator is required, use the attenuator on the optical distribution frame (ODF) side.
l If an optical attenuator is required, insert the attenuator in the IN interface instead of the OUT
interface.
l Add an attenuator when performing a loopback at an optical interface to prevent the optical
module from being damaged.
4.2 Bar Codes of the Boards

The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
Two types of bar codes are used for the boards of the OptiX OSN 3500, which are as follows:
l
16-digit manufacturing code + board version + board name + board feature code
20-digit manufacturing code + board version + board name + board feature code
The bar code is attached to the front panel of a board. Figure 4-1 shows the bar code with a 16digit manufacturing code.
Figure 4-1 Bar code of a board
Bar code
0364401055000015 -SSN3SL16A01
Last six digits of the BOM code

Internal code
Board version
Board name
5 Board feature code
Issue 03 (2013-02-20)

39

NOTE
The positions of bar codes vary according to boards. For details on the feature code of a board, see the
topic that describes the feature code of the board.
Issue 03 (2013-02-20)

40

5 Classification of Boards
Classification of Boards
Boards are functionally classified into cross-connect boards and system control boards, packet
processing boards, packet interface boards, SDH boards, PDH boards, WDM boards, optical
amplifier boards and dispersion compensation boards, auxiliary boards, and power boards.
NOTE
For details on the board version replacement relationship between boards, see 26.1 Board Version
Replacement in the Hardware Description.
Cross-Connect Boards and System Control Boards

Table 5-1 lists all cross-connect boards and system control boards and their applicable products.
Table 5-1 List of cross-connect boards and system control boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
TNN1SCA
System control and auxiliary

processing board
OptiX OSN 7500 II
TNN1PSXCS
Super Cross-connect and

Synchronous Timing Board
OptiX OSN 7500 II
T1PSXCSA
Super dual-plane crossconnect and synchronous

timing board
OptiX OSN 7500
N4GSCC,
N6GSCC
System Control and

Communication Board
OptiX OSN 7500, OptiX OSN 3500
N1PSXCS,
N2PSXCSA,
N3PSXCSA
Super Cross-connect and

Synchronous Timing Board
(supporting packet features)
OptiX OSN 3500
N1SXCSA
Super cross-connect and

synchronous timing board
(only applicable in TDM
mode)
OptiX OSN 3500

41

Board
Description
Applicable Product
R1PCXLN
SCC unit, cross-connect unit,

and optical interface unit
integrated board (supporting
the packet feature)
OptiX OSN 1500
Packet Processing Boards

Table 5-2 lists all packet processing boards and their applicable products.
Table 5-2 List of packet processing boards
Board
Description
Applicable Product
TNN1EX2
2x10GE processing board
OptiX OSN 7500 II
N1PEX2
2-port 10 Gigabit Ethernet

switching processing board
N1PEX1
1x10GE Ethernet processing

board
OptiX OSN 3500
N2PEX1
1x10GE Ethernet processing

board
N1PEG16
16xGE Ethernet processing

board
OptiX OSN 3500
TNN1EG8
8xGE processing board
OptiX OSN 7500 II
N1PEG8
8-Port Gigabit Ethernet

switching processing board
Q1PEGS2
OptiX OSN 1500A, OptiX OSN 1500B
R1PEGS1
R1PEFS8
8xFE processing board
R1PEF4F
4xFE optical processing

board
R1ML1
Multi-protocol 16xE1
electrical processing board
Packet Interface Boards

Table 5-3 lists all packet interface boards and their applicable products.
Issue 03 (2013-02-20)

42

Table 5-3 List of packet interface boards

Board
Description
Applicable Product
TNN1CO1
8-port channelized STM-1

CES optical interface board
OptiX OSN 7500 II
TNN1D75E
32-port 75-ohm E1 interface

board
OptiX OSN 7500 II
TNN1D12E
32-port 120-ohm E1
interface board
OptiX OSN 7500 II
TNN1ETMC
8xFE+4xFE/GE electrical
interface board
OptiX OSN 7500 II
TNN1AFO1
8-port ATM STM-1 service

interface board
OptiX OSN 7500 II
N1PEFF8
8xFE optical interface board
TNN1EFF8
8-port FE optical interface

board
OptiX OSN 7500 II
N1PETF8
8xFE electrical interface

board
N1MD12
interface board (120 ohms)
N1MD75
EoD Boards
Table 5-4 lists all EoD boards and their applicable products.
Table 5-4 List of EoD boards
Board
Description
Applicable Product
N1EDQ41
4-port 622/155 Mbit/s SDH

optical interface Ethernet
dual-mode multi-function
processing board
SDH Boards
Table 5-5 lists all SDH boards and their applicable products.
Issue 03 (2013-02-20)

43

Table 5-5 List of SDH boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
N4SLD64
2xSTM-64 optical interface

board
OptiX OSN 7500 II
N1SLD64

board
T2SL64,
T2SL64A

board
OptiX OSN 7500
N1SF64,
N1SF64A

board (with the forward error
correction (FEC) function)
N1SL64

board
N2SL64

board
OptiX OSN 3500
N4SL64

board
OptiX OSN 7500 II, OptiX OSN 7500,

OptiX OSN 3500
N4SLO16

board
OptiX OSN 7500 II
N1SLO16

board
N4SLQ16

board
OptiX OSN 7500 II
N1SLQ16,
N2SLQ16

board
N1SLD16

board
OptiX OSN 3500
N3SL16,
N3SL16A

board

OptiX OSN 3500, OptiX OSN 1500A,
OptiX OSN 1500B
N1SL16,
N1SL16A,
N2SL16,
N2SL16A

board
OptiX OSN 7500, OptiX OSN 3500,

N1SF16

board (with the outband FEC
function)

N3SLH41
16xSTM-4/STM-1 optical
interface board

OptiX OSN 3500

44

Issue 03 (2013-02-20)
Board
Description
Applicable Product
N3SLQ41
4xSTM-4/STM-1 optical
interface board

OptiX OSN 1500B
N1SLQ4,
N2SLQ4,
N1SLQ4A

board

N1SLD4,
N2SLD4,
N1SLD4A

board

R1SLD4

board (divided slot)
R1SL4

N1SL4, N2SL4,
N1SL4A

board

N1SLH1
16xSTM-1 signal processing

board

OptiX OSN 3500
N1SLT1

board

N1EU08
8xSTM-1 electrical interface

board

OptiX OSN 3500, OptiX OSN 1500B
N1OU08

board (LC)

N2OU08

board (SC)

OptiX OSN 1500B
N2SLO1,
N3SLO1

board

N1SLQ1,
N2SLQ1,
N1SLQ1A

board

R1SLQ1

N1EU04
4xSTM-1 electrical interface

board
N1MU04
4xE4/STM-1 electrical
interface board
OptiX OSN 1500B

45

Board
Description
Applicable Product
N1SEP1
2xSTM-1 line processing

board when interfaces are
available on the front panel

8xSTM-1 line processing

board when interfaces are
available on the
corresponding interface
board
N1SL1, N2SL1,
N1SL1A

board

R1SL1

PDH Boards
Table 5-6 lists all PDH boards and their applicable products.
Table 5-6 List of PDH boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
N1SPQ4
processing board
N2SPQ4
processing board

N1MU04
interface board

OptiX OSN 3500
N2PQ3
12xE3/T3 service processing

board

N1D34S
6xE3/T3 electrical switching

interface board

N1C34S
3xE3/T3 electrical switching

interface board

OptiX OSN 1500B
N1PD3, N2PD3

board

OptiX OSN 1500B
N1PL3, N2PL3

board

OptiX OSN 1500B
N1PL3A,
N2PL3A

board (Interfaces are
available on the front panel.)


46

Board
Description
Applicable Product
N1PQ1
63xE1 service processing

board

OptiX OSN 1500B
N2PQ1

board

N1PQM

board

N1D12B
32xE1/T1 electrical
switching interface board

N1D12S
32xE1/T1 electrical
(120 ohms)

N1D75S
32xE1 electrical switching


R1PD1, R2PD1

board
R1PL1

board
R1L12S
16xE1/T1 electrical
(120 ohms)
OptiX OSN 1500A
R1L75S
16xE1 electrical switching

OptiX OSN 1500A
N1PFL1
8xE1 optical processing

board

N1TSB8
8-port electrical switching

interface board

N1TSB4
4-port electrical switching

interface board
N1DX1
DDN service accessing and

converging board

OptiX OSN 1500B
N1DXA
DDN service converging and

processing board

N1DM12
DDN service interface board

OptiX OSN 1500B
EoS Boards
Table 5-7 lists all EoS boards and their applicable products.
Issue 03 (2013-02-20)

47

Table 5-7 List of EoS boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
N1EFT8
8xFE/16xFE transparent
transmission board

N1EFT8A
8xFE transparent
transmission board

N1EFS0A
16xFE switching and

processing board

OptiX OSN 1500B
N1EFS0
8xFE switching and

processing board
N2EFS0,
N4EFS0,
N5EFS0
8xFE switching and

processing board

OptiX OSN 1500B
N1EFS4,
N2EFS4,
N3EFS4
4xFE switching and

processing board

R1EFT4
4xFE transparent
transmission board (divided
slot)
N1EAS2
2x10GE Layer 2 switching

and processing board
N1EMS4
4xGE and 16xFE switching


N1EMS2
2xGE and 16xFE switching


N1EGS4,
N3EGS4,
N4EGS4
4xGE switching and

processing board

N1EGT2,
N2EGT2
2xGE transparent
transmission board

N2EGS2,
N3EGS2
2xGE switching and

processing board

N1EFF8,
N1EFF8A
8x100M Ethernet optical

interface board

OptiX OSN 1500B
N1ETF8,
N1ETF8A
8x100M Ethernet twistedpair interface board

OptiX OSN 1500B
N1ETS8
8x10/100M Ethernet twisted

pair interface switching
board

OptiX OSN 1500B

48

ATM Boards
Table 5-8 lists all ATM boards and their applicable products.
Table 5-8 List of ATM boards
Board
Description
Applicable Product
N1ADL4,
N1IDL4
1xSTM-4 ATM service

processing board

N1ADQ1,
N1IDQ1
4xSTM-1 ATM service

processing board

RPR Boards
Table 5-9 lists all PRP boards and their applicable products.
Table 5-9 List of RPR boards
Board
Description
Applicable Product
N2EGR2
2xGE ring processing board

N2EMR0
12xFE and 1xGE ring

processing board

SAN/Video Boards
Table 5-10 lists all SAN/video boards and their applicable products.
Table 5-10 List of SAN/video boards
Board
Description
Applicable Product
N1VST4
4-port video service

transparent transmission
board

N1MST4
4-port multi-service
transparent transmission
board

Microwave Boards
Table 5-11 lists all microwave boards and their applicable products.
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49

Table 5-11 List of microwave boards

Board
Description
Applicable Product
N1IFSD1
Dual-port IF board

N1RPWR
6-channel ODU power board

WDM Boards
Table 5-12 lists all WDM boards and their applicable products.
Table 5-12 List of WDM boards
Board
Description
Applicable Product
TN11CMR4
4-channel optical add/drop

multiplexing board

TN11CMR2,
TN11MR2,
N1MR2A,
N1MR2C

multiplexing board

N1MR2B

multiplexing board
TN11MR4
4-port optical add/drop

multiplexing board

OptiX OSN 1500B
N1CMD2
2-channel bidirectional
optical multiplexer and
demultiplexer board

N1LWX
Arbitrary bit rate wavelength

conversion board

N1FIB
Filter isolating board

Auxiliary Boards
Table 5-13 lists all auxiliary boards and their applicable products.
Table 5-13 List of auxiliary boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
T1EOW
Orderwire processing board
OptiX OSN 7500

50

Board
Description
Applicable Product
R1EOW
Orderwire processing board
T1AUX
System auxiliary interface

board
OptiX OSN 7500
N1AUX

board
OptiX OSN 3500
R1AUX,
R2AUX

board
R1AMU
Orderwire processing or
alarm cascading board
TN81FAN
Fan board
OptiX OSN 7500 II
N1FANA
Fan board (high power)
OptiX OSN 7500
N1FAN
Fan board
OptiX OSN 3500
R1FAN
Fan board
Optical Amplifier Boards and Dispersion Compensation Boards

Table 5-14 lists all optical amplifier boards and dispersion compensation boards and their
applicable products.
Table 5-14 List of optical amplifier boards and dispersion compensation boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
N1BPA
Optical booster and preamplifier board

N2BPA
Optical booster and preamplifier board

OptiX OSN 1500B
N1COA,
61COA, 62COA
Case-shaped optical
amplifier

N1DCU
Dispersion compensation
board
N2DCU
board

OptiX OSN 3500
TN11OBU1
Optical booster amplifier

board
TN12OBU1

board
OptiX OSN 7500 II

51

Board
Description
Applicable Product
N1BA2

board

N1RPC01
Forward Raman driving

board (external)

N1RPC02
Backward Raman driving

board (external)

Power Boards
Table 5-15 lists all power boards and their applicable products.
Table 5-15 List of power boards
Issue 03 (2013-02-20)
Board
Description
Applicable Product
TN81PIU
Uninterruptible power
module
OptiX OSN 7500 II
UPM
Uninterruptible power
module

T1PIU

(supporting standard
subracks)
OptiX OSN 7500
T1PIUB

(supporting type III subracks)
OptiX OSN 7500
N1PIUA

(supporting 1100 W
enhanced subrack.)
OptiX OSN 3500
N1PIUB

(supporting type III subracks)
OptiX OSN 3500
R1PIU

(supporting OptiX OSN
1500B subrack)
OptiX OSN 1500B
R1PIUA

(supporting OptiX OSN
1500A subrack)
OptiX OSN 1500A
R1PIUB

(supporting enhanced OptiX
OSN 1500B subrack)
OptiX OSN 1500B
R1PIUC

(supporting enhanced OptiX
OSN 1500A subrack)
OptiX OSN 1500A

52

6 Cross-Connect Boards and System Control Boards
Cross-Connect Boards and System Control

Boards
About This Chapter

This topic describes the system control boards and the cross-connect boards that have different
capacities.
6.1 SXCSA
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SXCSA (super cross-connect and synchronous timing board).
This topic also describes how to configure and commission the SXCSA.
6.2 PSXCS(A)
technical specifications of the PSXCS(A) (super dual-plane cross-connect and timing board).
This topic also describes how to configure and commission the PSXCS(A).
6.3 GSCC
technical specifications of the GSCC (system control and communication board). This topic also
describes how to configure and commission the GSCC.
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6.1 SXCSA
technical specifications of the SXCSA (super cross-connect and synchronous timing board).
This topic also describes how to configure and commission the SXCSA.
6.1.1 Version Description

The SXCSA is available in one functional version, namely, N1.
6.1.2 Application
The SXCSA is a super cross-connect and synchronous timing board. The SXCSA provides
service grooming and clock input/output functions in the OptiX OSN 3500 system.
The cross-connect and synchronous timing board provides the other boards in the system with
the timing information and grooms the services between line boards or tributary boards.
Figure 6-1 shows the position of the cross-connect and synchronous timing board in the OptiX
OSN system.
Figure 6-1 Position of the cross-connect and synchronous timing board in the system
Line
Line
SDH
Cross-connect and timing board
PDH
FE/GE
RPR
ATM
SAN
6.1.3 Functions and Features

The SXCSA grooms services and inputs/outputs clock signals.
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54

Cross-Connect Unit
Table 6-1 provides the functions and features of the cross-connect unit of the SXCSA.
Table 6-1 Functions and features of the cross-connect unit of the SXCSA
Function and
Feature
SXCSA
Basic functions
Realizes 200 Gbit/s higher order cross-connection at the VC-4 level

and 20 Gbit/s lower order cross-connection at the VC-3 or VC-12
level.
Service processing
l Supports the flexible service grooming and supports the fully nonblocking cross-connect, multicast, and broadcast services.
l Enables the communication between the SXCSA and the other
boards.
l Supports the tact switch and performs the protection switching
without interrupting services.
l Supports the SNCP protection at the VC-4-4c, VC-4-8c,
VC-4-16c, VC-4-64c, VC-4, VC-12, VC-3, and AU-3 levels.
l Supports VC-4-4c, VC-4-8c, VC-4-16c, and VC-4-64c
concatenation services.
l Supports a maximum of 40 linear MSP groups.
l Supports a maximum of 12 ring MSP groups.
l Supports a maximum of 2016 SNCP groups.
l Supports a maximum of 592 SNCMP groups.
l Supports a maximum of 512 SNCTP groups.
Protection schemes
Supports the 1+1 Hot Backup for the Cross-Connect and Timing
Units (non-revertive, by default).
Maintenance
features
Supports the PRBS function in the line direction.
Clock Unit
Table 6-2 provides the functions and features of the clock unit of the SXCSA.
Table 6-2 Functions and features of the clock unit of the SXCSA
Issue 03 (2013-02-20)
Function and
Feature
SXCSA
Basic functions
Provides the standard system synchronization clock.

55

Function and
Feature
SXCSA
Other functions
l Supports the processing of the S1 byte to realize the clock

protection switching.
l Supports the extraction, insertion, and management of the SSM
and clock ID.
l Provides the real-time clock (RTC).
l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
Input and output
l Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.
6.1.4 Working Principle and Signal Flow

The SXCSA consists of the synchronous timing module, cross-connect module, communication
and control module, and power module.
Figure 6-2 shows the functional block diagram of the SXCSA.
Figure 6-2 Functional block diagram of the SXCSA
Matrix
HPC
622 Mbit/s or 2.5 Gbit/s
SNCP
Service unit
LPC
Cross-connect module
T0
Communication
and conrol
module
38 MHz
OSC
Synchronous
timing module
(SETS)
T1
T2
T3
SETG
Clock external
output
T4
T0
Frame header
T0 (reference clock)
+3.3 V
Power
module
Communication
Power
module
Fuse
SCCunit
SDH unit
PDH unit
AUX
AUX
Service unit
Service unit
-48 V/-60 V
-48 V/-60 V
SETG: synchronous equipment timing generation function
Issue 03 (2013-02-20)

56

The functional modules of the cross-connect and synchronous timing boards are described
below.
Synchronous Timing Module

The synchronous timing module uses the centralized timing allocation mode as the clock mode.
The synchronous timing module also selects one clock source from reference clock sources as
the reference clock for the timing module. The reference clock sources are from the line board,
the tributary board, or the external synchronous clock source. The synchronous clock source and
2 Mbit/s or 2 MHz external synchronous clock source are then generated.
The precise 38 MHz oscillator ensures that the reference clock complies with ITU-T standards
in free-run mode.
The SDH clock (SETS) can work in the following modes:
l
Lock mode
Hold-over mode
Free-run mode
When working in lock mode, the SETS extracts the clock from three types of timing signals:
l
Timing signal (T1) from the STM-N line
Timing signal (T2) from the PDH line
Reference signal (T3) from the external synchronous clock source (2 MHz or 2 Mbit/s)
The timing module outputs the following timing signals:

l
T0, system clock
T4, external timing output signal (2 Mbit/s or 2 MHz)
Cross-Connect Module
The cross-connect module consists of two parts:
l
SNCP module, which tests relative alarms and reports the alarms to the software to trigger
the protection switching such as the SNCP switching and MSP switching.
Higher order and lower order cross-connect module, which performs the functions of higher
order and lower order cross-connect units.
Communication and Control Module

The communication and control module is a sub-system provided by the pinch board. It consists
of the CPU, register, Ethernet port, HDLC controller, FPGA loading controller, and bus driver.
This module is connected to external circuits through buses to manage and configure other units
of the boards.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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6.1.5 Front Panel

The front panel of the SXCSA has indicators and a bar code.
Diagram of the Front Panel

Figure 6-3 shows the appearance of the front panel of the SXCSA.
Figure 6-3 Front panel of the SXCSA
SXCSA
STAT
ACT
PROG
SRV
SYNC
SXCSA
Indicators
The front panel of the board has the following indicators:
l
Board hardware status indicator (STAT) two colors (red and green)
Service activation status indicator (ACT) one color (green)
Board software status indicator (PROG) two colors (red and green)
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58

Service alarm indicator (SRV) three colors (red, green, and yellow)
Synchronization clock status indicator (SYNC) two colors (red and green)
For the meanings of the status of the indicators, see 24 Indicators.
Interfaces
The front panel of the SXCSA has no interface. The AUX provides the SXCSA with the external
clock interface that can be set in 2048 kHz mode or 2048 kbit/s mode. The AUX provides two
BITS clock interfaces with 120-ohm or 75-ohm impedance. For details, see AUX.
6.1.6 Jumpers and DIP Switches

The SXCSA does not have any jumpers or DIP switches that are used for board settings.
6.1.7 Valid Slots

The SXCSA must be installed in a valid slot in the subrack. Otherwise, the SXCSA cannot work
normally.
The SXCSA can be installed in slots 9 and 10 in the subrack. By default, slot 9 houses the active
board and slot 10 houses the standby board.
6.1.8 Feature Code

The SXCSA does not have the feature code.
6.1.9 Configuring and Commissioning the Board

After you select a correct board, you need to configure and commission the board. The following
tasks need to be performed: checking the hardware of the board, configuring the board,
commissioning the board, and checking the operation of the board.
Checking the Hardware of the Board

Step 1 Required: Check the hardware of the board.
l The labels on the front panel of the board must be correct and clear.
l The daughter board of the board must be properly installed.
l All the components on both surfaces of the board must be available and intact.
Step 2 Required: Check whether the active board and standby board are installed in the correct slots.
Step 3 Required: Check whether the board is properly installed. The board must be pushed to the
bottom of the subrack along the guide rails, and the front panel of the board must be properly
locked. For the method for installing a board, see Replacing Boards Onsite.
Step 4 Required: Check the status of the indicators of the board when and after the board is powered
on. For the meanings of the status of the indicators, see 24 Indicators.
Step 5 Required: Check whether the version of the board software matches the version of the NE
software and the version of the U2000 software. Ensure that the version of the board software
is correct.
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59

Step 6 Required: Check the micro switch of the board. When the front panels of the active and standby
cross-connect boards are locked, the active/standby switching can be realized if you unlock the
front panel of the active board.
----End
Configuring the Board

Step 1 Add the logical board. For details, see Adding Boards.
Step 2 Set parameters for the XCS on the U2000. The following main parameters need to be set:
l Clock synchronization status
l Clock source priority
l Phase-locked source output by external clock
l Clock source switching
l Clock subnet configuration
For information about more parameters and the method for setting the parameters, see
Configuring Clocks.
----End
Commissioning the Board

Step 1 Optional: Test the frequency accuracy of the free-run clock. For details, see 28.5 Testing the
Frequency Accuracy of the Free-Run Clock.
Step 2 Optional: Test the clock holdover accuracy. For details, see 28.6 Testing the Clock Holdover
Accuracy.
Step 3 Required: Test the protection switching of the cross-connection. For details, see Testing the 1
+1 Protection of the Cross-Connect and Timing Board.
----End
Checking the Operation of the Board

Step 1 Required: Check the status of the indicators on the front panel of the board to ensure that the
board starts to work normally. When all the indicators are on and green, the board operates
normally. For the meanings of the status of the indicators, see 24.2 Alarm Indicators on the
Boards.
Step 2 Required: Query the alarms and performance events of the board. Modify the connections or
configurations of the board according to the alarms and performance events until the alarms are
cleared. For the method for querying the alarms and performance events of a board, see Viewing
the Current Alarms.
----End
6.1.10 Parameter Settings

You can set parameters for the SXCSA by using the U2000.
You can set the following parameters for the SXCSA by using the U2000:
Issue 03 (2013-02-20)

60

Clock synchronization status
Clock source priority
Clock source switching
Clock subnet configuration
Phase-locked source output by external clock
For the description of each parameter, see 27.8 Cross-Connect and Timing Units.
6.1.11 Maintaining the Board

This topic describes the alarms and faults that may occur when the board operates. This topic
also provides the methods and precautions to be taken for rectifying the faults.
Troubleshooting
Table 6-3 lists the faults that occur on the SXCSA frequently and the troubleshooting methods.
Table 6-3 Methods used to troubleshoot the faults that occur on the SXCSA frequently
Fault Symptom
Common Fault
Cause
Troubleshooting Method
Service unavailable
l The type of logical

board is not
consistent with the
type of the board
that is installed on
the NE.
See 28.2 Troubleshooting Service

Unavailability.
l The service
configuration is
incorrect.
l The running status
of the other boards
on the NE is
incorrect.
Clock tracing failure
l The clock source

priority table is
incorrectly
configured.
See 28.3 Troubleshooting the

Clock Tracing Failure.
Replacing the Board

For information on how to replace the SXCSA, see Replace a Cross-Connect and Timing Board.
NOTE
See General Precautions to get familiar with the precautions to be taken for replacing a board before you
replace the board.
Issue 03 (2013-02-20)

61

6.1.12 List of Alarms

This topic lists the alarms that may occur when the board operates. The alarms are reported
according to the logical board on the U2000.
6.1.12.1 Alarms of N1SXCSA

APS_FAIL
APS_INDI
BD_STATUS
CHIP_FAIL
BUS_ERR
CHIP_ABN
EXT_SYNC_LOS
CLK_NO_TRACE_MODE
COMMUN_FAIL
HSC_UNAVAIL
FPGA_ABN
HARD_BAD
LPS_UNI_BI_M
K1_K2_M
K2_M
NO_BD_SOFT
LTI
MS_APS_INDI_EX
PRBS_TEST
OOL
POWER_ABNORMAL
S1_SYN_CHANGE
SWITCH_DISABLE
SYN_BAD
SYNC_C_LOS
SYNC_F_M_SWITCH
SYNC_LOCKOFF
TEMP_OVER
TEST_STATUS
W_OFFLINE
NP1_SW_FAIL
W_R_FAIL
NP1_SW_INDI
TIME_FORCE_SWITCH
RPS_INDI
TIME_NO_TRACE_MOD
E
OTH_HARD_FAIL
TIME_LOS
EXT_TIME_LOC
PATCHFILE_NOTEXIST
OTH_BD_STATUS
PATCH_ERR
TIME_NOT_SUPPORT
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
6.1.13 List of Performance Events

None.
6.1.14 Technical Specifications

The technical specifications of the SXCSA include the cross-connect capacity, clock access
capability, mechanical specifications, and power consumption.
The cross-connect capacity of the SXCSA is as follows:
l
Issue 03 (2013-02-20)
Higher order cross-connect capacity: 200 Gbit/s

62

Lower order cross-connect capacity: 20 Gbit/s
Access capacity: 155 Gbit/s
Clock Access Capability

The clock access capability of the SXCSA is as follows:
l
External input clock: two channels of 2048 kbit/s or 2 MHz external clock signals
External output clock: two channels of 2048 kbit/s or 2 MHz external clock signals
Mechanical Specifications
The mechanical specifications of the SXCSA are as follows:
l
Dimensions (mm): 40 (W) x 220 (D) x 254.1 (H)
Weight (kg): 2.2
Power Consumption
The maximum power consumption of the SXCSA at room temperature (25C) is 63 W.
6.2 PSXCS(A)
technical specifications of the PSXCS(A) (super dual-plane cross-connect and timing board).
This topic also describes how to configure and commission the PSXCS(A).

PSXCS(A) is available in the following functional versions: N3PSXCSA, N1PSXCS and
N2PSXCSA.
Table 6-4 provides version description of PSXCS(A).
Table 6-4 Versions of the PSXCS(A) board
Issue 03 (2013-02-20)
Item
Description
Functional versions
PSXCS(A) is available in the following functional versions:

N1PSXCS, N2PSXCSA, and N3PSXCSA.

63

Item
Description
Differences
l Basic functions: packet data cross-connect capacity and

packet access capacity.
l Others:
N1PSXCS boards cannot work with single-slot packet
data boards.
N2PSXCSA/N3PSXCSA boards configured as
N1PSXCS cannot work with single-slot packet data
boards.
N2PSXCSA boards configured as N2PSXCSA cannot
work with two-slot packet data boards.
N3PSXCSA boards configured as N3PSXCSA or
N2PSXCSA cannot work with two-slot packet data
boards.
N2PSXCSA can substitute for N1PSXCS and N1SXCSA.
N3PSXCSA can substitute for N2PSXCSA, N1PSXCS, and
N1SXCSA.
Substitution
6.2.2 Application
The PSXCS(A) is a super cross-connect and synchronous timing board. The PSXCS(A) provides
service grooming and clock input/output functions in the OptiX OSN 3500 system.
The cross-connect and synchronous timing board provides the timing information to the other
boards in the system and grooms the services between SDH line boards, packet boards, or
tributary boards.
Figure 6-4 shows the position of The cross-connect and synchronous timing board in the system.
Figure 6-4 Position of the cross-connect and synchronous timing board in the system
Packet data
SDH/PDH
service
Higher order/
Lower order
cross-connect
unit
Packet data
Clock
unit
Packet data
processing
unit
Auxillary
unit
PIU
Auxillary
interface
-48 V/-60 V
XCS

The PSXCS(A) board grooms services and inputs/outputs clock signals.
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Cross-Connect Unit
Table 6-5 provides the functions and features of the cross-connect unit of the PSXCS(A) board.
Table 6-5 Functions and features of the cross-connect unit of the PSXCS(A)
Functions and
Features
Description
Basic functions
l The N1PSXCS board implements 200 Gbit/s higher order crossconnection at the VC-4 level, 20 Gbit/s lower order crossconnection at the VC-12 or VC-3 level, 80 Gbit/s packet data
cross-connect capacity and 60 Gbit/s packet access capacity.
l The N2PSXCSA/N3PSXCSA board implements 200 Gbit/s
higher order cross-connection at the VC-4 level, 20 Gbit/s lower
order cross-connection at the VC-12 or VC-3 level, 160 Gbit/s
packet data cross-connect capacity and 100 Gbit/s packet access
capacity.
Service processing
l Supports the flexible service grooming and supports the fully nonblocking cross-connect, multicast, and broadcast services.
l Communicates with other boards.
l Supports the tact switch and performs the protection switching
without service interruption.
l Supports the SNCP protection at the levels of VC-4-4c, VC-4-8c,
VC-4-16c, VC-4-64c, VC-4, VC-12, VC-3, and AU-3.
l Supports VC-4, VC-12, VC-3, and AU-3 services.
l Supports VC-4-4c, VC-4-8c, VC-4-16c, and VC-4-64c
l Supports a maximum of 40 linear MSP groups.
l Supports a maximum of 12 ring MSP groups.
l Supports a maximum of 8064 SNCP pairs.
l Supports a maximum of 592 SNCMP pairs.
l Supports a maximum of 512 SNCTP pairs.
Protection Scheme
Supports 1+1 hot standby. The default protection mode is the nonrevertive switching mode.
Maintenance
features
Supports the PRBS function in the line direction.
Others
Supports querying and reporting the working temperature of the

cross-connect and timing board and the entire equipment.
Clock Unit
Table 6-6 provides the functions and features of the clock unit of the PSXCS(A) board.
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Table 6-6 Functions and features of the clock unit of the PSXCS(A) board
Functions and
Features
Description
Basic functions
Provides the standard system synchronization clock.
Other functions
l Supports the processing of the S1 byte to perform clock protection

switching.
l Supports the extraction, insertion, and processing of the SSM and
clock ID.
l Supports the IEEE 1588v2 protocol.
l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
Input and output
l Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.

The PSXCS(A) consists of the higher order cross-connect matrix, lower order cross-connect
matrix, packet cross-connect matrix, communication and control module, clock unit, and power
module.
Figure 6-5 shows the functional block diagram of the PSXCS(A).
Figure 6-5 Functional block diagram of the PSXCS(A)
Backplane
Lower order crossconnect matrix
Higher order crossconnect matrix
Packet crossconnect matrix

+3.3 V
Clock unit
The board and system

Service unit/SCC unit/
AUX
Communication
and control unit
Power
module
Fuse
SCC unit
-48 V/-60 V
-48 V/-60 V
Higher Order Cross-Connect Matrix

Realizes higher order cross-connection at the VC-4 level.
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66

Lower Order Cross-Connect Matrix

Realizes lower order cross-connection at the VC-3 or VC-12 level.
Packet Cross-Connect Matrix

Cross-connects the packet data.

Communicates with the SCC unit and other boards, ensures communication with the other boards
when the GSCC cannot be detected, and generates the other control signals for the PSXCS and
system.
Clock Unit
The clock unit performs the following functions:
l
Traces external clock sources, line clock sources, or tributary clock sources, and provides
the PSXCS and the system with a synchronization clock source.
Through system timing, provides the nodes in the data stream of the system with the clock
signals that have proper frequency and phase. In this way, the components at each node
can meet the requirements regarding data setup and data holding during data receiving.
Provides the system with the frame indication signal that is used to indicate the position of
the frame header in the data.
Supports the IEEE 1588 V2 clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PSXCS require.
6.2.5 Front Panel

The front panel of the PSXCS(A) has indicators and a bar code.

Figure 6-6 shows the appearance of the front panel of the PSXCS(A).
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Figure 6-6 Front panel of the PSXCS(A)
PSXCS
PSXCSA
STAT
ACT
PROG
SRV
SYNC
STAT
ACT
PROG
SRV
SYNC
PSXCS
PSXCSA
N1PSXCS
N2PSXCSA/N3PSXCSA
Indicators
l
Board hardware status indicator (STAT) three colors (red, green, and yellow)
Synchronization clock status indicator (SYNC) two colors (red and green)
For the meanings of the status of the indicators, see 24.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the PSXCS(A) has no interface. The AUX provides the PSXCS(A) with the
external clock interface that can be set in 2048 kHz mode or 2048 kbit/s mode. The AUX provides
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68

two BITS clock interfaces with 120-ohm or 75-ohm impedance. For details, see the topic that
describes the interfaces of the AUX.

The PSXCS(A) does not have any jumpers or DIP switches that are used for board settings.
6.2.7 Valid Slots

The PSXCS(A) can be installed in slots 9 and 10 in the subrack.
By default, slot 9 is the slot for the working board, and slot 10 is the slot for the protection board.
6.2.8 Feature Code

The PSXCS(A) does not have the feature code.


is correct.
Step 6 Required: Check the micro switch of the board. When the front panels of the active and standby
cross-connect boards are locked, the active/standby switching can be realized if you unlock the
front panel of the active board.
----End

Step 1 Add the logical board. For details, see Adding Boards.
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69

Step 2 Set parameters for the XCS on the U2000. The following main parameters need to be set:
l Clock synchronization status
l Clock source priority
l Phase-locked source output by external clock
l Clock source switching
l Clock subnet configuration
For information about more parameters and the method for setting the parameters, see
Configuring Clocks.
----End

Step 1 Optional: Test the frequency accuracy of the free-run clock. For details, see 28.5 Testing the
Frequency Accuracy of the Free-Run Clock.
Step 2 Optional: Test the clock holdover accuracy. For details, see 28.6 Testing the Clock Holdover
Accuracy.
Step 3 Required: Test the protection switching of the cross-connection. For details, see Testing the 1
+1 Protection of the Cross-Connect and Timing Board.
----End

Boards.
the Current Alarms.
----End

You can set parameters for the PSXCS(A) by using the U2000.
You can set the following principal parameters for the PSXCS(A) by using the U2000:
l
Clock synchronization status
Clock source priority
Phase-locked source output by external clock
Clock source switching
Clock subnet configuration
For more parameters and the description of the parameters, see 27.8 Cross-Connect and Timing
Units.
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This topic describes the faults that may occur when the board operates. This topic also provides
the methods and precautions to be taken for rectifying the faults.
Troubleshooting
Table 6-7 lists the faults that occur on the PSXCS(A) frequently and the troubleshooting
methods.
Table 6-7 Methods used to troubleshoot the faults that occur on the PSXCS(A) frequently
Fault Symptom
Common Fault
Cause
Service unavailable
l The type of logical

board is not
consistent with the
type of the board
that is installed on
the NE.
See 28.2 Troubleshooting Service

Unavailability.
l The service
configuration is
incorrect.
l The running status
of the other boards
on the NE is
incorrect.
Clock tracing failure
l The clock source

priority table is
incorrectly
configured.
See 28.3 Troubleshooting the

Clock Tracing Failure.
Replacing the Board

For information on how to replace the PSXCS(A), see Replace a Cross-Connect and Timing
Board.
NOTE
replace the board.

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6.2.12.1 Alarms of N1PSCXS(A)

APS_FAIL
APS_INDI
BD_STATUS
BDID_ERROR
BUS_ERR
CHIP_ABN
CHIP_FAIL
CLK_NO_TRACE_MODE
COMMUN_FAIL
EXT_SYNC_LOS
FPGA_ABN
HARD_BAD
HSC_UNAVAIL
K1_K2_M
K2_M
LPS_UNI_BI_M
LTI
MS_APS_INDI_EX
NO_BD_SOFT
RPS_INDI
NP1_SW_FAIL
NP1_SW_INDI
OOL
OTH_BD_STATUS
OTH_HARD_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
PRBS_TEST
S1_SYN_CHANGE
SWITCH_DISABLE
SYN_BAD
SYNC_C_LOS
SYNC_F_M_SWITCH
SYNC_LOCKOFF
TEMP_OVER
TEST_STATUS
TIME_FORCE_SWITCH
TIME_LOS
TIME_NO_TRACE_MOD
E
W_OFFLINE
W_R_FAIL
EXT_TIME_LOC
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
TIME_NOT_SUPPORT
APS_MANUAL_STOP
APS_FAIL
APS_INDI
BD_STATUS
BDID_ERROR
BUS_ERR
CHIP_ABN
CHIP_FAIL
CLK_NO_TRACE_MODE
COMMUN_FAIL
EXT_SYNC_LOS
FPGA_ABN
HARD_BAD
HSC_UNAVAIL
K1_K2_M
K2_M
LPS_UNI_BI_M
LTI
MS_APS_INDI_EX
NO_BD_SOFT
RPS_INDI
NP1_SW_FAIL
NP1_SW_INDI
OOL
OTH_BD_STATUS
OTH_HARD_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
PRBS_TEST
S1_SYN_CHANGE
SWITCH_DISABLE
SYN_BAD
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72

SYNC_C_LOS
SYNC_F_M_SWITCH
SYNC_LOCKOFF
TEMP_OVER
TEST_STATUS
TIME_FORCE_SWITCH
TIME_LOS
TIME_NO_TRACE_MOD
E
W_OFFLINE
W_R_FAIL
EXT_TIME_LOC
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
TIME_NOT_SUPPORT
CES_K1_K2_M
CES_K2_M
CES_APS_INDI
CES_APS_FAIL
CES_MS_APS_INDI_EX
CES_LPS_UNI_BI_M
APS_MANUAL_STOP
APS_FAIL
APS_INDI
BD_STATUS
BDID_ERROR
BUS_ERR
CHIP_ABN
CHIP_FAIL
CLK_NO_TRACE_MODE
COMMUN_FAIL
EXT_SYNC_LOS
FPGA_ABN
HARD_BAD
HSC_UNAVAIL
K1_K2_M
K2_M
LPS_UNI_BI_M
LTI
MS_APS_INDI_EX
NO_BD_SOFT
RPS_INDI
NP1_SW_FAIL
NP1_SW_INDI
OOL
OTH_BD_STATUS
OTH_HARD_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
PRBS_TEST
S1_SYN_CHANGE
SWITCH_DISABLE
SYN_BAD
SYNC_C_LOS
SYNC_F_M_SWITCH
SYNC_LOCKOFF
TEMP_OVER
TEST_STATUS
TIME_FORCE_SWITCH
TIME_LOS
TIME_NO_TRACE_MOD
E
W_OFFLINE
W_R_FAIL
EXT_TIME_LOC
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
TIME_NOT_SUPPORT
CES_K1_K2_M
CES_K2_M
CES_APS_INDI
CES_APS_FAIL
CES_MS_APS_INDI_EX
CES_LPS_UNI_BI_M
APS_MANUAL_STOP
MPLS_PW_CSF
MPLS_PW_LCK
MPLS_PW_LOCK
MPLS_PW_OAMFAIL
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73


None.

The technical specifications of the PSXCS(A) include the cross-connect capacity, clock access
capability, mechanical specifications, and power consumption.
The cross-connect capacity of the N1PSXCS is as follows:
l
Packet switching capability: 80 Gbit/s
Access capacity:
TDM mode: 155 Gbit/s
Packet mode: 60 Gbit/s
The cross-connect capacity of the N2PSXCSA/N3PSXCSA is as follows:

l
Packet switching capability: 160 Gbit/s
Access capacity:
TDM mode: 155 Gbit/s
Packet mode: 100 Gbit/s
Clock Access Capability

The clock access capability of the PSXCS(A) is as follows:
l
External input clock: two channels of 2048 kbit/s or 2 MHz external clock signals
External output clock: two channels of 2048 kbit/s or 2 MHz external clock signals
The mechanical specifications of the N1PSXCS are as follows:
l
Weight (kg): 2.1
The mechanical specifications of the N2PSXCSA are as follows:

l
Weight (kg): 1.2
The mechanical specifications of the N3PSXCSA are as follows:

l
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74

Weight (kg): 1.5
Power Consumption
The maximum power consumption of the N1PSXCS at room temperature (25C) is 90 W.
The maximum power consumption of the N2PSXCSA at room temperature (25C) is 80 W.
The maximum power consumption of the N3PSXCSA at room temperature (25C) is 74 W.
6.3 GSCC
technical specifications of the GSCC (system control and communication board). This topic also
describes how to configure and commission the GSCC.

The GSCC is available in several functional versions. The functions provided by the functional
versions are different.
Table 6-8 describes the versions of the GSCC.
Table 6-8 Versions of the GSCC
Item
Description
Function
al
versions
The GSCC is available in the following functional versions: N4 and N6.
Differen
ces
Packet performance specifications differ between the N4GSCC and the N6GSCC.
For details, see Packet System Performance.
Substitut
ion
The GSCC boards of different versions cannot directly substitute for each other.
If the GSCC of a later version needs to substitute for the GSCC of an earlier
version, the NE software needs to be upgraded accordingly.
6.3.2 Application
The GSCC is the intelligent system control board. The GSCC works with the U2000 to manage
the boards on the equipment and realize the communication between different pieces of
equipment.
Figure 6-7 shows the position of the GSCC in the system.
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Figure 6-7 Position of the GSCC in the system

Auxiliary interface
Auxiliary unit
SCC unit
Other boards
PIU
-48 V/-60 V

The GSCC supports the system control, orderwire, communication, and system power supply
monitoring.
Table 6-9 provides the functions and features of the GSCC.
Table 6-9 Functions and features of the GSCC
Function and
Feature
GSCC
Basic functions
Performs the service configuration function and service grooming

function, monitors the service performance, and collects information
about the performance events and alarms.
Interfaces
l Provides the 10M/100M Ethernet port, which is used for

communicating with the NMS. The Ethernet port is accessed through
the AUX.
l Provides the F&f interface, which is accessed through the AUX and
is used to manage the COA.
l Provides one 64 kbit/s synchronous data port F1, which is accessed
through the AUX.
l Provides the RS232 OAM interface, which is used for connecting a
PC or workstation, and supports the remote maintenance by using a
modem that uses the RS232 DCE interface. The OAM interface is
accessed through the AUX.
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DCC
communication
Processes 160 DCCs (D1D3). In this manner, the link is provided for
transmitting the NM information.
Overhead
processing
Processes the E1, E2, F1, and serial14 bytes.

76

Function and
Feature
GSCC
Clock function
l Provides the RTC.
l Supports the high-precision clock synchronization feature, and

complies with the IEEE 1588 V2 protocol. The N4GSCC receives the
time information through interfaces S1S4 of the AUX. The S1, S3
and ALMI4 interfaces receive the first channel of time information,
and the S2, S4 and ALMI4 interfaces receive the second channel of
time information.
l Supports service performance monitoring and collects information
about the performance events and alarms.
Alarms and
maintenance
features
l Provides 16 alarm inputs and four alarm outputs through the AUX.
l Controls the four cabinet indicators through the AUX.
l Supports intelligent fan speed control and manages the fan alarms.
l Supports simulation package loading and diffused loading.
l Supports the function of detecting whether a packet data board is in
position.
Power supply
management
l Supports the monitoring of the 48 V or 60 V power supply.
Protection
schemes
Supports the 1+1 Hot Backup for the SCC Unit. When the active board
is faulty, services are switched to the standby board automatically.
l Supports the in-service check function for the PIU board and supports
the failure check function for the lightning protection module of the
PIU.
NOTE
In packet mode, two N4GSCC/N6GSCC boards are configured as 1+1 backup by
default.
Packet function
The N4GSCC and N6GSCC support the packet function.

For information about the performance of the packet system, see Packet
System Performance.

The GSCC consists of the communication and control module, OHP module, and power module.
Figure 6-8 shows the functional block diagram of the GSCC.
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Figure 6-8 Functional block diagram of the GSCC

Other
units
V1
V2
Phone
S1-S4
F1
OH
manager
OHP
OHP module
Reset
ALM CUT
Boot
ROM
RAM
Communication
and control
module
AUX interface
16-input/4-output
alarm control
ETH port
OAM interface
F&f interface
COM interface
NVRAM
Flash
PIU
interface
Power
module
AUX power monitor

and reset control
AUX unit
Input/Output alarm
ETH
OAM
F&f
COM
Control of subrack
indicators
Inter-board
communication
Power monitor
PIU test
Other
units
PIU unit
-48 V/-60 V

The communication and control module controls and manages the boards, realizes the
communication between NEs, manages the network, and performs other functions.
l
The system control module communicates with the boards in the subrack, manages the
boards, monitors the performance events and alarms of the boards, collects the status
information about the other functional modules, and performs the corresponding
management operations.
The communication and control module provides the function that NEs communicate with
each other through DCCs. The communication module transfers the OAM information to
other NEs through DCCs, reports the alarms and performance data of the equipment to the
network management terminal, and responds to the commands issued by the network
management terminal.
The communication and control module configures and operates the NE.
NOTE
The service protection is realized by the cross-connect and timing board. When services are switched, the
switching event is reported to the GSCC, which then reports the switching event to the NMS.
When the communication and control module fails, the following situations occur:
l
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Communication failure
78

The communication and control module cannot manage the boards in the subrack, monitor
the performance events and alarms of the boards, collect the status information about the
other functional modules, or perform the corresponding management operations.
l
DCC failure
The communication and control module cannot transfer the OAM information to other NEs
through the local NE, report the alarms and performance data of the equipment to the
network management terminal, or respond to the commands issued by the network
management terminal.
OHP Module
l
Receives overhead signals from the line slot.
Processes such bytes as E1, E2, F1 and serial14serial
Sends overhead signals to the line board.
Provides the following external interfaces:

One orderwire interface
Two SDH NNI audio interfaces
Interface F1
Broadcast data ports serial14serial
Figure 6-9 shows the orderwire bytes in the SDH frame.

Figure 6-9 Position of these orderwire bytes in the SDH frame
A1
A1
A1
A2
A2
A2
J0
B1
E1
F1
D1
D2
D3
Serial 1 Serial2
AU_PTR
B2
B2
D4
Serial 4
K1
K2
D5
D6
D7
D8
D9
D10
D11
D12
S1
B2
M1
Serial3
E2
Power Module
require.
6.3.5 Front Panel

The front panel of the GSCC has indicators and a bar code.
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79


Figure 6-10 shows the appearance of the N4GSCC/N6GSCC.
Figure 6-10 Front panel of the N4GSCC/N6GSCC
GSCC
STAT
ACT
PROG
SRV
PWRA
PWRB
PWRC
ALMC
RESET
ALM CUT
GSCC
Indicators
l
48 V power supply indicator of channel A (PWRA) two colors (red and green)
48 V power supply indicator of channel B (PWRB) two colors (red and green)
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80

+3.3 V backup power supply indicator of the system (PWRC) two colors (red and green)
Alarm mute indicator (ALMC) one color (yellow)
Interfaces
The front panel of the GSCC has no interface. The AUX provides interfaces for the GSCC. For
details, see AUX.
The front panel of the N4GSCC/N6GSCC has one warm reset switch and one alarm cut switch.
Table 6-10 describes the types and usage of the switches
Table 6-10 Types and usage of the switches of the GSCC
Switch
Type of
Switch
Usage
RESET
Warm reset
switch
Press the switch to perform a warm reset for the SCC unit.
ALM CUT
Alarm cut
switch
Press the switch to mute the alarm. Press the switch for five
seconds to mute the alarm permanently. Press the switch
again for five seconds to resume the alarm sound.

The GSCC has jumpers, which are used to set the input voltage and running state of the
equipment.
CAUTION
The jumpers are used for test and maintenance. Do not change the setting of jumpers at random.
Otherwise, the board may become faulty.
N4GSCC
Figure 6-11 shows the layout of the J2101, J7100, J3201, and J3202 jumpers on the N4GSCC.
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81

Figure 6-11 Position of the jumpers of the N4GSCC

Power
module
J3202
J3201
CPU
J7100
J2101
1
2
3
Table 6-11 lists the jumpers of the N4GSCC.

Table 6-11 Jumpers of the N4GSCC
Jumper
Function
Description
J2101
To enable the
battery
12: If jumper bits (positions) 1 and 2 are capped, the

database and clock are cleared.
battery is enabled. It is the default state.
J7100
To set the running

state of the board
Jumper J7100 is a group of two-pin jumpers located in

five rows. The jumper in the lowest row is reserved and
does not need to be set. In the case of the jumpers in the
top four rows, the value of a jumper bit is defined as
follows:
If a jumper bit is not capped, the value is 0.
If a jumper bit is capped, the value is 1.
The jumper bit values are queued from bottom to top
and from the higher bit to the lower bit, and form a fourbit binary number. For details, refer to Table 6-12.
J3202 and
J3201
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To set the input

voltage of the
equipment
When the jumpers are not capped, the equipment is

supplied with the 60 V power.
When the jumpers are capped, the equipment is
supplied with the 48 V power. It is the default state.

82

CAUTION
Set J3202 and J3201 correctly based on the power voltage provided in the telecommunications
room. If J3202 and J3201 are set incorrectly, the POWER_ABNORMAL alarm is generated.
Table 6-12 Jumper J7100

Value
Description
0b0000
Indicates the running state when the watchdog is started. It is the default
state.
0b0001
Changes to the self-test state of the SDRAM Burst.
0b0011
Indicates the commissioning state.
0b0100
Indicates the running state when the watchdog is stopped.
0b0101
The software is in the BIOS state. The SCC does not work even though
the NE software exists. The IP address of the parameter area, however,
is not changed, which is for querying.
0b0110
The software enters the exhibition mode.
0b1001
Indicates the running state when the watchdog is started.
0b1011
Erases the database.
0b1100
Erases the NE software, including the patches.
0b1101
Erases the database and NE software, including the patches.
0b1110
Erases the database, NE software, and NE.ini file.
0b1111
Erases the extended BIOS and system parameter area in the file system
and flash memory.
N6GSCC
Figure 6-12 shows the layout of the J18, J11, J30, and J31 jumpers on the N6GSCC.
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83

Figure 6-12 Position of the jumpers of the N6GSCC
Power
module
J30
321
J31
32 1
CPU
J18
1 23
J11
Table 6-13 lists the jumpers of the N6GSCC.

Table 6-13 Jumpers of the N6GSCC
Jumper
Function
Description
J18
To enable the
battery

database and clock are cleared.
battery is enabled. It is the default state.
J11
To set the running

state of the board
Jumper J11 is a group of two-pin jumpers located in

five rows. The jumper in the left-most row is reserved
and does not need to be set. In the case of the jumpers
in the right four rows, the value of a jumper bit is
defined as follows:
If a jumper bit is not capped, the value is 0.
If a jumper bit is capped, the value is 1.
The jumper bit values are queued from left to right and
from the higher bit to the lower bit, and form a four-bit
binary number. For details, refer to Table 6-14.
Issue 03 (2013-02-20)

84

Jumper
Function
Description
J30 and J31
To set the input

voltage of the
equipment
23 or jumpers are not capped: If jumper bits

(positions) 2 and 3 are capped or jumpers are not
capped, the equipment is supplied with the 60 V
power.
equipment is supplied with the 48 V power. It is the
default state.
CAUTION
Set J30 and J31 correctly based on the power voltage provided in the telecommunications room.
If J30 and J31 are set incorrectly, the POWER_ABNORMAL alarm is generated.
Table 6-14 Jumper J11
Value
Description
0b0000
Indicates the running state when the watchdog is started. It is the default
state.
0b0001
Changes to the self-test state of the SDRAM Burst.
0b0011
Indicates the commissioning state.
0b0100
Indicates the running state when the watchdog is stopped.
0b0101
The software is in the BIOS state. The SCC does not work even though
the NE software exists. The IP address of the parameter area, however,
is not changed, which is for querying.
0b0110
The software enters the exhibition mode.
0b1001
Indicates the running state when the watchdog is started.
0b1011
Erases the database.
0b1100
Erases the NE software, including the patches.
0b1101
Erases the database and NE software, including the patches.
0b1110
Erases the database, NE software, and NE.ini file.
0b1111
Erases the extended BIOS and system parameter area in the file system
and flash memory.
6.3.7 Valid Slots

The GSCC must be installed in a valid slot in the subrack. Otherwise, the GSCC cannot work
normally.
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85

The GSCC can be installed in slots 17 and 18 in the subrack. By default, slot 18 houses the active
board and slot 17 houses the standby board.
6.3.8 Feature Code

The GSCC does not have the feature code.


is correct.
Step 6 Required: Check the status of the ALM switch.
1.
Press the switch to mute the current alarm sound.
2.
Press the switch for five seconds to mute the alarm sound permanently. In this case, the
alarm mute indicator (ALMC) turns on (in yellow).
3.
Press the switch again for five seconds to resume the alarm sound. In this case, the ALMC
indicator turns off.
----End

Step 1 Required: Add the logical board. For details, see Adding Boards.
Step 2 Required: If the parameter settings of the GSCC are available on the U2000, download the
parameter settings to the GSCC. Otherwise, perform the following operations:
l Set the NE ID. For details, see Setting the NE ID.
l Set the NE name, date, and time. For details, see Setting the NE Name, Date, and Time.
----End
Issue 03 (2013-02-20)

86


Step 1 Check the setting of the jumper that controls the debugging status of the board. For the
description of the jumper, see 6.3.6 Jumpers and DIP Switches.
Step 2 Check and commission the circuit status on the data ports, including the F&f debugging serial
port and OAM NM port. For details, see 28.4 Configuring the F&f Debugging Serial Port
and OAM NM Port.
Step 3 Check the configurations of the data ports.
l For the configuration of the broadcast data port, see Configuring the Broadcast Data
Service.
l For the configuration of the F1 codirectional data port, see Configuring the F1 Data
Service.
----End

Boards.
the Current Alarms.
----End

You can set parameters for the GSCC by using the U2000.
You can set the following parameters for the GSCC by using the U2000:
l
NE ID
NE name, date, and time
F&f debugging serial port
OAM NM port
Broadcast data port
F1 data port

Troubleshooting
Table 6-15 lists the faults that occur on the GSCC frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

87

Table 6-15 Methods used to troubleshoot the faults that occur on the GSCC frequently
Fault Symptom
Common Fault Cause
ECC failure
l The running status of

the board becomes
abnormal.
l Check whether the running status of

the board is correct. See 24.2
Alarm Indicators on the Boards
to obtain the meanings of the status
of the indicators.
l The optical fibers are

incorrectly
connected.
l Check whether the optical fibers are

correctly connected.
Power supply alarm
The jumper that controls

the input voltage is
incorrectly set.
For information on how to set the

jumper, see 6.3.6 Jumpers and DIP
Switches.
Connection failure
between the NMS
computer and the
equipment
l An incorrect
network cable is
used to connect the
NMS computer to
the equipment.
l For information on the connection

of the network cable, see Checking
Connection Between the U2000
Computer and the Equipment.
l The IP address of the

NMS computer and
the IP address of the
equipment are not in
the same network
segment.
Repetitive GSCC resets
The GSCC is faulty.
l Ensure that the IP address of the

NMS computer and the IP address
of the equipment are correctly set.
For details, see Setting the IP
Address of the PC.
Replace the GSCC. For information on

how to replace the GSCC, see
Replacing a GSCC Board.
Replacing the Board

NOTE
replace the board.
For information on how to replace the GSCC, see Replacing a GSCC Board.

6.3.12.1 Alarms of N4GSCC
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APS_MANUAL_STOP
BD_AT_LOWPOWER
BD_NOT_INSTALLED
BD_STATUS
BOOTROM_BAD
CFCARD_FAILED

88

CFCARD_OFFLINE
CFCARD_W_R_DISABLED
CHIP_ABN
COMMUN_FAIL
DBMS_ERROR
DBMS_PROTECT_MODE
LAN_LOC
FPGA_ABN
HARD_BAD
SYSLOG_COMM_FAIL
MSSW_DIFFERENT
NE_POWER_OVER
NESF_LOST
NESTATE_INSTALL
PATCH_ACT_TIMEOUT
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
POWER_FAIL
REG_MM
RINGMAPM_MM
RTC_FAIL
SECU_ALM
SQUTABM_MM
SWDL_ACTIVATED_TI
MEOUT
SWDL_AUTOMATCH_INH
SWDL_INPROCESS
SWDL_CHGMNG_NOMATCH
SWDL_COMMIT_FAIL
SWDL_NEPKGCHECK
SWDL_ROLLBACK_FAI
L
SYNC_FAIL
TEMP_OVER
WRG_FANTYPE
WRG_BD_TYPE
CFCARD_FULL
BIOS_STATUS
DCC_CHAN_LACK
PATCH_PKGERR
NP1_MANUAL_STOP
STORM_CUR_QUENUM_O
VER
PATCH_DEACT_TIMEOUT
Ext_COMM_FAIL
LCS_DAYS_OF_GRACE
LCS_EXPIRED
LCS_FILE_NOT_EXIST
FEATURE_WITHOUT_LICENSE
SYNC_DISABLE
DCNSIZE_OVER
MEM_OVER
CPC_NODE_ID_ERR
SWDL_PKG_NOBDSOFT
CES_APS_MANUAL_STOP
PASSWORD_NEED_CH
ANGE
DB_RESTORE_FAIL
DBMS_DELETE
NTP_SYNC_FAIL
SSL_CERT_NOENC
SEC_RADIUS_FAIL
APS_MANUAL_STOP
BD_AT_LOWPOWER
BD_NOT_INSTALLED
BD_STATUS
BOOTROM_BAD
CFCARD_FAILED
6.3.12.2 Alarms of N6GSCC
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89

CFCARD_OFFLINE
CFCARD_W_R_DISABLED
CHIP_ABN
COMMUN_FAIL
DBMS_ERROR
DBMS_PROTECT_MODE
LAN_LOC
FPGA_ABN
HARD_BAD
SYSLOG_COMM_FAIL
MSSW_DIFFERENT
NE_POWER_OVER
NESF_LOST
NESTATE_INSTALL
PATCH_ACT_TIMEOUT
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
POWER_FAIL
REG_MM
RINGMAPM_MM
RTC_FAIL
SECU_ALM
SQUTABM_MM
SWDL_ACTIVATED_TI
MEOUT
SWDL_AUTOMATCH_INH
SWDL_INPROCESS
SWDL_CHGMNG_NOMATCH
SWDL_COMMIT_FAIL
SWDL_NEPKGCHECK
SWDL_ROLLBACK_FAI
L
SYNC_FAIL
TEMP_OVER
WRG_FANTYPE
WRG_BD_TYPE
CFCARD_FULL
BIOS_STATUS
DCC_CHAN_LACK
PATCH_PKGERR
NP1_MANUAL_STOP
STORM_CUR_QUENUM_O
VER
PATCH_DEACT_TIMEOUT
Ext_COMM_FAIL
LCS_DAYS_OF_GRACE
LCS_EXPIRED
LCS_FILE_NOT_EXIST
FEATURE_WITHOUT_LICENSE
SYNC_DISABLE
DCNSIZE_OVER
MEM_OVER
CPC_NODE_ID_ERR
SWDL_PKG_NOBDSOFT
CES_APS_MANUAL_STOP
PASSWORD_NEED_CH
ANGE
DB_RESTORE_FAIL
DBMS_DELETE
NTP_SYNC_FAIL
SSL_CERT_NOENC
SEC_RADIUS_FAIL

This topic lists the performance events that may occur when the board operates. The performance
events are reported according to the logical board on the U2000.
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90

6.3.13.1 Performance Events of N4GSCC

XCSTMPMAX
XCSTMPMIN
XCSTMPCUR
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR
6.3.13.2 Performance Events of N6GSCC

XCSTMPMAX
XCSTMPMIN
XCSTMPCUR
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR

The technical specifications of the GSCC include the mechanical specifications and power
consumption.
The mechanical specifications of the GSCC are as follows:
l
Dimensions (mm): 25.4 (W) x 220 (D) x 254.1 (H)
Weight of the N4GSCC (kg): 1.0
Weight of the N6GSCC (kg): 0.9
Power Consumption
The maximum power consumption of the N4GSCC at room temperature (25C) is 19 W.
The maximum power consumption of the N6GSCC at room temperature (25C) is 35 W.
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91

7 Packet Processing Boards
Packet Processing Boards
About This Chapter

The packet processing boards include the PEX1, PEX2, PEG16, and PEG8. They achieve the
packet switching function in the packet domain.
7.1 PEX1
technical specifications of the PEX1 (1x10GE Ethernet processing board). This topic also
describes how to configure and commission the PEX1.
7.2 PEX2
technical specifications of the PEX2 (2-port 10 Gigabit Ethernet switching processing board).
This topic also describes how to configure and commission the PEX2.
7.3 PEG8
technical specifications of the PEG8 (8-Port Gigabit Ethernet switching processing board). This
topic also describes how to configure and commission the PEG8
7.4 PEG16
technical specifications of the PEG16 (16xGE Ethernet processing board). This topic also
describes how to configure and commission the PEG16.
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92

7.1 PEX1
technical specifications of the PEX1 (1x10GE Ethernet processing board). This topic also
describes how to configure and commission the PEX1.

The PEX1 is available in N1 and N2.
Table 7-1 describes the versions of the PEX1.
Table 7-1 Versions of the PEX1
Item
Description
Functional versions
The PEX1 is available in two functional versions, namely, N1

and N2.
Differences
l Regarding interface specifications: interface types,

working modes
l Regarding service specifications: tunnel specifications,
Ethernet service capability
l Regarding protection schemes: MPLS PW APS, MCLAG
l Regarding clock synchronization: IEEE 1588v2
l Regarding maintenance features: MPLS OAM, loopback
capability
l Regarding other points: The N1PEX1 occupies two slots,
but the N2PEX1 occupies only one slot. Therefore, the
N1PEX1 and N2PEX1 boards cannot be used
interchangeably.
Substitution
None
7.1.2 Application
The PEX1 is mainly used in the packet data transmission field to transmit/receive data packets,
manage bandwidths, and realize switching of data packets.
Figure 7-1 shows the typical networking and application of the PEX1. The PEX1 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM domain can be overlapped with the packet domain
on the OptiX OSN equipment to transmit data in the two domains. In this way, the equipment
realizes the smooth evolution from the MSTP network to the packet switching network.
Issue 03 (2013-02-20)

93

Figure 7-1 Networking and application of the PEX1

OptiX OSN 3500/
7500
NMS
OptiX OSN 3500/

7500
OptiX OSN 3500/

7500
PSN
10GE ring
OptiX OSN 1500
OptiX OSN 1500

PSN
GE ring
OptiX OSN 1500
PSN
GE ring
OptiX OSN
3500/7500
OptiX OSN 1500
Traffic direction
FE interface board/FE processing board
GE convergence board
GE processing board
10GE processing board
Dual-domain (TDM domain and packet

domain) cross-connect board
PSN: packet switched network

The PEX1 processes and forwards 1x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
Table 7-2 provides the functions and features of the PEX1.
Table 7-2 Functions and features of the PEX1
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Provides one 10GE optical interface and receives/transmits and processes 1x10 GE
services independently.

94

Funct
ion
and
Featu
re
Description
Interfa
ce
types
l N1PEX1 supports 10GBASE-SR (LAN), 10GBASE-SW (WAN), 10GBASELR (LAN), 10GBASE-LW (WAN), 10GBASE-ER (LAN), 10GBASE-EW
(WAN), 10GBASE-ZR (LAN), and 10GBASE-ZW (WAN) Ethernet optical
interfaces. The optical interface uses the LC connector and supports the
transmission distances of 0.3 km, 10 km, 40 km, and 80 km.
l (N2PEX1) Supports the 10GBASE-LR (LAN), 10GBASE-ER (LAN), and
10GBASE-ZR (LAN) Ethernet optical interfaces. The optical interface uses the
LC connector and supports the transmission distances of 10 km, 40 km, and 80
km.
l (N2PEX1) Supports the CWDM and DWDM colored optical interfaces. The
optical interface uses the LC connector. The CWDM optical interface supports
the transmission distance of 70 km. The DWDM optical interface supports the
transmission distance of 40/80 km.
Functi
ons
when
being
used
with
an
interfa
ce
board
Does not support an interface board, and has one 10GE interface on its front panel.
Interfa
ce
charac
teristic
s
Hot
optical
module
swappin
g
Supports hot swapping of XFP optical modules.
Workin
g modes
10GE full-duplex
Supports the configuration of the LAN mode or WAN mode for the port
on the N1PEX1. The default mode of the port is the LAN mode. The
N2PEX1 supports only the LAN mode.
Flow
control
at ports
Autonegotiation
mode
Not supported
Nonautonegotia
tion mode
Not supported by the N1PEX1 but supported by the

N2PEX1
Query/
Setting
of port
status
Issue 03 (2013-02-20)
Supported

95

Funct
ion
and
Featu
re
Servic
e
specifi
cation
s
Description
Query
of
interfac
e types
Supported
Setting
of
optical
power
threshol
ds
Supported
Processi
ng
capabili
ty
Processes 10 Gbit/s services in full-duplex mode.
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported
Maximum
number of
PWs
16k
MS-PW
Supports static switching of MS-PWs.
Unidirectio
nal
Number of unidirectional MPLS tunnels (with tunnels

shared):
PW
specific
ations
Tunnel
specific
ations
N1PEX1: 4k
N2PEX1:
l When working with the N4GSCC: 4k
Bidirection
al
Number of bidirectional MPLS tunnels (with tunnels

shared):
N1PEX1: 2k
N2PEX1:
Issue 03 (2013-02-20)

96

Funct
ion
and
Featu
re
Description
MTU
MTU for
ports
l The N1PEX1 supports the setting of the packet length,

which ranges from 960 bytes to 9600 bytes. After the
setting becomes valid, the length of the packets that
enter or exit the ports is restricted by the pre-set MTU.
l The N2PEX1 supports the setting of the packet length,
setting becomes valid, the length of the packets that
enter or exit the ports is restricted by the pre-set MTU.
Ethernet
service
capabili
ty
Protec
tion
schem
es
Issue 03 (2013-02-20)
MPLS
Tunnel
APS
MTU for
services
For packet services carried by PWs, the PEX1 supports

the setting of the packet length, which ranges from 64
bytes to 9000 bytes; for packet services carried in other
modes, the N1PEX1 supports the setting of the packet
length, which ranges from 64 bytes to 9000 bytes, but the
N2PEX1 does not support the setting of the packet length.
E-Line
service
Number of supported E-Line services:

E-LAN
service
Number of supported E-LAN services: 1020.

Number of static MAC addresses in E-LAN services: 2k
E-AGGR
service
The N1PEX1 supports four E-AGGR services, each of

which supports 127 leaf ports; the N2PEX1 does not
support E-AGGR services.
Formats of
Ethernet
data frames
Supports the encapsulation in IEEE 802.3 format, Ethernet

II format, or IEEE 802.1q/p format.
Maximum
number of
QinQ links
1k
Maximum
number of
VLANs
4k
Jumbo
frame
Supports the Jumbo frame with a length not more than

9600 bytes.
Supports the 1+1 (single-ended/dual-ended) and 1:1 (dual-ended) MPLS

Tunnel APS.
Number of supported MPLS Tunnel APS protection groups: 1k.

97

Funct
ion
and
Featu
re
Description
MPLS
PW
APS

PW APS (only on the N2PEX1).
Supports PW FPS (single-ended) MPLS PW APS (only on the
N2PEX1).
Supports a maximum of 1k MPLS PW APS protection groups, and a PW
protection group can bind a maximum of 512 members (only on the
N2PEX1).
NOTE
MPLS PW APS and MPLS Tunnel APS share the protection resources.
LAG
l Supports manual link aggregation and static link aggregation.

l Supports the load sharing mode and load non-sharing mode.
l Complies with IEEE 802.3ad and IEEE 802.1AX.
Issue 03 (2013-02-20)
MCLAG
Supported only on N2PEX1 boards, which complies with IEEE 802.3ad

and IEEE 802.1AX.
Multipl
e
spannin
g tree
protocol
(MSTP)
Not supported
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Supports one channel of synchronous Ethernet clock signals.
IEEE
1588v2
Supports one channel of the IEEE 1588v2 clock (only on the

N2PEX1).
Maint
enanc
e
featur
es
ETH
OAM
IEEE
802.1ag
Supports CC, LB, LT, LM and 2DM.
IEEE
802.3ah
Supports OAM auto-discovery, remote loopback, fault

diagnosis, and link performance monitoring.

98

Funct
ion
and
Featu
re
Description
MPLS
OAM
MPLS
tunnel
OAM
Supports CV, FFD, BDI, FDI, MPLS Tunnel ping, and

MPLS Tunnel traceroute in compliance with ITU-T Y.
1711.
Number of MPLS tunnels that support OAM: 2k
NOTE
The N1PEX1 supports only the MPLS Tunnel OAM function.
MPLS PW
OAM
Supports CV, FFD, BDI, FDI, PW ping and PW

traceroute in compliance with ITU-T Y.1711. The number
of supported MPLS PW OAM is 2k.
NOTE
MPLS tunnel OAM and MPLS PW OAM share resources. Only
the N2PEX1 support the MPLS PW OAM function.
Loopba
ck
capabili
ty
RMON
perform
ance
Issue 03 (2013-02-20)
PHY layer
at Ethernet
ports
N1PEX1:
MAC layer
at Ethernet
ports
N1PEX1:
Inloops and outloops at the PHY layer of Ethernet ports

N2PEX1: does not support loopbacks at the PHY layer of
Ethernet ports.
Inloops at the MAC layer at Ethernet ports

N2PEX1: Supports inloops and outloops at the MAC layer
at Ethernet ports.
Supported
Inban
d
DCN
Supported
HQoS
Provides the HQoS function, including the scheduling function at multiple levels
for the flow queue and port queue and the bandwidth restricting function, and
provides the corresponding statistical information.
IGMP
snoopi
ng
Supported
Query
of
electro
nic
labels
Supported

99


The PEX1 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
temperature and voltage detecting module, clock module, and power module.
Figure 7-2 shows the functional block diagram of the PEX1.
Figure 7-2 Functional block diagram of the PEX1
Backplane
Two system clock signals
Working clock
Modules of the board
IEEE 1588 V2 packet

Synchronous Ethernet clock
1x10GE signals
Data processing
module
Packet forwarding
module
Network processing
module
Service
signal
Upstream transmission
module

Service Upstream scheduling
module
signal
Downstream
transmission module
Downstream
scheduling module
Transmission
management module
Switching network
buffering module
Parallel management bus
CPU
management
module
PSXCSA
IEEE 1588 V2 packet
Clock
module
PSXCSA
PSXCSA
Service
signal
PSXCSA
Data backup bus

Inter-board communication bus
GSCC
GSCC

Logic control
module
Modules of the
board
Temperature and voltage

detecting signals
Temperature and
voltage detecting
signals
- 48V / - 60 V
Power
module
- 48V / - 60 V
Receive Direction
The network processing module receives the 10xGE optical signals, decodes the signals, and
converts the serial signals into parallel signals. Then, the network processing module performs
route searching or address matching for the data packets, and transmits the corresponding packets
to the transmission management module. The transmission management module buffers and
grooms the packets, slices the packets into cells that the switching network requires, and sends
the cells to the switching network buffering module. The switching network buffering module
buffers the cells and sends the cells to the cross-connect unit.
Transmit Direction
The switching network buffering module processes the cells sent by the cross-connect unit and
sends the cells to the transmission management module. The transmission management module
rearranges the cells to form packets, performs buffering and QoS management for the packets,
and sends the packets to the network processing module. The network processing module
converts the parallel signals into serial signals and sends the signals to the 10xGE optical
interface.
Issue 03 (2013-02-20)

100

Network Processing Module

The network processing module performs route searching, address matching, and other functions
for data packets. The network processing module of the PEX1 can process the 10 Gbit/s data
packets in full-duplex mode.
Transmission Management Module

The transmission management module slices packets into cells, and performs QoS management
and large volume buffering for the cells.
l
QoS management: The transmission management module provides the scheduling function
at five levels including the flow queue and port queue, the bandwidth restricting function,
and the corresponding statistical information.
Large volume buffering: The transmission management module supports traffic of 10 Gbit/
s and can buffer data for 17 ms in both the upstream direction and downstream direction.
Switching Network Buffering Module

The switching network buffering module performs cell buffering, queue management,
scheduling, and other functions. This module and the cross-connect unit form a three-level
switching network to switch cells.
CPU Management Module

The CPU management module provides the parallel management bus, Ethernet bus, and other
buses to manage the modules of the PEX1. The CPU management module also monitors alarms
and performance events and reports the alarms and performance events to the SCC unit.
Logic Control Module

The logic control module controls the logic of the PEX1. The PEX1 occupies two slots. Each
board part that occupies one slot has the control part. The control logic of the PEX1 is realized
on the board part that occupies the slot with a smaller slot number between the two slots that
house the PEX1.
Temperature and Voltage Detecting Module

The temperature and voltage detecting module monitors the temperature and voltage.
Clock Module
The clock module performs the following functions:
l
Provides the clock signal for each module of the PEX1.
Supports the synchronous Ethernet clock.
Power Module
the PEX1 require.
Issue 03 (2013-02-20)

101

7.1.5 Front Panel

The front panel of the PEX1 has indicators, an interface, a bar code, and a laser safety class label.

Figure 7-3 shows the appearance of the front panel of the N1PEX1.
Figure 7-3 Front panel of the N1PEX1
PEX1
STAT
ACT
PROG
SRV
LINK
ACT
CLASS 1
LASER
PRODUCT
OUT1
IN1
PEX1
Figure 7-4 shows the appearance of the N2PEX1.
Issue 03 (2013-02-20)

102

Figure 7-4 Front panel of the N2PEX1
PEX1
STAT
ACT
PROG
SRV
LINK
ACT
CLASS 1
LASER
PRODUCT
OUT1
IN1
PEX1
Indicators
l
Connection status indicator (LINK) one color (green)
Data receiving and transmission indicator (ACT) one color (orange)
Issue 03 (2013-02-20)

103

Interfaces
The front panel of the PEX1 has one optical interface. Table 7-3 describes the type and usage
of the optical interface of the PEX1.
Table 7-3 Optical interface of the PEX1
Interface
Type of Interface
Usage
IN1
LC (pluggable)
Receives 10GE signals.
OUT1
LC (pluggable)
Transmits 10GE signals.

The PEX1 does not have any jumpers or DIP switches that are used for board settings.
7.1.7 Valid Slots

The PEX1 must be installed in a valid slot in the subrack. Otherwise, the PEX1 fails to work
normally.
The N1PEX1 occupies two slots, and it can be installed in slots 18, and 1116. The PEX1 slot
displayed on the U2000 is the slot that has a smaller slot number between the two slots that house
the PEX1. For example, if the PEX1 is installed in slots 1 and 2, the PEX1 slot displayed on the
U2000 is slot 1. The mapping relationships between the valid slots for the PEX1 and the allocated
bandwidths are as follows:
l
Slot 1: 5 Gbit/s
Slot 3: 7.5 Gbit/s
Slot 5, 7, 11, or 13: 10 Gbit/s
Slot 15: 7.5 Gbit/s
Table 7-4 lists the slots valid for the PEX1 and the corresponding logical slots of the N1PEX1
on the U2000.
Table 7-4 Slots valid for the N1PEX1 and the corresponding logical slots of the N1PEX1 on
the U2000
Issue 03 (2013-02-20)
Slot Valid for the PEX1
Corresponding Logical Slot
Slots 1 and 2
Slot 1
Slots 3 and 4
Slot 3
Slots 5 and 6
Slot 5
Slots 7 and 8
Slot 7
Slots 11 and 12
Slot 11
Slots 13 and 14
Slot 13

104

Slot Valid for the PEX1
Slots 15 and 16
Slot 15
The N2PEX1 occupies one slot, and it can be installed in slots 18, and 1116. The mapping
relationships between the valid slots for the N2PEX1 and the allocated bandwidths are as
follows:
l
Slots 13, and 16: 2.5 Gbit/s
Slots 46, and 1315: 5 Gbit/s
Slots 7 and 12: 10 Gbit/s
Slots 8 and 11: 20 Gbit/s

NOTE
l Two-slot boards can work only with cross-connect boards whose logical boards are N1PSXCS.
l One-slot boards cannot work with cross-connect boards whose logical boards are N1PSXCS.
l Two-slot boards and one-slot boards cannot be configured at the same time.
l When working with an EDQ41 board, a two-slot board cannot be installed in slot 1 or slot 15.
7.1.8 Feature Code

The PEX1 does not have the feature code.


Step 2 Required: Check and record the bandwidth and slot information of the board.
Step 3 Required: Check whether the cable matches the board. Ensure that the cable matches the board.
is correct.
----End
Issue 03 (2013-02-20)

105


Step 2 Optional: Configure the inband DCN. For details, see Configuring the Inband DCN.
Step 3 Required: Set the Ethernet interface as follows:
l Port enabled/disabled: When you configure services on a port of the Ethernet board, the port
must be set to Enabled.
l Working mode: Generally, the Ethernet interfaces of the interconnected equipment are
required to work in the same fixed working mode. If the working modes on two sides do not
match, packets may be lost or the bit rate may decrease. In the case of large volume of traffic,
services may be completely interrupted.
For details, see Parameter Description.
NOTE
For more information about the parameters of the board, see 27.1 Packet Processing Boards.
Step 4 Required: Configure services. The following Ethernet services can be configured according to
actual requirements:
l Configure the E-line service. For details, see Configuring E-Line Services.
l Configure the E-LAN service. For details, see Configuring E-LAN Services.
l Configure the E-AGGR service (only on the N1PEX1). For details, see Configuring E-AGGR
Services.
Step 5 Optional: Configure the MPLS OAM. For details, see Configuring the MPLS OAM.
Step 6 Optional: Configure the MPLS tunnel protection group. For details, see Configuring MPLS
Tunnel APS on a Per-NE Basis.
Step 7 Optional: Configure the link aggregation function on the Ethernet port. For details, see
Configuring an Ethernet LAG.
Step 8 Optional: Configure the QoS. For details, see Configuring the HQoS.
Step 9 Optional: Configure the IEEE 1588 V2 time and clock (only on the N2PEX1). For details, see
Configuring the IEEE 1588v2 Time Synchronization and Clock Synchronization.
Step 10 Optional: Configure the IGMP Snooping. For details, see Configuring the IGMP Snooping.
----End

Step 1 Required: Test the Ethernet service channel. For details, see Testing EoS Services.
----End

Step 1 Required: Check Ethernet services.
l Check the E-line service. For details, see Verifying the Correctness of E-Line Service
Configuration.
Issue 03 (2013-02-20)

106

l Check the E-LAN service. For details, see Verifying the Correctness of E-LAN Service
Configuration.
l Check the E-AGGR service (only on the N1PEX1). For details, see Verifying the Correctness
of E-AGGR Service Configuration.
Boards.
the Current Alarms.
----End
7.1.10 Configuring the Board Functions

The PEX1 supports the packet switching function and provides multiple packet switchingspecific functions and features, such as HQoS, LAG, and ETH OAM. Configure the functions
according to actual requirements.
You can configure the following packet switching functions for the N1PEX1 and N2PEX1 by
using the U2000:
l
HQoS
LAG
ETH OAM
MPLS Tunnel APS
MPLS OAM
IGMP Snooping
Inband DCN
LPT
The N2PEX1 also provides the following packet switching functions:

l
MPLS PW APS
MC-LAG
MS-PW

You can set parameters for the PEX1 by using the U2000.
Displayed Slots
The N1PEX1 occupies two slots in the subrack. The logical slot of the N1PEX1 displayed on
the U2000 is the slot that has a smaller slot number between the two slots that house the PEX1.
For the logical slots of the N1PEX1 displayed on the U2000, refer to Table 7-4.
The N2PEX1 occupies one slot in the subrack. The logical slot of the N2PEX1 displayed on the
NMS corresponds to the installation slot.
Issue 03 (2013-02-20)

107

Board Parameters
You can set the following principal parameter for the PEX1 by using the U2000:
l
Ethernet interface
For more parameters and the description of the parameters, see 27.1 Packet Processing
Boards.

Troubleshooting
Table 7-5 lists the faults that occur on the PEX1 frequently and the troubleshooting methods.
Table 7-5 Methods used to troubleshoot the faults that occur on the PEX1 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.
See Troubleshooting Packet Service

Interruptions.
l The service loses

packets or has
errored packets.
Protection switching
fault
l The tunnel APS

switching fails.
See Failure of Packet Service Protection

Switching.
l The PW APS
switching fails.
l The MC-LAG
switching fails.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PEX1, see Replacing a Packet Processing Board.

Issue 03 (2013-02-20)

108

7.1.13.1 Alarms of N1PEX1

ALM_ALS
BD_STATUS
ETH_APS_LOST
BUS_ERR
COMMUN_FAIL
ETH_APS_TYPE_MISMATCH
ETH_APS_PATH_MISMATCH
ETH_APS_SWITCH_FAIL
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_LOC
ETH_EFM_DF
ETH_EFM_EVENT
ETH_CFM_UNEXPERI
ETH_EFM_REMFAULT
ETH_LINK_DOWN
ETH_EFM_LOOPBACK
FDBSIZEALM_ELAN
FLOW_OVER
ETH_LOS
HARD_BAD
HARD_ERR
IN_PWR_ABN
LAG_DOWN
LAG_MEMBER_DOWN
LASER_MOD_ERR
LASER_SHUT
LOOP_ALM
LSR_BCM_ALM
LSR_NO_FITED
LSR_WILL_DIE
MAC_FCS_EXC
MPLS_TUNNEL_BDI
MPLS_TUNNEL_Excess
MPLS_TUNNEL_FDI
MPLS_TUNNEL_LOCV
MPLS_TUNNEL_MISMATCH
MPLS_TUNNEL_MISMERGE
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
MPLS_TUNNEL_UNKNOWN
NO_BD_SOFT
POWER_ABNORMAL
TEMP_OVER
PW_EXC_TRAFFIC
OUT_PWR_ABN
TEST_STATUS
TEM_HA
TEM_LA
PW_NO_TRAFFIC
W_OFFLINE
TR_LOC
IN_PWR_LOW
LPT_CFG_CLOSEPORT
WRG_BD_TYPE
IN_PWR_HIGH
ETHOAM_SELF_LOOP
TUNNEL_APS_DEGRADED
Issue 03 (2013-02-20)
TEMP_OVER
COMMUN_FAIL
TR_LOC
BUS_ERR
NO_BD_SOFT
TEST_STATUS
HARD_BAD
HARD_ERR
POWER_ABNORMAL
BD_STATUS
PW_NO_TRAFFIC
WRG_BD_TYPE

109

Issue 03 (2013-02-20)
LSR_NO_FITED
LASER_MOD_ERR
LASER_SHUT
ALM_ALS
LSR_WILL_DIE
IN_PWR_ABN
OUT_PWR_ABN
TEM_HA
TEM_LA
LSR_BCM_ALM
FLOW_OVER
LOOP_ALM
ETH_LOS
ETH_LINK_DOWN
MPLS_TUNNEL_LOCV
MAC_FCS_EXC
FDBSIZEALM_ELAN
MPLS_TUNNEL_Excess
MPLS_TUNNEL_FDI
MPLS_TUNNEL_UNKNOWN
MPLS_TUNNEL_BDI
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
ETH_CFM_UNEXPERI
PW_EXC_TRAFFIC
ETH_CFM_MISMERGE
ETH_EFM_DF
ETH_CFM_LOC
ETH_CFM_RDI
ETH_EFM_LOOPBACK
ETH_EFM_REMFAULT
ETH_EFM_EVENT
ETH_APS_SWITCH_FAIL
LAG_DOWN
ETH_APS_LOST
LAG_MEMBER_DOWN
MPLS_PW_MISMATCH
MPLS_PW_LOCV
MPLS_PW_Excess
MPLS_PW_BDI
MPLS_PW_MISMERGE
MPLS_PW_UNKNOWN
MPLS_PW_SD
MCLAG_CFG_MISMATCH
MPLS_PW_SF
MCSP_PATH_LOCV
LPT_CFG_CLOSEPORT
IN_PWR_HIGH
IN_PWR_LOW
PWAPS_TYPE_MISMATCH
PWAPS_PATH_MISMATCH
PWAPS_SWITCH_FAIL
PWAPS_LOST
ETHOAM_SELF_LOOP
TUNNEL_APS_DEGRADED
BWUTILIZATION_OVER
MPLS_PW_OAMFAIL
DROPRATIO_OVER
ETH_NO_FLOW
MPLS_TUNNEL_OAMFAIL
PORT_EXC_TRAFFIC
SRV_SHUTDOWN_LD

110


7.1.14.1 Performance Events of N1PEX1

Table 7-6 SDH
BDTEMPCUR
BDTEMPMAX
BDTEMPMIN
CPUUSAGECUR
CPUUSAGEMAX
CPUUSAGEMIN
MEMUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV
ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_UAS
ETH_CFM_CSLS
Table 7-7 ETH-OAM 802.1ag
Table 7-8 MPLS Tunnel OAM

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 7-9 Tunnel
Issue 03 (2013-02-20)
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_RX_BPS
TUNNEL_TX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_PPS
TUNNEL_REVERSE_RX_B
PS
TUNNEL_REVERSE_TX_
BPS
TUNNEL_REVERSE_RX
_PPS
TUNNEL_REVERSE_TX_P
PS

111

Table 7-10 PW
PW_SNDPKTS
PW_SNDBYTES
PW_DROPPKTS
PW_DROPBYTES
PW_RCVPKTS
PW_RCVBYTES
PW_BANDWIDTH_UTILISATION
PW_AVAILABILITY
PW_RX_BPS
PW_TX_BPS
PW_RX_PPS
PW_TX_PPS
Table 7-11 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
Table 7-12 QoS

QOS_PRI_DROPPKTS
QOS_PRI_DROPBYTES
Table 7-13 Statistics of RMON basic performance

ETHDROP
RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHCRCALI
ETHUNDER
ETHOVER
ETHFRG
ETHJAB
ETHCOL
RXPKT64
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024
Table 7-14 Statistics of RMON extended performance
Issue 03 (2013-02-20)
RXCTLPKTS
TXOCTETS
TXPKTS
TXCTLPKTS
TXBRDCAST
TXMULCAST
TXPKT64
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024

112

Table 7-15 Statistics of specific performance events of RMON

TXPAUSE
ETHALI
ETHFCS
PKT64
PKT65
PKT128
PKT256
PKT512
PKT1024
TXETHDROP

Table 7-16 SDH
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR

ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_CSLS
ETH_CFM_UAS
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 7-19 Tunnel

TUNNEL_RCVPKTS
Issue 03 (2013-02-20)
TUNNEL_RCVBYTES

TUNNEL_SNDPKTS
113

TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SND
PKTS
TUNNEL_REVERSE_SND
BYTES
TUNNEL_REVERSE_R
CVPKTS
TUNNEL_REVERSE_RCV
BYTES
TNL_REVERSE_BW_UTILISATION
TUNNEL_REVERSE_R
X_BPS
TUNNEL_REVERSE_RX_
PPS
TUNNEL_REVERSE_TX_B
PS
TUNNEL_REVERSE_T
X_PPS
TUNNEL_RX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_BPS
TUNNEL_TX_PPS
Table 7-20 MPLS PW OAM

MPLS_PW_LS
MPLS_PW_SLS
MPLS_PW_CSLS
MPLS_PW_UAS
MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV
Table 7-21 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDBYTES
PW_BANDWIDTH_U
TILISATION
PW_RX_BPS
PW_RX_PPS
PW_SNDPKTS
PW_TX_BPS
PW_TX_PPS
Table 7-22 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
VUNI_TX_UTILIZATION
VUNI_SND_DROPPKTS
VUNI_SND_DROPBYTES
VUNI_SND_DROPRATIO
Issue 03 (2013-02-20)
RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHUNDER
ETHOVER
ETHFRG
RXPKT64
RXPKT65

114

RXPKT128
RXPKT256
RXPKT512
RXPKT1024

RXPKT1519
TXPKT64
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
PKT64
PKT65
PKT128
PKT256
PKT512
PKT1024
PKT1519
RXUNICAST
TXUNICAST
TXMULCAST
TXBRDCAST
RXPAUSE
ETHFCS
ETHUTILIZ
RXCTLPKTS
TXETHOVER
TXPKTS
TXOCTETS
PORT_RX_BYTES_AVAILABILITY
RXBPS
TXBPS
RXPPS
TXPPS
Table 7-25 QoS

FLOW_RX_UTILIZATION
QOS_CARGRNBYTES
QOS_CARGRNPKTS
QOS_CARREDBYTES
QOS_CARREDPKTS
QOS_CARREDRATIO
QOS_CARYLWBYTES
QOS_CARYLWPKTS
QOS_STRM_MATCHBYTES
QOS_STRM_MATCHPKT
S
TNL_REVERSE_SNDDRO
PBYTES
TNL_REVERSE_SNDDRO
PPKTS
TNL_REVERSE_SNDDRO
PRATIO
TNL_SNDDROPBYTES
TNL_SNDDROPPKTS
TNL_SNDDROPRATIO

The technical specifications of the PEX1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Issue 03 (2013-02-20)

115

Parameters Specified for Optical Interfaces

Table 7-26 lists the parameters specified for the optical interfaces of the N1PEX1.
Table 7-26 Parameters specified for the optical interfaces of the N1PEX1
Parameter
Value
Type of
interface
10GBASE-SR
(LAN)
10GBASE-LR
(LAN)
10GBASE-ER
(LAN)
10GBASE-ZR
(LAN)
10GBASE-SW
(WAN)
10GBASE-LW
(WAN)
10GBASE-EW
(WAN)
10GBASE-ZW
(WAN)
Transmission
distance (km)
0.3
10
40
80
Type of fiber
Multi-mode LC
Single-mode LC
Single-mode
LC
Single-mode
LC
Launched
optical power
range (dBm)
-1.3 to -7.3
-6 to -1
-1 to 2
0 to 4
Operating
wavelength
range (nm)
840 to 860
1260 to 1330
1530 to 1565
1530 to 1565
Minimum
overload (dBm)
-1
0.5
-1
-7
Receiver
sensitivity
(dBm)
-7.5
-11
-15
-24
Minimum
extinction ratio
(dB)
8.2
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
30
Table 7-27 lists the parameters specified for the optical interfaces of the N2PEX1.
Issue 03 (2013-02-20)

116

Table 7-27 Parameters specified for the optical interfaces of the N2PEX1
Parameter
Value
Type of interface
10GBASE-LR (LAN)
10GBASE-ER
(LAN)
10GBASE-ZR
(LAN)
Transmission
distance (km)
10
40
80
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC
Launched optical
power range (dBm)
-6 to -1
-1 to 2
0 to 4
Operating
wavelength range
(nm)
1260 to 1330
1530 to 1565
1530 to 1565
Minimum overload
(dBm)
0.5
-1
-7
Receiver sensitivity
(dBm)
-11
-15
-24
Minimum extinction
ratio (dB)
8.2
Maximum -20 dB
spectral width (nm)
Minimum side mode

suppression ratio
(dB)
30
30
30
Table 7-28 and Table 7-29 lists the parameters specified for the colored optical interfaces of
the N2PEX1.
Table 7-28 CWDM parameters specified for the colored optical interfaces of the N2PEX1
Parameter
Value
CWDM
Issue 03 (2013-02-20)
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
Transmission distance (km)
70
Launched optical power range

(dBm)
0 to 4
Operating wavelength range

(nm)
1471 to 1611, in steps of 20

117

Parameter
Value
CWDM
Receiver sensitivity (dBm)
l 1451nm to 1551nm: -23

l 1571nm: -22
l 1591nm to 1611nm: -21
Minimum overload (dBm)
-9
Maximum allowed dispersion

(ps/nm)
1400
Minimum extinction ratio (dB)
8.2
Maximum -20 dB spectral width

(nm)
Minimum side mode

suppression ratio (dB)
30
Table 7-29 DWDM parameters specified for the colored optical interfaces of the N2PEX1
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
Transmission
distance (km)
40
80
Launched optical
power range
(dBm)
-1 to 2
-1 to 3
Central frequency
(THz)
192.10 to 196.00
192.10 to 196.00
Central frequency
deviation (GHz)
10
10
Receiver
sensitivity (dBm)
-17
-24
Minimum
overload (dBm)
-1
-9
Maximum allowed
dispersion (ps/nm)
800
1600

118

Parameter
Value
DWDM
Minimum
extinction ratio
(dB)
9.5
8.2
Maximum -20 dB
spectral width
(nm)
0.3
0.3
Minimum side
mode suppression
ratio (dB)
35
30
Laser Safety Class

The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
The mechanical specifications of the N1PEX1 are as follows:
l
Weight (kg): 2.4
The mechanical specifications of the N2PEX1 are as follows:

l
Weight (kg): 1.4
Power Consumption
The maximum power consumption of the N1PEX1 at room temperature (25C) is 107 W.
The maximum power consumption of the N2PEX1 at room temperature (25C) is 48 W.
7.2 PEX2
technical specifications of the PEX2 (2-port 10 Gigabit Ethernet switching processing board).
This topic also describes how to configure and commission the PEX2.

The PEX2 is available in one functional version, namely, N1.
Issue 03 (2013-02-20)

119

7.2.2 Application
The PEX2 is mainly used in the packet data transmission field to transmit/receive data packets,
manage bandwidths, and implement switching of data packets.
Figure 7-5 shows the typical networking and application of the PEX2. The PEX2 works with
on the OptiX OSN equipment so that the data can be transmitted in the two domains. In this
manner, an MSTP network can smoothly evolve to a packet switching network.
Figure 7-5 Networking and application of the PEX2
OptiX OSN 3500/
7500
NMS
OptiX OSN 3500/

7500
OptiX OSN 3500/

7500
PSN
10GE ring
OptiX OSN 1500
OptiX OSN 1500

PSN
GE ring
OptiX OSN 1500
PSN
GE ring
OptiX OSN
3500/7500
OptiX OSN 1500
Traffic direction
GE processing board


The PEX2 processes and forwards 2x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
Table 7-30 provides the functions and features of the PEX2.
Issue 03 (2013-02-20)

120

Table 7-30 Functions and features of the PEX2

Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 2x10 GE services.
Interfa
ce
types
l Supports the 10GBASE-LR (LAN), 10GBASE-ER (LAN), and 10GBASE-ZR

(LAN) Ethernet optical interfaces. The optical interface uses the LC connector
and supports the transmission distances of 10 km, 40 km, and 80 km.
l Supports the CWDM and DWDM colored optical interfaces. The optical
interface uses the LC connector. The CWDM optical interface supports the
transmission distance of 70 km. The DWDM optical interface supports the
transmission distance of 40/80 km.
Functi
ons
when
being
used
with
an
interfa
ce
board
Does not support an interface board, and has two 10GE interfaces on its front panel.
Interfa
ce
charac
teristic
s
Hot
optical
module
swappin
g
Supports hot swapping of XFP optical modules.
Workin
g modes
10GE Full-duplex (only in LAN mode)
Flow
control
at ports
Autonegotiation
mode
Not supported
Nonautonegotia
tion mode
Supported
Query/
Setting
of port
status
Issue 03 (2013-02-20)
Supported

121

Funct
ion
and
Featu
re
Servic
e
specifi
cation
s
Description
Query
of
interfac
e types
Supported
Setting
of
optical
power
threshol
ds
Supported
Processi
ng
capabili
ty
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported
Maximum
number of
PWs
16k
MS-PW
Unidirectio
nal

shared):
PW
specific
ations
Tunnel
specific
ations

Bidirection
al

shared):
MTU
Issue 03 (2013-02-20)
MTU for
ports
Supports the setting of the packet length, which ranges

from 960 bytes to 9000 bytes. After the setting becomes
valid, the length of the packets that enter or exit the ports
is restricted by the pre-set MTU.

122

Funct
ion
and
Featu
re
Description
Ethernet
service
capabili
ty
Protec
tion
schem
es
MTU for
services
For packet services carried by PWs, the PEX2 supports

modes, the PEX2 does not support the setting of the packet
length.
E-Line
service

E-LAN
service
Number of supported E-LAN services: 1020

E-AGGR
service
Not supported
Formats of
Ethernet
data frames

Maximum
number of
QinQ links
1k
Maximum
number of
VLANs
4k
Jumbo
frame

9000 bytes.
MPLS
Tunnel
APS

Tunnel APS.
Number of supported MPLS Tunnel APS protection groups: 1k
MPLS
PW
APS
Supports the PW FPS (single-ended), 1+1 (single-ended/dual-ended) and

1:1 (dual-ended) MPLS Tunnel APS.
protection group can bind a maximum of 512 members.
NOTE
LAG

MCLAG
Issue 03 (2013-02-20)
Supported, which complies with IEEE 802.3ad and IEEE 802.1AX.

123

Funct
ion
and
Featu
re
Description
Multipl
e
spannin
g tree
protocol
(MSTP)
Not supported
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Supports two channels of synchronous Ethernet clock signals.
IEEE
1588v2
Supports two channels of IEEE 1588v2 clock signals.
Maint
enanc
e
featur
es
ETH
OAM
IEEE
802.1ag
IEEE
802.3ah
Supports OAM auto-discovery, remote loopback, and link

performance monitoring.
MPLS
tunnel
OAM

1711.
MPLS PW
OAM
Supports CV, FFD, BDI, FDI, PW ping and PW traceroute

in compliance with ITU-T Y.1711.
Number of MPLS PWs that support OAM: 2k
MPLS
OAM
NOTE
MPLS tunnel OAM and MPLS PW OAM share resources.
Issue 03 (2013-02-20)
Loopba
ck
capabili
ty
PHY layer
at Ethernet
ports
Not supported
MAC layer
at Ethernet
ports
Inloops and outloops
RMON
perform
ance
Supported

124

Funct
ion
and
Featu
re
Description
Inban
d
DCN
Supported
HQoS
Provides the HQoS function, including the scheduling function at multiple levels
for the flow queue and port queue and the bandwidth restricting function, and
provides the corresponding statistical information.
IGMP
snoopi
ng
Supported
Query
of
electro
nic
labels
Supported

The PEX2 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
Figure 7-6 shows the functional block diagram of the PEX2.
Figure 7-6 Functional block diagram of the PEX2
Working clock
Clock
module
IEEE 1588 V2 packet

2x10GE signals
Backplane
PSXCSA
IEEE 1588 V2 packet
PSXCSA
PSXCSA
Upstream transmission
Service Upstream scheduling Service
module
module
signal
signal
Downstream
Downstream
transmission module
scheduling module
Transmission
Switching network
management module
buffering module
Parallel management bus Parallel management
bus
Data backup bus
CPU
Data processing
module
Packet forwarding
module
Network processing
module
Service
signal
management
module
PSXCSA
GSCC
GSCC

Logic control
module
Issue 03 (2013-02-20)
Temperature and
voltage detecting
signals
Temperature and
voltage detecting
signals
- 48V / - 60V
Power
module

- 48V / - 60V
125

Receive Direction
The network processing module receives 2x10GE optical signals, decodes the signals, and
converts the serial signals into parallel signals. Then, the network processing module performs
route searching or address matching for the data packets, and transmits the corresponding packets
to the transmission management module. The transmission management module buffers and
schedules the packets, slices the packets into cells that the switching network requires, and sends
the cells to the switching network buffering module. The switching network buffering module
buffers the cells and sends the cells to the cross-connect unit.
Transmit Direction
converts the parallel signals into serial signals and sends the signals to the 10xGE optical
interface.

for data packets. The network processing module of the PEX2 can process the 20 Gbit/s data

l
at five levels for the flow queue and port queue, and the bandwidth restricting function,
and provides the corresponding statistics information.


buses to manage the modules of the board. The CPU management module also monitors alarms
and performance events and reports the alarms and performance events to the SCC unit.

The logic control module controls the logic of the PEX2. It performs the following functions:
Issue 03 (2013-02-20)

126

Decodes the address signals of the peripheral modules, allocates the registers, and controls
the logic.
Reports and controls the board status, for example, the shutdown or startup of the laser.
Controls the logic of the CPU module and decodes the address signals of the CPU module.
Configures services, queries the performance, and controls alarms.
Implements some clock functions.
Temperature and Voltage Detecting Module

The temperature and voltage detecting module monitors the temperature and voltage.
Clock Module
l
Provides clock signals for each module of the PEX2.
Power Module
the PEX2 require.
7.2.5 Front Panel

The front panel of the PEX2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 7-7 shows the appearance of the front panel of the PEX2.
Issue 03 (2013-02-20)

127

Figure 7-7 Front panel of the PEX2
PEX2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
PEX2
Indicators
l
Interfaces
The front panel of the PEX2 has two optical interfaces. Table 7-31 describes the type and usage
of the optical interfaces of the PEX2.
Issue 03 (2013-02-20)

128

Table 7-31 Optical interfaces of the PEX2

Interface
Type of Interface
Usage
IN1-IN2
LC (pluggable)
Receives 10GE signals.
OUT1OUT2
LC (pluggable)
Transmits 10GE signals.

The PEX2 does not have any jumpers or DIP switches that are used for board settings.
7.2.7 Valid Slots

The PEX2 must be installed in a valid slot in the subrack. Otherwise, the PEX2 fails to work
normally.
The following part lists the valid slots of the PEX2 and the corresponding bandwidths:
l
Slots 1-3, and 16 (2.5 Gbit/s)
Slots 4-6 and 13-15 (5 Gbit/s)
Slots 7 and 12 (10 Gbit/s)
Slots 8 and 11 (20 Gbit/s)
7.2.8 Feature Code

The PEX2 does not have the feature code.


Issue 03 (2013-02-20)

129

is correct.
----End

NOTE
Step 9 Optional: Configure the IEEE 1588 V2 time and clock. For details, see Configuring the IEEE
1588v2 Time Synchronization and Clock Synchronization.
----End

----End

Issue 03 (2013-02-20)

130

Configuration.
Configuration.
Boards.
the Current Alarms.
----End

The PEX2 supports the packet switching function and provides multiple packet-specific
functions and features, such as HQoS, LAG, and ETH OAM. Configure the functions according
to actual requirements.
You can configure the following packet functions for the PEX2 by using the U2000:
l
HQoS
LAG
ETH OAM
MPLS Tunnel APS
MPLS OAM
IGMP Snooping
Inband DCN
LPT
MPLS PW APS
MC-LAG
MS-PW

You can set the parameters for the PEX2 by using the U2000.
You can set the following parameters for the PEX2 by using the U2000:
l
Ethernet interface
For information about more parameters and the description of each parameter, see 27.1 Packet
Processing Boards.

Issue 03 (2013-02-20)

131

Troubleshooting
Table 7-32 lists the faults that occur on the PEX2 frequently and the troubleshooting methods.
Table 7-32 Methods used to troubleshoot the faults that occur on the PEX2 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.

Interruptions.
l The service loses

packets or has
errored packets.
fault
l The tunnel APS

switching fails.

Switching.
l The PW APS
switching fails.
l The MC-LAG
switching fails.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PEX2, see Replacing a Packet Processing Board.

according to the logical board on the NMS.
Issue 03 (2013-02-20)
TEMP_OVER
COMMUN_FAIL
TR_LOC
BUS_ERR
NO_BD_SOFT
TEST_STATUS
HARD_BAD
HARD_ERR
POWER_ABNORMAL
BD_STATUS
PW_NO_TRAFFIC
WRG_BD_TYPE
LSR_NO_FITED
LASER_MOD_ERR
LASER_SHUT
ALM_ALS
LSR_WILL_DIE
IN_PWR_ABN
OUT_PWR_ABN
TEM_HA
TEM_LA
LSR_BCM_ALM
FLOW_OVER
LOOP_ALM

132

ETH_LOS
ETH_LINK_DOWN
MPLS_TUNNEL_LOCV
MAC_FCS_EXC
FDBSIZEALM_ELAN
MPLS_TUNNEL_Excess
MPLS_TUNNEL_FDI
MPLS_TUNNEL_UNKNOWN
MPLS_TUNNEL_BDI
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
ETH_CFM_UNEXPERI
PW_EXC_TRAFFIC
ETH_CFM_MISMERGE
ETH_EFM_DF
ETH_CFM_LOC
ETH_CFM_RDI
ETH_EFM_LOOPBACK
ETH_EFM_REMFAULT
ETH_EFM_EVENT
ETH_APS_SWITCH_FAIL
LAG_DOWN
ETH_APS_LOST
LAG_MEMBER_DOWN
MPLS_PW_MISMATCH
MPLS_PW_LOCV
MPLS_PW_Excess
MPLS_PW_BDI
MPLS_PW_MISMERGE
MPLS_PW_UNKNOWN
MPLS_PW_SD
MCLAG_CFG_MISMATCH
MPLS_PW_SF
MCSP_PATH_LOCV
LPT_CFG_CLOSEPORT
IN_PWR_HIGH
IN_PWR_LOW
PWAPS_TYPE_MISMATCH
PWAPS_PATH_MISMATCH
PWAPS_SWITCH_FAIL
PWAPS_LOST
ETHOAM_SELF_LOOP
TUNNEL_APS_DEGRADED
BWUTILIZATION_OVER
MPLS_PW_OAMFAIL
DROPRATIO_OVER
ETH_NO_FLOW
MPLS_TUNNEL_OAMFAIL
PORT_EXC_TRAFFIC
SRV_SHUTDOWN_LD

events are reported according to the logical board on the NMS.
Issue 03 (2013-02-20)

133


Table 7-33 SDH
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR

ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_CSLS
ETH_CFM_UAS
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 7-36 Tunnel
Issue 03 (2013-02-20)
TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SND
PKTS
TUNNEL_REVERSE_SND
BYTES
TUNNEL_REVERSE_R
CVPKTS
TUNNEL_REVERSE_RCV
BYTES
TUNNEL_REVERSE_R
X_BPS
TUNNEL_REVERSE_RX_
PPS
TUNNEL_REVERSE_TX_B
PS
TUNNEL_REVERSE_T
X_PPS
TUNNEL_RX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_BPS
TUNNEL_TX_PPS

134


MPLS_PW_LS
MPLS_PW_SLS
MPLS_PW_CSLS
MPLS_PW_UAS
MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV
Table 7-38 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDBYTES
PW_BANDWIDTH_U
TILISATION
PW_RX_BPS
PW_RX_PPS
PW_SNDPKTS
PW_TX_BPS
PW_TX_PPS
Table 7-39 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
VUNI_TX_UTILIZATION
VUNI_SND_DROPPKTS
VUNI_SND_DROPBYTES
VUNI_SND_DROPRATIO

RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHUNDER
ETHOVER
ETHFRG
RXPKT64
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024
Issue 03 (2013-02-20)
RXPKT1519
TXPKT64
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
PKT64
PKT65
PKT128
PKT256
PKT512
PKT1024
PKT1519

135

RXUNICAST
TXUNICAST
TXMULCAST
TXBRDCAST
RXPAUSE
ETHFCS
ETHUTILIZ
RXCTLPKTS
TXETHOVER
TXPKTS
TXOCTETS
RXBPS
TXBPS
RXPPS
TXPPS
Table 7-42 QoS

FLOW_RX_UTILIZATION
QOS_CARGRNBYTES
QOS_CARGRNPKTS
QOS_CARREDBYTES
QOS_CARREDPKTS
QOS_CARREDRATIO
QOS_CARYLWBYTES
QOS_CARYLWPKTS
QOS_STRM_MATCHBYTES
QOS_STRM_MATCHPKT
S
TNL_REVERSE_SNDDRO
PBYTES
TNL_REVERSE_SNDDRO
PPKTS
TNL_REVERSE_SNDDRO
PRATIO
TNL_SNDDROPBYTES
TNL_SNDDROPPKTS
TNL_SNDDROPRATIO

The technical specifications of the PEX2 include the parameters specified for optical interfaces,

Table 7-43 lists the parameters specified for the optical interfaces of the PEX2.
Table 7-43 Parameters specified for the optical interfaces of the PEX2
Issue 03 (2013-02-20)
Parameter
Value
Type of interface
10GBASE-LR
(LAN)
10GBASE-ER
(LAN)
10GBASE-ZR
(LAN)
Transmission
distance (km)
10
40
80
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC

136

Parameter
Value
Launched optical
power range (dBm)
-6 to -1
-1 to 2
0 to 4
Operating
wavelength range
(nm)
1260 to 1330
1530 to 1565
1530 to 1565
Minimum overload
(dBm)
0.5
-1
-7
(dBm)
-11
-15
-24
Minimum extinction
ratio (dB)
8.2
Maximum -20 dB
spectral width (nm)
Minimum side mode

30
30
30
Table 7-44 and Table 7-45 lists the parameters specified for the 10GE colored optical interfaces
of the PEX2.
Table 7-44 CWDM parameters specified for the colored optical interfaces of the PEX2
Parameter
Value
CWDM
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
70

(dBm)
0 to 4

(nm)
1471 to 1611, in steps of 20
l 1451nm to 1551nm: -23

l 1571nm: -22
l 1591nm to 1611nm: -21
Issue 03 (2013-02-20)
-9

(ps/nm)
1400

137

Parameter
Value
CWDM
8.2

(nm)
Minimum side mode

30
Table 7-45 DWDM parameters specified for the colored optical interfaces of the PEX2
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
Transmission
distance (km)
40
80
Launched optical
power range
(dBm)
-1 to 2
-1 to 3
Central frequency
(THz)
192.10 to 196.00
192.10 to 196.00
Central frequency
deviation (GHz)
10
10
Receiver
sensitivity (dBm)
-17
-24
Minimum
overload (dBm)
-1
-9
Maximum allowed
dispersion (ps/nm)
800
1600
Minimum
extinction ratio
(dB)
9.5
8.2
Maximum -20 dB
spectral width
(nm)
0.3
0.3
Minimum side
mode suppression
ratio (dB)
35
30

138

Laser Safety Class

The mechanical specifications of the PEX2 are as follows:
l
Weight (kg): 1.4
Power Consumption
The maximum power consumption of the PEX2 at room temperature (25C) is 49 W.
7.3 PEG8
technical specifications of the PEG8 (8-Port Gigabit Ethernet switching processing board). This
topic also describes how to configure and commission the PEG8

The PEG8 is available in one functional version, namely, N1.
7.3.2 Application
The PEG8 is mainly used in the packet data transmission field to transmit/receive data packets,
Figure 7-8 shows the typical networking and application of the PEG8. The PEG8 works with
8.1.2 Application describes the typical networking and application when the PEG8 works with
the PETF8.
the PEFF8.
the CQ1.
the MD12.
the MD75.
Issue 03 (2013-02-20)

139

Figure 7-8 Networking and application of the PEG8

OptiX OSN 3500/
7500
NMS
OptiX OSN 3500/

7500
OptiX OSN 3500/

7500
PSN
10GE ring
OptiX OSN 1500
OptiX OSN 1500

PSN
GE ring
OptiX OSN 1500
PSN
GE ring
OptiX OSN
3500/7500
OptiX OSN 1500
Traffic direction
GE processing board


The PEG8 processes and forwards 8xGE services and supports QoS functions such as traffic
management, congestion control, and queue scheduling for data packets.
Table 7-46 provides the functions and features of the PEG8.
Table 7-46 Functions and features of the PEG8
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Provides eight GE optical/electrical interfaces on the front panel of the board, and
receives/transmits and processes 8xGE signals.
When being used with an interface board:
l Works with the interface board PETF8/PEFF8/CQ1/MD12/MD75. One PEG8
board can receive/transmit the FE/channelized E1 STM-1/CES services from a
maximum of two interface boards.
l Works with the interface board MD12/MD75. One PEG8 board can receive/
transmit the ATM/IMA services from a maximum of two interface boards.
Issue 03 (2013-02-20)

140

Funct
ion
and
Featu
re
Description
Interfa
ce
types
l Supports the 1000BASE-SX, 1000BASE-LX, 1000BASE-VX, and 1000BASEZX optical interfaces. The optical interface uses the LC connector and supports
the transmission distances of 0.5 km, 10 km, 40 km, and 80 km.
l Supports the CWDM colored optical interfaces. The optical interface uses the
LC connector and supports the transmission distances of 40 km and 80 km.
l Supports the DWDM colored optical interfaces. The optical interface uses the
LC connector and supports the transmission distance of 120 km.
l Supports the GE electrical interfaces. The electrical interface uses the RJ45
connector and meets the specifications of the 1000BASE-T physical layer
provided in IEEE 802.3.
Interfa
ce
charac
teristic
s
Issue 03 (2013-02-20)
Hot
optical
module
swappin
g
Supports hot swapping of SFP optical modules.
Workin
g modes
Full-duplex and auto-negotiation for GE optical interfaces

Auto-negotiation for GE electrical ports (the negotiation result can only
be 1000M full duplex)
Flow
control
at ports
Autonegotiation
mode
Supported
Nonautonegotia
tion mode
Supported
Query/
Setting
of port
status
Supported
Query
of
interfac
e types
Supported
Setting
of
optical
power
threshol
ds
Supported

141

Funct
ion
and
Featu
re
Description
Servic
e
specifi
cation
s
Processi
ng
capabili
ty
The processing capability varies according to slots.
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported
Maximum
number of
PWs
16k
MS-PW
Unidirectio
nal

shared):
PW
specific
ations
Tunnel
specific
ations
l When a PEG8 is installed in any slot of slots 1-3 and 16, it processes
2.5 Gbit/s services in full-duplex mode.
l When a PEG8 is installed in any slot of slots 4-6 and 13-15, it
processes 5 Gbit/s services in full-duplex mode.

Bidirection
al

shared):
MTU
Ethernet
service
capabili
ty
Issue 03 (2013-02-20)
MTU for
ports

MTU for
services
For packet services carried by PWs, the PEG8 supports

modes, the PEG8 does not support the setting of the packet
length.
E-Line
service

E-LAN
service
Number of supported E-LAN services: 1020

E-AGGR
service
Not supported

142

Funct
ion
and
Featu
re
Protec
tion
schem
es
Description
Formats of
Ethernet
data frames

Maximum
number of
QinQ links
1k
Maximum
number of
VLANs
4k
Jumbo
frame

9000 bytes.
MPLS
Tunnel
APS

Tunnel APS.
MPLS
PW
APS

1:1 (dual-ended) MPLS PW APS.
Number of supported MPLS Tunnel APS protection groups: 1k

protection group can bind a maximum of 512 members.
NOTE
LAG

Issue 03 (2013-02-20)
MCLAG
Supported, which complies with IEEE 802.3ad and IEEE 802.1AX.
Multipl
e
spannin
g tree
protocol
(MSTP)
Not supported
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported

143

Funct
ion
and
Featu
re
Description
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Supports eight channels of synchronous Ethernet clock signals (only by

GE optical interfaces).
IEEE
1588v2
Supports eight channels of IEEE 1588v2 clock signals (only by GE

optical interfaces).
Maint
enanc
e
featur
es
ETH
OAM
IEEE
802.1ag
IEEE
802.3ah

MPLS
tunnel
OAM

1711.
MPLS PW
OAM
Supports CV, FFD, BDI, FDI, PW ping and PW traceroute

in compliance with ITU-T Y.1711.
Number of MPLS PWs that support OAM: 2k
MPLS
OAM
NOTE
MPLS tunnel OAM and MPLS PW OAM share resources.
Issue 03 (2013-02-20)
Loopba
ck
capabili
ty
PHY layer
at Ethernet
ports
Not supported
MAC layer
at Ethernet
ports
RMON
perform
ance
Supported
Inban
d
DCN
Supported
HQoS
Provides the HQoS function. The PEG8 provides the scheduling function at multiple
levels for the flow queue and port queue and the bandwidth restricting function, and
provides the corresponding statistics information.
IGMP
snoopi
ng
Supported

144

Funct
ion
and
Featu
re
Description
Query
of
electro
nic
labels
Supported

The PEG8 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
Figure 7-9 shows the functional block diagram of the PEG8.
Figure 7-9 Functional block diagram of the PEG8
Backplane
GE signals
Interface board
IEEE 1588 V2 packet

Interface board
Data processing
module
8xGE signals
Service
signal
Packet forwarding
module
Network processing
module
Upstream
transmission module
Downstream
scheduling module
Transmission
management module
Switching network
buffering module
CPU
management
module
Service
signal
PSXCSA
Parallel
management bus
Ethernet communication bus

GSCC
Other boards
System clock
Working clock
Interface board
Interface board/Eight GE signals
IEEE 1588 V2 packet
Interface board/Eight GE signals
Upstream
scheduling module
Downstream
transmission module
Service
signal

Clock module
Synchronous Ethernet
clock
IEEE 1588 V2 packet
Power
module
PSXCSA
PSXCSA
PSXCSA
- 48 V / - 60 V
- 48 V / - 60 V
Interface board
Receive Direction
The network processing module receives the signals sent from the GE interface on the front
panel or the interface board, decodes the signals, and converts the serial signals into parallel
signals. Then, the network processing module performs route searching or address matching for
the data packets, and sends the corresponding packets to the transmission management module.
The transmission management module buffers and schedules the packets, slices the packets into
Issue 03 (2013-02-20)

145

cells that the switching network requires, and sends the cells to the switching network buffering
module. The switching network buffering module buffers the cells and sends the cells to the
cross-connect unit.
Transmit Direction
converts the parallel signals into serial signals, and sends the signals to the GE interface on the
front panel of the board or the corresponding interface board through the backplane.

for data packets. The network processing module of the PEG8 can process 5 Gbit/s data packets
in full-duplex mode.

l
at five levels for the flow queue and port queue, and the bandwidth restricting function,
and provides the corresponding statistics information.


buses to manage the modules of the PEG8 and the interface board to which the PEG8
corresponds. The CPU management module also monitors alarms and performance events and
reports the alarms and performance events to the SCC unit.
Clock Module
l
Provides the clock signal for each module of the board.
Supports the transparent transmission of the IEEE 1588 V2 packets from the interface board
or the 8xGE signals to the PSXCSA.
Selects a clock source from the two system clocks sent from the PSXCSA and sends the
selected clock to the interface board and the modules of the PEG8.
Issue 03 (2013-02-20)

146

Selects a clock source from the synchronous Ethernet clock signals accessed by the interface
board or the 8xGE signals and sends the selected clock to the PSXCSA.
Power Module
the board require.
7.3.5 Front Panel

The front panel of the PEG8 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 7-10 shows the appearance of the front panel of the PEG8.
Figure 7-10 Front panel of the PEG8 with optical interfaces
PEG8
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
TX1
RX1
TX2
RX2
TX3
RX3
TX4
RX4
TX5
RX5
TX6
RX6
TX7
RX7
TX8
RX8
PEG8
Issue 03 (2013-02-20)

147

Indicators
l
Interfaces
The front panel of the PEG8 has eight optical/electrical interfaces. Table 7-47 describes the type
and usage of the interface of the PEG8.
Table 7-47 Interfaces of the PEG8
Interface
Type of Interface
Usage
RX1-RX8
LC/RJ-45 (pluggable)
Receives GE signals.
TX1-TX8
LC/RJ-45 (pluggable)
Transmits GE signals.

The PEG8 does not have any jumpers or DIP switches that are used for board settings.
7.3.7 Valid Slots

The PEG8 must be installed in a valid slot in the subrack. Otherwise, the PEG8 fails to work
normally.
The PEG8 can be installed in slots 16, and 1316 in the subrack.
l
When the PEG8 is installed in slots 1-3, and 16, the bandwidth is 2.5 Gbit/s.
When the PEG8 is installed in slots 4-6 and 13-15, the bandwidth is 5 Gbit/s.
When the PEG8 works with the interface board PETF8/PEFF8/CQ1/MD12/MD75, one PEG8
can work with a maximum of two PETF8/PEFF8/CQ1/MD12/MD75 boards. In this case, all the
optical interfaces on the PEG8 can be used. Table 7-48 lists the slots valid for the PEG8 and the
corresponding slots for the interface boards.
Table 7-48 Slots valid for the PEG8 and the corresponding slots for the PETF8/PEFF8/CQ1/
MD12/MD75
Issue 03 (2013-02-20)
Slot Valid for the PEG8
Corresponding Slot for the PETF8/PEFF8/CQ1/

MD12/MD75
Slot 1
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
148

Slot Valid for the PEG8
Corresponding Slot for the PETF8/PEFF8/CQ1/

MD12/MD75
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 6
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
7.3.8 Feature Code

The PEG8 does not have the feature code.


Step 3 Required: Check whether the interface board and cable match the board. Ensure that the
interface board and the cable match the board.
is correct.
----End

Issue 03 (2013-02-20)

149


NOTE
Step 4 Required: Configure services. The following services can be configured according to actual
requirements:
l Configure ATM/IMA service. For details, see Configuring ATM Services
----End

Step 2 Required: Test the ATM/IMA service. For details, see Testing ATM Services.
----End

Configuration.
Configuration.
Issue 03 (2013-02-20)

150

Boards.
the Current Alarms.
----End

The PEG8 supports the packet switching function and provides multiple packet-specific
functions and features, such as HQoS, LAG, and ETH OAM. Configure the functions according
to actual requirements.
You can configure the following packet functions for the PEG8 by using the U2000:
l
HQoS
LAG
ETH OAM
MPLS Tunnel APS
MPLS OAM
IGMP Snooping
Inband DCN
LPT
MPLS PW APS
MC-LAG
MS-PW

You can set the parameters for the PEG8 by using the U2000.
You can set the following parameters for the PEG8 by using the U2000:
l
Ethernet interface
Processing Boards.

Troubleshooting
Table 7-49 lists the faults that occur on the PEG8 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

151

Table 7-49 Methods used to troubleshoot the faults that occur on the PEG8 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.

Interruptions.
l The service loses

packets or has
errored packets.
fault
l The tunnel APS

switching fails.

Switching.
l The PW APS
switching fails.
l The MC-LAG
switching fails.
Replacing the Optical/Electrical Module

The OptiX OSN equipment supports pluggable optical/electrical modules. If an optical/electrical
module is faulty, replace only the faulty optical/electrical module instead of the associated board.
For information on how to replace an optical/electrical module, see Replacing a Pluggable
Optical/Electrical Module.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PEG8, see Replacing a Packet Processing Board.

7.3.13.1 Alarms of N1PEG8
Issue 03 (2013-02-20)
TEMP_OVER
COMMUN_FAIL
TR_LOC
BUS_ERR
NO_BD_SOFT
TEST_STATUS
HARD_BAD
HARD_ERR
POWER_ABNORMAL
BD_STATUS
PW_NO_TRAFFIC
WRG_BD_TYPE
LSR_NO_FITED
LASER_MOD_ERR
LASER_SHUT
ALM_ALS
LSR_WILL_DIE
IN_PWR_ABN

152

OUT_PWR_ABN
TEM_HA
TEM_LA
LSR_BCM_ALM
FLOW_OVER
LOOP_ALM
ETH_LOS
ETH_LINK_DOWN
MPLS_TUNNEL_LOCV
MAC_FCS_EXC
FDBSIZEALM_ELAN
MPLS_TUNNEL_Excess
MPLS_TUNNEL_FDI
MPLS_TUNNEL_UNKNOWN
MPLS_TUNNEL_BDI
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
ETH_CFM_UNEXPERI
PW_EXC_TRAFFIC
ETH_CFM_MISMERGE
ETH_EFM_DF
ETH_CFM_LOC
ETH_CFM_RDI
ETH_EFM_LOOPBACK
ETH_EFM_REMFAULT
ETH_EFM_EVENT
ETH_APS_SWITCH_FAIL
LAG_DOWN
ETH_APS_LOST
LAG_MEMBER_DOWN
MPLS_PW_MISMATCH
MPLS_PW_LOCV
MPLS_PW_Excess
MPLS_PW_BDI
MPLS_PW_MISMERGE
MPLS_PW_UNKNOWN
MPLS_PW_SD
MCLAG_CFG_MISMATCH
MPLS_PW_SF
MCSP_PATH_LOCV
LPT_CFG_CLOSEPORT
IN_PWR_HIGH
IN_PWR_LOW
PWAPS_TYPE_MISMATCH
PWAPS_PATH_MISMATCH
PWAPS_SWITCH_FAIL
PWAPS_LOST
ETHOAM_SELF_LOOP
TUNNEL_APS_DEGRADED
BWUTILIZATION_OVER
MPLS_PW_OAMFAIL
DROPRATIO_OVER
ETH_NO_FLOW
MPLS_TUNNEL_OAMFAIL
PORT_EXC_TRAFFIC
SRV_SHUTDOWN_LD

Issue 03 (2013-02-20)

153

7.3.14.1 Performance Events of N1PEG8

Table 7-50 SDH
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR

ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_CSLS
ETH_CFM_UAS
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 7-53 Tunnel
Issue 03 (2013-02-20)
TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SND
PKTS
TUNNEL_REVERSE_SND
BYTES
TUNNEL_REVERSE_RC
VPKTS
TUNNEL_REVERSE_RCV
BYTES
TUNNEL_REVERSE_RX_
BPS
TUNNEL_REVERSE_RX_
PPS
TUNNEL_REVERSE_TX_
BPS
TUNNEL_REVERSE_TX_
PPS
TUNNEL_RX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_BPS
TUNNEL_TX_PPS

154


MPLS_PW_LS
MPLS_PW_SLS
MPLS_PW_CSLS
MPLS_PW_UAS
MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV
Table 7-55 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDPKTS
PW_SNDBYTES
PW_AVAILABILITY
PW_RX_BPS
PW_RX_PPS
PW_TX_BPS
PW_TX_PPS
Table 7-56 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
VUNI_TX_UTILIZATION
VUNI_SND_DROPPKTS
VUNI_SND_DROPBYTES
VUNI_SND_DROPRATIO

RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHUNDER
ETHOVER
ETHFRG
ETHJAB
RXPKT64
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024
Issue 03 (2013-02-20)
RXPKT1519
TXPKT64
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
PKT64
PKT65
PKT128
PKT256
PKT512
PKT1024
PKT1519

155

TXMULCAST
TXBRDCAST
RXPAUSE
ETHALI
ETHFCS
ETHUTILIZ
RXCTLPKTS
TXPKTS
TXOCTETS
RXBPS
TXBPS
RXPPS
TXPPS
Table 7-59 QoS

FLOW_RX_UTILIZATION
QOS_CARGRNBYTES
QOS_CARGRNPKTS
QOS_CARREDBYTES
QOS_CARREDPKTS
QOS_CARREDRATIO
QOS_CARYLWBYTES
QOS_CARYLWPKTS
QOS_STRM_MATCHBYTES
QOS_STRM_MATCHPKT
S
TNL_REVERSE_SNDDRO
PBYTES
TNL_REVERSE_SNDDRO
PPKTS
TNL_REVERSE_SNDDRO
PRATIO
TNL_SNDDROPBYTES
TNL_SNDDROPPKTS
TNL_SNDDROPRATIO

The technical specifications of the PEG8 include the parameters specified for optical interfaces,

Table 7-60 lists the parameters specified for the optical interfaces of the PEG8.
Table 7-60 Parameters specified for the optical interfaces of the PEG8
Issue 03 (2013-02-20)
Parameter
Value
Type of
interface
1000BASE-SX
1000BASE-LX
1000BASEVX
1000BASE-ZX
Transmission
distance (km)
0.5
10
40
80
Type of fiber
Multi-mode LC
Single-mode LC
Single-mode
LC
Single-mode LC

156

Parameter
Value
Launched
optical power
range (dBm)
-9.5 to -2.5
-9 to -3
-5 to 0
-2 to 5
Operating
wavelength
range (nm)
770 to 860
1270 to 1355
1270 to 1355
1500 to 1580
Minimum
overload
(dBm)
-3
-3
-3
Receiver
sensitivity
(dBm)
-17
-20
-23
-23
Minimum
extinction ratio
(dB)
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Table 7-61 and Table 7-62 lists the parameters specified for the GE colored optical interfaces
of the PEG8.
Table 7-61 CWDM parameters specified for the colored optical interfaces of the PEG8
Parameter
Value
CWDM
Issue 03 (2013-02-20)
Nominal bit rate
1250000 kbit/s
Type of fiber
Single-mode LC
40
80

(dBm)
0 to 5
0 to 5

(nm)
1471 to 1611, in steps of

20
1471 to 1611, in steps of 20
-19
-28
-3
-9

157

Parameter
Value
CWDM

(ps/nm)
800
1600
8.2
8.2
Maximum -20 dB spectral

width (nm)
Minimum side mode

30
30
Table 7-62 DWDM parameters specified for the colored optical interfaces of the PEG8
Parameter
Value
DWDM
Nominal bit rate
1250000 kbit/s
Type of fiber
Single-mode LC
120

(dBm)
-1 to 3
Central frequency (THz)
192.1 to 196.0
Central frequency deviation

(GHz)
10
-28
-9

(ps/nm)
2400
8.2

(nm)
0.3
Minimum side mode

30
Parameters Specified for Electrical Interfaces

Table 7-63 lists the parameters specified for the electrical interfaces of the PEG8.
Issue 03 (2013-02-20)

158

Table 7-63 Parameters specified for the electrical interfaces of the PEG8
Parameter
Value
Nominal bit rate
1000 Mbit/s
Code pattern
4D-PAM5
Type of interface
RJ-45
Laser Safety Class

The mechanical specifications of the PEG8 are as follows:
l
Weight (kg): 1.2
Power Consumption
The maximum power consumption of the PEG8 at room temperature (25C) is 47 W.
7.4 PEG16
technical specifications of the PEG16 (16xGE Ethernet processing board). This topic also
describes how to configure and commission the PEG16.

The PEG16 is available in one functional version, namely, N1.
7.4.2 Application
The PEG16 is mainly used in the packet data transmission field to transmit/receive data packets,
manage bandwidths, and realize switching and aggregation of data packets.
Figure 7-11 shows the typical networking and application when the PEG16 works with the other
boards on the network. The PEG16 works with the cross-connect board that provides the packet
switching function to meet the requirement of packet features. With this board, the TDM domain
can be overlapped with the packet domain on the OptiX OSN equipment to transmit data in the
two domains. In this way, the equipment realizes the smooth evolution from the MSTP network
to the packet switching network.
For the typical networking and application when the PEG16 works with the PETF8, see 8.1.2
Application.
Issue 03 (2013-02-20)

159

Figure 7-11 Networking and application of the PEG16

OptiX OSN 3500/
7500
NMS
OptiX OSN 3500/

7500
OptiX OSN 3500/

7500
PSN
10GE ring
OptiX OSN 1500
OptiX OSN 1500

PSN
GE ring
OptiX OSN 1500
PSN
GE ring
OptiX OSN
3500/7500
OptiX OSN 1500
Traffic direction
GE processing board


The PEG16 receives/transmits and forwards 16xGE services, and supports the QoS functions
such as traffic measurement, congestion control, and queue scheduling for data packets.
Table 7-64
Table 7-64 Functions and features of the PEG16
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 16xGE services.
Interfa
ce
types
l Supports the 1000BASE-SX, 1000BASE-LX, 1000BASE-VX, and 1000BASEZX optical interfaces. The optical interface uses the LC connector and supports
the transmission distances of 0.5 km, 10 km, 40 km, and 80 km.
l Supports the CWDM colored optical interfaces. The optical interface uses the
LC connector and supports the transmission distance of 40 km.
Issue 03 (2013-02-20)

160

Funct
ion
and
Featu
re
Description
Functi
ons
when
being
used
with
an
interfa
ce
board
Provides interfaces on its front panel or works with the interface board PETF8. One
PEG16 board can receive/transmit the FE services of a maximum of two interface
boards.
Interfa
ce
charac
teristic
s
Hot
optical
module
swappin
g
Workin
g modes
Full-duplex and auto-negotiation for GE interfaces
Flow
control
at ports
Autonegotiation
mode
Not supported
Nonautonegotia
tion mode
Not supported
Servic
e
specifi
Issue 03 (2013-02-20)
Query/
Setting
of port
status
Supported
Query
of
interfac
e types
Supported
Setting
of
optical
power
threshol
ds
Supported
Processi
ng
capabili
ty

161

Funct
ion
and
Featu
re
Description
cation
s
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported
Maximum
number of
PWs
16k
MS-PW
Tunnel
specific
ations
Unidirectio
nal
Number of unidirectional MPLS tunnels (with the tunnels

shared): 4k
Bidirection
al
Number of bidirectional MPLS tunnels (with the tunnels

shared): 2k
MTU
MTU for
ports

MTU for
services

from 64 bytes to 9000 bytes.
E-Line
service
PW
specific
ations
Ethernet
service
capabili
ty
Issue 03 (2013-02-20)

E-LAN
service
Number of supported E-LAN services: 1020.
E-AGGR
service
4, each of which supports 127 leaf ports
Formats of
Ethernet
data frames

Maximum
number of
QinQ links
1k
Maximum
number of
VLANs
4k
Jumbo
frame

9000 bytes.
Number of static MAC addresses in E-LAN services: 2k.

162

Funct
ion
and
Featu
re
Description
Protec
tion
schem
es
MPLS
Tunnel
APS

Tunnel APS.
MPLS
PW
APS
Not supported
LAG
Number of supported MPLS Tunnel APS protection groups:1k

MCLAG
Not supported
Multipl
e
spannin
g tree
protocol
(MSTP)
Not supported
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Provides two GE optical interfaces (that is, the first two optical
interfaces) that support the synchronous Ethernet clock feature.
IEEE
1588v2
Not supported
Maint
enanc
e
featur
es
ETH
OAM
IEEE
802.1ag
IEEE
802.3ah

MPLS
tunnel
OAM

1711.
MPLS
OAM

MPLS PW
OAM
Issue 03 (2013-02-20)
Not supported

163

Funct
ion
and
Featu
re
Description
Loopba
ck
capabili
ty
PHY layer
at Ethernet
ports
MAC layer
at Ethernet
ports
Inloops
RMON
perform
ance
Supported
Inban
d
DCN
Supported
HQoS
Provides the hierarchical QoS function. The board provides the scheduling function
at multiple levels including the flow queue and port queue, the bandwidth restricting
function, and the corresponding statistical information.
IGMP
snoopi
ng
Supported
Query
of
electro
nic
labels
Supported

The PEG16 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
Figure 7-12 shows the functional block diagram of the PEG16.
Issue 03 (2013-02-20)

164

Figure 7-12 Functional block diagram of the PEG16

Backplane
GE signals
Interface board
IEEE 1588 V2 packet

Interface board
Data processing
module
16xGE signals
Upstream
Service
signal transmission module
Service
signal
Upstream
scheduling module
Packet forwarding
module
Downstream
transmission module
Downstream
scheduling module
Network processing
module
Transmission
management module
Switching network
buffering module
Service
signal
Parallel
management bus
Ethernet communication bus

CPU management
module
GSCC
Other boards
System clock
Working clock
Interface board
Interface board/First two GE signals
IEEE 1588 V2 packet
Interface board/First two GE signals
PSXCSA

Clock module
Synchronous Ethernet
clock
IEEE 1588 V2 packet
Power
module
PSXCSA
PSXCSA
PSXCSA
- 48 V / - 60 V
- 48 V / - 60 V
Interface board
Receive Direction
The network processing module receives the signals sent from the GE interface on the front
panel or the interface board, decodes the signals, and converts the serial signals into parallel
signals. Then, the network processing module performs route searching or address matching for
the data packets, and sends the corresponding packets to the transmission management module.
The transmission management module buffers and grooms the packets, slices the packets into
cells that the switching network requires, and sends the cells to the switching network buffering
module. The switching network buffering module buffers the cells and sends the cells to the
cross-connect unit.
Transmit Direction
converts the parallel signals into serial signals, and sends the signals to the GE interface on the
front panel of the PEG16 or the corresponding interface board through the backplane.

for data packets. The network processing module of the PEG16 can process the 10 Gbit/s data

Issue 03 (2013-02-20)

165

at five levels including the flow queue and port queue, the bandwidth restricting function,
and the corresponding statistical information.


buses to manage the modules of the PEG16 and the interface board to which the PEG16
corresponds. The CPU management module also monitors alarms and performance events and
reports the alarms and performance events to the SCC unit.
Clock Module
l
Provides the clock signal for each module of the PEG16.
Supports the transparent transmission of the IEEE 1588 V2 packets from the interface board
or the first two channels of GE signals to the PSXCS.
Selects a clock source from the two system clocks sent from the PSXCS and sends the
selected clock to the interface board and the modules of the PEG16.
Selects a clock source from the synchronous Ethernet clock signals accessed by the interface
board or the first two channels of GE signals and sends the selected clock to the PSXCS.
Power Module
the PEG16 require.
7.4.5 Front Panel

The front panel of the PEG16 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 7-13 shows the appearance of the front panel of the PEG16.
Issue 03 (2013-02-20)

166

Figure 7-13 Front panel of the PEG16
PEG16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT9
OUT1
IN9 OUT10 IN10 OUT11 IN11 OUT12 IN12
IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4
OUT1
OUT13 IN13 OUT14 IN14
IN15 OUT16 IN16
5
OUT5 IN5
OUT6 IN6 OUT7 IN7 OUT8 IN8
PEG16
Indicators
l
Interfaces
The front panel of the PEG16 has sixteen GE optical interfaces. Table 7-65 describes the types
and usage of the optical interfaces of the PEG16.
Issue 03 (2013-02-20)

167

Table 7-65 Optical interfaces of the PEG16

Interface
Type of Interface
Usage
IN1IN16
LC (pluggable)
Receives GE signals.
OUT1
OUT16
LC (pluggable)
Transmits GE signals.

The PEG16 does not have any jumpers or DIP switches that are used for board settings.
7.4.7 Valid Slots

The PEG16 occupies two slots and can be installed in any two adjacent slots among slots 16
and 1316. The PEG16 slot displayed on the U2000 is the slot that has a smaller slot number
between the two slots that house the PEG16. For example, if the PEG16 is installed in slots 1
and 2, the PEG16 slot displayed on the U2000 is slot 1.
When the PEG16 works with the interface board PETF8, one PEG16 board can work with a
maximum of two PETF8 boards. In this case, all the optical interfaces on the PEG16 can be
used. Table 7-66 lists the slots valid for the PEG16 and the corresponding slots for the PETF8.
Table 7-66 Slots valid for the PEG16 and the corresponding slots for the PETF8
Slot Valid for the
PEG16
Corresponding Slot for the

PETF8
Slots 1 and 2
Slot 1
Slots 3 and 4
Slot 3
Slots 21 and 22
Slots 5 and 6
Slot 5
Slots 25 and 26
Slots 13 and 14
Slot 13
Slots 29 and 30
Slots 15 and 16
Slot 15
Slots 33 and 34
NOTE
l The dual-slot board PEG16 cannot be configured together with the single-slot board N2PEX1/
N1PEX2/N1PEG8.
l When working with the cross-connect board SSN1PSXCS and the EDQ41 board, the dual-slot board
PEG16 cannot be housed in slot 1 or slot 15.
7.4.8 Feature Code

The PEG16 does not have the feature code.
Issue 03 (2013-02-20)

168



interface board and the cable match the board.
is correct.
----End

NOTE
l Configure the E-AGGR service. For details, see Configuring E-AGGR Services.
Issue 03 (2013-02-20)

169

----End

----End

Configuration.
Configuration.
l Check the E-AGGR service. For details, see Verifying the Correctness of E-AGGR Service
Configuration.
Boards.
the Current Alarms.
----End

The PEG16 supports the packet switching function and provides multiple packet switchingspecific functions and features, such as HQoS, LAG, and ETH OAM. Configure the functions
according to actual requirements.
You can configure the following packet switching functions for the PEG16 by using the
U2000:
l
HQoS
LAG
ETH OAM
Issue 03 (2013-02-20)

170

MPLS Tunnel APS
MPLS OAM
IGMP Snooping
Inband DCN
LPT
MS-PW

You can set parameters for the PEG16 by using the U2000.
Displayed Slots
The PEG16 occupies two slots in the subrack. The logical slot of the PEG16 displayed on the
U2000 is the slot that has a smaller slot number between the two slots that house the PEG16.
For the logical slots of the PEG16 displayed on the U2000, refer to Table 7-66.
Board Parameters
You can set the following principal parameter for the PEG16 by using the U2000:
l
Ethernet interface
For more parameters and the description of the parameters, see 27.1 Packet Processing
Boards.

Troubleshooting
Table 7-67 lists the faults that occur on the PEG16 frequently and the troubleshooting methods.
Table 7-67 Methods used to troubleshoot the faults that occur on the PEG16 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.

Interruptions.
l The service loses

packets or has
errored packets.
fault
Issue 03 (2013-02-20)
The MPLS APS

switching fails.
See Troubleshooting.

171

Replacing the Board

NOTE
replace the board.
For information on how to replace the PEG16, see Replacing a Packet Processing Board.

7.4.13.1 Alarms of N1PEG16
Issue 03 (2013-02-20)
ALM_ALS
BD_STATUS
ETH_APS_LOST
BUS_ERR
COMMUN_FAIL
ETH_APS_SWITCH_FAIL
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_LOC
ETH_EFM_DF
ETH_EFM_EVENT
ETH_CFM_UNEXPERI
ETH_EFM_REMFAULT
ETH_LINK_DOWN
ETH_EFM_LOOPBACK
FDBSIZEALM_ELAN
FLOW_OVER
ETH_LOS
HARD_BAD
HARD_ERR
IN_PWR_ABN
LAG_DOWN
LAG_MEMBER_DOWN
LASER_MOD_ERR
LASER_SHUT
LOOP_ALM
LSR_BCM_ALM
LSR_NO_FITED
LSR_WILL_DIE
MAC_FCS_EXC
MPLS_TUNNEL_BDI
MPLS_TUNNEL_Excess
MPLS_TUNNEL_FDI
MPLS_TUNNEL_LOCV
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
MPLS_TUNNEL_UNKNOWN
NO_BD_SOFT
POWER_ABNORMAL
TEMP_OVER
PW_EXC_TRAFFIC
OUT_PWR_ABN
TEST_STATUS
TEM_HA
TEM_LA
PW_NO_TRAFFIC
W_OFFLINE
TR_LOC
IN_PWR_LOW
LPT_CFG_CLOSEPORT
WRG_BD_TYPE
IN_PWR_HIGH
ETHOAM_SELF_LOOP

172

TUNNEL_APS_DEGRADED

7.4.14.1 Performance Events of N1PEG16

Table 7-68 SDH
BDTEMPCUR
BDTEMPMAX
BDTEMPMIN
CPUUSAGECUR
CPUUSAGEMAX
CPUUSAGEMIN
MEMUSAGECUR
MEMUSAGEMAX
MEMUSAGEMIN
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR

ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV
ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_UAS
ETH_CFM_CSLS

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 7-71 Tunnel

TUNNEL_SNDPKTS
Issue 03 (2013-02-20)
TUNNEL_SNDBYTES

TUNNEL_RCVPKTS
173

TUNNEL_RCVBYTES
TUNNEL_RX_BPS
TUNNEL_TX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_PPS
TUNNEL_REVERSE_RX_B
PS
TUNNEL_REVERSE_TX_
BPS
TUNNEL_REVERSE_RX
_PPS
TUNNEL_REVERSE_TX_P
PS
Table 7-72 PW
PW_SNDPKTS
PW_SNDBYTES
PW_DROPPKTS
PW_DROPBYTES
PW_RCVPKTS
PW_RCVBYTES
PW_AVAILABILITY
PW_RX_BPS
PW_TX_BPS
PW_RX_PPS
PW_TX_PPS
Table 7-73 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
Table 7-74 QoS

QOS_PRI_DROPPKTS
QOS_PRI_DROPBYTES

ETHDROP
RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHCRCALI
ETHUNDER
ETHOVER
ETHFRG
ETHJAB
ETHCOL
RXPKT64
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024

RXCTLPKTS
Issue 03 (2013-02-20)
TXOCTETS
TXPKTS
174

TXCTLPKTS
TXBRDCAST
TXMULCAST
TXPKT64
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
Table 7-77 Statistics of specific performance events of RMON

TXPAUSE
ETHALI
ETHFCS
PKT64
PKT65
PKT128
PKT256
PKT512
PKT1024
TXETHDROP

The technical specifications of the PEG16 include the Ethernet performance specifications, laser
safety class, parameters specified for optical interfaces, mechanical specifications, and power
consumption.

Table 7-78 lists the parameters specified for the optical interfaces of the PEG16.
Table 7-78 Parameters specified for the optical interfaces of the PEG16
Issue 03 (2013-02-20)
Parameter
Value
Type of
interface
1000BASE-SX
1000BASE-LX
1000BASEVX
1000BASE-ZX
Transmission
distance (km)
0.5
10
40
80
Type of fiber
Multi-mode LC
Single-mode LC
Single-mode
LC
Single-mode LC
Launched
optical power
range (dBm)
-9.5 to -2.5
-9 to -3
-5 to 0
-2 to 5
Operating
wavelength
range (nm)
770 to 860
1270 to 1355
1270 to 1355
1500 to 1580
Minimum
overload
(dBm)
-3
-3
-3

175

Parameter
Value
Receiver
sensitivity
(dBm)
-17
-20
-23
-23
Minimum
extinction ratio
(dB)
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Table 7-79 lists the parameters specified for the colored optical interfaces of the PEG16.
Table 7-79 Parameters specified for the colored optical interfaces of the PEG16
Parameter
Value
CWDM
Issue 03 (2013-02-20)
Nominal bit rate
1250000 kbit/s
Type of fiber
Single-mode LC
40

(dBm)
0 to 5

(nm)
1471 to 1611, in steps of 20
-19
-3

(ps/nm)
800
8.2

(nm)
Minimum side mode

30

176

Laser Safety Class

The mechanical specifications of the PEG16 are as follows:
l
Weight (kg): 2.3
Power Consumption
The maximum power consumption of the PEG16 at room temperature (25C) is 137 W.
Issue 03 (2013-02-20)

177

8 Packet Interface Boards
Packet Interface Boards
About This Chapter

The packet interface boards include the PETF8, PEFF8, CQ1, MD12, and MD75. They provide
packet switching boards with cable input/output interfaces for myriad signals.
8.1 PETF8
technical specifications of the PETF8 (8xFE electrical interface board). This topic also describes
how to configure and commission the PETF8.
8.2 PEFF8
technical specifications of the PEFF8 (8-port fast Ethernet optical interface processing board).
This topic also describes how to configure and commission the PEFF8.
8.3 CQ1
technical specifications of the CQ1 (4-channel channelized STM-1 CES optical interface board).
8.4 MD12
technical specifications of the MD12 (multi-protocol 32-channels E1 interface processing
board). This topic also describes how to configure and commission the MD12.
8.5 MD75
Issue 03 (2013-02-20)

178

8.1 PETF8
technical specifications of the PETF8 (8xFE electrical interface board). This topic also describes
how to configure and commission the PETF8.

The PETF8 is available in one functional version, namely, N1.
8.1.2 Application
The PETF8 is mainly used in the packet data transmission field to transmit/receive data packets,
Figure 8-1 shows the typical networking and application of the PETF8. The PETF8 works with
on the OptiX OSN equipment to transmit data in the two domains. In this way, the equipment
realizes the smooth evolution from the MSTP network to the packet switching network.
Figure 8-1 Networking and application of the PETF8
NMS
NE1
User A2
NE2
PSN
NE4
NE3
User B2
Traffic direction
User B1
PEG8/PEG16
PETF8
Dual-domain (TDM domain
and packet domain) cross- User A1
connect board
Issue 03 (2013-02-20)

179


The PETF8 receives/transmits 8xFE electrical signals and works with the PEG8/PEG16 to
process services.
Table 8-1 provides the functions and features of the PETF8. When the PETF8 works with the
PEG8, 7.3.3 Functions and Features describes the functions and features of the PETF8; when
the PETF8 works with the PEG16, 8.1.3 Functions and Features describes the functions and
features of the PETF8.
Table 8-1 Functions and features of the PETF8
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 8xFE electrical signals.
Interfa
ce
types
Uses the RJ45 connector and meets the specifications of the 100BASE-TX physical
layer provided in IEEE 802.3.
Interfa
ce
charac
teristic
s
Hot
optical
module
swappin
g
Not supported
Workin
g modes
Supports the configuration of the full-duplex mode or auto-negotiation

mode for the FE electrical port (in auto-negotiation mode, only the 100
Mbit/s full-duplex working mode is supported).
Flow
control
at ports
Autonegotiation
mode
Not supported
Nonautonegotia
tion mode
Not supported
Query/
Setting
of port
status
Supported
Query
of
interfac
e types
Not supported

180

Funct
ion
and
Featu
re
Servic
e
specifi
cation
s
Description
Setting
of
optical
power
threshol
ds
Not supported
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported
MTU for
ports
When working with the PEG16, the PETF8 does not

support the setting of the packet length, which takes the
default value of 9600 bytes. When working with the
PEG8, the PETF8 supports the setting of the packet length,
setting becomes valid, the length of a packet that enters or
exits a port is restricted by the MTU pre-set for the port.
MTU for
services
For packet services carried by PWs, the PETF8 supports

modes, the PETF8 does not support the setting of the
packet length.
E-Line
service
Supported
E-LAN
service
Supported
E-AGGR
service
Not supported
Formats of
Ethernet
data frames

Jumbo
frame
When working with PEG8 boards, PETF8 boards support

a jumbo frame with a maximum length of 1976 bytes.
MTU
Ethernet
service
capabili
ty
When working with PEG16 boards, PETF8 boards

support a jumbo frame with a maximum length of 9000
bytes.
MS-PW
Issue 03 (2013-02-20)
Supports static MS-PWs.

181

Funct
ion
and
Featu
re
Description
Protec
tion
schem
es
MPLS
Tunnel
APS

Tunnel APS.
MPLS
PW
APS

1:1 (dual-ended) MPLS PW APS when working with the PEG8.
LAG
Does not support MPLS PW APS when working with the PEG16.

MCLAG
Supports MC-LAG when working with the PEG8 in compliance with

802.3ad and IEEE 802.1AX.
Does not support MC-LAG when working with the PEG16.
Issue 03 (2013-02-20)
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Supports eight channels of synchronous Ethernet clocks.
IEEE
1588v2
Supports eight channels of IEEE 1588v2 clocks.
Loopb
ack
capabi
lity
PHY
layer at
Ethernet
ports
Inloops
MAC
layer at
Ethernet
ports
Inban
d
DCN
Supported
HQoS

182

Funct
ion
and
Featu
re
Description
IGMP
snoopi
ng
Supported
Query
of
electro
nic
labels
Supported

The PETF8 consists of the access and converging module, control and driving module, voltage
detecting module, clock module, and power module.
Figure 8-2 shows the functional block diagram of the PETF8.
Figure 8-2 Functional block diagram of the PETF8
Voltage detecting
module
8xFE electrical
signals
Voltage detecting
signal
Management bus
IEEE
Control and
GE service
1588 V2 driving module
signal
Backplane
GE
Access and
converging
module
Synchronous
clock
IEEE
Working
1588 V2
clock signal
signal
One system clock
Working clock
signal
Clock
module
IEEE 1588 V2 packet
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
Modules of
the board
Modules of
the board
Pow er
module
Fuse
Fuse
PEG16/PEG8
+3.3 V backup pow er
Upstream Direction
The services in the upstream direction are accessed by the FE ports. The service packets are
added with different VLAN tags according to the ingress ports. Then, the services are transmitted
to the GE port on the backplane side. As a result, the FE services are converged into the GE
services. After the PEG16 receives the packets, the PEG8/PEG16 identifies the ports to which
the services correspond according to the VLAN tags and strips the VLAN tags.
Issue 03 (2013-02-20)

183

Downstream Direction
The services in the downstream direction are added with VLAN tags on the PEG8/PEG16
according to the destination ports. Then, the services are accessed by the GE port on the
backplane side. The VLAN tags indicate the destination ports of the service packets. The service
packets are sent to the destination ports after the VLAN tags are stripped.
Access and Converging Module

The access and converging module performs the following functions:
l
Transmits/Receives 8xFE electrical signals.
Converges 8xFE services into 1xGE services on the backplane side.
Extracts the IEEE 1588 V2 clock information.
Control and Driving Module

The control and driving module performs the following functions:
l
Detects the system status through the management control bus.

Checks whether the board is properly inserted.
Detects the voltage of the PETF8.
Realizes the hot-swappable function of the PETF8.
Voltage Detecting Module

The voltage detecting module monitors the voltage.
Clock Module
l
Provides the working clock signal for each module of the PETF8.
Power Module
the PETF8 require.
8.1.5 Front Panel

The front panel of the PETF8 has indicators, interfaces, and a bar code.

Figure 8-3 shows the appearance of the front panel of the PETF8.
Issue 03 (2013-02-20)

184

Figure 8-3 Front panel of the PETF8
PETF8
STAT
ACT
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
PETF8
Indicators
l
Service alarm indicator (SRV) two colors (red and green)
Connection status indicator (LINK) one color (green and located on the RJ45 connector)
Data receiving and transmission indicator (ACT) one color (orange and located on the
RJ45 connector)
Issue 03 (2013-02-20)

185

Interfaces
The front panel of the PETF8 has eight FE electrical interfaces. Table 8-2 describes the types
and usage of the electrical interfaces of the PETF8.
Table 8-2 Electrical interfaces of the PETF8
Interface
Type of Interface
Usage
FE1FE8
RJ-45
Transmits and receives FE signals.

The PETF8 does not have any jumpers or DIP switches that are used for board settings.
8.1.7 Valid Slots

The PETF8 must be installed in a valid slot on the subrack. Otherwise, the PETF8 fails to work
normally.
The PETF8 can be installed in slots 1926, and 2936 in the subrack.
The PETF8 works as the interface board for the PEG8 and PEG16. For the slots valid for the
PEG8 and PEG16 and the corresponding slots for the PETF8, refer to Table 7-48 and Table
7-66.
8.1.8 Feature Code

The PETF8 does not have the feature code.


Issue 03 (2013-02-20)

186

is correct.
----End

NOTE
----End

----End

Issue 03 (2013-02-20)

187

Configuration.
Configuration.
Boards.
the Current Alarms.
----End

You can set the parameters for the PETF8 by using the U2000.
You can set the following parameters for the PETF8 by using the U2000:
l
Ethernet interface
For more parameters the description of the parameters, see 27.1 Packet Processing Boards.

Troubleshooting
Table 8-3 lists the faults that occur on the PETF8 frequently and the troubleshooting methods.
Table 8-3 Methods used to troubleshoot the faults that occur on the PETF8 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.

Interruptions.
l The service loses

packets or has
errored packets.
fault
l The tunnel APS

switching fails.

Switching.
l The PW APS
switching fails.
l The MC-LAG
switching fails.
Issue 03 (2013-02-20)

188

Replacing the Board

NOTE
replace the board.
For information on how to replace the PETF8, see Replacing a Packet Interface Board.

8.1.12.1 Alarms of N1PETF8
Issue 03 (2013-02-20)
TEMP_OVER
HARD_BAD
HARD_ERR
POWER_ABNORMAL
BD_STATUS
WRG_BD_TYPE
FLOW_OVER
LOOP_ALM
ETH_LOS
ETH_LINK_DOWN
MAC_FCS_EXC
FDBSIZEALM_ELAN
MPLS_TUNNEL_LOCV
MPLS_TUNNEL_Excess
MPLS_TUNNEL_UNKNOWN
MPLS_TUNNEL_BDI
MPLS_TUNNEL_FDI
MPLS_TUNNEL_SD
MPLS_TUNNEL_SF
ETH_CFM_UNEXPERI
PW_EXC_TRAFFIC
ETH_CFM_MISMERGE
ETH_EFM_DF
ETH_CFM_LOC
ETH_CFM_RDI
ETH_EFM_LOOPBACK
ETH_EFM_REMFAULT
ETH_EFM_EVENT
ETH_APS_LOST
ETH_APS_SWITCH_FAIL
LAG_MEMBER_DOWN
PW_NO_TRAFFIC
LPT_CFG_CLOSEPORT
MPLS_PW_Excess
LAG_DOWN
MPLS_PW_LOCV
MPLS_PW_UNKNOWN
MPLS_PW_MISMATCH
MPLS_PW_MISMERGE
MPLS_PW_SF
MPLS_PW_BDI
MPLS_PW_SD
PWAPS_SWITCH_FAIL
PWAPS_TYPE_MISMATCH
PWAPS_PATH_MISMATCH
MCLAG_CFG_MISMATCH
PWAPS_LOST
MCSP_PATH_LOCV
ETHOAM_SELF_LOOP
PORTMODE_MISMATCH
TUNNEL_APS_DEGRADED
BWUTILIZATION_OVER
MPLS_PW_OAMFAIL
DROPRATIO_OVER

189

ETH_NO_FLOW
MPLS_TUNNEL_OAMFAIL
PORT_EXC_TRAFFIC
SRV_SHUTDOWN_LD

8.1.13.1 Performance Events of N1PETF8

Table 8-4 SDH
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR

ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_CSLS
ETH_CFM_UAS
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
NOTE
Table 8-7 provides the statistical items of tunnel supported by the N1PETF8 when the N1PETF8 works
together with the PEG8.
Table 8-7 Tunnel
Issue 03 (2013-02-20)
TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SNDP
KTS
TUNNEL_REVERSE_SN
DBYTES
TUNNEL_REVERSE_RC
VPKTS
TUNNEL_REVERSE_RCV
BYTES

190

NOTE
Table 8-8 provides the statistical items of tunnel supported by the N1PETF8 when the N1PETF8 works
together with the PEG8.
Table 8-8 Tunnel

TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TUNNEL_REVERSE_SN
DPKTS
TUNNEL_REVERSE_SND
BYTES
TUNNEL_REVERSE_RC
VPKTS
TUNNEL_REVERSE_RC
VBYTES
NOTE
Table 8-9 provides the statistical items of MPLS PW OAM supported by the N1PETF8 when the N1PETF8
works together with the PEG8. When working together with the PEG16, the N1PETF8 does not support
MPLS PW OAM performance measurement.

MPLS_PW_LS
MPLS_PW_SLS
MPLS_PW_CSLS
MPLS_PW_UAS
MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV
Table 8-10 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDBYTES
PW_BANDWIDTH_UT
ILISATION
PW_SNDPKTS
Table 8-11 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES
NOTE
Table 8-12 and Table 8-13 provide the statistical items supported by the N1PETF8 when the N1PETF8
works together with the PEG8.
Issue 03 (2013-02-20)

191


RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHUNDER
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024

RXPKT1519
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
PKT65
PKT128
PKT256
PKT512
PKT1024
PKT1519
RXUNICAST
TXUNICAST
TXMULCAST
TXBRDCAST
ETHFCS
TXPKTS
TXOCTETS
NOTE
Table 8-14 and Table 8-15 provide the statistical items supported by the N1PETF8 when the N1PETF8
works together with the PEG16.

RXPKTS
RXOCTETS
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024
RXBRDCAST
RXMULCAST
ETHUNDER
Issue 03 (2013-02-20)
TXPKTS
TXOCTETS
TXUNICAST
TXBRDCAST
TXMULCAST
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
RXUNICAST
RXPKT1519
PKT1519
ETHFCS

192

PKT65
PKT128
PKT256
PKT512
PKT1024
PORT_RX_BYTES_AVA
ILABILITY

The technical specifications of the PETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.

Table 8-16 lists the parameters specified for the electrical interfaces of the PETF8.
Table 8-16 Parameters specified for the electrical interfaces of the PETF8
Parameter
Value
Nominal bit rate
100 Mbit/s
Type of electrical interface
RJ-45
Line code pattern
MLT-3 encoding signal (100M)
Specifications of the
interface
Complies with IEEE 802.3u.
The mechanical specifications of the PETF8 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the PETF8 at room temperature (25C) is 6 W.
8.2 PEFF8
technical specifications of the PEFF8 (8-port fast Ethernet optical interface processing board).
This topic also describes how to configure and commission the PEFF8.

The PEFF8 is available in one functional version, namely, N1.
Issue 03 (2013-02-20)

193

8.2.2 Application
The PEFF8 is mainly used in the packet data transmission field to transmit/receive data packets,
manage bandwidths, and implement switching of data packets.
Figure 8-4 shows the typical networking and application of the PEFF8. The PEFF8 works with
Figure 8-4 Networking and application of the PEFF8
NMS
NE1
User A2
NE2
PSN
NE4
NE3
User B2
Traffic direction
User B1
PEG8
PEFF8
Dual-domain (TDM domain
and packet domain) cross- User A1
connect board

The PEFF8 receives/transmits 8xFE optical signals and works with the PEG8 to process services.
Table 8-17 lists the functions and features of the PEFF8. When working with the PEG8, the
PEFF8 supports the functions and features as described in 7.3.3 Functions and Features.
Issue 03 (2013-02-20)

194

Table 8-17 Functions and features of the PEFF8

Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 8xFE optical signals.
Interfa
ce
types
Supports 100Base-FX/LX/VX/ZX Ethernet optical interfaces. The optical interface

uses the LC connector and supports the transmission distances of 2 km, 15 km, 40
km, and 80 km.
Interfa
ce
charac
teristic
s
Hot
optical
module
swappin
g
Workin
g modes
100M full duplex
Flow
control
at ports
Autonegotiation
mode
Not supported
Nonautonegotia
tion mode
Not supported
Servic
e
specifi
cation
s
Issue 03 (2013-02-20)
Query/
Setting
of port
status
Supported
Query
of
interfac
e types
Supported
Setting
of
optical
power
threshol
ds
Supported
Service
bearing
modes
MPLS
Supported
QinQ
Supported
Port
Supported

195

Funct
ion
and
Featu
re
Description
MTU
Ethernet
service
capabili
ty
Protec
tion
schem
es
MTU for
ports

MTU for
services
For packet services carried by PWs, the PEFF8 supports

modes, the PEFF8 does not support the setting of the
packet length.
E-Line
service
Supported
E-LAN
service
Supported
E-AGGR
service
Not supported
Formats of
Ethernet
data frames

Jumbo
frame

1976 bytes.
MS-PW
Supports static MS-PWs.
MPLS
Tunnel
APS

Tunnel APS.
MPLS
PW
APS

1:1 (dual-ended) MPLS PW APS.
LAG

Issue 03 (2013-02-20)
MCLAG
Supported when working with a PEG8 board in compliance with 802.3ad

and IEEE 802.1AX.
LPT for
packet
services
Point-topoint LPT
Supported
Point-tomultipoint
LPT
Supported

196

Funct
ion
and
Featu
re
Description
Clock
synchr
onizati
on
Synchro
nous
Ethernet
Supports eight channels of synchronous Ethernet clock signals.
IEEE
1588v2
Supports eight channels of IEEE 1588v2 clocks.
Loopb
ack
capabi
lity
PHY
layer at
Ethernet
ports
Inloops
MAC
layer at
Ethernet
ports
Inban
d
DCN
Supported
HQoS
RMO
N
perfor
mance
Supported
IGMP
snoopi
ng
Supported
Query
of
electro
nic
labels
Supported

The PEFF8 consists of the access and converging module, control and driving module,
Figure 8-5 shows the functional block diagram of the PEFF8.
Issue 03 (2013-02-20)

197

Figure 8-5 Functional block diagram of the PEFF8

Voltage
detecting module
Voltage detecting signal
8xFE optical
signals
GE
Access and
converging
module
Synchronous
clock
IEEE
1588v2
signal
Management bus
Control and
driving module
IEEE1588v2 signal
Working clock
signal
Backplane
GE service
PEG8
PEG8
Working clock signal

One channel of system clock
Clock
module

IEEE 1588 V2 packet
PEG8
PEG8
PEG8
Each module of board

Each module
of board
Pow er
module
Fuse
Fuse
PEG8
+3.3 V backup pow er
Upstream direction
The services in the upstream direction are accessed by the FE ports. The service packets are
added with different VLAN tags based on the ingress ports. Then, the services are transmitted
to the GE port on the backplane side. As a result, the FE services are converged into the GE
services. After receiving the packets, the PEG8 identifies the ports to which the services
correspond based on the VLAN tags and strips the VLAN tags.
Downstream direction
The services in the downstream direction are added with VLAN tags on the PEG8 based on the
destination ports. Then, the services are accessed by the GE port on the backplane side. The
destination ports of the service packets are determined based on the VLAN tags. After the
destination ports of the service packets are determined, the VLAN tags are striped and the
services are sent to the destination ports.
Access and Converging Module

The access and converging module performs the following functions:
l
Transmits/Receives 8xFE optical signals.
Converges 8xFE services into 1xGE services on the backplane side.
Extracts IEEE 1588 V2 clock information.
Control and Driving Module

The control and driving module performs the following functions:
l
Detects the system status through the management control bus.

Checks whether the board is properly inserted.
Tests the voltage status.
Issue 03 (2013-02-20)

198

Implements the hot-pluggable function of the PEFF8.
Voltage Test Module

The voltage test module mainly provides the voltage monitoring function.
Clock Module
l
Provides the working clock signal for each module of the PEFF8.
Power Module
the board require.
8.2.5 Front Panel

The front panel of the PEFF8 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 8-6 shows the appearance of the front panel of the PEFF8.
Issue 03 (2013-02-20)

199

Figure 8-6 Front panel of the PEFF8
PEFF8
STAT
ACT
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4

OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
L/A 1
L/A 2
L/A 3
L/A 4
L/A 5
L/A 6
L/A 7
L/A 8
PEFF8
Indicators
l
Service alarm indicator (SRV) two colors (red and green)
Connection status indicator (L/A1-L/A8) two colors (yellow and green)
Interfaces
The front panel of the PEFF8 has eight FE optical interfaces. Table 8-18 describes the interfaces
of the PEFF8.
Issue 03 (2013-02-20)

200

Table 8-18 Interfaces of the PEFF8

Interface
Type of Interface
Usage
IN1-IN8
LC (pluggable)
Receives FE signals.
OUT1OUT8
LC (pluggable)
Transmits FE signals.
8.2.6 Valid Slots

The PEFF8 must be installed in a valid slot on the subrack. Otherwise, the PEFF8 fails to work
normally.
The PEFF8 can be installed in slots 1926, and 2936 in the subrack.
The PEFF8 works as the interface board of the PEG8. For the slots valid for the PEG8, see Table
7-48.
8.2.7 Feature Code

The PEFF8 does not have the feature code.


is correct.
----End

Issue 03 (2013-02-20)

201

NOTE
----End

----End

Configuration.
Configuration.
Boards.
Issue 03 (2013-02-20)

202

the Current Alarms.
----End

The PEFF8 supports the packet switching function and multiple packet functions and features,
such as HQoS, LAG, and ETH OAM. Configure the functions according to actual requirements.
You can configure the following packet functions for the PEFF8 by using the U2000:
l
HQoS
LAG
ETH OAM
MPLS Tunnel APS
MPLS OAM
IGMP Snooping
Inband DCN
LPT
MPLS PW APS
MC-LAG
MS-PW

You can set the parameters for the PEFF8 by using the U2000.
You can set the following parameters for the PEFF8 by using the U2000.
l
Ethernet interface
Processing Boards.

Troubleshooting
Table 8-19 lists the faults that occur on the PEFF8 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

203

Table 8-19 Methods used to troubleshoot the faults that occur on the PEFF8 frequently
Fault Symptom
Common Fault
Cause
Service
troubleshooting
l The service is
interrupted.

Interruptions.
l The service loses

packets or has
errored packets.
fault
l The tunnel APS

switching fails.

Switching.
l The PW APS
switching fails.
l The MC-LAG
switching fails.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PEFF8, see Replacing a Packet Interface Board.

8.2.12.1 Alarms of N1PEFF8
Issue 03 (2013-02-20)
TEMP_OVER
HARD_BAD
HARD_ERR
POWER_ABNO
RMAL
BD_STATUS
WRG_BD_TYPE
LSR_NO_FITED
LASER_MOD_ERR
LASER_SHUT
ALM_ALS
LSR_WILL_DIE
IN_PWR_ABN
OUT_PWR_AB
N
TEM_HA
TEM_LA
LSR_BCM_AL
M
FLOW_OVER
LOOP_ALM
ETH_LOS
ETH_LINK_DOWN
MCLAG_CFG_MISMATCH
FDBSIZEALM_
ELAN
MPLS_TUNNEL_L
OCV
MPLS_TUNNEL_Excess

204

MPLS_TUNNEL
_MISMATCH
MPLS_TUNNEL_
MISMERGE
MPLS_TUNNEL_UNKNOWN
MPLS_TUNNEL
_BDI
MPLS_TUNNEL_F
DI
MPLS_TUNNEL_SD
MPLS_TUNNEL
_SF
ETH_CFM_UNEXP
ERI
PW_EXC_TRAFFIC
ETH_CFM_MIS
MERGE
ETH_EFM_DF
ETH_CFM_LOC
ETH_CFM_RDI
ETH_EFM_LOOPB
ACK
ETH_EFM_REMFAULT
ETH_EFM_EVE
NT
ETH_APS_SWITC
H_FAIL
ETH_APS_PAT
H_MISMATCH
LAG_DOWN
ETH_APS_LOST
LAG_MEMBER
_DOWN
IN_PWR_LOW
PW_NO_TRAFFIC
IN_PWR_HIGH
MPLS_PW_Excess
MPLS_PW_MISMATCH
MPLS_PW_LOC
V
MPLS_PW_UNKN
OWN
MPLS_PW_BDI
MPLS_PW_MIS
MERGE
PWAPS_TYPE_MI
SMATCH
MPLS_PW_SD
MPLS_PW_SF
PWAPS_LOST
PWAPS_PATH_MISMATCH
PWAPS_SWITC
H_FAIL
LPT_CFG_CLOSEPORT
MCSP_PATH_LOCV
ETHOAM_SELF
_LOOPSSN1PEF
F8
MAC_FCS_EXC
TUNNEL_APS_DEGRADED
BWUTILIZATI
ON_OVER
MPLS_PW_OAMF
AIL
DROPRATIO_OVER
ETH_NO_FLO
W
MPLS_TUNNEL_O
AMFAIL
PORT_EXC_TRAFFIC
SRV_SHUTDO
WN_LD

Issue 03 (2013-02-20)

205

8.2.13.1 Performance Events of N1PEFF8

Table 8-20 SDH
BDTEMPMIN
BDTEMPCUR
BDTEMPMAX
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
ETH_CFM_LS
ETH_CFM_SLS
ETH_CFM_CSLS
ETH_CFM_UAS
ETH_CFM_FLR
ETH_CFM_FL
ETH_CFM_FD
ETH_CFM_FDV

MPLS_TUNNEL_LS
MPLS_TUNNEL_SLS
MPLS_TUNNEL_CSLS
MPLS_TUNNEL_UAS
MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 8-23 Tunnel

TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SNDP
KTS
TUNNEL_REVERSE_SN
DBYTES
TUNNEL_REVERSE_RC
VPKTS
TUNNEL_REVERSE_RCV
BYTES
Issue 03 (2013-02-20)
MPLS_PW_LS
MPLS_PW_SLS
MPLS_PW_CSLS
MPLS_PW_UAS
MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV

206

Table 8-25 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDBYTES
PW_BANDWIDTH_UT
ILISATION
PW_SNDPKTS
Table 8-26 L2VPN

VUNI_RCVPKTS
VUNI_RCVBYTES
VUNI_SNDPKTS
VUNI_SNDBYTES

RXOCTETS
RXPKTS
RXBRDCAST
RXMULCAST
ETHUNDER
RXPKT65
RXPKT128
RXPKT256
RXPKT512
RXPKT1024

RXPKT1519
TXPKT65
TXPKT128
TXPKT256
TXPKT512
TXPKT1024
TXPKT1519
PKT65
PKT128
PKT256
PKT512
PKT1024
PKT1519
RXUNICAST
TXUNICAST
TXMULCAST
TXBRDCAST
ETHFCS
TXPKTS
TXOCTETS

The technical specifications of the PEFF8 include the parameters specified for optical interfaces,
Specifications Specified for Optical Interfaces

Table 8-29 provides the specifications of the optical interfaces on the PEFF8.
Issue 03 (2013-02-20)

207

Table 8-29 Specifications of the electrical interfaces

Item
Value
Type of
interface
100BASEZX
100BASEVX
100BASE-LX
100BASE-FX
Transmission
distance (km)
80
40
15
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode LC
Multi-mode LC
Launched
optical power
range (dBm)
-5 to 0
-5 to 0
-15 to -8
-19 to -14
Operating
wavelength
range (nm)
1480 to 1580
1263 to 1360
1261 to 1360
1270 to 1380
Minimum
overload
(dBm)
-10
-10
-8
-14
Receiver
sensitivity
(dBm)
-34
-34
-28
-30
Minimum
extinction ratio
(dB)
10
10
8.2
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
Laser Safety Class

The mechanical specifications of the PEFF8 are as follows:
l
Weight: 0.5 kg
Issue 03 (2013-02-20)

208

Power Consumption
The maximum power consumption of the PEFF8 at room temperature (25C) is 13 W.
8.3 CQ1
technical specifications of the CQ1 (4-channel channelized STM-1 CES optical interface board).

The CQ1 is available in one functional version, namely, N1.
8.3.2 Application
The CQ1 directly receives channelized STM-1 services from the TDM domain, transmits the
channelized STM-1 services on the packet ring, and directly separates the channelized STM-1
services from other services on the Base Station Controller (BSC) side. In this manner, the
smooth evolution from the TDM domain to the packet domain is implemented.
Figure 8-7 shows the application of the CQ1. The CQ1 works with the PEG8 to transmit
channelized STM-1 services on the packet ring.
Issue 03 (2013-02-20)

209

Figure 8-7 Networking and application of the CQ1

BSC
RNC
NMS
GE
STM-1
CQ1
PEX2
PEX2
PEG8
PEG8
PEX2
PEX2
10GE Ring
CQ1
STM-1
Ring
Packet ring
FE
TDM ring
GE Ring
STM-1
Ring
STM1/STM-4
Ring
E1
E1
FE
Traffic direction
Dual-domain (TDM
domain and packet
domain) crossconnect board
NodeB
BTS
BTS
NodeB

The CQ1 receives four-port channelized STM-1 services, and works with the PEG8 to process
CES service signals.
Table 8-30 provides the functions and features of the CQ1.
Table 8-30 Functions and features of the CQ1
Issue 03 (2013-02-20)
Function and
Feature
CQ1
Basic functions
Transmits and receives four-port channelized STM-1 optical signals, and

works with the PEG8 to process four-port channelized STM-1 CES
services.
Interface types
Supports different types of standard optical interfaces, namely, S-1.1,

L-1.1, and L-1.2 to meet requirements for transmission distances. The
characteristics of the optical interfaces comply with ITU-T G.957.

210

Function and
Feature
CQ1
Interface
characteristics
ALS
Not supported
Loopback types of the port
Inloop
Outloop
Non-loopback
CES
Auto disabling of port loopback
Supported
Detection and query of optical

module information
Supported
Hot insertion and removal of SFP

optical modules
Supported
Supported CES services
252
Supported emulation mode
CESoPSN
SAToP
Supports the timeslot compression function. In the case of the CES

service in CESoPSN mode, the CQ1 compresses idle timeslots to
improve the bandwidth utilization on the NNI side.
The jitter compensation buffering time of CES services can be set to a
value in the range of 0.375 ms to 16 ms with a step of 0.125 ms.
The packet loading time of CES services can be set to a value in the range
of 0.25 ms to 5 ms with a step of 0.125 ms.
NOTE
l The packet loading time needs to be set to the same value for the NEs at both
ends.
l The jitter compensation buffering time needs to be more than at least two times
of the packet loading time.
Protection
scheme
Supports the 1+1 and 1:1 Packet-based linear MSP.
SSM protocol
Supported
PRBS
Not supported
Query of laser
transmission
distance
Supported

The CQ1 consists of the line processing module, CES service processing module, management
module, clock module, and power module.
Figure 8-8 shows the functional block diagram of the CQ1.
Issue 03 (2013-02-20)

211

Figure 8-8 Functional block diagram of the CQ1

Backplane
4-port channelized
STM-1 signals
Line
processing
module
Service signal
Management bus
3.3.V
.
.
1.2 V
.
.
.
Clock
module
Service
signal
PEG8
Management bus
Management
module
Line clock
CES service
processing
module
Management bus
Line clock
Systemclock
Power
module
PEG8
PEG8
PEG8
+3.3 V backup
power supply
Receive Direction
In the receive direction, the line processing module receives four-channel channelized STM-1
services through the interfaces on the front panel of the CQ1 board. The line processing module
demultiplexes STM-1 signals into VC-12 signals, and demaps the VC-12 signals into E1 signals.
Then, the line processing module processes the overhead bytes, pointers, and alarm signals, and
sends the E1 signals to the CES service processing module. Then, the CES service processing
module rearranges the E1 frames, processes the rearranged signals based on the service type,
and performs PWE3 encapsulation and PW scheduling. Finally, the CES service processing
module sends the processed signals to the PEG8 through the interface on the backplane.
Transmit Direction
In the transmit direction, the CES service processing module receives service signals from the
PEG8, identifies the service type, and performs PWE3 decapsulation and queue scheduling.
Then, the CES service processing module sends the processed signals to the line processing
module. The line processing module maps the E1 service signals into VC-12 signals, and
multiplexes the VC-12 signals into STM-1 signals. Then, the line processing module processes
the overhead bytes, pointers, and alarm signals, and sends out the STM-1 signals through the
interface on the front panel of the CQ1.
Line Processing Module

The line processing module performs the following functions.
l
In the receive direction, the line processing module receives four-port channelized STM-1
services, demultiplexes STM-1 signals into VC-12 signals, and demaps the VC-12 signals
into E1 signals. Then, the line processing module processes the overhead bytes, pointers,
and alarm signals.
In the transmit direction, the line processing module receives E1 signals from the PEG8,
maps the E1 service signals into VC-12 signals, and multiplexes the VC-12 signals into
STM-1 signals. Then, the line processing module processes the overhead bytes, pointers,
Issue 03 (2013-02-20)

212

and alarm signals, and sends out the STM-1 signals through the interface on the front panel
of the CQ1.
l
In the case of a service fault, the line processing module implements the LMSP, and
performs service switching.
The line processing module extracts and restores line clock signals.
CES Service processing module

The CES service processing module performs the following functions.
l
In the receive direction, the CES service processing module receives signals from the line
processing module, rearranges the E1 frames, and processes the signals (for example,
compresses timeslots for the CES service). Then, the CES service processing module
performs PWE3 encapsulation and PW scheduling, and sends the processed signals to the
PEG8 through the interface on the backplane.
In the transmit direction, the CES service processing module receives signals from the
PEG8, performs interface conversion, and performs PWE3 decapsulation and service
scheduling. Then, the CES service processing module processes the signals, and sends the
processed signals to the line processing module.
Management Module
The management module manages and controls the modules on the CQ1.
Clock Module
The clock module provides clock information for the modules on the CQ1.
Power Module
the board require.
8.3.5 Front Panel

The front panel of the CQ1 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 8-9 shows the appearance of the front panel of the CQ1.
Issue 03 (2013-02-20)

213

Figure 8-9 Front panel of the CQ1
CQ1
STAT
ACT
SRV
OUT1 IN1OUT2 IN2 OUT3 IN3OUT4 IN4
CQ1
Indicators
l
Interfaces
The front panel of the CQ1 has four optical interfaces. Table 8-31 describes the type and usage
of the optical interfaces of the CQ1.
Issue 03 (2013-02-20)

214

Table 8-31 Interfaces of the CQ1

Optical
Interface
Type of Interface
Usage
IN1-IN4
LC (pluggable)
Channelized STM-1 signal input interface
OUT1OUT4
LC (pluggable)
Channelized STM-1 signal output interface

The CQ1 does not have any jumpers or DIP switches that are used for board settings.
8.3.7 Valid Slots

The CQ1 must be installed in a valid slot on the subrack. Otherwise, the CQ1 fails to work
normally.
The CQ1 can be installed in any slot of slots 19-26 and slots 29-36.
The CQ1 needs to be used with the PEG8. Table 7-48 lists the slots valid for the PEG8 and the
corresponding slots for the CQ1.
8.3.8 Feature Code

The CQ1 does not have any feature code.


Step 4 Required: Install the board. For information on how to install the board, see Replacing Boards
Onsite. Ensure that the board is in proper contact with the bottom of the subrack and that the
front panel of the board is properly locked.
is correct.
----End
Issue 03 (2013-02-20)

215


Step 2 Required: Configure the CES service interface. For details, see Configuring CES Ports.
NOTE
For more information about the parameters of the board, see 27.3 Packet Interface Boards.
Step 3 Required: Configure services. For details, see Operation Tasks for Configuring CES
Services.
Based on the actual requirements, you can configure the following CES services:
l UNI-UNI CES services (For the configuration example, see Configuration Example (UNIUNI CES Services).)
l UNI-NNI CES services (For the configuration example, see Configuration Example (UNINNI CES Services).)
Step 4 Optional: Configure linear MSP. For details, see Creating Packet-Based Linear MSP.
----End

Step 1 Required: Test the CES service channel. For details, see Testing CES Services.
----End

Boards.
the Current Alarms.
----End

You can set the parameters for the CQ1 by using the U2000.
You can set the following parameters for the CQ1 by using the U2000.
l
J0
J1
J2
C2
V5
SDH interface
Issue 03 (2013-02-20)

216

For more parameters and the description of the parameters, see 27.3 Packet Interface
Boards.

Troubleshooting
Table 8-32 lists the faults that occur on the CQ1 frequently and the troubleshooting methods.
Table 8-32 Methods used to troubleshoot the faults that occur on the CQ1 frequently
Fault Symptom
Common Fault
Cause
Service fault
l The service is
interrupted.
See CES Service Troubleshooting.
l Bit errors are

generated in the
service.
Replacing the Board

NOTE
replace the board.
For information on how to replace the CQ1, see Replacing a Packet Interface Board.

8.3.12.1 Alarms of N1CQ1
Issue 03 (2013-02-20)
CES_LOSPKT_EXC
CES_MISORDERPKT_EX
C
CES_STRAYPKT_EXC
CES_MALPKT_EXC
CES_JTRUDR_EXC
CES_JTROVR_EXC
CES_RDI
CESPW_OPPOSITE_RAI
CESPW_OPPOSITE_ACFAULT
R_OOF
R_LOS
R_LOF
B2_SD
R_LOC
B2_EXC
BIP_SD
B3_EXC
B3_SD

217

BIP_EXC
ALM_E1RAI
AU_AIS
BD_STATUS
HP_SLM
J0_MM
AU_LOP
HP_REI
HP_UNEQ
HP_TIM
HP_LOM
HARD_BAD
HP_RDI
IN_PWR_LOW
IN_PWR_ABN
HARD_ERR
LFA
LASER_MOD_ERR
IN_PWR_HIGH
LP_RDI_VC12
LMFA
LASER_SHUT
LP_SLM_VC12
LP_REI_VC12
LOOP_ALM
LSR_BCM_ALM
LP_TIM_VC12
LP_RFI
MS_AIS
LSR_NO_FITED
LP_UNEQ_VC12
OUT_PWR_ABN
MS_RDI
LSR_WILL_DIE
TEM_LA
POWER_ABNORMAL
MS_REI
TU_AIS_VC12
TEMP_OVER
TEM_HA
V5_VCAIS
TU_LOP_VC12
TF
WRG_BD_TYPE
UP_E1_AIS

8.3.13.1 Performance Events of N1CQ1

Table 8-33 SDH
Issue 03 (2013-02-20)
RSBBE
RSES
RSSES
RSUAS
RSCSES
MSES
MSUAS
MSBBE
MSSES
MSFEBBE
MSCSES
MSFESES
MSFEUAS
MSFEES
AUPJCHIGH
AUPJCLOW
MSFECSES
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES

218

HPFESES
HPFEUAS
HPFECSES
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
LPBBE
LPES
LPSES
LPUAS
LPCSES
LPFEBBE
LPFEES
LPFESES
LPFEUAS
CES_LOSPKTS
CES_MISORDERPKTS
CES_STRAYPKTS
CES_MALPKTS
CES_JTRUDR
CES_JTROVR
LPFECSES
Table 8-34 CES

The technical specifications of the CQ1 include the parameters specified for optical interfaces,
Specifications of Optical Interfaces

Table 8-35 provides the specifications of the optical interfaces on the CQ1.
Table 8-35 Specifications of the optical interfaces on the CQ1
Issue 03 (2013-02-20)
Item
Value
Nominal bit rate
155520 kbit/s
Line code
NRZ
Type of optical
interface
S-1.1
L-1.1
L-1.2
Type of Fiber
Single-mode LC
Single-mode LC
Single-mode LC
Transmission
distance (km)
2 to 15
15 to 40
40 to 80
Operating
wavelength range
(nm)
1261 to 1360
1263 to 1360
1480 to 1580

219

Item
Value
Launched optical
power range
(dBm)
-15 to -8
-5 to 0
-5 to 0
Receiver
sensitivity (dBm)
-28
-34
-34
Minimum
overload (dBm)
-8
-10
-10
Minimum
extinction ratio
(dB)
8.2
10
10
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
Laser Safety Class

The mechanical specifications of the N1CQ1 are as follows:
l
Weight: 0.5 kg
Power Consumption
The maximum power consumption of the N1CQ1 at the room temperature (25C) is 10 W.
8.4 MD12
NOTE
The interface on the MD12 is a 120-ohm E1 interface.

The MD12 is available in one functional version, namely, N1.
Issue 03 (2013-02-20)

220

8.4.2 Application
The MD12 directly receives E1 services from the TDM domain, transmits the E1 services on
the packet ring, and directly separates the E1 services from other services on the BSC side. In
this manner, the smooth evolution from the TDM domain to the packet domain is implemented.
Figure 8-10 shows the application of the MD12. The MD12 works with the PEG8 to transmit
E1 services on the packet ring.
Figure 8-10 Networking and application of the MD12
RNC
BSC
GE
STM-1
NMS
CQ1
PEX2
PEX2
PEG8
10GE Ring
Packet ring
PEG8
PEG8
MD12
FE
STM1/STM-4
Ring
E1
FE
E1
TDM ring
Traffic direction
Dual-domain (TDM
domain and packet
GE Ring
GE Ring
PEG8
STM1/STM-4
Ring
NodeB
BTS
NodeB
BTS

The MD12 receives and transmits 32xE1 signals and works with the PEG8 to process E1 CES
and ATM/IMA services.
Table 8-36 provides the functions and features of the MD12.
Issue 03 (2013-02-20)

221

Table 8-36 Functions and features of the MD12

Function
and
Feature
MD12
Basic
functions
Transmits and receives 32xE1 signals, and works with the PEG8 to process E1
CES and ATM/IMA services.
Interface
types
Supports 120-ohm E1 electrical interface. The electrical interface uses the DB44
connector.
Interface
characteri
stics
Loopba
ck types
of the
port
Inloop
Auto
disablin
g of
port
loopbac
k
Supported
Numbe
r of
CES
service
s
32
Emulati
on
mode
CESoPSN, SAToP
Timesl
ot
compre
ssion
functio
n
In the case of the CES services in CESoPSN mode, the MD12

compresses idle timeslots to improve the bandwidth utilization on the
NNI side.
Jitter
compen
sation
bufferi
ng time
of CES
service
s
The jitter compensation buffering time of CES services can be set to

a value in the range of 0.375 ms to 16 ms with a step of 0.125 ms.
CES
Issue 03 (2013-02-20)
Outloop
Non-loopback

222

Function
and
Feature
MD12
Packet
loading
time of
CES
packets
The packet loading time of CES services can be set to a value in the
range of 0.125 ms to 5 ms with a step of 0.125 ms.
NOTE
l The packet loading time needs to be set to the same value for the NEs at
both ends.
l The jitter compensation buffering time needs to be more than at least two
times of the packet loading time.
ATM/
IMA
Issue 03 (2013-02-20)
Numbe
r of
IMA
groups
32
Maxim
um
number
of E1
links in
each
IMA
group
16
Numbe
r of VUNI
ports
512
Numbe
r of VNNI
ports
128
Cell
concate
nation
Type
Concatenation, non-concatenation
Quantit
y
31
ATM
OAM
Type
CC, LB, RDI, AIS
Quantit
y
512
Service
categor
ies
CBR, UBR, UBR+, rt-VBR, nrt-VBR
ATM
QoS
Supported

223

Function
and
Feature
MD12
Clock
function
Restores four CES adaptive clock recover (ACR) clocks.

Clocks that are recovered from services over ports 1 and 9 can be added to the
clock priority list.
NOTE
Clock recovery over ports 1 to 16 is independent of clock recovery over ports 17 to 32. That
is, clocks that are recovered from services over ports 1 to 16 can be transmitted out of ports
1 to 16 and clocks that are recovered from services over ports 17 to 32 can be transmitted
out of ports 17 to 32.
Clock
mode
Line Clock Mode and Null.
Line code
of E1 link
HDB3 code
Frame
format of
E1 link
Unframed format, double-framed format, or E1 CRC-4 multiframe format

(default value)
Maintena
nce
features
l Supports the warm reset and cold reset. The warm reset does not affect
services.
l Supports the query of the board manufacturer information.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the tributary PRBS function.

The MD12 consists of the tributary processing module, service processing module, management
module, clock module, and power supply module.
Figure 8-11 shows the functional block diagram of the MD12.
Issue 03 (2013-02-20)

224

Figure 8-11 Functional block diagram of the MD12

Backplane
32xE1
signals
Tributary
processing
module
Service
processing
module
Service signal
Management bus
3.3. V
.
.
.
.
.
1.2 V
Clock
module
PEG8
Management bus
Management
module
Line clock
Service
signal
Management bus
PEG8
Line clock
System clock
Power
module
PEG8
PEG8
+3.3 V backup
power supply
Receive Direction
The tributary processing module receives E1 signals, and performs the functions of impedance
matching, signal equalization, level conversion, clock recovery, de-jitter, and decoding. After
the tributary processing module processes the E1 signals, the signals are sent to the service
processing module for framing, PWE3 encapsulation and mapping, and PW scheduling. Then,
the signals are sent to the PEG8 through the backplane interface module.
Transmit Direction
The cross-connect unit receives packets from the backplane interface module, and sends the
packets to the service processing module. The service processing module decapsulates the
packets, buffers the data in queues, schedules the queues based on service types, and then
processes and converts the data. The converted data is sent to the tributary processing module.
The tributary processing module performs the functions of coding, dejitter, pulse shaping, and
line drive, and then sends the services to E1 interfaces.
Tributary Processing Module

The tributary processing module consists of 32 independent receive channels and transmit
channels.
l
The receive channels implement the functions of impedance matching, signal equalization,
level conversion, clock recovery, de-jitter, and decoding.
The transmit channels implement the functions of coding, dejitter, pulse shaping, and line
drive.
Service Processing Module

The service processing module performs the following functions:
Issue 03 (2013-02-20)

225

In the receive direction, the service processing module obtains the PW information of each
E1 service, performs PWE3 encapsulation and PW scheduling, and then sends the signals
to the PEG8 through the backplane interface.
In the transmit direction, the service processing module receives the services from the
PEG8, identifies different service types, and performs PWE3 decapsulation and service
scheduling.
Management Module
The management module manages and controls the modules on the MD12.
Clock Module
Provides the clock signal for each module of the MD12.
Power Module
the board require.
8.4.5 Front Panel

The front panel of the MD12 has interfaces and a bar code.

Figure 8-12 shows the appearance of the front panel of the MD12.
Issue 03 (2013-02-20)

226

Figure 8-12 Front panel of the MD12
MD12
MD12
Interfaces
The front panel of the MD12 has four DB44 interfaces. Table 8-37 describes the types and usage
of the interfaces of the MD12.
Table 8-37 Interfaces of the MD12
Issue 03 (2013-02-20)
Interface
Type of Interface
Usage
1-8
DB44
Receives E1 signals from the 1st channel to the 8th

channel.
9-16
DB44
Receives E1 signals from the 9th channel to the 16th

channel.

227

Interface
Type of Interface
Usage
17-24
DB44

channel.
25-32
DB44
Receives E1 signals from the 25th channel to the

32nd channel.
Table 8-38 lists the pins of the DB44 interface.

Table 8-38 Pin description of the DB44 interfaces on the MD12
Front View
30
15
44
Pin
Usage
Pin
Usage
38
R1 to receive the
first channel of
signals
34
R5 to receive the
fifth channel of
signals
R2 to receive the
second channel
of signals
33
R3 to receive the
third channel of
signals
32
R4 to receive the
fourth channel of
signals
31
T1 to transmit
the first channel
of signals
11
T2 to transmit
the second
channel of
signals
10
T3 to transmit
the third channel
of signals
T4 to transmit
the fourth
channel of
signals
23
37
22
36
21
35
31
16
20
15
30
14
29
13
28
12
27
19
18
17
16
26
25
24
R6 to receive the
sixth channel of
signals
R7 to receive the
seventh channel of
signals
R8 to receive the
eighth channel of
signals
T5 to transmit the
fifth channel of
signals
T6 to transmit the
sixth channel of
signals
T7 to transmit the
seventh channel of
signals
T8 to transmit the
eighth channel of
signals

The MD12 does not have any jumpers or DIP switches that are used for board settings.
Issue 03 (2013-02-20)

228

8.4.7 Valid Slots

The MD12 must be installed in a valid slot in the subrack. Otherwise, the MD12 fails to work
normally.
The MD12 can be installed in any slot of slots 19-26 and slots 29-36.
The MD12 needs to be used with the PEG8. Table 7-48 lists the slots valid for the PEG8 and
the corresponding slots for the MD12.
8.4.8 Feature Code

The MD12 does not have the feature code.


is correct.
----End

Step 2 Required: Configure the CES service. For details, see Configuring CES Ports. Configure the
ATM port. For details, see Configuring ATM Interfaces
NOTE
Step 3 Required: Configure services. Based on the actual requirements, you can configure the
following CES services:
Issue 03 (2013-02-20)

229

l UNI-UNI ATM services (For the configuration example, see Configuration Example (UNIUNI ATM Services).)
l UNI-NNI ATM services (For the configuration example, see Configuration Example (UNIsNNI ATM Services).)
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the MD12 by using the U2000.
You can set the PDH interfaces parameters for the MD12 by using the U2000.
For the description of the PDH interfaces parameter, see 27.3 Packet Interface Boards.

Troubleshooting
Table 8-39 lists the faults that occur on the MD12 frequently and the troubleshooting methods.
Table 8-39 Methods used to troubleshoot the faults that occur on the MD12 frequently
Fault Symptom
Common Fault Cause
CES service fault
l The service is interrupted.

l Bit errors are generated in the service.
Issue 03 (2013-02-20)

230

Fault Symptom
Common Fault Cause
ATM/IMA service fault

Replacing the Board

NOTE
replace the board.
For information on how to replace the MD12, see Replacing a Packet Interface Board.

8.4.12.1 Alarms of N1MD12
Issue 03 (2013-02-20)
TEMP_OVER
HARD_BAD
POWER_ABNORMAL
BD_STATUS
ALM_E1RAI
WRG_BD_TYPE
CES_LOSPKT_EXC
CES_MISORDERPKT_EX
C
CES_STRAYPKT_EXC
CES_MALPKT_EXC
CES_JTRUDR_EXC
CES_JTROVR_EXC
CES_RDI
CESPW_OPPOSITE_RAI
T_ALOS
UP_E1_AIS
E1_LOC
LFA
LMFA
HARD_ERR
IMA_GROUP_RE_DOWN
IMA_TXCLK_MISMATCH
ALM_IMA_LIF
ALM_IMA_LODS
ALM_IMA_RFI
ALM_IMA_RE_TX_UNUSABLE
ALM_IMA_RE_RX_UNUSABLE
ATMPW_LOSPKT_EXC
ATMPW_MISORDERPKT
_EXC
ATMPW_UNKNOWNCE
LL_EXC
CES_ACR_LOCK_ABN
VP_AIS
VP_RDI
VC_AIS
VC_RDI
VP_LOC
VC_LOC
OCD
LCD
UHCS
CHCS

231

LOOP_ALM
IMA_GROUP_LE_DOWN

8.4.13.1 Performance Events of N1MD12

Table 8-40 SDH
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
E1_LCV_SDH
E1_LES_SDH
E1_LSES_SDH
CES_LOSPKTS
CES_MISORDERPKTS
CES_STRAYPKTS
CES_MALPKTS
CES_JTRUDR
CES_JTROVR
MPLS_PW_FL
MPLS_PW_FD
PW_RCVPKTS
PW_RCVBYTES
PW_SNDPKTS
PW_SNDBYTES
E1_LLOSS_SDH
Table 8-41 CES
CES_RX_PKTS

MPLS_PW_FLR
MPLS_PW_FDV
Table 8-43 PW
Table 8-44 ATM

ATM_UNI1_INCELLS
Issue 03 (2013-02-20)
ATM_UNI1_OUTCELLS

ATM_UNI2_INCELLS
232

ATM_UNI2_OUTCELLS
ATM_CORRECTED_HCSER
R
ATM_UNCORRECTED_H
CSERR
ATM_RCVCELLS
ATM_RCVIDLECELLS
ATM_SNDCELLS
ATM_IF_INRATE_MAX
ATM_IF_INRATE_MIN
ATM_IF_INRATE_AVG
ATM_IF_OUTRATE_M
AX
ATM_IF_OUTRATE_MIN
ATM_IF_OUTRATE_AVG
ATM_CELL_AVAILABILITY
ATM_UNI1_INRATE_MAX
ATM_UNI1_INRATE_MI
N
ATM_UNI1_INRATE_A
VG
ATM_UNI1_OUTRATE_MA
X
ATM_UNI1_OUTRATE_
MIN
ATM_UNI1_OUTRATE_
AVG
ATM_UNI2_INRATE_MAX
ATM_UNI2_INRATE_MI
N
ATM_UNI2_INRATE_A
VG
ATM_UNI2_OUTRATE_MA
X
ATM_UNI2_OUTRATE_
MIN
ATM_UNI2_OUTRATE_
AVG
PORT_RX_BW_UTILIZATION
PORT_TX_BW_UTILIZATION
Table 8-45 ATM PWE3

ATMPW_SNDCELLS
ATMPW_RCVCELLS
ATMPW_UNKNOWNCELLS

The technical specifications of the MD12 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
Specifications of Electrical Interfaces

Table 8-46 Specifications of the electrical interfaces of the MD12
Item
Value
Nominal bit rate
2048 kbit/s
DB44
Code pattern
HDB3 code
Signal bit rate at the output port
Compliant with ITU-T G.703
Permitted frequency deviation at the

input port
Issue 03 (2013-02-20)

233

Item
Value
Allowed attenuation at the input port

Input jitter tolerance
The mechanical specifications of the MD12 are as follows:
l
Weight: 0.5 kg
Power Consumption
The maximum power consumption of the MD12 at the room temperature (25C) is 12 W.
8.5 MD75
NOTE
The interface on the MD12 is a 120-ohm E1 interface.

The MD75 is available in one functional version, namely, N1.
8.5.2 Application
The MD75 directly receives E1 services from the TDM domain, transmits the E1 services on
the packet ring, and directly separates the E1 services from other services on the BSC side. In
this manner, the smooth evolution from the TDM domain to the packet domain is implemented.
Figure 8-13 shows the application of the MD75. The MD75 works with the PEG8 to transmit
E1 services on the packet ring.
Issue 03 (2013-02-20)

234

Figure 8-13 Networking and application of the MD75

RNC
BSC
GE
STM-1
NMS
CQ1
PEX2
PEX2
PEG8
10GE Ring
Packet ring
PEG8
PEG8
MD75
STM1/STM-4
Ring
FE
E1
E1
TDM ring
Traffic direction
Dual-domain (TDM
domain and packet
GE Ring
GE Ring
PEG8
STM1/STM-4
Ring
FE
NodeB
BTS
BTS
NodeB

The MD75 receives and transmits 32xE1 signals and works with the PEG8 to process E1 CES
and ATM/IMA services.
Table 8-47 provides the functions and features of the MD75.
Table 8-47 Functions and features of the MD75
Issue 03 (2013-02-20)
Functio
n and
Feature
MD75
Basic
functions
Transmits and receives 32xE1 signals, and works with the PEG8 to process E1
CES and ATM/IMA services.
Interface
types
Supports 75-ohm E1 electrical interface. The electrical interface uses the DB44
connector.

235

Functio
n and
Feature
MD75
Interface
character
istics
Loo
pbac
k
type
s of
the
port
Inloop
Auto
disa
blin
g of
port
loop
back
Supported
Num
ber
of
CES
servi
ces
32
Emu
latio
n
mod
e
CESoPSN, SAToP
Tim
eslot
com
pres
sion
func
tion
In the case of the CES services in CESoPSN mode, the MD75 compresses
idle timeslots to improve the bandwidth utilization on the NNI side.
Jitter
com
pens
ation
buff
erin
g
time
of
CES
servi
ces
The jitter compensation buffering time of CES services can be set to a

value in the range of 0.375 ms to 16 ms with a step of 0.125 ms.
CES
Issue 03 (2013-02-20)
Outloop
Non-loopback

236

Functio
n and
Feature
ATM/
IMA
Issue 03 (2013-02-20)
MD75
Pack
et
loadi
ng
time
of
CES
pack
ets
The packet loading time of CES services can be set to a value in the range
of 0.125 ms to 5 ms with a step of 0.125 ms.
Num
ber
of
IMA
grou
ps
32
Max
imu
m
num
ber
of
E1
links
in
each
IMA
grou
p
16
Num
ber
of
VUNI
ports
512
Num
ber
of
VNNI
ports
128
Cell
conc
aten
ation
Type
Concatenation, non-concatenation
Quanti
ty
31
NOTE
l The packet loading time needs to be set to the same value for the NEs at both
ends.
l The jitter compensation buffering time needs to be more than at least two times
of the packet loading time.

237

Functio
n and
Feature
Clock
function
MD75
AT
M
OA
M
Type
CC, LB, RDI, AIS
Quanti
ty
512
Serv
ice
cate
gori
es
CBR, UBR, UBR+, rt-VBR, nrt-VBR
AT
M
QoS
Supported
Recovers four CES ACR clocks.

Clocks that are recovered from services over ports 1 and 9 can be added to the
clock priority list.
NOTE
Clock recovery over ports 1 to 16 is independent of clock recovery over ports 17 to 32. That
is, clocks that are recovered from services over ports 1 to 16 can be transmitted out of ports
1 to 16 and clocks that are recovered from services over ports 17 to 32 can be transmitted
out of ports 17 to 32.
Clock
mode
Line Clock Mode and Null.
Line code
of E1 link
HDB3 code
Frame
format of
E1 link
Unframed format, double-framed format, or E1 CRC-4 multiframe format

(default value)
Loopbac
k mode
Inloop, outloop, or non-loopback (default value)
Maintena
nce
features
services.
l Supports the query of the board manufacturer information.
l Supports the tributary PRBS function.

The MD75 consists of the tributary processing module, service processing module, management
module, clock module, and power supply module.
Issue 03 (2013-02-20)

238

Figure 8-14 shows the functional block diagram of the MD75.

Figure 8-14 Functional block diagram of the MD75
Backplane
32xE1
signals
Tributary
processing
module
Service
processing
module
Service signal
Management bus
3.3. V
.
.
.
.
.
1.2 V
Clock
module
PEG8
Management bus
Management
module
Line clock
Service
signal
Management bus
PEG8
Line clock
System clock
Power
module
PEG8
PEG8
+3.3 V backup
power supply
Receive Direction
The tributary processing module receives E1 signals, and performs the functions of impedance
matching, signal equalization, level conversion, clock recovery, de-jitter, and decoding. After
the tributary processing module processes the E1 signals, the signals are sent to the service
processing module for framing, PWE3 encapsulation and mapping, and PW scheduling. Then,
the signals are sent to the PEG8 through the backplane interface module.
Transmit Direction
The cross-connect unit receives packets from the backplane interface module, and sends the
packets to the service processing module. The service processing module decapsulates the
packets, buffers the data in queues, schedules the queues based on service types, and then
processes and converts the data. The converted data is sent to the tributary processing module.
The tributary processing module performs the functions of coding, dejitter, pulse shaping, and
line drive, and then sends the services to E1 interfaces.
Tributary Processing Module

The tributary processing module consists of 32 independent receive channels and transmit
channels.
l
The receive channels implement the functions of impedance matching, signal equalization,
level conversion, clock recovery, de-jitter, and decoding.
The transmit channels implement the functions of coding, dejitter, pulse shaping, and line
drive.
Issue 03 (2013-02-20)

239

Service Processing Module

The service processing module performs the following functions:
l
In the receive direction, the service processing module obtains the PW information of each
E1 service, performs PWE3 encapsulation and PW scheduling, and then sends the signals
to the PEG8 through the backplane interface.
In the transmit direction, the service processing module receives the services from the
PEG8, identifies different service types, and performs PWE3 decapsulation and service
scheduling.
Management Module
The management module manages and controls the modules on the MD75.
Clock Module
Provides the clock signal for each module of the MD75.
Power Module
the board require.
8.5.5 Front Panel

The front panel of the MD75 has interfaces and a bar code.

Figure 8-15 shows the appearance of the front panel of the MD75.
Issue 03 (2013-02-20)

240

Figure 8-15 Front panel of the MD75
MD75
MD75
Interfaces
The front panel of the MD75 has four DB44 interfaces. Table 8-48 describes the types and usage
of the interfaces of the MD75.
Table 8-48 Interfaces of the MD75
Issue 03 (2013-02-20)
Interface
Type of Interface
Usage
1-8
DB44
Receives E1 signals from the 1st channel to the 8th

channel.
9-16
DB44

channel.

241

Interface
Type of Interface
Usage
17-24
DB44

channel.
25-32
DB44
Receives E1 signals from the 25th channel to the

32nd channel.
Table 8-49 lists the pins of the DB44 interface.

Table 8-49 Pin description of the DB44 interfaces on the MD75
Front View
30
15
44
Pin
Usage
Pin
Usage
38
R1 to receive the
first channel of
signals
34
R5 to receive the
fifth channel of
signals
R2 to receive the
second channel
of signals
33
R3 to receive the
third channel of
signals
32
R4 to receive the
fourth channel of
signals
31
T1 to transmit
the first channel
of signals
11
T2 to transmit
the second
channel of
signals
10
T3 to transmit
the third channel
of signals
T4 to transmit
the fourth
channel of
signals
23
37
22
36
21
35
31
16
20
15
30
14
29
13
28
12
27
19
18
17
16
26
25
24
R6 to receive the
sixth channel of
signals
R7 to receive the
seventh channel of
signals
R8 to receive the
eighth channel of
signals
T5 to transmit the
fifth channel of
signals
T6 to transmit the
sixth channel of
signals
T7 to transmit the
seventh channel of
signals
T8 to transmit the
eighth channel of
signals

The MD75 does not have any jumpers or DIP switches that are used for board settings.
Issue 03 (2013-02-20)

242

8.5.7 Valid Slots

The MD75 must be installed in a valid slot in the subrack. Otherwise, the MD75 fails to work
normally.
The MD75 can be installed in any slot of slots 19-26 and slots 29-36.
The MD75 needs to be used with the PEG8. Table 7-48 lists the slots valid for the PEG8 and
the corresponding slots for the MD75.
8.5.8 Feature Code

The MD75 does not have any feature code.


is correct.
----End

Step 2 Required: Configure the CES service. For details, see Configuring CES Ports. Configure the
ATM port. For details, see Configuring ATM Interfaces
NOTE
Step 3 Required: Configure services. Based on the actual requirements, you can configure the
following CES services:
Issue 03 (2013-02-20)

243

l UNI-UNI ATM services (For the configuration example, see Configuration Example (UNIUNI ATM Services).)
l UNI-NNI ATM services (For the configuration example, see Configuration Example (UNIsNNI ATM Services).)
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the MD75 by using the U2000.
You can set the PDH interfaces parameters for the MD75 by using the U2000.
For the description of the PDH interfaces parameter, see 27.3 Packet Interface Boards.

Troubleshooting
Table 8-50 lists the faults that occur on the MD75 frequently and the troubleshooting methods.
Table 8-50 Methods used to troubleshoot the faults that occur on the MD75 frequently
Fault Symptom
Common Fault Cause
Service fault

Issue 03 (2013-02-20)

244

Fault Symptom
Common Fault Cause
ATM/IMA service fault

Replacing the Board

NOTE
replace the board.
For information on how to replace the MD75, see Replacing a Packet Interface Board.

8.5.12.1 Alarms of N1MD75
Issue 03 (2013-02-20)
TEMP_OVER
HARD_BAD
POWER_ABNORMAL
BD_STATUS
ALM_E1RAI
WRG_BD_TYPE
CES_LOSPKT_EXC
CES_MISORDERPKT_EX
C
CES_STRAYPKT_EXC
CES_MALPKT_EXC
CES_JTRUDR_EXC
CES_JTROVR_EXC
CES_RDI
CESPW_OPPOSITE_RAI
T_ALOS
UP_E1_AIS
E1_LOC
LFA
LMFA
HARD_ERR
IMA_GROUP_RE_DOWN
IMA_TXCLK_MISMATCH
ALM_IMA_LIF
ALM_IMA_LODS
ALM_IMA_RFI
ATMPW_LOSPKT_EXC
ATMPW_MISORDERPKT
_EXC
ATMPW_UNKNOWNCE
LL_EXC
CES_ACR_LOCK_ABN
VP_AIS
VP_RDI
VC_AIS
VC_RDI
VP_LOC
VC_LOC
OCD
LCD
UHCS
CHCS

245

LOOP_ALM
IMA_GROUP_LE_DOWN

8.5.13.1 Performance Events of N1MD75

Table 8-51 SDH
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
E1_LCV_SDH
E1_LES_SDH
E1_LSES_SDH
CES_LOSPKTS
CES_MISORDERPKTS
CES_STRAYPKTS
CES_MALPKTS
CES_JTRUDR
CES_JTROVR
MPLS_PW_FL
MPLS_PW_FD
PW_RCVPKTS
PW_RCVBYTES
PW_SNDPKTS
PW_SNDBYTES
E1_LLOSS_SDH
Table 8-52 CES
CES_RX_PKTS

MPLS_PW_FLR
MPLS_PW_FDV
Table 8-54 PW
Table 8-55 ATM

ATM_UNI1_INCELLS
Issue 03 (2013-02-20)
ATM_UNI1_OUTCELLS

ATM_UNI2_INCELLS
246

ATM_UNI2_OUTCELLS
ATM_CORRECTED_HCSER
R
ATM_UNCORRECTED_H
CSERR
ATM_RCVCELLS
ATM_RCVIDLECELLS
ATM_SNDCELLS
ATM_IF_INRATE_MAX
ATM_IF_INRATE_MIN
ATM_IF_INRATE_AVG
ATM_IF_OUTRATE_M
AX
ATM_IF_OUTRATE_MIN
ATM_IF_OUTRATE_AVG
ATM_CELL_AVAILABILITY
ATM_UNI1_INRATE_MAX
ATM_UNI1_INRATE_MI
N
ATM_UNI1_INRATE_A
VG
ATM_UNI1_OUTRATE_MA
X
ATM_UNI1_OUTRATE_
MIN
ATM_UNI1_OUTRATE_
AVG
ATM_UNI2_INRATE_MAX
ATM_UNI2_INRATE_MI
N
ATM_UNI2_INRATE_A
VG
ATM_UNI2_OUTRATE_MA
X
ATM_UNI2_OUTRATE_
MIN
ATM_UNI2_OUTRATE_
AVG
PORT_RX_BW_UTILIZATION
PORT_TX_BW_UTILIZATION
Table 8-56 ATM PWE3

ATMPW_SNDCELLS
ATMPW_RCVCELLS
ATMPW_UNKNOWNCELLS

The technical specifications of the MD12 include the parameters specified for interfaces,
Specifications of Electrical Interfaces

Table 8-57 Specifications of the electrical interfaces of the MD75
Item
Value
Nominal bit rate
2048 kbit/s
DB44
Code pattern
HDB3 code
Signal bit rate at the output port
Compliant with ITU-T G.703
Permitted frequency deviation

at the input port
Issue 03 (2013-02-20)

247

Item
Value
Allowed attenuation at the input

port
The mechanical specifications of the MD75 are as follows:
l
Weight: 0.5 kg
Power Consumption
The maximum power consumption of the MD75 at room temperature (25C) is 12 W.
Issue 03 (2013-02-20)

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9 EoD Boards
EoD Boards
About This Chapter

The OptiX OSN equipment supports the EoD (Ethernet over Dual Domains) board EDQ41,
which bridges Ethernet services between the TDM domain and packet domain.
9.1 EDQ41
This topic describes the version, application, functions, working principle, front panel, valid
slots, and technical specifications of the EDQ41 (4-port 622/155 Mbit/s SDH optical interface
Ethernet double domain multiple function processing board).
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9 EoD Boards
9.1 EDQ41
This topic describes the version, application, functions, working principle, front panel, valid
slots, and technical specifications of the EDQ41 (4-port 622/155 Mbit/s SDH optical interface
Ethernet double domain multiple function processing board).

The EDQ41 is available in one functional version, namely, N1.
9.1.2 Application
The EDQ41 is mainly used for interoperation between the SDH network and the packet network.
The board converges the TDM signals and Ethernet packets from the SDH access network and
deconverges the TDM signals to the SDH ring and the Ethernet packets to the packet ring. In
this manner, the board achieves the interoperation between the TDM domain and the packet
domain, facilitating the smooth evolution of the network.
Figure 9-1 shows the typical networking and application of the EDQ41.
Figure 9-1 Networking and application of the EDQ41
RNC
BSC
STM-16/STM-64 ring
10GE ring
E1
GE ring
FE
FE
STM-1/STM-4 ring
Issue 03 (2013-02-20)
Networking in the
TDM domain
Networking in the
packet domain
TDM traffic direction
Packet traffic direction

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9 EoD Boards
The EDQ41 is applicable in four typical networking scenarios. Figure 9-2 shows the service
signal flow in each application scenario.
l
Application 1: The EDQ41 receives EoS services from other NEs and then converts the
EoS services to packet services, therefore implementing transition from the STM-1/STM-4
SDH network to the GE/10GE packet network.
Application 2: The EDQ41 receives EoS services from line boards on the same NE and
then converts the EoS services to packet services, therefore implementing transition from
the SDH network to the GE/10GE packet network.
Application 3: The EDQ41 board receives SDH services (including SDH services and EoS
services) from SDH line board, processes and then distributes the services to GE/10GE
packet networks and STM-1/STM-4 SDH networks.
Application 4: The EDQ41 board receives SDH services (including pure SDH services and
EoS services) from SDH line boards, processes and then sends the services directly to the
SDH network. In this case, the EDQ41 board functions like an SDH line board.
NOTE
The EDQ41 supports the maximum processing capacity of 2.5 Gbit/s. Therefore, only 2.5 Gbit/s services
of the services received from STM-N (1N64) line boards can be processed and sent to the packet network.
Figure 9-2 Service signal flow on the EDQ41

Application 2:
Application 1:
STM-1/STM-4
ring
EDQ41
borad
Packet
core
GE/10GE
ring
Packet
board
EDQ41
borad
TDM
core
Application 3:
STM-1/STM-4
ring
Packet
core
Packet
board
TDM
core
SDH
board
GE/10GE
ring
STM-N
Application 4:
EDQ41
borad
Packet
core
Packet
board
TDM
core
SDH
board
GE/10GE
ring
STM-1/STM-4
ring
STM-N
EDQ41
borad
Packet
core
Packet
board
TDM
core
SDH
board
STM-N

The EDQ41 processes 4x155 Mbit/s or 4x622 Mbit/s SDH services and 2.5 Gbit/s EoS services
at the same time.
As a dual-domain board, the EDQ41 is applicable in the case of SDH services, packet services,
and EoS services. Table 9-1, Table 9-2, and Table 9-3 provide the functions and features of the
EDQ41 in each service application scenario.
Table 9-1 Functions and features of the EDQ41
Issue 03 (2013-02-20)
Function and
Feature
Description
Basic functions
Transmits and receives 4xSTM-1/STM-4 optical signals.

251

Function and
Feature
Description
interface
l The STM-1 or STM-4 optical module can be used.
9 EoD Boards
l When the STM-1 optical module is used, the standard S-1.1, L-1.1,
and L-1.2 optical interfaces are supported. The optical interfaces
comply with ITU-T G.957.
l When the STM-4 optical module is used, the standard S-4.1, L-4.1,
L-4.2, and Ve-4.2 optical interfaces are supported. The optical
interfaces of the S-4.1, L-4.1, and L-4.2 types comply with ITUT G.957. The optical interface of the Ve-4.2 type complies with
the standards defined by Huawei.
Specifications of
optical modules
l Supports the detection and query of the information about optical

modules.
l Supports the usage and detection of SFP pluggable optical
modules, facilitating the maintenance of optical modules.
l Provides the ALS function. The optical interface supports the
function of setting the on/off state of a laser.
Service processing
l Supports VC-12/VC-3/VC-4 services when the STM-1 optical

module is used.
l Supports VC-12/VC-3/VC-4/VC-4-4c services when the STM-4
optical module is used.
Overhead processing
l Processes the section overheads of STM-4/STM-1 signals.

l Processes path overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports the ECC communication.
Loopback function
l Supports inloops and outloops at optical interfaces.

l Supports inloops and outloops at the VC-4 level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the

management and maintenance of the equipment.
Protection scheme
l Supports Two-fiber ring MSP.

l Supports Four-fiber ring MSP.
l Supports Linear MSP.
l Supports SNCP.
l Supports SNCMP.
l Supports SNCTP.
l Supports fiber-shared virtual trail protection.
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9 EoD Boards
Function and
Feature
Description
Maintenance
features
l Supports the warm reset and cold reset. A warm reset does not
affect services.
l Supports the PRBS function in the line direction and cross-connect
direction.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.
Table 9-2 Packet features of the EDQ41
Issue 03 (2013-02-20)
Function
and
Feature
Description
Basic
functions
Bridges a maximum of 2.5 Gbit/s EoS services to the packet domain.
Format of
service
frames
l Supports the encapsulation in IEEE 802.3 format, Ethernet II format, or IEEE

802.1q/p format.
Maximum
uplink
bandwidth
2.5 Gbit/s
MTU
MTU for ports
Supports the query of the MTUs

specified for ports but does not support
MTU setting. The default MTU
specified for ports is 9000 bytes.
MTU for services
Supports the setting of the packet

length, which ranges from 64 bytes to
9000 bytes.
l Supports the Jumbo frame with a length not more than 9000 bytes.
Type of
Ethernet
services
l Supports point-to-point E-Line services.
HQoS
Supports the UNI port policy.
LAG
Supports VCG-side manual load non-sharing LAG protection.
Protection
scheme
l Supports LAG.
Maintenan
ce features
l Supports the performance statistics and report of VCTRUNKs.
l Supports multipoint-to-multipoint E-LAN services.
l Supports MC-LAG.
l Supports the query and report of alarms.

253

Function
and
Feature
Description
ETH
OAM
Not supported.
MSTP
Not supported.
IGMP
Snooping
Not supported.
Number of
supported
E-Line
services
Number of
supported
E-LAN
services
1k
9 EoD Boards
NOTE
The board does not support creation of maintenance points but supports transparent
transmission of ETH OAM packets.
Table 9-3 EoS data features of the EDQ41
Issue 03 (2013-02-20)
Function and
Feature
EDQ41
Basic function
Supports transparent transmission of Ethernet services.
Encapsulation
format
Supports the GFP-F protocol.
EPL
Supports transparent transmission of PORT-based EPL services.

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9 EoD Boards
Function and
Feature
EDQ41
Number of
VCTRUNKs
Binds a maximum of 63 VCTRUNKs, equivalent to 504 VC-12s, 48

VC-3s, or 16 VC-4s.
Configuration features:
l The first eight VC-4s (including VC-3s and VC-12s in the VC-4s)
and the last eight VC-4s (including VC-3s and VC-12s in the
VC-4s) cannot be bound to the same VCTRUNK.
l Only 5th to 8th and the 13th to 16th VC-4s can bind VC-12 paths.
In addition, VC-12s in the 5th to 8th VC-4s cannot be bound to the
same VCTRUNK as the VC-12s in the 13th to 16th VC-4s.
l VC-3 and VC-4 signals can be bound to any of the 1st to 16th
VC-4s.
l VCTRUNK1 to VCTRUNK63 can be bound to any of the 1st to
16th VC-4s.
l VCTRUNK1 to VCTRUNK8 each can be bound to a maximum
of eight VC-4s. VCTRUNK9 to VCTRUNK63 each can be bound
to a maximum of one VC-4, three VC-3s, or 63 VC-12s.
l A VC-4 cannot bind VC-3 and VC-12 paths at the same time.
LCAS
Dynamically increases or decreases the bandwidth and protects the

bandwidth in compliance with ITU-T G.7042.
Test frames
Supports the transmitting and receiving of GFP test frames or Ethernet

test frames.

The EDQ41 consists of network processing module, encapsulation/mapping and SDH overhead
processing module, clock module, logic control module, O/E converting module, SDH overhead
processing module, and power module.
Figure 9-3 shows the functional block diagram of the EDQ41.
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9 EoD Boards
Figure 9-3 Functional block diagram of the EDQ41

Backplane
Packet
switching unit
Encapsulation/
mapping and
SDH overhead
processing
module
Network
processing
module
Communication unit
Clock
module
Logic control
module
Reference clock and
frame header unit
O/E
converting
module
4xSTM1/STM-4
+3.3 V
SCC
SCC
SDH crossconnect unit

(pure SDH
services)
SDH
overhead
processing
module
Power
module
SDH crossconnect unit

(EoS services)
Power
module
Fuse
-48 V/-60 V
-48 V/-60 V
Services in the SDH Domain

l
In the transmit direction: The O/E converting module converts the received STM-1/STM-4
optical signals into electrical signals and sends the electrical signals to the SDH overhead
processing module. Then, the SDH overhead processing module extracts and processes the
overheads, converts the signals into a format that applies to the backplane bus, and then
sends the signals to the SDH cross-connect unit.
In the receive direction: The SDH overhead processing module inserts overhead bytes into
the electrical signals from the SDH cross-connect unit, and sends the electrical signals to
the E/O converting module. The E/O converting module converts the STM-1/STM-4
electrical signals into optical signals, and then sends the optical signal to fibers for
transmission.
Services Transmitted from the SDH Domain to the Packet Domain

The mapping module demaps the signals from the SDH cross-connect module and compensates
the delay of virtual concatenation. The mapping module decapsulates the packets through
alignment and sends the data to the network processing module. The network processing module
Issue 03 (2013-02-20)

256

9 EoD Boards
processes the data according to service types and configuration requirements, and then sends
Ethernet services to the packet switching unit.
Services Transmitted from the Packet Domain to the SDH Domain

The network processing module processes the Ethernet services from the packet switching unit,
and then sends the services to the mapping module. The mapping module encapsulates the
Ethernet services in LAPS or GFP format and concatenates the services. Then, the mapping unit
converts the Ethernet services into STM-16 signals and sends the signals to the SDH crossconnect unit.

The network processing module performs the functions at the MAC layer, including code
conversion, Ethernet packet framing, CRC check, and Ethernet performance statistics. In
addition, the network processing module classifies the services according to service types and
configuration requirements. Then, the module encapsulates or decapsulates frames. The module
supports the Ethernet/VLAN encapsulation formats.
The module supports the following functions:
l
Traffic detection and traffic classification
Unicast, multicast, and broadcast of flows
Priorities of data
Weighted fair queuing (WFQ) scheduling
Three service classes
Encapsulation/Mapping and SDH Overhead Processing Module

The encapsulation/mapping and SDH overhead processing module performs encapsulation/
mapping functions and processes SDH overheads.
l
In the upstream direction, the mapping module encapsulates Ethernet signals in LAPS,
GFP-F, or HDLC format and then performs concatenation. The module supports LCAS.
Then, the mapping module converts Ethernet signals into SDH signals.
In the downstream direction, the mapping module demaps SDH signals and compensates
the delay of virtual concatenation. The mapping module decapsulates packets accordingly
through the alignment operation. The decapsulated data is finally transmitted to the network
processing module.

The logic control module is connected to external circuits through the bus. The logic control
module performs the following functions:
l
Manages and configures the other modules on the local board.
Implements inter-board communication through the internal Ethernet interface.
O/E Converting Module

l
Issue 03 (2013-02-20)
In the receive direction, the O/E converting unit converts the received optical signals into
electrical signals.
257

9 EoD Boards
In the transmit direction, the O/E converting unit converts the received electrical signals
into SDH optical signals and transmits the optical signals to optical fibers.
This module also detects the R_LOS alarm and provides the ALS function.
SDH Overhead Processing Module

The SDH overhead processing module includes the RST, MST, MSA, and HPT sub-modules.
This module provides the inloop and outloop functions.
l
RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first row of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first row of the RSOH.
MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte. In
addition, the sub-module generates the B2_SD or B2_EXC alarm after checking the B2
byte and sends the MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
MSA sub-module
In the receive direction, the MSA sub-module de-interleaves AUGs, divides an AUG
into N AU-4s, detects the AU_LOP and AU_AIS alarms, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the AU-PTR to a VC-4 to generate
an AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT submodule sends the HP_REI alarm to the opposite end after detecting byte B3. In addition,
the sub-module generates the HP_TIM and HP_SLM alarms, and sends the HP_RDI
alarm to the opposite end after detecting bytes J1 and C2 (the sub-module also generates
the HP_UNEQ alarm if it detects the VC-4 path unequipped).
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT submodule writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip.
Power Module
the board require.
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9 EoD Boards
9.1.5 Front Panel

The front panel of the EDQ41 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 9-4 shows the front panel of the EDQ41.
Figure 9-4 Front panel of the EDQ41
EDQ41
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
EDQ41
Indicators
l
For the meanings of the indicators, see 24.2 Alarm Indicators on the Boards.
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9 EoD Boards
Interfaces
The front panel of the EDQ41 has four optical interfaces. Table 9-4 lists the types and usage of
the optical interfaces of the EDQ41.
Table 9-4 Interfaces of the EDQ41
Interface
Type of Interface
Usage
IN1-IN4
LC (pluggable)
Receives the STM-1/STM-4 optical signals.
OUT1OUT4
LC (pluggable)
Transmits the STM-1/STM-4 optical signals.

The EDQ41 does not have any jumpers or DIP switches for board settings.
9.1.7 Valid Slots

The EDQ41 must be installed in a valid slot in the subrack. Otherwise, the EDQ41 fails to work
normally.
EDQ41 can be housed in any of slots 4-8 and slots 11-14. The bandwidth of SDH services in all
slots is 2.5 Gbit/s, and the bandwidth of packet services in all slots is 2.5 Gbit/s.
NOTE
The EDQ41 cannot work with a cross-connect board whose logical board is configured as N1PSXCS.
9.1.8 Feature Code

The number code that follows the board name in the bar code is the feature code of the EDQ41.
The feature code of the EDQ41 indicates the type of optical interface.
Table 9-5 provides the relationship between the feature code of the EDQ41 and types of optical
interfaces.
Table 9-5 Relationship between the feature code of the EDQ41 and types of optical interfaces
Issue 03 (2013-02-20)
Board
Feature Code
Type of Optical Interface
SSN1EDQ4103
03
S-1.1
SSN1EDQ4104
04
L-1.1
SSN1EDQ4105
05
L-1.2
SSN1EDQ4108
08
S-4.1
SSN1EDQ4109
09
L-4.1
SSN1EDQ4110
10
L-4.2

260

9 EoD Boards
Board
Feature Code
SSN1EDQ4111
11
Ve-4.2
SSN1EDQ4112
12
S-1.1x2/S-4.1x2a
a: Port 1 and port 2 operate at 622 Mbit/s, port 3 and port 4 operate at 155 Mbit/s.


is correct.
----End

Step 2 Required: Add the ports. For details, see Querying and Configuring Ports on Boards.
Step 3 Required: Set the SDH interface.
l J0 byte: Generally, use the default value. The default value of the J0 byte to be sent is HuaWei
SBS and the default value of the J0 byte to be received is Disabled.
l J1 byte: The setting of the J1 byte on the interconnected equipment must be consistent.
Generally, use the default value. The default value of the J1 byte to be sent is HuaWei
SBS and the default value of the J1 byte to be received is Disabled.
l C2 byte: The setting of the C2 byte on the interconnected equipment must be consistent. Set
the C2 byte according to the actual service type. Generally, use the default value, which is
TUG structure.
l Laser status: Set this parameter to Open when you configure and commission the board.
For details, see 28.7 Checking Board Parameters.
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9 EoD Boards
NOTE
For more information about the parameters of the board, see 27.5 SDH Processing Boards.
Step 4 Optional: Create the protection subnet. For details, see Configuring the Protection Subnet.
Step 5 Required: Configure services. For details, see Configuring Cross-Domain Services.
Step 6 Optional: Configure the manual LAG. For details, see Configuring an Ethernet LAG.
Step 7 Optional: Configure test frames. For details, see Configuring Test Frames.
----End

Step 1 Required: Test the specifications of the optical interface. For details, see Testing Specifications
of Optical Interfaces.
Step 2 Required: Test the network protection switching. For details, see Testing SDH Network
Protection Switching.
Step 3 Required: Test the point-to-point BER. For details, see Testing the Point-to-Point BER.
----End

Step 1 Required: Check the dual-domain services. For details, see Testing Cross-domain Services.
Boards.
the Current Alarms.
----End

The EDQ41 supports the packet switching function and multiple Ethernet features, such as
HQoS, LAG, and LCAS. Configure the functions according to actual requirements.
You can configure the following Ethernet functions for the EDQ41 by using the U2000:
l
HQoS
LAG
MC-LAG
LCAS
Test Frame
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9 EoD Boards

You can set the parameters for the EDQ41 by using the U2000.
You can set the following parameters for the EDQ41 by using the U2000:
SDH Parameters
l
J0
J1
J2
C2
For the description of parameters, see 27.5 SDH Processing Boards.
Packet Data Parameters

l
VCTRUNK interfaces
Processing Boards.
EoS Parameters
l
Working mode
Enabling LCAS
Maximum frame length
Mapping protocol
For more parameters and the description of the parameters, see 27.4.2 Ethernet Parameters.

Troubleshooting
Table 9-6 lists the faults that occur on the EDQ41 frequently and the troubleshooting methods.
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9 EoD Boards
Table 9-6 Methods used to troubleshoot the faults that occur on the EDQ41 frequently
Fault Symptom
Common Fault
Cause
SDH service
interruption
l The optical fiber

or connector
becomes
abnormal.
See Service Interruption on a Board or a Port.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The services on a
single Ethernet
port are
interrupted.
EoS service
interruption
See Interruption of an Ethernet Service.
l The services on
all the Ethernet
ports are
interrupted.
Transient EoS
service interruption
l The services on a
single Ethernet
port are
transiently
interrupted.
See Troubleshooting Transient Service

Interruptions.
l The protocol
becomes
abnormal.
Packet service fault
The packet Ethernet

services are faulty.

Interruptions.
Bit error
l The optical power

becomes
abnormal.
See Troubleshooting Bit Errors.
l The equipment
becomes faulty.
Pointer justification
l The clock
configuration is
incorrect.
See Troubleshooting Pointer Justification.
l The precision of
the external clock
source is very
low.
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9 EoD Boards
Fault Symptom
Common Fault
Cause
failure
l The MSP
switching fails.
See Troubleshooting Protection Switching

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
l The MC-LAG
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.
See Troubleshooting the NEs Being

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
interconnection fault
An SDH overhead
occurs.
See Troubleshooting Device Interconnection

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EDQ41, see Replacing an EoD board.

9.1.13.1 Alarms of N1EDQ41
Issue 03 (2013-02-20)
ALM_ALS
ALM_GFP_dCSF
ALM_GFP_dLFD
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD

265

Issue 03 (2013-02-20)
9 EoD Boards
B3_EXC
B3_EXC_VC3
B3_EXC_VC4
B3_SD
B3_SD_VC3
B3_SD_VC4
BD_STATUS
BIP_EXC
BIP_SD
BUS_ERR
C2_PDI
C2_VCAIS
COMMUN_FAIL
DCN_FAIL
FCS_ERR
FSELECT_STG
HARD_BAD
HARD_ERR
HP_LOM
HP_REI
HP_SLM
HP_RDI
HP_UNEQ
IN_PWR_ABN
HP_TIM
IN_PWR_LOW
J0_MM
IN_PWR_HIGH
LAG_MEMBER_DOWN
LASER_MOD_ERR
LAG_DOWN
LCAS_FOPR
LCAS_FOPT
LASER_SHUT
LCAS_PLCT
LCAS_TLCR
LCAS_PLCR
LOOP_ALM
LP_RDI_VC12
LCAS_TLCT
LP_REI_VC12
LP_REI_VC3
LP_RDI_VC3
LP_SLM_VC3
LP_TIM_VC12
LP_SLM_VC12
LP_UNEQ_VC12
LP_UNEQ_VC3
LP_TIM_VC3
LSR_COOL_ALM
LSR_NO_FITED
LSR_BCM_ALM
MCLAG_CFG_MISMATCH
MCSP_PATH_LOCV
LSR_WILL_DIE
MS_AIS
MS_RDI
MOD_TYPE_MISMATCH
NO_BD_SOFT
NO_LSR_PARA_FILE
MS_REI
OUT_PWR_ABN
POWER_ABNORMAL
OH_LOOP
PS
R_LOC
R_LOF
R_LOS
SLAVE_WORKING
T_LOSEX
TEM_HA
TEM_LA
TEMP_OVER
TEST_STATUS
TF
TIME_NOT_SUPPORT
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
WRG_BD_TYPE
MPLS_PW_OAMFAIL
MPLS_TUNNEL_OAMFAIL

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9.1.14.1 Performance Events of N1EDQ41

Table 9-7 SDH
Issue 03 (2013-02-20)
LPBBE
LPES
LPSES
LPUAS
LPCSES
LPFEBBE
LPFEES
LPFESES
LPFEUAS
LPFECSES
CPUUSAGEMAX
CPUUSAGEMIN
CPUUSAGECUR
BDTEMPMAX
BDTEMPMIN
BDTEMPCUR
VC3BBE
VC3ES
VC3SES
VC3UAS
VC3CSES
VC3FEBBE
VC3FEES
VC3FESES
VC3FECSES
VC3FEUAS
MEMUSAGEMAX
MEMUSAGEMIN
MEMUSAGECUR
RSBBE
RSES
RSSES
RSUAS
RSCSES
RSOOF
RSOFS
MSBBE
MSES
MSUAS
MSCSES
MSSES
MSFEBBE
MSFEES
MSFESES
MSFEUAS
MSFECSES
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES
HPFESES
HPFEUAS
HPFECSES
TLBMAX
TLBMIN
TLBCUR
OSPICCVMAX
OSPICCVMIN
OSPICCVCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX

267

OSPITMPMIN
9 EoD Boards
OSPITMPCUR

MPLS_TUNNEL_FLR
MPLS_TUNNEL_FL
MPLS_TUNNEL_FD
MPLS_TUNNEL_FDV
Table 9-9 Tunnel

TUNNEL_RCVPKTS
TUNNEL_RCVBYTES
TUNNEL_SNDPKTS
TUNNEL_SNDBYTES
TNL_BW_UTILISATION
TUNNEL_REVERSE_SND
PKTS
TUNNEL_REVERSE_SND
BYTES
TUNNEL_REVERSE_R
CVPKTS
TUNNEL_REVERSE_RCV
BYTES
TUNNEL_RX_BPS
TUNNEL_TX_BPS
TUNNEL_RX_PPS
TUNNEL_TX_PPS
TUNNEL_REVERSE_R
X_BPS
TUNNEL_REVERSE_TX_
BPS
TUNNEL_REVERSE_RX_P
PS
TUNNEL_REVERSE_T
X_PPS

MPLS_PW_FLR
MPLS_PW_FL
MPLS_PW_FD
MPLS_PW_FDV
Table 9-11 PW
PW_RCVPKTS
PW_RCVBYTES
PW_SNDPKTS
PW_SNDBYTES
PW_BANDWIDTH_UTI
LISATION
PW_RX_BPS
PW_TX_BPS
PW_RX_PPS
PW_TX_PPS

ETHUNDER
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9 EoD Boards

RXBGOOD
TXBGOOD
RXBBAD
TXBBAD
RXPKTS
TXPKTS
RXPPS
TXPPS

The technical specifications of the EDQ41 include the parameters specified for optical interfaces,
Specifications of Optical Interfaces

The EDQ41 supports the STM-1/STM-4 optical modules.
Table 9-14 provides the specifications of STM-1 optical interfaces on the EDQ41.
Table 9-14 Specifications of STM-1 optical interfaces on the EDQ41
Item
Value
Nominal bit rate
155520 kbit/s
Line code
NRZ
Type of optical
interface
S-1.1
L-1.1
L-1.2
Type of Fiber
Single-mode LC
Single-mode LC
Single-mode LC
Transmission
distance (km)
2 to 15
15 to 40
40 to 80
Operating
wavelength range
(nm)
1261 to 1360
1263 to 1360
1480 to 1580
Launched optical
power range
(dBm)
-15 to -8
-5 to 0
-5 to 0
Receiver
sensitivity (dBm)
-28
-34
-34
Minimum
overload (dBm)
-8
-10
-10
Minimum
extinction ratio
(dB)
8.2
10
10
Table 9-15 provides the specifications specified for STM-4 optical interfaces on the EDQ41.
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Table 9-15 Specifications of STM-4 optical interfaces on the EDQ41

Item
Value
Nominal bit rate
622080 kbit/s
Line code
NRZ
Type of optical
interface
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
2 to 15
15 to 40
40 to 80
80 to 100
Operating wavelength
range (nm)
1274 to 1356
1280 to 1335
1480 to 1580
1480 to 1580
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Launched optical
power range (dBm)
-15 to -8
-3 to -2
-3 to -2
-3 to -2
(dBm)
-28
-28
-28
-34
Minimum Overload
(dBm)
-8
-8
-8
-13
Minimum extinction
ratio (dB)
8.2
10
10
10.5
The mechanical specifications of the EDQ41 are as follows:
l
Weight: 1.0 kg
Power Consumption
The maximum power consumption of the EDQ41 at room temperature (25C) is 70 W.
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10
SDH Boards
About This Chapter

This topic describes the SDH boards that operate at the STM-64, STM-16, STM-4, and STM-1
rates.
10.1 SL1
technical specifications of the SL1 (1xSTM-1 optical interface board). This topic also describes
how to configure and commission the SL1.
10.2 SL1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1A (1xSTM-1 optical interface board).
10.3 SLQ1
technical specifications of the SLQ1 (4xSTM-1 optical interface board).
10.4 SLQ1A
technical specifications of the SLQ1A (4xSTM-1 optical interface board).
10.5 SLO1
technical specifications of the SLO1 (8xSTM-1 optical interface board).
10.6 SLT1
technical specifications of the SLT1 (12xSTM-1 optical interface board).
10.7 SLH1
technical specifications of the SLH1 (16xSTM-1 signal processing board). This topic also
describes how to configure and commission the SLH1.
10.8 SEP1
technical specifications of the SEP1 (8xSTM-1 line processing board). This topic also describes
how to configure and commission the SEP1.
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10.9 SL4
technical specifications of the SL4 (1xSTM-4 optical interface board).
10.10 SL4A
10.11 SLD4
technical specifications of the SLD4 (2xSTM-4 optical interface board).
10.12 SLD4A
technical specifications of the SLD4A (2xSTM-4 optical interface board).
10.13 SLQ4
10.14 SLQ4A
10.15 SL16
10.16 SL16A
technical specifications of the SL16A (1xSTM-16 optical interface board). This topic also
describes how to configure and commission the SL16A.
10.17 SLD16
technical specifications of the SLD16 (2xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLD16.
10.18 SLQ16
technical specifications of the SLQ16 (4xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLQ16.
10.19 SLO16
technical specifications of the SLO16 (8xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLO16.
10.20 SF16
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).
10.21 SL64
technical specifications of the SL64 (1xSTM-64 optical interface board). This topic also
describes how to configure and commission the SL64.
10.22 SLD64
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10.23 SF64
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
This topic also describes how to configure and commission the SF64.
10.24 SF64A
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
10.25 SLQ41
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board). This topic also
10.26 SLH41
technical specifications of the SLH41 (16xSTM-1/STM-4 optical interface board with the
variable rate). This topic also describes how to configure and commission the SLH41.
10.27 EU04
technical specifications of the EU04 (4xSTM-1 electrical interface board).
10.28 EU08
10.29 OU08
technical specifications of the OU08 (8xSTM-1 optical interface board).
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10.1 SL1
technical specifications of the SL1 (1xSTM-1 optical interface board). This topic also describes
how to configure and commission the SL1.

The SL1 is available in several functional versions. The functions provided by the functional
versions are different.
The SL1 is available in the following functional versions: N1 and N2. The difference between
the functional versions is with regard to whether they support the tandem connection monitoring
(TCM) function and AU-3 services.
The N1SL1 is no longer manufactured.
Table 10-1 describes the versions of the SL1.
Table 10-1 Versions of the SL1
Item
Description
Functional versions
The SL1 is available in the following functional versions: N1 and N2.
Differences
l Service processing: AU-3 service processing.

l Maintenance features: loopbacks on VC-4 paths and TCM
function.
Substitution
Through the board version replacement function, the N1SL1A and

the N1SL1 can substitute each other.
NOTE
When you configure the multiplex section protection (MSP) or sub-network connection protection (SNCP),
you cannot configure the N1SL1 as the protection board if the working board is the N2SL1 on which the
TCM function is enabled or AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.
10.1.2 Application
The SL1 is a line board. The SL1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 10-1 shows the application of the SDH processing boards. The SDH processing boards
can form a ring network or a chain network in the system.
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Figure 10-1 Networking and application of the SDH processing boards
NE1
NE2
NE4
NE3
Service flow
Line board
NOTE
The SL1 does not support the two-fiber bidirectional ring MSP.

The SL1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 10-2 provides the functions and features of the SL1.
Table 10-2 Functions and features of the SL1
Function and
Feature
SL1
Basic functions
Transmits and receives 1xSTM-1 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-1,

S-1.1, L-1.1, L-1.2, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-1.2 type comply
with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Supports the usage and detection of the small form-factor pluggable
(SFP) optical module, which facilitates the maintenance of the optical
module.
l Provides the automatic laser shutdown (ALS) function. The optical
interface supports the setting of the on/off state of a laser.
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Function and
Feature
SL1
Service
processing
l Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l The N2SL1 supports the AU-3 services.
l Supports the transparent transmission and termination of the path

overheads.
l Supports one channel of ECC communication.
Alarms and
performance
events
Provides various alarms and performance events, which facilitates the

Protection
schemes
l Supports the Two-fiber ring MSP.

l Supports the Four-fiber ring MSP.
l Supports the Linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
Maintenance
features

l The N1SL1 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l The N2SL1 supports the TCM function.
l Supports the Cause by Cross function.
l Supports the press-to-collect function in fault data collection.

The SL1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module.
Figure 10-2 shows the functional block diagram of the SL1.
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10 SDH Boards
Figure 10-2 Functional block diagram of the SL1

155 MHz
O/E
155 Mbit/s
E/O
SPI
155
Mbit/s CDR
E/O
K1 and K2
insertion/extraction
K1 and K2
High-speed
bus
....
O/E
Backplane
Reference clock
Cross-connect
unit
155 Mbit/s
....
155 Mbit/s
155
Mbit/s
155 MHz
PLL
RST MST MSA HPT
High-speed
bus
CDR
SPI
DCC
155 Mbit/s
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power
PLL: phase-locked loop
SPI: SDH physical interface
RST: regenerator section

termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration
SDH: synchronous digital hierarchy

l
Converts the received optical signals into electrical signals, in the receive direction.
Converts the electrical signals into SDH optical signals, and then sends the SDH optical
signals to fibers for transmission, in the transmit direction.
The SPI detects the R_LOS alarm and provides the laser shut down function.
CDR Module
This module restores the clock signal.

this module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l
RST sub-module
In the receive direction, the RST sub-module terminates the regenerator section
overhead (RSOH). That is, the RST sub-module detects the frame alignment bytes (A1
and A2), descrambles all the bytes except the first line of the RSOH, restores and checks
the regenerator section trace byte (J0), and checks the B1 byte.
scrambles all the bytes except the first line of the RSOH.
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MST sub-module
In the receive direction, the MST sub-module terminates the multiplex section overhead
(MSOH). That is, the MST sub-module generates the multiplex section-alarm indication
signal (MS_AIS) alarm and detects the multiplex section-remote defect indication
(MS_RDI) alarm after detecting the K2 byte, and detects the multiplex section-remote
error indication (MS_REI) alarm and generates the B2-excessive errors (B2_EXC)
alarm after checking the B2 byte.
writes the B2 byte.
MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the administration unit
group (AUG), divides an AUG into N AU-4s, detects the administration unit-loss of
pointer (AU_LOP) alarm and the administration unit-alarm indication signal (AU_AIS)
alarm, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
HPT sub-module
In the receive direction, the HPT sub-module terminates the path overhead (POH). That
is, the HPT sub-module detects the higher order path-remote error indication (HP_REI)
alarm after checking the B3 byte, generates the higher order path-trace identifier
mismatch (HP_TIM) alarm and the higher order path-signal label mismatch (HP_SLM)
alarm and detects the higher order path-remote defect indication (HP_RDI) alarm after
detecting the J1 and C2 bytes, and generates the higher order path-unequipped
(HP_UNEQ) alarm after detecting the C2 byte.
Logic and Control Module

l
Manages and configures the other modules of the board.
Performs inter-board communication through the internal Ethernet interface.
Traces the clock signal from the active and standby cross-connect units.
Controls the laser.
Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
Selects the clock signal and frame header signal from the active and standby cross-connect
units.
Controls the indicators on the board.
Power Module
require.
10.1.5 Front Panel

The front panel of the SL1 has indicators, interfaces, and a bar code.
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Figure 10-3 shows the appearance of the front panel of the SL1.
Figure 10-3 Front panel of the SL1
SL1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
SL1
Indicators
l

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Interfaces
The front panel of the SL1 has one optical interface. Table 10-3 describes the types and usage
of the optical interfaces of the SL1.
Table 10-3 Optical interfaces of the SL1
Interface
Type of Interface
Usage
IN
LC
Receives optical signals.
OUT
LC
Transmits optical signals.

The SL1 does not have any jumpers or DIP switches that are used for board settings.
10.1.7 Valid Slots

The SL1 must be installed in a valid slot in the subrack. Otherwise, the SL1 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL1 vary with the cross-connect capacity of the subrack. The slots valid
for the board are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SL1 can be installed in slots 18 and
1117.
10.1.8 Feature Code

The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
Table 10-4 provides the relationship between the feature code of the SL1 and the type of optical
interface.
Table 10-4 Relationship between the feature code of the SL1 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SL110 and
SSN2SL110
10
S-1.1
SSN1SL111 and
SSN2SL111
11
L-1.1

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10 SDH Boards
Board
Feature Code
SSN1SL112 and
SSN2SL112
12
L-1.2
SSN1SL113 and
SSN2SL113
13
Ve-1.2
SSN1SL114 and
SSN2SL114
14
I-1


is correct.
----End

l J0 byte: Generally, use the default value. The default value of the J0 to be received is
Disabled.
Generally, use the default value. The default value of the J1 to be received is Disabled.
TUG structure.
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NOTE
For the other parameters to be set, see 27.5 SDH Processing Boards.
Step 3 Required: Configure a protection subnet. For details, see Configuring the Protection Subnet.
Step 4 Required: Configure services. For details, see Configuring the SDH Services.
----End

----End

Boards.
the Current Alarms.
----End

You can set parameters for the SL1 by using the U2000.
You can set the following parameters for the SL1 by using the U2000:
l
J0
J1
J2
C2
For the description of each parameter, see 27 Parameter Settings.

Troubleshooting
Table 10-5 lists the faults that occur on the SL1 frequently and the troubleshooting methods.
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NOTE
The SL1 uses the SFP optical module. When the SL1 operates and an abnormal alarm occurs on the optical
interface, check whether the optical module is properly installed. To check whether the optical module is
properly installed, you can re-seat the optical module.
Table 10-5 Methods used to troubleshoot the faults that occur on the SL1 frequently
Fault
Symptom
Common Fault Cause
Service
interruption
l The optical fiber or connector

becomes abnormal.
See Troubleshooting TDM Service

Interruptions.
l An incorrect operation is
performed.
l The types or settings of the
boards are inconsistent.
l The optical power becomes
abnormal.
Bit error
l The equipment becomes faulty.

l The clock configuration is
incorrect.
Pointer
justification
See Troubleshooting Pointer

Justification.
l The precision of the external

clock source is very low.
Protection
switching
failure
l The MSP switching fails.
NEs being
unreachable to
the U2000
l A single NE becomes
unreachable to the U2000.
l The SNCP switching fails.
See Troubleshooting Protection

Switching Faults.
l The clock protection switching

fails.
Unreachable.
l All the NEs in a subnet become

unreachable to the U2000.
l An NE becomes unreachable to
the U2000 frequently.
Equipment
interconnection
fault
An SDH overhead interconnection

fault occurs.
See Troubleshooting Device

Interconnection Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SL1, see Replacing an SDH Board.
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10.1.12.1 Alarms of N1SL1
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ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_FAIL
C2_PDI
C2_VCAIS
FSELECT_STG
COMMUN_FAIL
FPGA_ABN
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LASER_MOD_ERR
IN_PWR_ABN
J0_MM
LP_RDI_VC12
LASER_SHUT
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LSR_WILL_DIE
LSR_COOL_ALM
LSR_NO_FITED
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
R_LOF
POWER_ABNORMAL
OUT_PWR_ABN
SLAVE_WORKING
R_LOS
R_LOC
TEM_HA
SPARE_PATH_ALM
R_OOF
TF
TEM_LA
T_LOSEX
TU_AIS_VC3
TR_LOC
TEST_STATUS
W_R_FAIL
TU_LOP_VC12
TU_AIS_VC12
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
TU_LOP_VC3
TIME_NOT_SUPPORT
PS
PATCH_ERR
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
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ALM_ALS
ALM_AU3AIS
ALM_AU3B3OVER
ALM_AU3B3SD
ALM_AU3LOP
ALM_AU3RDI
ALM_AU3REI
ALM_AU3SLM
ALM_AU3TIM
ALM_AU3UNEQ
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_FAIL
C2_PDI
C2_VCAIS
FSELECT_STG
COMMUN_FAIL
FPGA_ABN
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LASER_MOD_ERR
IN_PWR_ABN
J0_MM
LP_RDI_VC12
LASER_SHUT
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LSR_WILL_DIE
LSR_COOL_ALM
LSR_NO_FITED
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
R_LOF
POWER_ABNORMAL
OUT_PWR_ABN
SLAVE_WORKING
R_LOS
R_LOC
TC_DEG
SPARE_PATH_ALM
R_OOF
TC_LTC
TC_EXC
T_LOSEX
TC_RDI
TC_ODI
TC_INCAIS
TC_UNEQ
TC_REI
TC_OEI
TEST_STATUS
TEM_HA
TC_TIM
TU_AIS_VC12
TF
TEM_LA
TU_LOP_VC3
TU_AIS_VC3
TR_LOC

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PATCH_ERR
W_R_FAIL
TU_LOP_VC12
SWDL_PKG_NOBDSOFT
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
PS
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

10.1.13.1 Performance Events of N1SL1

AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES

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HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

The technical specifications of the SL1 include the parameters specified for optical interfaces,

Table 10-6 lists the parameters specified for the optical interfaces of the SL1.
Table 10-6 Parameters specified for the optical interfaces of the SL1
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code
pattern
Non-return to zero (NRZ)
Application
code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Single-mode LC Single-mode LC
Single-mode
LC
Single-mode LC
Single-mode LC
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Parameter
Value
Operating
wavelength
range (nm)
1260 to 1360
1261 to 1360
1263 to 1360
1480 to 1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0
Receiver
sensitivity
(dBm)
-23
-28
-34
-34
-34
Minimum
overload (dBm)
-8
-8
-10
-10
-10
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Laser Safety Class

The mechanical specifications of the N1SL1 and N2SL1 are as follows:
l
Weight of the N1SL1 (kg): 0.6
Power Consumption
The maximum power consumption of the N1SL1 at room temperature (25C) is 17 W.
10.2 SL1A
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The SL1A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SL1 and the N1SL1A can substitute
each other.
10.2.2 Application
The SL1A is a line board. The SL1A can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1A converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SL1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 10-7 provides the functions and features of the SL1A.
Table 10-7 Functions and features of the SL1A
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Function and
Feature
SL1A
Basic functions

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Function and
Feature
SL1A
Specifications of
the optical
interface

S-1.1, L-1.1, L-1.2, and Ve-1.2.
Specifications of
the optical
module
module.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.
Maintenance
features

l Supports inloops and outloops on VC-4 paths.
services.

The SL1A consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-5 shows the functional block diagram of the SL1A.
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Figure 10-5 Functional block diagram of the SL1A

155 MHz
O/E
155 Mbit/s
E/O
SPI
155
Mbit/s CDR
E/O
K1 and K2
RST MST MSA HPT
CDR
SPI
K1 and K2
High-speed
bus
....
O/E
Backplane
Reference clock
Cross-connect
unit
155 Mbit/s
....
155 Mbit/s
155
Mbit/s
155 MHz
PLL
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
HPT: higher order path termination IIC: inter-integrated circuit
CDR: clock and data recovery

l
CDR Module

l
RST sub-module
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MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.2.5 Front Panel

The front panel of the SL1A has indicators, interfaces, a bar code, and a laser safety class label.
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Figure 10-6 shows the appearance of the front panel of the SL1A.
Figure 10-6 Front panel of the SL1A
SL1A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
SL1A
Indicators
l

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Interfaces
The front panel of the SL1A has one optical interface. Table 10-8 describes the types and usage
of the optical interfaces of the SL1A.
Table 10-8 Optical interfaces of the SL1A
Interface
Type of Interface
Usage
IN
LC
OUT
LC
10.2.6 Valid Slots

The slots valid for the SL1A vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL1A are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SL1A can be installed in slots 18 and
1117.
10.2.7 Feature Code

The feature code of the SL1A indicates the type of optical interface.
Table 10-9 provides the relationship between the feature code of the SL1A and the type of optical
interface.
Table 10-9 Relationship between the feature code of the SL1A and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SL1A10
10
S-1.1
SSN1SL1A11
11
L-1.1
SSN1SL1A12
12
L-1.2
SSN1SL1A13
13
Ve-1.2
SSN1SL1A14
14
I-1

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You can set the parameters for the SL1A by using the U2000.
You can set the following parameters for the SL1A by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SL1A include the parameters specified for optical interfaces,
laster safety class, mechanical specifications, and power consumption.

Table 10-10 lists the parameters specified for the optical interfaces of the SL1A.
Table 10-10 Parameters specified for the optical interfaces of the SL1A
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Transmissio
n distance
(km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength
range (nm)
1260 to 1360
1261 to 1360
1263 to 1360 1480 to 1580
1480 to 1580
Launched
optical
power range
(dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0
Receiver
sensitivity
(dBm)
-23
-28
-34
-34
-34

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Parameter
Value
Minimum
overload
(dBm)
-8
-8
-10
-10
-10
Minimum
extinction
ratio (dB)
8.2
8.2
10
10
10
Maximum
-20 dB
spectral
width (nm)
Minimum
side mode
suppression
ratio (dB)
30
30
Laser Safety Class

The mechanical specifications of the SL1A are as follows:
l
Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SL1A at room temperature (25C) is 17 W.
10.3 SLQ1

The SLQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ1 is no longer manufactured.
Table 10-11 describes the versions of the SLQ1.
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Table 10-11 Versions of the SLQ1

Item
Description
Functional
versions
The SLQ1 is available in two functional versions, namely, N1 and N2.
Differences

l Maintenance features: loopbacks on VC-4 paths.
Substitution
Through the board version replacement function, the N3SLQ41 can

substitute for the N1SLQ1 and N2SLQ1 at the same line rate. The
N1SLQ1 and the N1SLQ1A can substitute each other.
NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLQ1 as the protection board if the
working board is the N2SLQ1 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
10.3.2 Application
The SLQ1 is a line board. The SLQ1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLQ1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ1 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board
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The SLQ1 transmits and receives 4xSTM-1 optical signals, performs O/E conversion for the
line.
Table 10-12 provides the functions and features of the SLQ1.
Table 10-12 Functions and features of the SLQ1
Function and
Feature
SLQ1
Basic functions
Specifications of l Supports different types of standard optical interfaces, namely, the I-1,
the optical
S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.
interface
l The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
comply with the standards defined by Huawei.
Specifications of l Supports the detection and query of the information about the optical
the optical
module.
module
facilitates the maintenance of the optical module.
Service
processing
Overhead
processing
l The N2SLQ1 supports the AU-3 services.

overheads.
l Supports one to four channels of ECC communication.
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Alarms and
performance
events

Protection
schemes
SNCTP, and SNCMP.

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Function and
Feature
SLQ1
Maintenance
features

l The N1SLQ1 supports inloops on VC-4 paths.
services.
l The N2SLQ1 supports the TCM function.

The SLQ1 consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-8 shows the functional block diagram of the SLQ1.
Figure 10-8 Functional block diagram of the SLQ1
155 MHz
O/E
155 Mbit/s
E/O
SPI
O/E
E/O
155
Mbit/s
Backplane
Reference clock
Cross-connect
unit
K1 and K2
High-speed
bus
RST MST MSA HPT
CDR
SPI
K1 and K2
155 Mbit/s
....
....
155 Mbit/s
155
Mbit/s CDR
155 MHz
PLL
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
The functional modules of the STM-1 units are described as follows:

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l
CDR Module

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
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l
Controls the laser.
units.
Power Module
require.
10.3.5 Front Panel

The front panel of the SLQ1 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-9 shows the appearance of the front panel of the SLQ1.
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Figure 10-9 Front panel of the SLQ1
SLQ1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ1
Indicators
l
Interfaces
The front panel of the SLQ1 has four optical interfaces. Table 10-13 describes the types and
usage of the optical interfaces of the SLQ1.
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Table 10-13 Optical interfaces of the SLQ1

Interface
Type of Interface
Usage
IN1-IN4
LC
OUT1-OUT4
LC
10.3.6 Valid Slots

The slots valid for the SLQ1 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLQ1 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SLQ1 can be installed in slots 18 and
1117 in the subrack.
10.3.7 Feature Code

The feature code of the SLQ1 indicates the type of optical interface.
Table 10-14 provides the relationship between the feature code of the SLQ1 and the type of
optical interface.
Table 10-14 Relationship between the feature code of the SLQ1 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLQ110 and
SSN2SLQ110
10
S-1.1
SSN1SLQ111 and
SSN2SLQ111
11
L-1.1
SSN1SLQ112 and
SSN2SLQ112
12
L-1.2
SSN1SLQ113 and
SSN2SLQ113
13
Ve-1.2
SSN1SLQ114 and
SSN2SLQ114
14
I-1
SSN1SLQ115
15
Ie-1

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You can set the parameters for the SLQ1 by using the U2000.
You can set the following parameters for the SLQ1 by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLQ1 include the parameters specified for optical interfaces,

Table 10-15 lists the parameters specified for the optical interfaces of the SLQ1.
Table 10-15 Parameters specified for the optical interfaces of the SLQ1
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Ie-1
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
0 to 2
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode
LC
Multi-mode LC
Operating
wavelength
range (nm)
1260 to
1360
1261 to 1360
1263 to
1360
1480 to
1580
1480 to 1580
1270 to 1380
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0
-19 to -14
Receiver
sensitivity
(dBm)
-23
-28
-34
-34
-34
-30
Minimum
overload (dBm)
-8
-8
-10
-10
-10
-14
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Parameter
Value
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Laser Safety Class

The mechanical specifications of the N1SLQ1 and N2SLQ1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLQ1 at room temperature (25C) is 15 W.
10.4 SLQ1A

The SLQ1A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLQ1 and the N1SLQ1A can substitute
each other.
10.4.2 Application
The SLQ1A is a line board. The SLQ1A can be used on the OptiX OSN equipment series to
transmit and receive STM-1 optical signals. The SLQ1A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
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SLQ1A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SLQ1A transmits and receives STM-1 optical signals, performs O/E conversion for the
line.
Table 10-16 provides the functions and features of the SLQ1A.
Table 10-16 Functions and features of the SLQ1A
Function and
Feature
SLQ1A
Basic functions
Specifications of l Supports different types of standard optical interfaces, namely, the I-1,
the optical
S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.
interface
l The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
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Function and
Feature
10 SDH Boards
SLQ1A
the optical
module.
module
Service
processing
Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
SNCTP, and SNCMP.
Maintenance
features

services.

The SLQ1A consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-11 shows the functional block diagram of the SLQ1A.
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Figure 10-11 Functional block diagram of the SLQ1A

155 MHz
155 Mbit/s
155 Mbit/s
O/E
E/O
S
P
I
155
Mbit/s
E/O
S
P
I
155
Mbit/s
CDR
Cross-connect unit
K1 and K2
Cross-connect unit
K1 and K2 insertion/extraction
High-speed
bus
....
155 Mbit/s
O/E
155
Mbit/s
155
Mbit/s
....
155 Mbit/s
CDR
Reference clock
155 MHz
PLL
RST
155
Mbit/s
MS
T
MS
A
HPT
High-speed
bus
155
Mbit/s
DCC
SDH overhead processing module
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
Cross-connect unit A
Cross-connect unit B
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
+3.3 V
+3.3 V backup power

l
CDR Module

l
RST sub-module
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l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10.4.5 Front Panel

The front panel of the SLQ1A has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-12 shows the appearance of the front panel of the SLQ1A.
Figure 10-12 Front panel of the SLQ1A
SLQ1A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ1A
Indicators
l
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Interfaces
The front panel of the SLQ1A has four optical interfaces. Table 10-17 describes the types and
usage of the optical interfaces of the SLQ1A.
Table 10-17 Optical interfaces of the SLQ1A
Interface
Type of Interface
Usage
IN1IN4
LC
OUT1OUT4
LC
10.4.6 Valid Slots

The slots valid for the SLQ1A vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLQ1A are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SLQ1A can be installed in slots 18
and 1117 in the subrack.
10.4.7 Feature Code

The feature code of the SLQ1A indicates the type of optical interface.
Table 10-18 provides the relationship between the feature code of the SLQ1A and the type of
optical interface.
Table 10-18 Relationship between the feature code of the SLQ1A and the type of optical
interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLQ1A10
10
S-1.1
SSN1SLQ1A11
11
L-1.1
SSN1SLQ1A12
12
L-1.2
SSN1SLQ1A13
13
Ve-1.2

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Board
Feature Code
SSN1SLQ1A14
14
I-1
SSN1SLQ1A15
15
Ie-1

You can set the parameters for the SLQ1A by using the U2000.
You can set the following parameters for the SLQ1A by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLQ1A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.

Table 10-19 lists the parameters specified for the optical interfaces of the SLQ1A.
Table 10-19 Parameters specified for the optical interfaces of the SLQ1A
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Ie-1
Transmissio
n distance
(km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
0 to 2
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Multi-mode
LC
Operating
wavelength
range (nm)
1260 to
1360
1261 to
1360
1263 to
1360
1480 to
1580
1480 to
1580
1270 to
1380

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Parameter
Value
Launched
optical
power range
(dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0
-19 to -14
Receiver
sensitivity
(dBm)
-23
-28
-34
-34
-34
-30
Minimum
overload
(dBm)
-8
-8
-10
-10
-10
-14
Minimum
extinction
ratio (dB)
8.2
8.2
10
10
10
10
Maximum
-20 dB
spectral
width (nm)
Minimum
side mode
suppression
ratio (dB)
30
30
Laser Safety Class

The mechanical specifications of the SLQ1A are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLQ1A at room temperature (25C) is 15 W.
10.5 SLO1
technical specifications of the SLO1 (8xSTM-1 optical interface board).
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The SLO1 is available in two functional versions, namely, N2 and N3. The difference between
The N3SLO1 is discontinued.
Table 10-20 describes the versions of the SLO1.
Table 10-20 Versions of the SLO1
Item
Description
Functional
versions
The SLO1 is available in two functional versions, namely, N2 and N3.
Differences

l Maintenance features: loopbacks on VC-4 paths, TCM function, and
PRBS function.
Substitution
When the N2SLO1 is not configured with the TCM function and AU-3
services, the N3SLO1 can substitute for the N2SLO1.
NOTE
When you configure the MSP or SNCP, you cannot configure the N3SLO1 as the protection board if the
working board is the N2SLO1 on which the TCM function is enabled or AU-3 services are configured.
10.5.2 Application
The SLO1 is a line board. The SLO1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLO1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLO1 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board
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The SLO1 transmits and receives 8xSTM-1 optical signals, performs O/E conversion for the
line.
Table 10-21 provides the functions and features of the SLO1.
Table 10-21 Functions and features of the SLO1 board
Function and
Feature
SLO1
Basic functions
Receives and transmits 8xSTM-1 optical signals.
Specifications of
the optical interface
l Supports different types of standard optical interfaces, namely, the

I-1, S-1.1, L-1.1, L-1.2, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1,
and L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-1.2 type
Specifications of
the optical module
l Supports the detection and query of the information about the

optical module.
setting of the on/off state of a laser.
Service processing

l The N2SLO1 supports the AU-3 services.
Overhead
processing
l Processes the path overheads.

l Supports one to eight channels of ECC communication.
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Alarms and
performance events

Protection schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.

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Function and
Feature
SLO1
Maintenance
features

l The N3SLO1 supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not
affect services.
l Supports the upgrade of the board software without affecting
services.
l The N2SLO1 supports the TCM function.
l The N3SLO1 also supports the PRBS function in the line direction
and cross-connect direction.

The SLO1 consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-14 shows the functional block diagram of the SLO1.
Figure 10-14 Functional block diagram of the SLO1
155 MHz
O/E
155 Mbit/s
E/O
SPI
O/E
E/O
155
Mbit/s
Backplane
Reference clock
Cross-connect
unit
K1 and K2
High-speed
bus
RST MST MSA HPT
CDR
SPI
K1 and K2
155 Mbit/s
....
....
155 Mbit/s
155
Mbit/s CDR
155 MHz
PLL
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
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l
CDR Module

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
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l
Controls the laser.
units.
Power Module
require.
10.5.5 Front Panel

The front panel of the SLO1 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-15 and Figure 10-16 show the appearance of the front panel of the SLO1.
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Figure 10-15 Front panel of the SLO1 (with level optical interfaces)
SLO1
STAT
ACT
PROG
SRV
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8
CLASS 1
LASER
PRODUCT
SLO1
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Figure 10-16 Front panel of the SLO1 (with slanting optical interfaces)
SLO1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
TX1
RX1
TX2
RX2
TX3
RX3
TX4
RX4
TX5
RX5
TX6
RX6
TX7
RX7
TX8
RX8
SLO1
Indicators
l
Interfaces
The front panel of the SLO1 has eight optical interfaces. Table 10-22 describes the types and
usage of the optical interfaces of the SLO1.
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Table 10-22 Optical interfaces of the SLO1

Interface
Type of
Interface
Usage
IN1-IN8/RX1-RX8
LC
OUT1-OUT8/TX1TX8
LC
CAUTION
For SLO1 boards with level optical interfaces, use optical attenuators only on the ODF side.
10.5.6 Valid Slots

The slots valid for the SLO1 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLO1 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SLO1 can be installed in slots 18 and
1117. In this case, eight optical interfaces can be configured.
10.5.7 Feature Code

The feature code of the SLO1 indicates the type of optical interface.
Table 10-23 provides the relationship between the feature code of the SLO1 and the type of
optical interface.
Table 10-23 Relationship between the feature code of the SLO1 and the type of optical interface
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Board
Feature Code
Type of Optical interface
SSN2SLO110 and
SSN3SLO110
10
S-1.1
SSN2SLO111 and
SSN3SLO111
11
L-1.1
SSN2SLO112 and
SSN3SLO112
12
L-1.2

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Board
Feature Code
SSN2SLO113 and
SSN3SLO113
13
Ve-1.2
SSN2SLO114 and
SSN3SLO114
14
I-1

You can set the parameters for the SLO1 by using the U2000.
You can set the following parameters for the SLO1 by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLO1 include the parameters specified for optical interfaces,

Table 10-24 lists the parameters specified for the optical interfaces of the SLO1.
Table 10-24 Parameters specified for the optical interfaces of the SLO1
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
NRZ
Application code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Operating
wavelength range
(nm)
1261 to
1360
1261 to
1360
1263 to
1360
1480 to
1580
1480 to
1580
Launched optical
power range (dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0

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Parameter
Value
(dBm)
-23
-28
-34
-34
-34
Minimum overload
(dBm)
-8
-8
-10
-10
-10
Minimum extinction
ratio (dB)
8.2
8.2
10
10
10
Maximum -20 dB
spectral width (nm)
Minimum side mode suppression ratio

(dB)
30
30
Laser Safety Class

The mechanical specifications of the N2SLO1 are as follows:
l
Weight (kg): 1.1
The mechanical specifications of the N3SLO1 are as follows:

l
Weight (kg): 1.2
Power Consumption
The maximum power consumption of the N2SLO1 at room temperature (25C) is 26 W.
10.6 SLT1
technical specifications of the SLT1 (12xSTM-1 optical interface board).

The SLT1 is available in one functional version, namely, N1.
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10.6.2 Application
The SLT1 is a line board. The SLT1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLT1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLT1 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SLT1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 10-25 provides the functions and features of the SLT1.
Table 10-25 Functions and features of the SLT1
Function and
Feature
SLT1
Basic functions
Specifications of Supports S-1.1, L-1.1 and L-1.2 standard optical interfaces whose
the optical
characteristics comply with ITU-T G.957.
interface
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Function and
Feature
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SLT1
the optical
module.
module
facilitates the maintenance of the optical module.
Service
processing
Overhead
processing

overheads.
l Supports one to twelve channels of ECC communication. Port 1 to port
8 support the ECC communication by using bytes D1D12. Port 9 to
port 12 support the ECC communication by using bytes D1D3.
l Supports the time synchronization feature and transmission of the time
information by using the section overhead bytes.
Alarms and
performance
events

Protection
schemes
SNCTP, and SNCMP.
Maintenance
features

services.

The SLT1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module. The external services are accessed by the
external interface boards EU08 and OU08. The EU08 is an electrical interface board and the
OU08 is an optical interface board.
Figure 10-18 shows the functional block diagram of the SLT1.
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Figure 10-18 Functional block diagram of the SLT1

155 MHz
O/E
155 Mbit/s
E/O
SPI
155
Mbit/s CDR
E/O
K1 and K2
RST MST MSA HPT
CDR
SPI
K1 and K2
High-speed
bus
....
O/E
Backplane
Reference clock
Cross-connect
unit
155 Mbit/s
....
155 Mbit/s
155
Mbit/s
155 MHz
PLL
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination

l
CDR Module

l
RST sub-module
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MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.6.5 Front Panel

The front panel of the SLT1 has indicators, interfaces, a bar code, and a laser safety class label.
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Figure 10-19 shows the appearance of the front panel of the SLT1.
Figure 10-19 Front panel of the SLT1
SLT1
STAT
ACT
PROG
SRV
OUT1 IN1 OUT2 IN2 OUT3 IN3 OUT4 IN4 OUT5 IN5 OUT6 IN6 OUT7 IN7 OUT8 IN8 OUT9 IN9 OUT10IN10OUT11IN11OUT12IN12
CLASS 1
LASER
PRODUCT
SLT1
Indicators
l

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Interfaces
The front panel of the SLT1 has 12 optical interfaces. Table 10-26 describes the types and usage
of the optical interfaces of the SLT1.
Table 10-26 Optical interfaces of the SLT1
Interface
Type of
Interface
Usage
IN1IN12
LC
OUT1OUT12
LC
CAUTION
The optical interfaces of the SLT1 are level optical interfaces. Hence, use an optical attenuator
only on the ODF side.
10.6.6 Valid Slots

The slots valid for the SLT1 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
When the cross-connect capacity is 200 Gbit/s, the SLT1 can be installed in slots 18 and
1116. When the SLT1 is installed in slots 14, 15, and 16, one to eight optical interfaces
can be configured. When the SLT1 is installed in slots 58 and 1114, one to twelve optical
interfaces can be configured.
10.6.7 Feature Code

The feature code of the SLT1 indicates the type of optical interface.
Table 10-27 provides the relationship between the feature code of the SLT1 and the type of
optical interface.
Table 10-27 Relationship between the feature code of the SLT1 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLT123
23
S-1.1
SSN1SLT124
24
L-1.1
SSN1SLT125
25
L-1.2

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You can set the parameters for the SLT1 by using the U2000.
You can set the following parameters for the SLT1 by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLT1 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.

Table 10-28 lists the parameters specified for the optical interfaces of the SLT1.
Table 10-28 Parameters specified for the optical interfaces of the SLT1
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
NRZ
Application code
S-1.1
L-1.1
L-1.2
2 to 15
15 to 40
40 to 80
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC

(nm)
1261 to 1360
1263 to 1360
1480 to 1580
Launched optical power

range (dBm)
-15 to -8
-5 to 0
-5 to 0
-28
-34
-34
-8
-10
-10
Minimum extinction ratio

(dB)
8.2
10
10

width (nm)
Minimum side mode

30

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Laser Safety Class

The mechanical specifications of the SLT1 are as follows:
l
Weight (kg): 1.3
Power Consumption
The maximum power consumption of the SLT1 at room temperature (25C) is 22 W.
10.7 SLH1
technical specifications of the SLH1 (16xSTM-1 signal processing board). This topic also
describes how to configure and commission the SLH1.

The SLH1 is available in one functional version, namely, N1.
10.7.2 Application
The SLH1 is a line board. The SLH1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SLH1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SLH1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
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NE1
NE2
NE4
NE3
Service flow
Line board

The SLH1 processes STM-1 optical and electrical signals.
Table 10-29 provides the functions and features of the SLH1.
Table 10-29 Functions and features of the SLH1
Function and
Feature
SLH1
Basic functions
Processes 16xSTM-1 signals.
Specifications of
the optical
module
l Supports the detection and query of the information about optical

modules.
Service
processing
Overhead
processing

overheads. Supports the setting and query of the J0, J1, and C2 bytes.
l Supports one to sixteen channels of ECC communication. Port 1 to
port 8 support the ECC communication by using bytes D1-D12. Port
9 to port 16 support the ECC communication by using bytes D1-D3.
Alarms and
performance
events
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Function and
Feature
SLH1
Protection
schemes
10 SDH Boards

l Supports the TPS protection when used with the interface board and
the switching and bridging board.
Maintenance
features
l Supports inloops on VC-4 paths.

l Supports warm resets and cold resets. A warm reset does not affect
services.
When the SLH1 works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 10-30.
Table 10-30 Access capabilities of the SLH1 when the SLH1 works with different interface
boards and electrical interface switching boards
Interface Board
SLH1
None
The SLH1 cannot transmit/receive signals.
EU08
Transmits/Receives and processes 8-channel or 16-channel electrical

signals.
OU08
Transmits/Receives and processes 8-channel or 16-channel optical

signals.
EU08 + OU08
Transmits/Receives and processes 8-channel electrical signals and 8channel optical signals.
EU08 + TSB8
Transmits/Receives and processes 8-channel or 16-channel STM-1

electrical signals, and realizes the 1:N (N3) TPS protection.

The SLH1 consists of the CDR module, SDH overhead processing module, logic and control
module, and power module. The external services are accessed by the external interface boards
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EU08 and OU08. The EU08 is an electrical interface board and the OU08 is an optical interface
board.
Figure 10-21 shows the functional block diagram of the SLH1 when the SLH1 works with the
EU08 by describing how to process 1xSTM-1 signals.
Figure 10-21 Functional block diagram of the SLH1 when the SLH1 works with the EU08
155 MHz
SPI
EU08
155 Mbit/s
Encode/
Decode
K1 and K2
K1 and K2
High-speed
bus
....
155 Mbit/s
Backplane
Reference clock
Cross-connect
unit
155 Mbit/s
CMI
Transformer
155
155
Mbit/s CDR Mbit/s
155 MHz
PLL
RST MST MSA HPT
CDR
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
Logic and
control module
LOS
+3.3 V
Power
module
Frame header
Communication
Fuse
Power
module
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
Figure 10-22 shows the functional block diagram of the SLH1 when the SLH1 works with the
OU08 by describing how to process 1xSTM-1 signals.
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Figure 10-22 Functional block diagram of the SLH1 when the SLH1 works with the OU08
155 MHz
PLL
155 MHz
155
155
Mbit/s CDR Mbit/s
OU08
155 Mbit/s
K1 and K2
K1 and K2
155 Mbit/s
High-speed
bus
....
O/E
155 Mbit/s
Backplane
Reference clock
Cross-connect
unit
SPI
RST
MST MSA HPT
CDR
E/O
155 Mbit/s
High-speed
bus
DCC
SDH overhead
processing module
LOS
Laser shutdown
Frame header
Logic and
Communication
control module
+3.3 V
Power
module
Fuse
Power
module
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
CDR Module

l
RST sub-module
MST sub-module
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10 SDH Boards
writes the B2 byte.
l
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.7.5 Front Panel

The front panel of the SLH1 has indicators and a bar code.

The front panel of the SLH1 does not have an interface. Hence, the SLH1 must be used with the
EU08 or OU08. Figure 10-23 shows the appearance of the front panel of the SLH1.
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Figure 10-23 Front panel of the SLH1
SLH1
STAT
ACT
PROG
SRV
SLH1
Indicators
l

The SLH1 does not have any jumpers or DIP switches that are used for board settings.
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10.7.7 Valid Slots

The SLH1 must be installed in a valid slot in the subrack. Otherwise, the SLH1 fails to work
normally.
The slots valid for the SLH1 vary with the cross-connect capacity of the subrack. The SLH1
needs to work with the OU08/EU08 and TSB8. The slots valid for the SLH1 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SLH1 can be installed in slots 25 and
1316.
10.7.8 Board Protection

The SLH1 supports the 1:N (N3) tributary protection switching (TPS) protection.
Protection Principle
The TPS protection is equipment-level protection. When the working board fails, the accessed
signals are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
The SLH1 can work with the EU08 and TSB8 to realize one 1:N (N3) TPS protection group
for 8xSTM-1 or 16xSTM-1 electrical signals. Figure 10-24 shows the TPS protection provided
by the SLH1.
Figure 10-24 TPS protection provided by the SLH1
Service signal
Service signal
Switching
control bus
Crossconnect and
timing board
Interface board N
Interface board
Working board N
Working board
Working board 1
Protection board
Interface board 1
Protection
switching board
Failed
Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the corresponding working board through position 1 of the control switch on the interface
board.
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Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding interface board switches from position 1 to position 2. At the
same time, the control switch of the protection switching board switches to the
corresponding position so that the protection board can protect the failed working board.
NOTE
TPS trigger conditions on the OptiX OSN equipment are detected by the cross-connect and timing board.
Therefore, TPS is successful even though the system control board cannot be detected or is faulty.
Hardware Configuration
Figure 10-25 shows the slot configuration for two 1:3 TPS protection groups for 16xSTM-1
signals of the SLH1.
EU08
PIU
PIU
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
3
6
S
L
O
T
3
7
AUX
EU08
S
L
O
T
3
1
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working 2
S
L
O
T
1
1
Working 2
Working 1
S
L
O
T
1
0
FAN
Working 2
Working 1
S
L
O
T
9
XCS
S S S S
L L L L
O O O O
T T T T
5 6 7 8
XCS
S
L
O
T
4
Protection 1
FAN
S S S
L L L
O O O
T T T
1 2 3
Working 1
S
L
O
T
3
0
GSCC
TSB8
EU08
EU08
EU08
EU08
FAN
S
L
O
T
2
9
TSB8
S
L
O
T
2
8
TSB8
S
L
O
T
2
7
Protection 2
S
L
O
T
2
6
S
L
O
T
2
3
EU08
EU08
S
L
O
T
2
5
S
L
O
T
2
2
EU08
EU08
S
L
O
T
2
4
S
L
O
T
2
1
EU08
S
L
O
T
2
0
EU08
S
L
O
T
1
9
TSB8
Figure 10-25 Slot configuration for two 1:3 TPS protection groups of the SLH1
Fiber routing area
In Figure 10-25, the board in slot 2 protects the boards in slots 3-5. The board in slot 16 protects
the boards in slots 13-15.
Table 10-31 lists the slots for the SLH1, EU08, and TSB8.
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Table 10-31 Slots for the SLH1, EU08, and TSB8

Board
Protection Group 1
Protection Group 2
SLH1 (protection
board)
Slot 2
Slot 16
TSB8
Slots 19-20
Slots 35-36
SLH1 (working
board)
Slots 3-5
Slots 13-15
EU08
Slots 21-26
Slots 29-34
NOTE
When the equipment is configured for two 1:3 TPS protection groups for 8xSTM-1 signals of the SLH1,
the TSB8 and EU08 can be inserted only in the odd slots.


is correct.
----End

Disabled.
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TUG structure.
NOTE
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SLH1 by using the U2000.
You can set the following parameters for the SLH1 by using the U2000:
l
J0
J1
C2

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Troubleshooting
Table 10-32 lists the faults that occur on the SLH1 frequently and the troubleshooting methods.
Table 10-32 Methods used to troubleshoot the faults that occur on the SLH1 frequently
Fault Symptom
Common Fault
Cause
Service interruption
l The optical fiber,

cable, or
connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
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Fault Symptom
Common Fault
Cause
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLH1, see Replacing an SDH Board.

10.7.12.1 Alarms of N1SLH1(B)
Issue 03 (2013-02-20)
ALM_ALS
AU_LOP
AU_AIS
AU_CMM
B2_EXC
B1_EXC
B1_SD
B3_EXC_VC3
B2_SD
B3_EXC
BD_STATUS
B3_SD
B3_SD_VC3
BIP_SD
BIP8_ECC
BIP_EXC
C2_VCAIS
CHIP_FAIL
C2_PDI
FSELECT_STG
HP_LOM
COMMUN_FAIL
HP_REI
HP_SLM
HP_RDI
HP_UNEQ
IN_PWR_ABN

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HP_TIM
LASER_MOD_ERR
LASER_SHUT
J0_MM
LP_RDI_VC12
LP_RDI_VC3
LOOP_ALM
LP_REI_VC3
LP_SLM_VC12
LP_REI_VC12
LP_TIM_VC12
LP_TIM_VC3
LP_SLM_VC3
LP_UNEQ_VC3
LSR_COOL_ALM
LP_UNEQ_VC12
LSR_WILL_DIE
MS_AIS
LSR_NO_FITED
MS_REI
R_LOF
MS_RDI
NO_BD_SOFT
RELAY_FAIL
OH_LOOP
OUT_PWR_ABN
SUBCARD_ABN
POWER_ABNORMAL
R_LOC
TEM_LA
R_LOS
R_OOF
TPS_ALM
SLAVE_WORKING
SPARE_PATH_ALM
TU_AIS_VC3
T_LOSEX
TEM_HA
W_R_FAIL
TEST_STATUS
TF
PATCH_NOT_CONFIRM
TR_LOC
TU_AIS_VC12
MOD_TYPE_MISMATCH
TU_LOP_VC12
TU_LOP_VC3
SWDL_PKG_NOBDSOFT
PS
PATCH_ERR
PATCHFILE_NOTEXIST
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

10.7.13.1 Performance Events of N1SLH1(B)
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES

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MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

The technical specifications of the SLH1 include the parameters specified for optical interfaces,
Parameters Specified for Interfaces

The OU8 or EU08 provides interfaces for the SLH1. For the parameters specified for the
interfaces, see Technical Specifications of the EU08 and Technical Specifications of the OU08.
The mechanical specifications of the SLH1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLH1 at room temperature (25C) is 27 W.
10.8 SEP1
technical specifications of the SEP1 (8xSTM-1 line processing board). This topic also describes
how to configure and commission the SEP1.

The SEP1 is available in one functional version, namely, N1.
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10.8.2 Application
The SEP1 is a line board. The SEP1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SEP1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SEP1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SEP1 processes STM-1 signals. When the interfaces are available on the front panel of the
SEP1 (the logical board of the SEP1 is displayed as SEP1 on the U2000), the SEP1 processes
2xSTM-1 electrical signals. When the SEP1 is used with the interface board (the logical board
of the SEP1 is displayed as SEP on the U2000), the SEP1 processes 8xSTM-1 optical/electrical
signals or 4xSTM-1 electrical signals. The physical boards of the two types of logical boards
(SEP1 and SEP) are the SEP1. When the logical boards do not need to be differentiated, both
the SEP1 and SEP are defined as SEP1.
Table 10-33 provides the functions and features of the SEP1.
Table 10-33 Functions and features of the SEP1
Function and
Feature
SEP1
Basic functions
l Processes 2xSTM-1 signals when the interfaces are available on the

front panel.
l Processes 8xSTM-1 or 4xSTM-1 signals when the SEP1 works with
an interface board.
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Function and
Feature
SEP1
Service
processing
Overhead
processing

overheads.
l Supports one or two channels of ECC communication.
Alarms and
performance
events

Protection
schemes

l Supports the TPS protection when used with the interface board and
the switching and bridging board.
Maintenance
features

services.
When the SEP1 works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 10-34.
Table 10-34 Access capabilities of the SEP1 when the SEP1 works with different interface
boards and electrical interface switching boards
Issue 03 (2013-02-20)
Interface Board
SEP1
None
Transmits/Receives and processes 2xSTM-1 electrical signals, but does

not support the TPS protection.
EU04
Transmits/Receives and processes 4xSTM-1 electrical signals.

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Interface Board
SEP1
EU08
Transmits/Receives and processes 8xSTM-1 electrical signals.
OU08
Transmits/Receives and processes 8xSTM-1 optical signals.
EU04 + TSB4
Transmits/Receives and processes 4xSTM-1 electrical signals, and

supports the TPS protection.
EU08 + TSB8

EU04 + TSB8

NOTE
One SEP1 can transmit/receive services from only one interface board. When the SEP1 works with an
interface board, the two interfaces on the front panel of the SEP1 are invalid.

The SEP1 consists of the line interface module, CDR module, SDH overhead processing module,
logic and control module, and power module. The external services are accessed by the external
interface boards EU04//EU08/OU08. The EU04/EU08 is an electrical interface board and the
OU08 is an optical interface board.
Figure 10-27 shows the functional block diagram of the SEP1.
Figure 10-27 Functional block diagram of the SEP1
155 MHz
SPI
Port 1
155 Mbit/s
Port 2
CMI Encode/
Decode
Transformer
CMI
155 Mbit/s
155 Mbit/s
CDR
Transformer
Encode/
Decode
155
Mbit/s
K1 and K2
K1 and K2
155 Mbit/s
....
155 Mbit/s
NRZ
Backplane
Reference clock
Cross-connect
unit
155 MHz
PLL
NRZ CDR
High-speed
bus
155
Mbit/s
RST MST
MSA HPT
High-speed
bus
DCC
155 Mbit/s
SDH overhead
processing module
LOS
Frame header
Logic and
control module
+3.3 V
Power
module
Communication
Fuse
Power
module
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power

termination
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Figure 10-28 shows the functional block diagram of the SEP when the SEP works with the
EU08. When the SEP works with the EU04, the function block diagram is the same except that
the number of signals accessed and processed by the SEP is different.
Figure 10-28 Functional block diagram of the SEP when the SEP works with the EU08
Backplane
155 MHz
PLL
Reference clock
K1 and K2
EU08
SPI
155 Mbit/s
CMI
Encode/
Port 1
Transformer
155 Mbit/s
Decode
155 Mbit/s
CDR
155 Mbit/s
155 Mbit/s
CMI
Port 8
Encode/
155 Mbit/s Transformer
Decode
CDR
155 Mbit/s
K1 and K2
High-speed
bus
RST MST MSA HPT
155 Mbit/s
High-speed
bus
DCC
SDH overhead
processing module
LOS
Logic and
control module
+3.3 V
Power
module
Frame header
Communication
Fuse
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power

termination
Figure 10-29 shows the functional block diagram of the SEP when the SEP works with the
OU08.
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Figure 10-29 Functional block diagram of the SEP when the SEP works with the OU08
Backplane
155 MHz
PLL
155 OU08
Mbit/s
O/E
155
Port 1 Mbit/s
E/O
155
Mbit/s O/E
Port 8 155
Mbit/s E/O
Reference clock
K1 and K2
NRZ
SP
I
NRZ
155
Mbit/s
CDR
155 Mbit/s
155
Mbit/s
CDR
155 Mbit/s
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power

termination
NOTE
If the SEP works with the OU08 that uses electrical modules, it works in the same way as it does when it
works with the EU08.
Line Interface Module and CDR Module

l
In the receive direction, the received electrical signals (CMI codes) are isolated through
the converter and then transmitted to the decoding unit. The CDR module restores the clock
signals after decoding.
In the transmit direction, the SDH signals, which are processed by the SDH overhead
processing module, are transmitted to the encoding unit. The converter isolates the 155
Mbit/s electrical signals (CMI codes) and sends the signals. The encoding and decoding
units monitor R_LOS alarms.

l
RST sub-module
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l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10.8.5 Front Panel

The front panel of the SEP1 has indicators, interfaces, and a bar code.

Figure 10-30 shows the appearance of the front panel of the SEP1.
Figure 10-30 Front panel of the SEP1
SEP1
STAT
ACT
PROG
SRV
AOUT
AIN
BOUT
BIN
SEP1
Indicators
l
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Interfaces
The front panel of the SEP1 has two pairs of electrical interfaces. Table 10-35 describes the
types and usage of the electrical interfaces of the SEP1.
Table 10-35 Electrical interfaces of the SEP1
Interface
Type of Interface
Usage
AINBIN
75-ohm SMB
Receives the STM-1 signals.
AOUTBOUT
75-ohm SMB
Transmits the STM-1 signals.
Note: The SEP1 can be used with the interface board EU04, EU08, or OU08. In this case, the
SEP1 is defined as SEP. When the SEP1 is used with the interface board, the two interfaces
on the front panel are invalid.

The SEP1 does not have any jumpers or DIP switches that are used for board settings.
10.8.7 Valid Slots

The SEP1 must be installed in a valid slot in the subrack. Otherwise, the SEP1 cannot work
normally.
NOTE
When the SEP1 is used with the interface board, the logical board of the SEP1 is displayed as SEP on the
U2000.
The slots valid for the SEP1 are as follows:

l
When the SEP1 is connected to cables by using the interfaces on its front panel, the SEP1
can be installed in slots 16 and 1316 in the subrack.
When the SEP1 is used with the interface board, the SEP1 can be installed in slots 25 and

The TPS protection is equipment-level protection. When the working board fails, the accessed
services are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
NOTE
When the SEP1 is used with the interface board, the logical board of the SEP1 is displayed as SEP on the
U2000.
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The SEP can work with the EU08 and TSB8 to provide two 1:N (N3) TPS protection groups
for 8xSTM-1 electrical signals.
The SEP can also work with the EU04 and TSB4 to provide two 1:N (N3) TPS protection
groups for 4xSTM-1 electrical signals.
When the SEP works with the EU08 and TSB8 to realize the TPS protection, the protection
principle and valid slots of the involved boards are the same as the protection principle and valid
slots of the involved boards when the SEP works with the EU04 and TSB4 to realize the TPS
protection. Figure 10-31 shows the TPS protection provided by the SEP.
Figure 10-31 TPS protection provided by the SEP
Service signal
Service signal
Switching
control bus
Crossconnect and
timing board
Interface board N
Interface board
Working board N
Working board
Working board 1
Protection board
Interface board 1
Protection
switching board
Failed
Normal state
board.
Switching state
NOTE
Figure 10-32 shows the slot configuration for the two 1:3 TPS protection groups of the SEP.
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FAN
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
1
0
Working 1
Working 1
XCS
XCS
S
L
O
T
1
1
S
L
O
T
1
2
S
L
O
T
3
7
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working 2
S
L
O
T
9
Working 2
S S S S
L L L L
O O O O
T T T T
5 6 7 8
S
L
O
T
3
6
FAN
Working 2
S
L
O
T
4
Protection 1
FAN
S S S
L L L
O O O
T T T
1 2 3
Working 1
S
L
O
T
3
0
AUX
S
L
O
T
2
9
GSCC
S
L
O
T
2
8
TSB8
S
L
O
T
2
7
Protection 2
S
L
O
T
2
6
EU08
S
L
O
T
2
5
EU08
EU08
S
L
O
T
2
4
EU08
S
L
O
T
2
3
PIU
S
L
O
T
2
2
EU08
S
L
O
T
2
1
EU08
S
L
O
T
2
0
TSB8
S
L
O
T
1
9
PIU
Figure 10-32 Slot configuration for the two 1:3 TPS protection groups of the SEP
Fiber routing area
Table 10-36 lists the slots for the SEP, EU08, and TSB8.
Table 10-36 Slots for the SEP, EU08, and TSB8
Issue 03 (2013-02-20)
Board
Protection Group 1
Protection Group 2
SEP (working board)
Slot 2
Slot 16
TSB8
Slot 19
Slot 35
SEP (working board)
Slots 3-5
Slots 13-15
EU08
Slots 21, 23, and 25

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10 SDH Boards
10.8.9 Feature Code

The IFSD1 does not have a feature code.

CAUTION
When the SEP1 works with the EU08, ensure that the EU08 is installed before the SEP1.
Otherwise, the opposite end may receive the R_LOF alarm.

is correct.
----End

Disabled.
TUG structure.
NOTE
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10 SDH Boards
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SEP1 by using the U2000.
You can set the following parameters for the SEP1 by using the U2000:
l
J0
J1
J2
C2

Troubleshooting
Table 10-37 lists the faults that occur on the SEP1 frequently and the troubleshooting methods.
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10 SDH Boards
Table 10-37 Methods used to troubleshoot the faults that occur on the SEP1 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber,

cable, or
connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
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Fault Symptom
Common Fault
Cause
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SEP1, see Replacing an SDH Board.

10.8.13.1 Alarms of N1SEP1
Issue 03 (2013-02-20)
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_FAIL
C2_PDI
C2_VCAIS
FSELECT_STG
COMMUN_FAIL
FPGA_ABN
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LP_RDI_VC12
J0_MM
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
POWER_ABNORMAL
R_LOC
R_LOF
R_LOS
R_OOF
SLAVE_WORKING
SPARE_PATH_ALM

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10 SDH Boards
T_LOSEX
TEST_STATUS
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
PS
SWDL_PKG_NOBDSOFT
MOD_TYPE_MISMATCH
WRG_BD_TYPE

10.8.14.1 Performance Events of N1SEP1

AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS

The technical specifications of the SEP1 include the parameters specified for interfaces,
Parameters Specified for Interfaces

Table 10-38 lists the parameters specified for the interfaces of the SEP1.
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Table 10-38 Parameters specified for the interfaces of the SEP1

Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
CMI and NRZ
Connector
SMB
The mechanical specifications of the SEP1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SEP1 at room temperature (25C) is 17 W.
10.9 SL4

The SL4 is available in two functional versions, namely, N1 and N2. The difference between
The N1SL4 is no longer manufactured.
Item
Description
Functional versions
The SL4 is available in two functional versions, namely, N1 and N2.
Differences

l Maintenance features: loopbacks on VC-4 paths.
Substitution
Through the board version replacement function, the N1SL4 and the
N1SL4A can substitute each other.
NOTE
When you configure the MSP or SNCP, you cannot configure the N1SL4 as the protection board if the
working board is the N2SL4 on which the TCM function is enabled or AU-3 services are configured.
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10.9.2 Application
and receive STM-4 optical signals. The SL4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SL4 transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
line.
Function and
Feature
SL4
Basic functions
Receives and transmits 1xSTM-4 optical signals, and processes

1xSTM-4 standard or concatenation services.
Specifications of
the optical
interface

I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
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Function and
Feature
SL4
Specifications of
the optical module
module.
l Supports the usage and monitoring of the SFP optical module, which
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, and

VC-4-4c concatenation services.
Overhead
processing

overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.
Alarms and
performance
events

Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
l Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4 supports a maximum of two MSP protection rings.
Maintenance
features

l The N1SL4 supports inloops on VC-4 paths.
services.
services.

The SL4 consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-34 shows the functional block diagram of the .SL4
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155 MHz
622 Mbit/s
622 Mbit/s
O/E
S
P
I
E/O
622
Mbit/s
Reference clock
155 MHz
PLL
622
Mbit/s
CDR
K1 and K2
Cross-connect unit
Cross-connect unit
622 Mbit/s
High-speed bus
622 Mbit/s
O/E
E/O
....
....
622 Mbit/s
S
P
I
622
Mbit/s
CDR
622
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
622 Mbit/s
DCC
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
+3.3 V
+3.3 V backup power

l
CDR Module

l
RST sub-module
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10 SDH Boards
l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10 SDH Boards
10.9.5 Front Panel

The front panel of the SL4 has indicators, interfaces, a bar code, and a laser safety class label.

SL4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
SL4
Indicators
l
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Interfaces
Interface
Type of Interface
Usage
IN
LC
OUT
LC
The SL4 can use the swappable optical modules to facilitate maintenance.
10.9.6 Valid Slots

The slots valid for the SL4 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL4 are as follows:

l
1117.
10.9.7 Feature Code

Table 10-42 provides the relationship between the feature code of the SL4 and the type of optical
interface.
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SL410 and
SSN2SL410
10
S-4.1
SSN1SL411 and
SSN2SL411
11
L-4.1

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10 SDH Boards
Board
Feature Code
SSN1SL412 and
SSN2SL412
12
L-4.2
SSN1SL413 and
SSN2SL413
13
Ve-4.2
SSN1SL414 and
SSN2SL414
14
I-4

You can set the parameters for the SL4 by using the U2000.
l
J0
J1
J2
C2


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code pattern
NRZ
Application code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Single-mode
LC
Single-mode
LC
Singlemode LC
Singlemode LC
Singlemode LC
Operating
wavelength range
(nm)
1261 to 1360
1274 to 1356
1280 to
1335
1480 to
1580
1480 to
1580

368

10 SDH Boards
Parameter
Value
Launched optical
power range
(dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2
Receiver
sensitivity (dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the N1SL4 and N2SL4 are as follows:
l
Power Consumption
10.10 SL4A

The SL4A is available in one functional version, namely, N1.
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Through the board version replacement function, the N1SL4 and the N1SL4A can substitute
each other.
10.10.2 Application
The SL4A is a line board. The SL4A can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SL4A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4A converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SL4A transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
line.
Table 10-44 provides the functions and features of the SL4A.
Issue 03 (2013-02-20)
Function and
Feature
SL4A
Basic functions


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10 SDH Boards
Function and
Feature
SL4A
Specifications of
the optical
interface
Supports different types of standard optical interfaces, namely, the I-4,

S-4.1, L-4.1, L-4.2, and Ve-4.2. The characteristics of the optical
interfaces of the I-4, S-4.1, L-4.1, and L-4.2 types comply with ITU-T
G.957. The characteristics of the optical interface of the Ve-4.2 type
Supports the CWDM and DWDM colored optical interfaces. The optical
interface uses the LC connector. The CWDM optical interface supports
the transmission distance of 80 km, and the DWDM optical interface
supports the transmission distance of 120 km.
Specifications of
the optical module
module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and

Overhead
processing

overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.
Alarms and
performance
events

Protection
schemes
l Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4A supports a maximum of two MSP protection
rings.
Maintenance
features

services.
services.
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The SL4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module.
Figure 10-37 shows the functional block diagram of the SL4A.
Figure 10-37 Functional block diagram of the SL4A
155 MHz
622 Mbit/s
622 Mbit/s
O/E
S
P
I
E/O
622
Mbit/s
Reference clock
155 MHz
PLL
622
Mbit/s
CDR
K1 and K2
Cross-connect unit
Cross-connect unit
622 Mbit/s
High-speed bus
622 Mbit/s
O/E
E/O
....
....
622 Mbit/s
S
P
I
622
Mbit/s
CDR
622
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
622 Mbit/s
DCC
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
+3.3 V
+3.3 V backup power

l
CDR Module

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RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
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Power Module
require.
10.10.5 Front Panel

The front panel of the SL4A has indicators, interfaces, a bar code, and a laser safety class label.

SL4A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
SL4A
Indicators
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Interfaces
The front panel of the SL4A has one optical interface. Table 10-45 describes the types and usage
of the optical interfaces of the SL4A.
Interface
Type of Interface
Usage
IN
LC
OUT
LC
The SL4A can use the swappable optical modules to facilitate maintenance.
10.10.6 Valid Slots

The slots valid for the SL4A vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL4A are as follows:

l
1117.
10.10.7 Feature Code

Table 10-46 provides the relationship between the feature code of the SL4A and the type of
optical interface.
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SL4A10
10
S-4.1
SSN1SL4A11
11
L-4.1

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10 SDH Boards
Board
Feature Code
SSN1SL4A12
12
L-4.2
SSN1SL4A13
13
Ve-4.2
SSN1SL4A14
14
I-4

l
J0
J1
J2
C2


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code pattern
NRZ
Application code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Single-mode
LC
Single-mode
LC
Singlemode LC
Singlemode LC
Singlemode LC
Operating
wavelength range
(nm)
1261 to 1360
1274 to 1356
1280 to
1335
1480 to
1580
1480 to
1580
Launched optical
power range
(dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2

376

10 SDH Boards
Parameter
Value
Receiver
sensitivity (dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
30
30
Table 10-48 and Table 10-49 list the parameters specified for the colored optical interfaces of
the SL4A.
Table 10-48 CWDM parameters specified for the colored optical interfaces of the SL4A
Parameter
Value
CWDM
Issue 03 (2013-02-20)
Nominal bit rate
622080 kbit/s
Type of fiber
Single-mode LC
80

(dBm)
0 to 5
Operating wavelength range (nm)
1471 to 1611, in steps of 20
-28
-9
Maximum allowed dispersion (ps/

nm)
1600
8.2

(nm)
Minimum side mode suppression

ratio (dB)
30

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10 SDH Boards
Table 10-49 DWDM parameters specified for the colored optical interfaces of the SL4A
Parameter
Value
DWDM
Nominal bit rate
622080 kbit/s
Type of fiber
Single-mode LC
120

(dBm)
-1 to 3
192.10 to 196.00

(GHz)
10
-28
-9

(ps/nm)
2400
8.2

width (nm)
0.3
Minimum side mode

30
Laser Safety Class

l
Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SL4A at room temperature (25C) is 17 W.
10.11 SLD4
technical specifications of the SLD4 (2xSTM-4 optical interface board).
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The SLD4 is available in two functional versions, namely, N1 and N2. The difference between
The N1SLD4 is no longer manufactured.
Table 10-50 describes the versions of the SLD4.
Table 10-50 Versions of the SLD4
Item
Description
Functional
versions
The SLD4 is available in two functional versions, namely, N1 and N2.
Differences

l Maintenance features: loopbacks on VC-4 paths and TCM function.
Substitution
Through the board version replacement function, the N1SLD4 and the
N1SLD4A can substitute each other.
NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLD4 as the protection board if the
working board is the N2SLD4 on which the TCM function is enabled or AU-3 services are configured.
10.11.2 Application
The SLD4 is a line board. The SLD4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLD4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLD4 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board
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The SLD4 transmits and receives 2xSTM-4 optical signals, performs O/E conversion for the
line.
Table 10-51 provides the functions and features of the SLD4.
Table 10-51 Functions and features of the SLD4
Function and
Feature
SLD4
Basic functions

Specifications of
the optical
interface

I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
Specifications of
the optical module
module.
Service
processing

l The N2SLD4 supports the AU-3 services.
Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
l Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection
rings, and one SLD4 supports a maximum of four MSP protection
rings.
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Function and
Feature
SLD4
Maintenance
features

l The N1SLD4 supports inloops on VC-4 paths.
services.
services.
l The N2SLD4 supports the TCM function.

The SLD4 consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-40 shows the functional block diagram of the SLD4.
Figure 10-40 Functional block diagram of the SLD4
155 MHz
622 Mbit/s
622 Mbit/s
O/E
E/O
S
P
I
622
Mbit/s
CDR
Reference clock
155 MHz
PLL
622
Mbit/s
K1 and K2
Cross-connect unit
Cross-connect unit
622 Mbit/s
High-speed bus
622 Mbit/s
O/E
E/O
....
....
622 Mbit/s
S
P
I
622
Mbit/s
CDR
622
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
622 Mbit/s
DCC
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
Issue 03 (2013-02-20)

+3.3 V
+3.3 V backup power
381

10 SDH Boards

l
CDR Module

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
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10 SDH Boards

l
Controls the laser.
units.
Power Module
require.
10.11.5 Front Panel

The front panel of the SLD4 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-41 shows the appearance of the front panel of the SLD4.
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10 SDH Boards
Figure 10-41 Front panel of the SLD4
SLD4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
SLD4
Indicators
l
Interfaces
The front panel of the SLD4 has two optical interfaces. Table 10-52 describes the types and
usage of the optical interfaces of the SLD4.
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10 SDH Boards
Table 10-52 Optical interfaces of the SLD4

Interface
Type of Interface
Usage
IN1-IN2
LC
OUT1-OUT2
LC
The SLD4 can use the swappable optical modules to facilitate maintenance.
10.11.6 Valid Slots

The slots valid for the SLD4 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLD4 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SLD4 can be installed in slots 18 and
1117.

The feature code of the SLD4 indicates the type of optical interface.
Table 10-53 provides the relationship between the feature code of the SLD4 and the type of
optical interface.
Table 10-53 Relationship between the feature code of the SLD4 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLD410 and
SSN2SLD410
10
S-4.1
SSN1SLD411 and
SSN2SLD411
11
L-4.1
SSN1SLD412 and
SSN2SLD412
12
L-4.2
SSN1SLD413 and
SSN2SLD413
13
Ve-4.2
SSN1SLD414 and
SSN2SLD414
14
I-4

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10 SDH Boards

You can set the parameters for the SLD4 by using the U2000.
You can set the following parameters for the SLD4 by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLD4 include the parameters specified for optical interfaces,

Table 10-54 lists the parameters specified for the optical interfaces of the SLD4.
Table 10-54 Parameters specified for the optical interfaces of the SLD4
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2
Receiver
sensitivity
(dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13

386

10 SDH Boards
Parameter
Value
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the N1SLD4 and N2SLD4 are as follows:
l
Weight of the N1SLD4 (kg): 0.6
Weight of the N2SLD4 (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLD4 at room temperature (25C) is 17 W.
10.12 SLD4A
technical specifications of the SLD4A (2xSTM-4 optical interface board).

The SLD4A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLD4 and the N1SLD4A can substitute
each other.
10.12.2 Application
The SLD4A is a line board. The SLD4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLD4A converts the received optical signals
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10 SDH Boards
SLD4A converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLD4A transmits and receives STM-4 optical signals, performs O/E conversion for the
line.
Table 10-55 provides the functions and features of the SLD4A.
Table 10-55 Functions and features of the SLD4A
Function and
Feature
SLD4A
Basic functions

Specifications of
the optical
interface

I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
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10 SDH Boards
Function and
Feature
SLD4A
Specifications of
the optical module
module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and

Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
l Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection
rings, and one SLD4A supports a maximum of four MSP protection
rings.
Maintenance
features

services.
services.

The SLD4A consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-43 shows the functional block diagram of the SLD4A.
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10 SDH Boards
Figure 10-43 Functional block diagram of the SLD4A

155 MHz
622 Mbit/s
622 Mbit/s
O/E
S
P
I
E/O
622
Mbit/s
Reference clock
155 MHz
PLL
622
Mbit/s
CDR
K1 and K2
Cross-connect unit
Cross-connect unit
622 Mbit/s
High-speed bus
622 Mbit/s
O/E
E/O
....
....
622 Mbit/s
S
P
I
622
Mbit/s
CDR
622
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
622 Mbit/s
DCC
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
+3.3 V
+3.3 V backup power

l
CDR Module

l
RST sub-module
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10 SDH Boards
l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10 SDH Boards
10.12.5 Front Panel

The front panel of the SLD4A has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-44 shows the appearance of the front panel of the SLD4A.
Figure 10-44 Front panel of the SLD4A
SLD4A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
SLD4A
Indicators
l
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10 SDH Boards
Interfaces
The front panel of the SLD4A has two optical interfaces. Table 10-56 describes the types and
usage of the optical interfaces of the SLD4A.
Table 10-56 Optical interfaces of the SLD4A
Interface
Type of Interface
Usage
IN1IN2
LC
OUT1OUT2
LC
The SLD4A can use the swappable optical modules to facilitate maintenance.
10.12.6 Valid Slots

The slots valid for the SLD4A vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLD4A are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SLD4A can be installed in slots 18
and 1117.

The feature code of the SLD4A indicates the type of optical interface.
Table 10-57 provides the relationship between the feature code of the SLD4A and the type of
optical interface.
Table 10-57 Relationship between the feature code of the SLD4A and the type of optical
interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLD4A10
10
S-4.1
SSN1SLD4A11
11
L-4.1
SSN1SLD4A12
12
L-4.2

393

10 SDH Boards
Board
Feature Code
SSN1SLD4A13
13
Ve-4.2
SSN1SLD4A14
14
I-4

You can set the parameters for the SLD4A by using the U2000.
You can set the following parameters for the SLD4A by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLD4A include the parameters specified for optical

Table 10-58 lists the parameters specified for the optical interfaces of the SLD4A.
Table 10-58 Parameters specified for the optical interfaces of the SLD4A
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2

394

10 SDH Boards
Parameter
Value
Receiver
sensitivity
(dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the SLD4A are as follows:
l
Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SLD4A at room temperature (25C) is 17 W.
10.13 SLQ4

The N1SLQ4 is no longer manufactured.
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Item
Description
Functional
versions
The SLQ4 is available in two functional versions, namely, N1 and N2.
Differences

Substitution
Through the board version replacement function, the N3SLQ41 can substitute
for the N1SLQ4 and N2SLQ4 at the same line rate. The N1SLQ4 and the
N1SLQ4A can substitute each other.
NOTE
10.13.2 Application
The SLQ4 is a line board. The SLQ4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLQ4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ4 converts
signals.
NE1
NE2
NE4
NE3
Service flow
Line board
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The SLQ4 transmits and receives STM-4 optical signals, performs O/E conversion for the
line.
Function and
Feature
SLQ4
Basic functions
Specifications of
the optical
interface

S-4.1, L-4.1, L-4.2, and Ve-4.2.
Specifications of
the optical
module
module.
Service
processing

Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
l Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4 supports a maximum of eight MSP protection rings.
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Function and
Feature
SLQ4
Maintenance
features

l The N1SLQ4 supports inloops on VC-4 paths.
services.

155 MHz
622 Mbit/s
622 Mbit/s
O/E
E/O
S
P
I
622
Mbit/s
CDR
Reference clock
155 MHz
PLL
622
Mbit/s
K1 and K2
Cross-connect unit
Cross-connect unit
622 Mbit/s
High-speed bus
622 Mbit/s
O/E
E/O
....
....
622 Mbit/s
S
P
I
622
Mbit/s
CDR
622
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
622 Mbit/s
DCC
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3 V
DC/DC
converter
Frame header
Communication
Fuse
SCC unit
Cross-connect unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
DC/DC
converter
Fuse

termination
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+3.3 V
+3.3 V backup power
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10 SDH Boards

l
CDR Module

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
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l
Controls the laser.
units.
Power Module
require.
10.13.5 Front Panel


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SLQ4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ4
Indicators
l
Interfaces
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Interface
Type of Interface
Usage
IN1-IN4
LC
OUT1-OUT4
LC
The SLQ4 can use the swappable optical modules to facilitate maintenance.
10.13.6 Valid Slots

The SLQ4 can be installed in slots 18 and 1116 in the subrack.
NOTE
l Slot bandwidth
l Board version
When the cross-connect capacity is 200 Gbit/s, the SLQ4 can be installed in slots 18 and
1116. When the SLQ4 is installed in slots 14, 15, and 16, two optical interfaces can be
configured. When the SLQ4 is installed in slots 58 and 1114, four optical interfaces can
be configured.

optical interface.
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Board
Feature Code
SSN1SLQ410 and
SSN2SLQ410
10
S-4.1
SSN1SLQ411 and
SSN2SLQ411
11
L-4.1
SSN1SLQ412 and
SSN2SLQ412
12
L-4.2
SSN1SLQ413 and
SSN2SLQ413
13
Ve-4.2
SSN1SLQ414 and
SSN2SLQ414
14
I-4

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l
J0
J1
J2
C2


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Parameter
Value
Nominal bit rate
622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2
Receiver
sensitivity
(dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13

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Parameter
Value
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the SLQ4 are as follows:
l
Weight (kg): 1.0
Power Consumption
10.14 SLQ4A

The SLQ4A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLQ4 and the N1SLQ4A can substitute
each other.
10.14.2 Application
The SLQ4A is a line board. The SLQ4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLQ4A converts the received optical signals
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SLQ4A converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLQ4A transmits and receives STM-4 optical signals, performs O/E conversion for the
line.
Table 10-64 provides the functions and features of the SLQ4A.
Table 10-64 Functions and features of the SLQ4A
Function and
Feature
SLQ4A
Basic functions
Specifications of
the optical
interface

S-4.1, L-4.1, L-4.2, and Ve-4.2.
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Function and
Feature
SLQ4A
Specifications of
the optical
module
module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
Overhead
processing

overheads.
Alarms and
performance
events

Protection
schemes
l Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4A supports a maximum of eight MSP protection rings.
Maintenance
features

services.

The SLQ4A consists of the O/E converting module, CDR module, SDH overhead processing
Figure 10-49 shows the functional block diagram of the SLQ4A.
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Figure 10-49 Functional block diagram of the SLQ4A

155 MHz
622 Mbit/s
622 Mbit/s
O/E
E/O
S
P
I
622
Mbit/s
E/O
S
P
I
K1 and K2
High-speed
bus
....
622 Mbit/s
O/E
622
Mbit/s
622 Mbit/s
....
622 Mbit/s
CDR
Reference clock
155 MHz
PLL
622
Mbit/s
RST
622
CDR Mbit/s
MST
MSA
High-speed
bus
HPT
622 Mbit/s
Cross-connect
unit
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
DCC
SCC unit
IIC
LOS
Laser shutdown
Logic and
control
module
+3.3
V
DC/DC
converter
DC/DC
converter
Frame header
Communication
Fuse
Fuse
Cross-connect
unit
SCC unit
-48 V/ -60 V
-48 V/ -60 V
+3.3 V
+3.3 V backup
power

termination

l
CDR Module

l
RST sub-module
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l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10.14.5 Front Panel

The front panel of the SLQ4A has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-50 shows the appearance of the front panel of the SLQ4A.
Figure 10-50 Front panel of the SLQ4A
SLQ4A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ4A
Indicators
l
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Interfaces
The front panel of the SLQ4A has four optical interfaces. Table 10-65 describes the types and
usage of the optical interfaces of the SLQ4A.
Table 10-65 Optical interfaces of the SLQ4A
Interface
Type of Interface
Usage
IN1IN4
LC
OUT1OUT4
LC
The SLQ4A can use the swappable optical modules to facilitate maintenance.
10.14.6 Valid Slots

The SLQ4A can be installed in slots 18 and 1116 in the subrack.
NOTE
l Slot bandwidth
l Board version
When the cross-connect capacity is 200 Gbit/s, the SLQ4A can be installed in slots 18
and 1116. When the SLQ4A is installed in slots 14, 15, and 16, two optical interfaces
can be configured. When the SLQ4A is installed in slots 58 and 1114, four optical

The feature code of the SLQ4A indicates the type of optical interface.
Table 10-66 provides the relationship between the feature code of the SLQ4A and the type of
optical interface.
Table 10-66 Relationship between the feature code of the SLQ4A and the type of optical
interface
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Board
Feature Code
SSN1SLQ4A10
10
S-4.1
SSN1SLQ4A11
11
L-4.1
SSN1SLQ4A12
12
L-4.2

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Board
Feature Code
SSN1SLQ4A13
13
Ve-4.2
SSN1SLQ4A14
14
I-4

You can set the parameters for the SLQ4A by using the U2000.
You can set the following parameters for the SLQ4A by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SLQ4A include the parameters specified for optical

Table 10-67 lists the parameters specified for the optical interfaces of the SLQ4A.
Table 10-67 Parameters specified for the optical interfaces of the SLQ4A
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Parameter
Value
Nominal bit rate
622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-3 to +2
-3 to +2
-3 to +2

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Parameter
Value
Receiver
sensitivity
(dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the SLQ4A are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLQ4A at room temperature (25C) is 17 W.
10.15 SL16

The SL16 is available in three functional versions, namely, N1, N2, and N3. The difference
between the three versions is with regard to whether they support the TCM function and AU-3
services. The N1SL16 and N2SL16 are discontinued.
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Item
Description
Functional
versions
The SL16 is available in three functional versions, namely, N1, N2, and N3.
Differences
l Specifications of optical interfaces: DWDM colored optical interfaces.

l REG specifications: REG function.
Substitutio
n
The N1SL16 and N2SL16 cannot be substituted with each other.

The N3SL16 supports the board version replacement function.
l The N3SL16 can substitute for the N1SL16.
l When the AU-3 services are not required, the N3SL16 can substitute for
the N2SL16.
After the N3SL16 substitutes for the N1SL16 or N2SL16, the configuration
and service status of the N3SL16 are the same as the configuration and service
status of the N1SL16 or N2SL16.
NOTE
In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l You cannot configure the N1SL16 as the protection board if the working board is the N2SL16 or
N3SL16 on which the TCM function is enabled. Otherwise, the services are interrupted when a
l You cannot configure the N1SL16 or N3SL16 as the protection board if the working board is the
N2SL16 on which the AU-3 services are configured. Otherwise, the services are interrupted when a
10.15.2 Application
and receive STM-16 optical signals. The SL16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL16
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
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NE1
NE2
NE4
NE3
Service flow
Line board

The SL16 receives and transmits 1xSTM-16 optical signals and processes overhead bytes.
Function and
Feature
SL16
Basic functions
Specifications
of the optical
interface

L-16.2, L-16.2Je, V-16.2Je (with the booster amplifier (BA)), and
U-16.2Je (with the BA and pre-amplifier (PA)). The characteristics of
the optical interface of the L-16.2 type comply with ITU-T G.957 and
ITU-T G.692. The characteristics of the optical interfaces of the
L-16.2Je, V-16.2Je (with the BA), and U-16.2Je (with the BA and PA)
types comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with ITUT G.692. The U-16.2Je optical interface can be directly connected to
the dense wavelength division multiplexing (DWDM) equipment.
l The N3SL16 supports DWDM colored optical interfaces, which use
LC connectors and support the transmission distances of 170 km and
640 km.
Specifications
of the optical
module
module.
l Supports fixed optical modules.
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Function and
Feature
SL16
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c

concatenation services, VC-4-8c concatenation services, and
Overhead
processing

overheads.
Alarms and
performance
events

Specifications
of the REG
The N2SL16/N3SL16 board supports the setting and query of the REG
working mode.
Protection
schemes
SNCP, SNCMP, and SNCTP.
l Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SL16 supports a maximum of two MSP protection rings.
Maintenance
features

l The N1SL16 supports inloops on VC-4 paths. The N3SL16 board
supports inloops and outloops on paths.
services.
l The N2SL16 and N3SL16 support the TCM function.
l The N2SL16/N3SL16 board supports the TCM function.
l The N3SL16 board also supports the PRBS function in the line
direction.

The SL16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, power module.
Figure 10-52 shows the functional block diagram of the SL16.
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155 MHz
2.488
Gbit/s
O/E
SPI 2.488 DEMUX 16x155

E/O
Gbit/s
Mbit/s
. .
. .
2.488
Gbit/s
O/E
E/O
SPI
2.488
Gbit/s
MUX
16x155
Mbit/s
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
O/E
converting
module
155 MHz
PLL
Backplane
Reference clock
Cross-connect
unit
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination

l
MUX/DEMUX Module
l
In the receive direction, the DEMUX part demultiplexes the high rate electrical signals into
multiple parallel electrical signals, and recovers the clock signal at the same time.
In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high rate electrical signals.

This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
l
RST sub-module
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
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l
MST sub-module
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
writes the B2 byte.
MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT submodule detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.

l
Controls the laser.
units.
Power Module
require.
10.15.5 Front Panel

The front panel of the SL16 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
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SL16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
APD
Receiver
MAX:-9dBm
OUT
IN
SL16
Indicators
l

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Interfaces
Interface
Type of Interface
Usage
IN
LC
OUT
LC
10.15.6 Valid Slots

The slots valid for the SL16 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL16 are as follows:

l
1114.

Table 10-71 describes the relationship between the feature code of the SL16 and the type of
optical interface
Issue 03 (2013-02-20)
Board
Feature Code
Type of Optical
Interface
SSN1SL1600, SSN3SL1600
00
Fixed-wavelength
optical interface
SSN1SL1601, SSN2SL1601, and SSN3SL1601
01
L-16.2
02
L-16.2Je
03
V-16.2Je
04
U-16.2

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l
J0
J1
J2
C2


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
2488320 kbit/s
Line code
pattern
NRZ
Application
code
L-16.2
L-16.2Je
V-16.2Je (BA)
U-16.2Je (BA+PA)
Transmissio
n distance
(km)
50 to 80
80 to 100
100 to 140
140 to 170
Type of fiber
Singlemode LC
Singlemode LC
Single-mode LC
Single-mode LC
Operating
wavelength
range (nm)
1500 to
1580
1530 to
1560
1530 to 1565
1550.12
Launched
optical
power range
(dBm)
-2 to +3
5 to 7
-2 to +3
(without
the BA)
-2 to +3
(without
the BA
or PA)
15 to 18
(with the
BA)
Receiver
sensitivity
(dBm)
-28
-28
-28
-28
(without
the PA
or BA)
-32 (with
the PA)
13 to 15
(with the
BA)

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Parameter
Value
Minimum
overload
(dBm)
-9
-9
-9
-9
(without
the PA
or BA)
Dispersion
tolerance (ps/
nm)
1600
2000
2800
3400
Minimum
extinction
ratio (dB)
8.2
8.2
8.2
8.2
Maximum
-20 dB
spectral
width (nm)
Minimum
side mode
suppression
ratio (dB)
30
30
30
30
-10 (with
the PA)
Note: The optical interface of the Le-16.2 type is the same as the optical interface of the
L-16.2Je type.
The launched optical power of the optical interface of the V-16.2Je type is measured when
the BA is added. The launched optical power of the optical interface of the U-16.2Je type is
measured when the BA and PA are added. When no amplifier is added, the launched optical
power of the optical interfaces of the V-16.2Je and U-16.2Je types ranges from -2 dBm to 3
dBm.
Table 10-73 lists the parameters specified for the colored optical interfaces of the N3SL16.
Table 10-73 Parameters specified for the colored optical interfaces of the N3SL16
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
2488320 kbit/s
Type of fiber
Single-mode LC
Dispersion-limited distance (km)
170
640
Launched optical power range (dBm)
-2 to +3
-5 to -1
-28
-28
-9
-9

421

Parameter
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Value
DWDM

nm)
3400
10880
8.2
10
Central frequency deviation (GHz)
20
20

ratio (dB)
30
35
Maximum -20 dB spectral width (nm)
0.4
0.2
Maximum optical path penalty (dB)
Optical signal-to-noise ratio (dB)
20
20
Laser Safety Class

The mechanical specifications of the SL16 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the N1SL16 and N2SL16 at room temperature (25C) is
19 W.
10.16 SL16A
technical specifications of the SL16A (1xSTM-16 optical interface board). This topic also
describes how to configure and commission the SL16A.

The SL16A is available in the following functional versions: N3, N2, and N1. The N1SL16A
and N2SL16A are discontinued.
Table 10-74 describes the versions of the SL16A.
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Item
Description
Functional versions
The SL16A is available in the following functional versions: N3, N2,

and N1. The N1SL16A and N2SL16A are discontinued.
Differences
l Specifications of optical interfaces: DWDM colored optical

interfaces.
l REG specifications: REG function.
function.
Substitution
l The N1SL16A and N2SL16A cannot be substituted with each

other.
l The N3SL16A supports the board version replacement function.
The N3SL16A can substitute for the N1SL16A.
When the AU-3 services are not configured, the N3SL16A can
substitute for the N2SL16A.
l After the N3SL16A substitutes for the N1SL16A or N2SL16A,
the configuration and service status of the N3SL16A are the same
as the configuration and service status of the N1SL16A or
N2SL16A.
NOTE
In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l You cannot configure the N1SL16A as the protection board if the working board is the N2SL16A or
N3SL16A on which only the TCM function is enabled. Otherwise, the services are interrupted when
a switching operation is performed.
l You cannot configure the N3SL16A or N1SL16A as the protection board if the working board is the
N2SL16A on which only the AU-3 services are configured. Otherwise, the services are interrupted
when a switching operation is performed.
10.16.2 Application
The SL16A is a line board. The SL16A can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SL16A converts the received optical signals
SL16A converts the electrical signals sent from the cross-connect side into optical signals and
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NE1
NE2
NE4
NE3
Service flow
Line board

The SL16A receives and transmits 1xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 10-75 describes the functions and features of the SL16A.
Function and
Feature
SL16A
Basic functions
optical interface
Supports different types of standard optical interfaces, namely, the

I-16, S-16.1, L-16.1, and L-16.2. The characteristics of the optical
interfaces comply with ITU-T G.957 and ITU-T G.692.
The N3SL16A supports the CWDM and DWDM colored optical
interfaces. The optical interface uses the LC connector. The CWDM
optical interface supports the transmission distance of 80 km, and
the DWDM optical interface supports the transmission distance of
120 km.
optical module

optical module.
l Supports the usage and monitoring of the SFP optical module,
which facilitates the maintenance and upgrading of the optical
module.
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10 SDH Boards
Function and
Feature
SL16A
Service processing
l Supports the VC-12 services, VC-3 services, VC-4 services,

VC-4-4c concatenation services, VC-4-8c concatenation
services, and VC-4-16c concatenation services.
l The N2SL16A supports the AU-3 services.
Overhead processing

overheads.
Alarms and
performance events

REG
The N2SL16A/N3SL16A board supports the setting and query of

the REG working mode.
Protection schemes

l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes two sets of K bytes.
One SL16A supports a maximum of two MSP rings.
Maintenance features

l The N1SL16A supports inloops on VC-4 paths. The N3SL16A
board supports inloops and outloops on VC-4 paths.
affect services.
l Supports the query of the manufacturing information of the
board.
l The N2SL16A/N3SL16A board supports the TCM function.
services.
l The N3SL16A board also supports the PRBS function in the line
direction.
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10 SDH Boards

The N1SL16A/N2SL16A/N3SL16A consists of the O/E converting module, MUX/DEMUX
module, SDH overhead processing module, logic and control module, and power module.
Figure 10-55 shows the functional block diagram of the N1SL16A/N2SL16A/N3SL16A.
Figure 10-55 Functional block diagram of the N1SL16A/N2SL16A/N3SL16A
155 MHz
2.488
Gbit/s
2.488
Gbit/s
O/E
DEMUX 16x155
Mbit/s
SPI
2.488
Gbit/s
2.488
Gbit/s
E/O
O/E
converting
module
MUX
16x155
Mbit/s
155 MHz
PLL
Backplane
Reference clock
Cross-connect
unit
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
HPT: higher order path termination -

l
MUX/DEMUX Module
l

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10 SDH Boards
RST sub-module
byte.
MST sub-module
writes the B2 byte.
MSA sub-module
justifications.
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
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10 SDH Boards
10.16.5 Front Panel

The front panel of the SL16A has indicators, interfaces, a bar code, a laser safety class label,
and an APD alarm label.

SL16A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
APD
Receiver
MAX:-9dBm
OUT
IN
SL16A
Indicators
l
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10 SDH Boards
Interfaces
The front panel of the SL16A has one optical interface. Table 10-76 describes the types and
usage of the optical interfaces of the SL16A.
Interface
Type of Interface
Usage
IN
LC
OUT
LC

The SL16A does not have any jumpers or DIP switches that are used for board settings.
10.16.7 Valid Slots

The SL16A must be installed in a valid slot in the subrack. Otherwise, the SL16A fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL16A vary with the cross-connect capacity of the subrack. The slots
valid for the SL16A are as follows:
l
1114.

Table 10-77 describes the relationship between the feature code of the SL16A and the type of
optical interface.
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10 SDH Boards
Board
Feature Code
SSN1SL16A01,
SSN2SL16A01,
SSN3SL16A01
01
I-16
SSN1SL16A02,
SSN2SL16A02,
SSN3SL16A02
02
S-16.1
SSN1SL16A03,
SSN2SL16A03,
SSN3SL16A03
03
L-16.1
SSN1SL16A04,
SSN2SL16A04,
SSN3SL16A04
04
L-16.2
SSN3SL16A06
06
I-16
SSN3SL16A07
07
S-16.1
SSN3SL16A08
08
L-16.1
SSN3SL16A09
09
L-16.2


is correct.
----End
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10 SDH Boards

Disabled.
TUG structure.
NOTE
----End

----End

Boards.
the Current Alarms.
----End

Issue 03 (2013-02-20)

431

J0
J1
J2
C2
10 SDH Boards

Troubleshooting
Table 10-78 lists the faults that occur on the SL16A frequently and the troubleshooting methods.
NOTE
The SL16A uses the SFP optical module. When the SL16A operates and an abnormal alarm occurs on the
optical interface, check whether the optical module is properly installed. To check whether the optical
module is properly installed, you can re-seat the optical module.
Table 10-78 Methods used to troubleshoot the faults that occur on the SL16A frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
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10 SDH Boards
Fault Symptom
Common Fault
Cause
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SL16A, see Replacing an SDH Board.

This topic lists the alarms that may occur when the board operates.
10.16.12.1 Alarms of N1SL16A
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC

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10 SDH Boards
BIP_SD
CHIP_FAIL
C2_PDI
C2_VCAIS
FSELECT_STG
COMMUN_FAIL
FPGA_ABN
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LASER_MOD_ERR
IN_PWR_ABN
J0_MM
LP_RDI_VC12
LASER_SHUT
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LSR_WILL_DIE
LSR_COOL_ALM
LSR_NO_FITED
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
R_LOF
POWER_ABNORMAL
OUT_PWR_ABN
SLAVE_WORKING
R_LOS
R_LOC
TEM_HA
SPARE_PATH_ALM
R_OOF
TF
TEM_LA
T_LOSEX
TU_AIS_VC3
TR_LOC
TEST_STATUS
W_R_FAIL
TU_LOP_VC12
TU_AIS_VC12
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
TU_LOP_VC3
MOD_TYPE_MISMATCH
PS
PATCH_ERR
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL
Issue 03 (2013-02-20)
ALM_ALS
ALM_AU3AIS
ALM_AU3B3OVER
ALM_AU3B3SD
ALM_AU3LOP
ALM_AU3RDI
ALM_AU3REI
ALM_AU3SLM
ALM_AU3TIM
ALM_AU3UNEQ
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC

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10 SDH Boards
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_FAIL
C2_PDI
C2_VCAIS
FSELECT_STG
COMMUN_FAIL
FPGA_ABN
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LASER_MOD_ERR
IN_PWR_ABN
J0_MM
LP_RDI_VC12
LASER_SHUT
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LSR_WILL_DIE
LSR_COOL_ALM
LSR_NO_FITED
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
R_LOF
POWER_ABNORMAL
OUT_PWR_ABN
SLAVE_WORKING
R_LOS
R_LOC
TC_DEG
SPARE_PATH_ALM
R_OOF
TC_LTC
TC_EXC
T_LOSEX
TC_RDI
TC_ODI
TC_INCAIS
TC_UNEQ
TC_REI
TC_OEI
TEST_STATUS
TEM_HA
TC_TIM
TU_AIS_VC12
TF
TEM_LA
TU_LOP_VC3
TU_AIS_VC3
TR_LOC
PATCH_ERR
W_R_FAIL
TU_LOP_VC12
SWDL_PKG_NOBDSOFT
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
MOD_TYPE_MISMATCH
PS
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

ALM_ALS
Issue 03 (2013-02-20)
ALM_AU3AIS

ALM_AU3B3OVER
435

Issue 03 (2013-02-20)
10 SDH Boards
ALM_AU3B3SD
ALM_AU3LOP
ALM_AU3RDI
ALM_AU3REI
ALM_AU3SLM
ALM_AU3TIM
ALM_AU3UNEQ
AU_LOP
AU_AIS
AU_CMM
B2_EXC
B1_EXC
B1_SD
B3_EXC_VC3
B2_SD
B3_EXC
BD_STATUS
B3_SD
B3_SD_VC3
BIP_SD
BIP8_ECC
BIP_EXC
C2_VCAIS
CHIP_ABN
C2_PDI
COMMUN_FAIL
FPGA_ABN
CHIP_FAIL
HP_LOM
HP_RDI
FSELECT_STG
HP_SLM
HP_TIM
HP_REI
IN_PWR_ABN
J0_MM
HP_UNEQ
LASER_SHUT
LOOP_ALM
LASER_MOD_ERR
LP_RDI_VC3
LP_REI_VC12
LP_RDI_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_REI_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LP_TIM_VC12
LSR_COOL_ALM
LSR_NO_FITED
LP_UNEQ_VC3
MS_AIS
MS_RDI
LSR_WILL_DIE
NO_BD_SOFT
OH_LOOP
MS_REI
R_LOS
POWER_ABNORMAL
OUT_PWR_ABN
SPARE_PATH_ALM
R_LOC
R_LOF
TC_EXC
T_LOSEX
SLAVE_WORKING
TC_ODI
TC_INCAIS
TC_DEG
TC_REI
TC_OEI
TC_LTC
TEM_HA
TC_TIM
TC_RDI
TEST_STATUS
TEM_LA
TC_UNEQ
TU_AIS_VC12
TF
TEMP_OVER
TU_LOP_VC3
TU_AIS_VC3
TR_LOC
PATCH_NOT_CONFIRM
W_R_FAIL
TU_LOP_VC12
SWDL_PKG_NOBDSOFT
PATCHFILE_NOTEXIST
PATCH_ERR
TIME_NOT_SUPPORT
PS

436

WRG_BD_TYPE
IN_PWR_HIGH
10 SDH Boards
IN_PWR_LOW
DCN_FAIL

This topic lists the performance events that may occur when the board operates.
10.16.13.1 Performance Events of N1SL16A

AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES

437

10 SDH Boards
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

438

10 SDH Boards


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
2488320 kbit/s
Line code
type
NRZ
Application
code
I-16
S-16.1
L-16.1
L-16.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode LC
Single-mode LC
Operating
wavelength
range (nm)
1266 to 1360
1260 to 1360
1280 to 1335
1500 to 1580
Launched
optical power
range (dBm)
-10 to -3
-5 to 0
-2 to +3
-2 to +3
Receiver
sensitivity
(dBm)
-18
-18
-27
-28
Minimum
overload
(dBm)
-3
-9
-9
Dispersion
tolerance (ps/
nm)
12
1600
Minimum
extinction
ratio (dB)
8.2
8.2
8.2
8.2
Maximum -20
dB spectral
width (nm)

439

Parameter
Value
Minimum
side mode
suppression
ratio (dB)
10 SDH Boards
30
30
30
Table 10-80 and Table 10-81 list the parameters specified for the colored optical interfaces of
the N3SL16A.
Table 10-80 CWDM parameters specified for the colored optical interfaces of the N3SL16A
Parameter
Value
CWDM
Nominal bit rate
2488320 kbit/s
Type of fiber
Single-mode LC
80

(dBm)
0 to 5
1471 to 1611, in steps of 20
-28
-9

nm)
1600
8.2

(nm)

ratio (dB)
30
Table 10-81 DWDM parameters specified for the colored optical interfaces of the N3SL16A
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
2488320 kbit/s
Type of fiber
Single-mode LC
120

440

Parameter
10 SDH Boards
Value
DWDM

(dBm)
-1 to 3
192.10 to 196.00

(GHz)
10
-28
-9

(ps/nm)
2400
8.2

width (nm)
0.3
Minimum side mode

30
Laser Safety Class

l
Weight of the N1SL16A (kg): 0.6
Power Consumption
The maximum power consumption of the N1SL16A at room temperature (25C) is 20 W.
Issue 03 (2013-02-20)

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10 SDH Boards
10.17 SLD16

The SLD16 is available in one functional version, namely, N1. The N1SLD16 is discontinued.
10.17.2 Application
The SLD16 is a line board. The SLD16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLD16 converts the received optical signals
SLD16 converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLD16 receives and transmits 2xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 10-82 provides the functions and features of the SLD16.
Issue 03 (2013-02-20)

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10 SDH Boards

Function and
Feature
SLD16
Basic functions
Specifications
of the optical
interface

I-16, S-16.1, L-16.1, and L-16.2. The characteristics of the optical
interfaces comply with ITU-T G.957 and ITU-T G.692.
l Supports the output of the standard wavelengths that comply with ITUT G.692.
Specifications
of the optical
module
module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c

concatenation services, VC-4-8c concatenation services, and VC-4-16c
Overhead
processing

overheads.
l Supports the time synchronization feature and transmission of the time
information by using the section overhead bytes.
Alarms and
performance
events

Specifications
of the REG
Does not support the REG.
Protection
schemes

l Supports the fiber-shared MSP and processes four sets of K bytes. A
single optical interface can process two sets of K bytes. One SLD16
supports a maximum of four MSP rings.
Issue 03 (2013-02-20)

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10 SDH Boards
Function and
Feature
SLD16
Maintenance
features

services.

The SLD16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 10-58 shows the functional block diagram of the SLD16 by describing how to process
1xSTM-16 signals.
155 MHz
O/E

E/O
Gbit/s
Mbit/s
2.488
Gbit/s
O/E
. .
. .
2.488
Gbit/s
E/O
SPI
2.488
Gbit/s
MUX
16x155
Mbit/s
Backplane
Reference clock
Cross-connect
unit
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
O/E
converting
module
155 MHz
PLL
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
Issue 03 (2013-02-20)

444

10 SDH Boards

l
MUX/DEMUX Module
l

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
Issue 03 (2013-02-20)

445

10 SDH Boards

l
Controls the laser.
units.
Power Module
require.
10.17.5 Front Panel


Issue 03 (2013-02-20)

446

10 SDH Boards
SLD16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
SLD16
Indicators
l
Interfaces
Issue 03 (2013-02-20)

447

10 SDH Boards

Interface
Type of Interface
Usage
IN1IN2
LC
OUT1OUT2
LC

The SLD16 does not have any jumpers or DIP switches that are used for board settings.
10.17.7 Valid Slots

The SLD16 must be installed in a valid slot in the subrack. Otherwise, the SLD16 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLD16 vary with the cross-connect capacity of the subrack. The slots
valid for the SLD16 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SLD16 can be installed in slots 7, 8, 11,
and 12.

Table 10-84 provides the relationship between the feature code of the SLD16 and the type of
optical interface.
Table 10-84 Relationship between the feature code of the SLD16 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLD1600
00
SSN1SLD1601
01
I-16
SSN1SLD1602
02
S-16.1
SSN1SLD1603
03
L-16.1
SSN1SLD1604
04
L-16.2

448

10 SDH Boards


is correct.
----End

Disabled.
TUG structure.
NOTE
----End

Issue 03 (2013-02-20)

449

10 SDH Boards
----End

Boards.
the Current Alarms.
----End

l
J0
J1
J2
C2

Troubleshooting
Table 10-85 lists the faults that occur on the SLD16 frequently and the troubleshooting methods.
NOTE
The SLD16 uses the SFP optical module. When the SLD16 operates and an abnormal alarm occurs on the
Issue 03 (2013-02-20)

450

10 SDH Boards
Table 10-85 Methods used to troubleshoot the faults that occur on the SLD16 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
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10 SDH Boards
Fault Symptom
Common Fault
Cause
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLD16, see Replacing an SDH Board.

10.17.12.1 Alarms of N1SLD16
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_ABN
C2_PDI
C2_VCAIS
FSELECT_STG
CHIP_FAIL
COMMUN_FAIL
HP_RDI
FPGA_ABN
HP_LOM
HP_TIM
HP_REI
HP_SLM
J0_MM
HP_UNEQ
IN_PWR_ABN
LOOP_ALM
LASER_MOD_ERR
LASER_SHUT
LP_REI_VC12
LP_RDI_VC12
LP_RDI_VC3
LP_SLM_VC3
LP_REI_VC3
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_NO_FITED
LP_UNEQ_VC3
LSR_COOL_ALM
MS_RDI
LSR_WILL_DIE
MS_AIS
R_LOF
MS_REI

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10 SDH Boards
NO_BD_SOFT
SPARE_PATH_ALM
OH_LOOP
OUT_PWR_ABN
TEM_LA
POWER_ABNORMAL
R_LOC
TF
R_LOS
SLAVE_WORKING
TU_AIS_VC3
T_LOSEX
TEM_HA
W_R_FAIL
TEMP_OVER
TEST_STATUS
PATCH_NOT_CONFIRM
TR_LOC
TU_AIS_VC12
TIME_NOT_SUPPORT
TU_LOP_VC12
TU_LOP_VC3
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
PATCH_ERR
PS
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

10.17.13.1 Performance Events of N1SLD16
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

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Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
2488320 kbit/s
Line code
type
NRZ
Application
code
I-16
S-16.1
L-16.1
L-16.2
Transmissio
n distance
(km)
0 to 2
2 to 15
15 to 40
40 to 80
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC
Single-mode LC
Operating
wavelength
range (nm)
1266 to 1360
1260 to 1360
1280 to 1335
1500 to 1580
Launched
optical
power range
(dBm)
-10 to -3
-5 to 0
-2 to +3
-2 to +3
Receiver
sensitivity
(dBm)
-18
-18
-27
-28
Minimum
overload
(dBm)
-3
-9
-9
Dispersion
tolerance
(ps/nm)
12
1600
Minimum
extinction
ratio (dB)
8.2
8.2
8.2
8.2

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10 SDH Boards
Parameter
Value
Maximum
-20 dB
spectral
width (nm)
Minimum
side mode
suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the SLD16 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the SLD16 at room temperature (25C) is 23 W.
10.18 SLQ16
technical specifications of the SLQ16 (4xSTM-16 optical interface board). This topic also

The N2SLQ16 is discontinued.
Issue 03 (2013-02-20)
Item
Description
Functional Versions
The SLQ16 is available in two functional versions, namely, N1 and

N2.

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10 SDH Boards
Item
Description
Differences

function.
Substitution
When the AU-3 services and TCM function are not required, the
N1SLQ16 and N2SLQ16 can be substituted with each other.
NOTE
10.18.2 Application
The SLQ16 is a line board. The SLQ16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLQ16 converts the received optical signals
SLQ16 converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLQ16 receives and transmits 4xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 10-88 describes the functions and features of the SLQ16.
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10 SDH Boards

Function and
Feature
SLQ16
Basic functions
Specifications of

S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.
Specifications of
the optical module

optical module.
Service processing
l Supports the VC-12 services, VC-3 services, VC-4 services,

VC-4-4c concatenation services, VC-4-8c concatenation services,
and VC-4-16c concatenation services.
Overhead
processing
l Supports the configuration of the D1-D12, E1, and E2 bytes as

transparent transmission bytes or into other unused overheads bytes.
overheads.
Alarms and
performance events

Specifications of
the REG
Protection schemes

l Supports the fiber-shared MSP and processes eight sets of K bytes.
A single optical interface can process two sets of K bytes. One
SLQ16 supports a maximum of eight MSP rings.
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Function and
Feature
SLQ16
Maintenance
features

l The N1SLQ16 supports inloops and outloops on VC-4 paths.
services.
services.

The SLQ16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
Figure 10-61 shows the functional block diagram of the SLQ16 by describing how to process
1xSTM-16 signals.
155 MHz
2.488
Gbit/s
O/E

E/O
Gbit/s
Mbit/s
. .
. .
2.488
Gbit/s
O/E
E/O
SPI
2.488
Gbit/s
MUX
16x155
Mbit/s
Backplane
Reference clock
Cross-connect
unit
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
O/E
converting
module
155 MHz
PLL
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
Issue 03 (2013-02-20)

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10 SDH Boards

l
MUX/DEMUX Module
l

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
Issue 03 (2013-02-20)

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10 SDH Boards

l
Controls the laser.
units.
Power Module
require.
10.18.5 Front Panel


Figure 10-62 shows the appearance of the front panel of the N1SLQ16.
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10 SDH Boards
Figure 10-62 Front panel of the N1SLQ16
SLQ16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
SLQ16
Figure 10-63 shows the appearance of the front panel of the N2SLQ16.
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10 SDH Boards
Figure 10-63 Front panel of the N2SLQ16
SLQ16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
SLQ16
Indicators
l
Interfaces
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10 SDH Boards

Interface
Type of Interface
Usage
IN1-IN4
LC
OUT1-OUT4
LC

The SLQ16 does not have any jumpers or DIP switches that are used for board settings.
10.18.7 Valid Slots

The SLQ16 must be installed in a valid slot in the subrack. Otherwise, the SLQ16 fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLQ16 are as follows:

l
When the cross-connect capacity is 200 Gbit/s,

The SLQ16 can be installed in slots 14, 15, and 16. In this case, two optical interfaces
can be configured.
The SLQ16 can be installed in slots 58 and 1114. In this case, four optical interfaces
can be configured.

Table 10-90 describes the relationship between the feature code of the SLQ16 and the type of
optical interface.
Issue 03 (2013-02-20)
Board
Feature
Code
Type of Optical
Interface
SSN1SLQ1601, SSN2SLQ1601
01
I-16
02
S-16.1
03
L-16.1
04
L-16.2

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10 SDH Boards
Board
Feature
Code
Type of Optical
Interface
SSN1SLQ16A10
10
I-16
SSN1SLQ16A11
11
S-16.1
SSN1SLQ16A12
12
L-16.1
SSN1SLQ16A13
13
L-16.2


is correct.
----End

Disabled.
TUG structure.
Issue 03 (2013-02-20)

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10 SDH Boards
NOTE
----End

----End

Boards.
the Current Alarms.
----End

l
J0
J1
J2
C2

Troubleshooting
Table 10-91 lists the faults that occur on the SLQ16 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

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NOTE
The SLQ16 uses the SFP optical module. When the SLQ16 operates and an abnormal alarm occurs on the
Table 10-91 Methods used to troubleshoot the faults that occur on the SLQ16 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
Issue 03 (2013-02-20)

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Fault Symptom
Common Fault
Cause
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLQ16, see Replacing an SDH Board.

10.18.12.1 Alarms of N1SLQ16
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_ABN
C2_PDI
C2_VCAIS
FSELECT_STG
CHIP_FAIL
COMMUN_FAIL
HP_RDI
HP_REI
HP_LOM
HP_TIM
HP_UNEQ

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10 SDH Boards
HP_SLM
J0_MM
LASER_MOD_ERR
IN_PWR_ABN
LOOP_ALM
LP_RDI_VC12
LASER_SHUT
LP_REI_VC12
LP_REI_VC3
LP_RDI_VC3
LP_SLM_VC3
LP_TIM_VC12
LP_SLM_VC12
LP_UNEQ_VC12
LP_UNEQ_VC3
LP_TIM_VC3
LSR_NO_FITED
LSR_WILL_DIE
LSR_COOL_ALM
MS_RDI
MS_REI
MS_AIS
PATCH_NOT_CONFIRM
OH_LOOP
NO_BD_SOFT
R_LOF
POWER_ABNORMAL
PATCH_ERR
SLAVE_WORKING
PATCHFILE_NOTEXIST
OUT_PWR_ABN
TEM_HA
R_LOS
R_LOC
TEST_STATUS
R_OOF
T_LOSEX
TU_AIS_VC12
SPARE_PATH_ALM
TEM_LA
TU_LOP_VC3
TF
TEMP_OVER
TIME_NOT_SUPPORT
TU_AIS_VC3
TR_LOC
W_R_FAIL
TU_LOP_VC12
PS
SWDL_PKG_NOBDSOFT
MOD_TYPE_MISMATCH
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

10.18.13.1 Performance Events of N1SLQ16
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES

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10 SDH Boards
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
2488320 kbit/s
Line code type
NRZ
Application code
I-16
S-16.1
L-16.1
L-16.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode LC
Single-mode
LC
Operating
wavelength range
(nm)
1266 to 1360
1260 to 1360 1280 to 1335
1500 to 1580
Launched optical
power range (dBm)
-10 to -3
-5 to 0
-2 to +3
-2 to +3
(dBm)
-18
-18
-27
-28

469

10 SDH Boards
Parameter
Value
Minimum overload
(dBm)
-3
-9
-9
Dispersion tolerance
(ps/nm)
12
1600
Minimum extinction
ratio (dB)
8.2
8.2
8.2
8.2
Maximum -20 dB
spectral width (nm)
Minimum side mode

30
30
30
Laser Safety Class

l
Weight of the N1SLQ16 (kg): 0.9
Weight of the N2SLQ16 (kg): 1.3
Power Consumption
10.19 SLO16
technical specifications of the SLO16 (8xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLO16.

The SLO16 is available in the following functional versions: N1.
10.19.2 Application
The SLO16 is a line board. The SLO16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLO16 converts the received optical signals
Issue 03 (2013-02-20)

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10 SDH Boards
SLO16 converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLO16 receives and transmits 8xSTM-16 optical signals, processes overhead bytes, and
performs the MSP protection.
Table 10-93 provides the functions and features of the SLO16.
Table 10-93 Functions and features of the SLO16
Function and
Feature
SLO16
Basic functions
Specifications of

S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.
Specifications of
the optical module

optical module.
Issue 03 (2013-02-20)

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10 SDH Boards
Function and
Feature
SLO16
Service processing

Overhead
processing

l Supports the configuration of the D1D12, E1, and E2 bytes as
transparent transmission bytes or into other unused overheads bytes.
overheads.
l Supports one to eight channels of ECC communication.
Alarms and
performance events

Specifications of
the REG
Protection schemes

l Supports SNCP.
l Supports SNCMP.
l Supports SNCTP.
l Supports the fiber-shared MSP and processes 16 sets of K bytes. A
single optical interface can process two sets of K bytes. One SLO16
supports a maximum of 16 MSP rings.
Maintenance
features

services.
services.

The SLO16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
Issue 03 (2013-02-20)

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10 SDH Boards
Figure 10-65 shows the functional block diagram of the SLO16 by describing how to process
1xSTM-16 signals.
Figure 10-65 Functional block diagram of the SLO16
155 MHz
2.488
Gbit/s
O/E

E/O
Gbit/s
Mbit/s
. .
. .
2.488
Gbit/s
O/E
E/O
SPI
2.488
Gbit/s
MUX
16x155
Mbit/s
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
O/E
converting
module
155 MHz
PLL
Backplane
Reference clock
Cross-connect
unit
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination

l
MUX/DEMUX Module
l

l
RST sub-module
Issue 03 (2013-02-20)

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10 SDH Boards
l
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
Issue 03 (2013-02-20)

474

10 SDH Boards
10.19.5 Front Panel

The front panel of the SLO16 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-66 shows the appearance of the front panel of the SLO16.
Figure 10-66 Front panel of the SLO16
SLO16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
TX1
RX1
TX2
RX2
TX3
RX3
TX4
RX4
TX5
RX5
TX6
RX6
TX7
RX7
TX8
RX8
SLO16
Indicators
l
Issue 03 (2013-02-20)

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10 SDH Boards
Interfaces
The front panel of the SLO16 has eight optical interfaces. Table 10-94 describes the types and
usage of the optical interfaces of the SLO16.
Table 10-94 Optical interfaces of the SLO16
Interface
Type of Interface
Usage
RX1RX8
LC
TX1TX8
LC

The SLO16 does not have any jumpers or DIP switches that are used for board settings.
10.19.7 Valid Slots

The SLO16 must be installed in a valid slot in the subrack. Otherwise, the SLO16 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLO16 vary with the cross-connect capacity of the subrack. The slots
valid for the SLO16 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SLO16 can be installed in slots 7, 8, 11,

The feature code of the SLO16 indicates the type of optical interface.
Table 10-95 provides the relationship between the feature code of the SLO16 and the type of
optical interface.
Table 10-95 Relationship between the feature code of the SLO16 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SLO1610
10
I-16

476

10 SDH Boards
Board
Feature Code
SSN1SLO1611
11
S-16.1
SSN1SLO1612
12
L-16.1
SSN1SLO1613
13
L-16.2


is correct.
----End

Disabled.
TUG structure.
NOTE
Issue 03 (2013-02-20)

477

10 SDH Boards
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SLO16 by using the U2000.
You can set the following parameters for the SLO16 by using the U2000:
l
J0
J1
J2
C2

Troubleshooting
Table 10-96 lists the faults that occur on the SLO16 frequently and the troubleshooting methods.
NOTE
The SLO16 uses the SFP optical module. When the SLO16 operates and an abnormal alarm occurs on the
Issue 03 (2013-02-20)

478

10 SDH Boards
Table 10-96 Methods used to troubleshoot the faults that occur on the SLO16 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Issue 03 (2013-02-20)

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10 SDH Boards
Fault Symptom
Common Fault
Cause
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLO16, see Replacing an SDH Board.

10.19.12.1 Alarms of N1SLO16
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
C2_PDI
BIP_EXC
BIP_SD
COMMUN_FAIL
C2_VCAIS
CHIP_ABN
HP_RDI
FSELECT_STG
HP_LOM
HP_TIM
HP_REI
HP_SLM
J0_MM
HP_UNEQ
IN_PWR_ABN
LOOP_ALM
LASER_MOD_ERR
LASER_SHUT
LP_REI_VC12
LP_RDI_VC12
LP_RDI_VC3
LP_SLM_VC3
LP_REI_VC3
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_NO_FITED
LP_UNEQ_VC3
LSR_COOL_ALM
MS_RDI
LSR_WILL_DIE
MS_AIS
PATCH_ERR
MS_REI
NO_BD_SOFT
R_LOC
OH_LOOP
OUT_PWR_ABN

480

10 SDH Boards
SLAVE_WORKING
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
PS
POWER_ABNORMAL
R_LOF
R_LOS
T_LOSEX
TEM_HA
TEST_STATUS
TEM_LA
TEMP_OVER
TU_AIS_VC12
TF
TR_LOC
TU_LOP_VC3
R_OOF
DCN_FAIL
BIP8_ECC
TU_AIS_VC3
TU_LOP_VC12
LSR_INVALID
SWDL_PKG_NOBDSOFT
MOD_TYPE_MISMATCH
AU_CMM
CHIP_FAIL
SPARE_PATH_ALM
W_R_FAIL
IN_PWR_HIGH
IN_PWR_LOW
WRG_BD_TYPE

10.19.13.1 Performance Events of N1SLO16
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS

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10 SDH Boards
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

The technical specifications of the SLO16 include the parameters specified for optical interfaces,

Table 10-97 lists the parameters specified for the optical interfaces of the SLO16.
Table 10-97 Parameters specified for the optical interfaces of the SLO16
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
2488320 kbit/s
Line code pattern
NRZ
Application code
I-16
S-16.1
L-16.1
L-16.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode LC
Single-mode
LC
Operating
wavelength range
(nm)
1266 to 1360
1260 to 1360 1280 to 1335
1500 to 1580
Launched optical
power range (dBm)
-10 to -3
-5 to 0
-2 to +3
-2 to +3
(dBm)
-18
-18
-27
-28
Minimum overload
(dBm)
-3
-9
-9
(ps/nm)
12
1600
Minimum extinction
ratio (dB)
8.2
8.2
8.2
8.2
Maximum -20 dB
spectral width (nm)

482

Parameter
Value
Minimum side mode

10 SDH Boards
30
30
30
Laser Safety Class

The mechanical specifications of the SLO16 are as follows:
l
Weight (kg): 1.0
Power Consumption
10.20 SF16
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).

The SF16 is available in one functional version, namely, N1.
10.20.2 Application
The SF16 is a line board. The SF16 can be used on the OptiX OSN equipment series to transmit
and receive STM-16 optical signals. The SF16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF16
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NE1
NE2
NE4
NE3
Service flow
Line board

The SF16 receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the FEC function)
and processes overhead bytes.
Table 10-98 provides the functions and features of the SF16.
Table 10-98 Functions and features of the SF16
Function and
Feature
SF16
Basic functions
l Receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the
FEC function).
l Supports the enabling or disabling of the FEC function.
Specifications
of the optical
interface

Ue-16.2c, Ue-16.2d, and Ue-16.2f. The characteristics of the optical
interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with ITUT G.692 and can be directly connected to the DWDM equipment.
l Supports the DWDM colored optical interfaces. The optical interface
uses the LC connector. The DWDM optical interface supports the
transmission distance of 640 km.
Specifications
of the optical
module
module.
l Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.
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Function and
Feature
SF16
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c

l Encapsulates and encodes the signals with the FEC function, and
processes overhead bytes, which comply with ITU-T G.709.
Overhead
processing
l Supports the processing of the OTU, ODU, and OPU overhead bytes,
performance monitoring, and alarm detection, which comply with ITUT G.709.
overheads.
Alarms and
performance
events
l Reports various alarms and performance events.
Specifications
of the REG
Protection
schemes
l Supports the alarms and performance events that are related to the OTU
layer, ODU layer, OPU layer, and FEC function.
l Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SF16 supports a maximum of two MSP protection rings.
Maintenance
features

services.

The SF16 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, and power module.
Figure 10-68 shows the functional block diagram of the SF16.
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Figure 10-68 Functional block diagram of the SF16

155 MHz PLL
2.666
Gbit/s
2.666
Gbit/s
2.666
Gbit/s
O/E
S
P
I
DEMUX
16x166
Mbit/s
Reference clock
155 MHz PLL
K1 and K2 insertion/
extraction
16x155
Mbit/s
K1 and K2
High-speed
bus
FEC
2.666
Gbit/s
E/O
16x166
Mbit/s
155 MHz
16x155
Mbit/s
RST
MST
MSA
HPT
High-speed
bus
MUX
DCC
SDH overhead processing
module
166 MHz PLL
Frame header
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
DC/DC
converter
Communication
Fuse
DC/DC
converter
Cross-connect
unit
Cross-connect
unit
Cross-connect
unit
Cross-connect
unit
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup
power

termination
The functional modules are described as follows:

l
MUX/DEMUX Module
l
In the upstream direction, the reverse process is performed. The FEC encoding and
decoding module receives the 2.666 Gbit/s signals from the DEMUX module. After frame
searching, FEC encoding, data packets encapsulation, and scrambling in the FEC module,
the 2.488 Gbit/s signals are recovered and then transmitted to the SDH overhead processing
module. The frame format of the 2.666 Gbit/s signals complies with ITU G.709.
In the downstream direction, the FEC encoding and decoding module receives 2.488 Gbit/
s SDH signals, which are sent by the SDH overhead processing module. After frame
FEC Module
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10 SDH Boards
searching, FEC encoding, data packet encapsulation, and scrambling, the 2.488 Gbit/s SDH
signals are converted into 2.666 Gbit/s signals and then transmitted to the MUX module.
l
The FEC processing module is connected to the logic and control module through a CPU
bus. The CPU controls the working modes of the FEC module by configuring the internal
register. The working mode can be the regenerator mode, namely, REG mode. The CPU
can monitor the performance through the internal register.

l
RST sub-module
byte.
MST sub-module
writes the B2 byte.
MSA sub-module
justifications.
HPT sub-module

l
Controls the laser.
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10 SDH Boards
units.
Power Module
require.
10.20.5 Front Panel

The front panel of the SF16 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-69 shows the appearance of the front panel of the SF16.
Figure 10-69 Front panel of the SF16
SF16
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
SF16
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10 SDH Boards
Indicators
l
Interfaces
The front panel of the SF16 has one optical interface. Table 10-99 describes the types and usage
of the optical interfaces of the SF16.
NOTE
The SF16 uses the unswappable optical module.
Table 10-99 Optical interfaces of the SF16

Interface
Type of
Interface
Usage
IN
LC
OUT
LC
10.20.6 Valid Slots

The slots valid for the SF16 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SF16 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SF16 can be installed in slots 58 and
1114.

The feature code of the SF16 indicates the type of optical interface.
Table 10-100 provides the relationship between the feature code of the SF16 and the type of
optical interface.
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Table 10-100 Relationship between the feature code of the SF16 and the type of optical interface
Board
Feature Code
SSN1SF1600
00
Colored optical interface
SSN1SF1601
01
Ue-16.2c/Ue-16.2d/Ue-16.2f

You can set the parameters for the SF16 by using the U2000.
You can set the following parameters for the SF16 by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SF16 include the parameters specified for optical interfaces,

Table 10-101 lists the parameters specified for the optical interfaces of the SF16.
Table 10-101 Parameters specified for the optical interfaces of the SF16
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
2666057.143 kbit/s
Processing capability
1xSTM-16 standard services or concatenation services
Line code pattern
NRZ
Application codea
Ue-16.2c
Ue-16.2d
Ue-16.2f
FEC + BA (14) +
PA
FEC + BA (17) +
PA
FEC + BA (17) + RA + PA
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC
Operating
wavelength range
(nm)
1550.12
Launched optical
power range (dBm)b
-5 to -1
-5 to -1
-5 to -1

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10 SDH Boards
Parameter
Value
Launched optical
power range (dBm)c
13 to 15
13 to 15
15 to 18
(dBm)b
-27.5
-27.5
-27.5
(dBm)d
-37
-37
-42
Minimum overload
(dBm)d
-10
-10
-10
Minimum extinction
ratio (dB)b
10
10
10
(ps/nm)
12800
12800
12800
Maximum -20 dB
spectral width (nm)
Minimum side mode

suppression ratio
(dB)
30
30
30
a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14)" indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA + PA
+ RA" indicates that the specifications of the optical interface are measured when the FEC,
BA, PA, and Raman amplifier are used.
b: The parameter values are applicable only to the optical modules. The parameter values of
the amplifier are not provided.
c: The parameter values are applicable to the BA.
d: The parameter values are applicable to the PA.
Table 10-102 lists the parameters specified for the colored optical interfaces of the SF16.
Table 10-102 Parameters specified for the colored optical interfaces of the SF16
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
2666057.143 kbit/s
Type of fiber
Single-mode LC
640
-2 to 2.5
192.1 to 196.0

491

Parameter
10 SDH Boards
Value
DWDM
20
-28
-9
Maximum allowed dispersion (ps/nm)
10880
10
0.1

(dB)
35
With the FEC: 16

Without the FEC: 21
Laser Safety Class

The mechanical specifications of the SF16 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the SF16 at room temperature (25C) is 26 W.
10.21 SL64
technical specifications of the SL64 (1xSTM-64 optical interface board). This topic also
describes how to configure and commission the SL64.

The SL64 is available in several functional versions. The N2SL64 is discontinued. The functions
provided by the functional versions are different.
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Item
Description
Functional versions
The SL64 is available in the following functional versions: N4, N2

and N1.
Differences
l The N1SL64/N4SL64 supports the board version replacement

function, but does not support the TCM function or AU-3 services.
l The N2SL64 does not support the board version replacement
function, but supports the TCM function and AU-3 services, the
TCM function and AU-3 services cannot be available at the same
time.
l The N4SL64 supports pluggable XFP optical modules.
l The N4SL64 detects and reports voltage performance.
l SL64 boards of different versions support different loopback
functions. For details, see 10.21.3 Functions and Features.
Substitution
When the TCM function and AU-3 services are not required, the
N1SL64 can substitute for the N2SL64.
The N4SL64 supports the board version replacement function to
substitute for the N1SL64/N2SL64.
NOTE
l When you configure the MSP or SNCP, you cannot configure the N1SL64 as the protection board if
the working board is the N2SL64 on which the TCM function is enabled or AU-3 services are
configured. Otherwise, the services are interrupted when a switching operation is performed.
10.21.2 Application
and receive STM-64 optical signals. The SL64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL64
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NE1
NE2
NE4
NE3
Service flow
Line board

The SL64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 10-104 describes the functions and features of the SL64.
Issue 03 (2013-02-20)
Function
and Feature
SL64
Basic
functions

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10 SDH Boards
Function
and Feature
SL64
Specifications
of the optical
interface
l The N1SL64/N2SL64 supports different types of standard optical

interfaces, namely, the I-64.1, I-64.2, S-64.2b, L-64.2b (BA), Le-64.2,
Ls-64.2, and V-64.2b (BA + PA + dispersion compensation unit (DCU)).
The characteristics of the optical interfaces of the S-64.2b, L-64.2b,
Ls-64.2, and V-64.2b types comply with ITU-T G.691 and ITU-T G.692.
The characteristics of the optical interface of the Le-64.2 type comply
l The N4SL64 supports different types of standard optical interfaces,
namely, the I-64.1, S-64.2b, Le-64.2, P1L1-2D2, and V-64.2b (BA + PA
+ DCU). The characteristics of the optical interfaces of the I-64.1,
S-64.2b, Le-64.2, and V-64.2b types comply with ITU-T G.691. The
characteristics of the optical interface of the P1L1-2D2 type comply with
ITU-T G.959.
l The N1SL64/N2SL64 supports the DWDM colored optical interfaces,
which use LC connectors. The DWDM optical interface supports the
transmission distance of 40 km.
l The N4SL64 supports the CWDM and DWDM colored optical
interfaces. The optical interface uses the LC connector. The CWDM
optical interface supports the transmission distance of 70 km, and the
DWDM optical interface supports the transmission distance of 40 km and
80 km.
l Supports the output of the standard wavelengths that comply with ITUT G.692 and can be directly connected to the WDM equipment.
Specifications
of the optical
module
module.
l N1SL64/N2SL64 supports fixed optical modules.
l Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.
l The N4SL64 supports the usage and detection of the pluggable XFP
optical module, which facilitates the maintenance and upgrading of the
optical module.
Service
processing

l The N1SL64 and N2SL64 support the VC-4-4c concatenation services,
VC-4-8c concatenation services, Vc-4-16c concatenation services, and
Overhead
processing

overheads.
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Function
and Feature
SL64
Alarms and
performance
events
l Reports various alarms and performance events.
Specifications
of the REG
Supports the setting and query of the REG working mode.
Protection
schemes
10 SDH Boards

l Supports SNCP.
l Supports SNCMP.
l Supports SNCTP.
l Supports the fiber-shared MSP and processes two sets of K bytes. One
SL64 supports a maximum of two MSP rings.
Maintenance
features

l The N1SL64/N4SL64 supports inloops and outloops on VC-4 paths.
services.
l The N4SL64 detects and reports voltage performance.
l The N4SL64 also supports the PRBS function in the line direction.

The SL64 consists of the O/E converting module, MUX/DEMUX Module, SDH overhead
Figure 10-71 shows the functional block diagram of the N1SL64/N2SL64/N4SL64.
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Figure 10-71 Functional block diagram of the N1SL64/N2SL64/N4SL64

622 MHz
9.953
Gbit/s
9.953
Gbit/s
O/E
DEMUX 16x622
Mbit/s
SPI
9.953
Gbit/s
9.953
Gbit/s
E/O
O/E
converting
module
MUX
16x622
Mbit/s
MUX/
DEMUX
622 MHz
PLL
Backplane
Reference clock
Cross-connect
unit
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
Frame header
Logic and
Communication
control module
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination

l
MUX/DEMUX Module
l

l
RST sub-module
byte.
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l
MST sub-module
writes the B2 byte.
MSA sub-module
justifications.
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.21.5 Front Panel

The front panel of the SL64 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
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Figure 10-72 shows the appearance of the front panel of the .
Figure 10-72 Appearance of the front panel of the SL64
SL64
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
APD
Receiver
MAX:-9dBm
OUT
IN
SL64
Figure 10-73 shows the appearance of the N4SL64.
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Figure 10-73 Appearance of the front panel of the N4SL64
SL64
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
SL64
Indicators
l
Interfaces
The front panel of the SL64 has one optical interface. Table 10-105 describes the types and
usage of the optical interfaces of the SL64.
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Interface
Type of Interface
Usage
IN
LC
OUT
LC

The SL64 does not have any jumpers or DIP switches that are used for board settings.
10.21.7 Valid Slots

The SL64 must be installed in a valid slot in the subrack. Otherwise, the SL64 fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SL64 vary with the cross-connect capacity of the subrack. The slots valid
for the SL64 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the N1SL64 can be installed in slots 7, 8,
11, and 12; the N4SL64 can be installed in slots 5-8 and 11-14.

Table 10-106 describes the relationship between the feature code of the SL64 and the type of
optical interface.
Issue 03 (2013-02-20)
Board
Feature Code
SSN1SL6400
00
Fixed-wavelength optical
interface
SSN4SL6401M01
01M01
interface
SSN1SL6401
01
I-64.2
SSN1SL6402, SSN4SL6402
02
S-64.2b
SSN1SL6403
03
Le-64.2

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10 SDH Boards
Board
Feature Code
SSN1SL6404
04
Ls-64.2
SSN1SL6405
05
L-64.2b
SSN1SL6406
06
V-64.2b
SSN2SL6400
00
interface
SSN2SL6411
11
I-64.2
SSN2SL6412
12
S-64.2b
SSN2SL6413
13
Le-64.2
SSN2SL6404
04
Ls-64.2
SSN2SL6415
15
L-64.2b
SSN2SL6416
16
V-64.2b
SSN4SL6401
01
I-64.1
SSN4SL6403
03
P1L1-2D2
SSN4SL6404
04
V-64.2b
SSN4SL6405
05
Le-64.2


is correct.
----End
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10 SDH Boards

Disabled.
TUG structure.
NOTE
----End

----End

Boards.
the Current Alarms.
----End

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503

J0
J1
J2
C2
10 SDH Boards

Troubleshooting
Table 10-107 lists the faults that occur on the SL64 frequently and the troubleshooting methods.
Table 10-107 Methods used to troubleshoot the faults that occur on the SL64 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
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Fault Symptom
Common Fault
Cause
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SL64, see Replacing an SDH Board.

Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC

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10 SDH Boards
BIP_SD
CHIP_ABN
C2_PDI
C2_VCAIS
FPGA_ABN
CHIP_FAIL
COMMUN_FAIL
HP_RDI
FSELECT_STG
HP_LOM
HP_TIM
HP_REI
HP_SLM
J0_MM
HP_UNEQ
IN_PWR_ABN
LOOP_ALM
LASER_MOD_ERR
LASER_SHUT
LP_REI_VC12
LP_RDI_VC12
LP_RDI_VC3
LP_SLM_VC3
LP_REI_VC3
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_NO_FITED
LP_UNEQ_VC3
LSR_COOL_ALM
MS_RDI
LSR_WILL_DIE
MS_AIS
R_LOF
MS_REI
NO_BD_SOFT
SLAVE_WORKING
OH_LOOP
OUT_PWR_ABN
TC_DEG
POWER_ABNORMAL
R_LOC
TC_LTC
R_LOS
R_OOF
TC_RDI
SPARE_PATH_ALM
T_LOSEX
TC_UNEQ
TC_EXC
TC_INCAIS
TEMP_OVER
TC_ODI
TC_OEI
TR_LOC
TC_REI
TC_TIM
TU_LOP_VC12
TEM_HA
TEM_LA
PATCHFILE_NOTEXIST
TEST_STATUS
TF
PS
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC3
PATCH_NOT_CONFIRM
W_R_FAIL
PATCH_ERR
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL
MOD_TYPE_MISMATCH
Issue 03 (2013-02-20)
ALM_ALS
ALM_AU3AIS
ALM_AU3B3OVER
ALM_AU3B3SD
ALM_AU3LOP
ALM_AU3RDI

506

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10 SDH Boards
ALM_AU3REI
ALM_AU3SLM
ALM_AU3TIM
ALM_AU3UNEQ
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
DID_ERROR
BIP_EXC
BIP_SD
BIP8_ECC
C2_PDI
C2_VCAIS
CHIP_FAIL
COMMUN_FAIL
FPGA_ABN
FSELECT_STG
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
J0_MM
LASER_MOD_ERR
LASER_SHUT
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LSR_COOL_ALM
LSR_NO_FITED
LSR_WILL_DIE
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
R_LOF
OH_LOOP
OUT_PWR_ABN
SLAVE_WORKING
POWER_ABNORMAL
R_LOC
TC_DEG
R_LOS
R_OOF
TC_LTC
SPARE_PATH_ALM
T_LOSEX
TC_RDI
TC_EXC
TC_INCAIS
TC_UNEQ
TC_ODI
TC_OEI
TEST_STATUS
TC_REI
TC_TIM
TU_AIS_VC12
TEM_HA
TEM_LA
TU_LOP_VC3
TF
TR_LOC
PATCH_ERR
TU_AIS_VC3
TU_LOP_VC12
SWDL_PKG_NOBDSOFT
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_NOT_CONFIRM
PS
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

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10 SDH Boards
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_ABN
C2_PDI
C2_VCAIS
FPGA_ABN
CHIP_FAIL
COMMUN_FAIL
HP_RDI
FSELECT_STG
HP_LOM
HP_TIM
HP_REI
HP_SLM
J0_MM
HP_UNEQ
IN_PWR_ABN
LOOP_ALM
LASER_MOD_ERR
LASER_SHUT
LP_REI_VC12
LP_RDI_VC12
LP_RDI_VC3
LP_SLM_VC3
LP_REI_VC3
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_INVALID
LP_UNEQ_VC3
LSR_COOL_ALM
MOD_TYPE_MISMATCH
LSR_NO_FITED
LSR_WILL_DIE
MS_REI
MS_AIS
MS_RDI
OH_LOOP
NO_BD_SOFT
PATCH_ERR
PATCH_NOT_CONFIRM
OUT_PWR_ABN
R_LOC
POWER_ABNORMAL
PATCHFILE_NOTEXIST
R_OOF
R_LOF
PS
T_LOSEX
SLAVE_WORKING
R_LOS
TEMP_OVER
TEM_HA
SPARE_PATH_ALM
TIME_NOT_SUPPORT
TEST_STATUS
TEM_LA
TU_AIS_VC3
TR_LOC
TF
W_R_FAIL
TU_LOP_VC12
TU_AIS_VC12
TU_LOP_VC3
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL
WRG_BD_TYPE

508

10 SDH Boards


AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR

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10 SDH Boards
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

RSBBE
RSES
RSSES
RSUAS
RSCSES
RSOOF
RSOFS
MSBBE
MSES
MSUAS
MSCSES
MSSES
MSFEBBE
MSFEES
MSFESES
MSFEUAS
MSFECSES
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES
HPFESES
HPFEUAS
HPFECSES
TLBMAX
TLBMIN
TLBCUR
OSPICCVMAX
OSPICCVMIN
OSPICCVCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
INVOLTMAX
INVOLTMIN
INVOLTCUR

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10 SDH Boards

Table 10-108 and Table 10-109 list the parameters specified for the optical interfaces of the
SL64.
Table 10-108 Parameters specified for the optical interfaces of the N1SL64/N2SL64
Issue 03 (2013-02-20)
Paramet
er
Value
Nominal
bit rate
9953280 kbit/s
Line code
type
NRZ
Applicati
on code
I-64.1
I-64.2
S-64.
2b
L-64.2b (BA)
Le-64
.2
Ls-64
.2
V-64.2b (BA +
PA + DCU)
Transmiss
ion
distance
(km)
0 to 2
0 to
25
2 to 40
35 to 80
35 to
60
55 to
80
80 to 120
Type of
fiber
Singl
emode
LC
Singl
emode
LC
Single
-mode
LC
Single-mode
LC
Singl
emode
LC
Singl
emode
LC
Single-mode LC
Operating
wavelengt
h range
(nm)
1290
to
1330
1530
to
1565
1530
to
1565
1530 to 1565
1530
to
1565
1530
to
1565
1550.12
Mean
launched
optical
power
(dBm)
-6 to
-1
-5 to
-1
-1 to
+2
-4 to +2
(without the
BA)
0 to 4
4 to 7
-4 to -1 (without
the BA, PA, or
DCU)
Receiver
sensitivity
(dBm)
-11
Minimum
overload
(dBm)
-1
-1
-1
-1
-8
-8
-1
Minimum
extinction
ratio (dB)
8.2
8.2
8.2
8.2
8.2
8.2
13 to 15 (with
the BA)
-14
-14
-14
13 to 15 (with the
BA)
-21
-21
-14 (without the

PA, BA, or DCU)
-26 (with the PA)

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10 SDH Boards
Paramet
er
Value
Dispersio
n
tolerance
(ps/nm)
6.6
500
800
1600
1200
1600
2040 (with the

DCU)
Maximum
-20 dB
spectral
width
(nm)
Minimum
side mode
suppressi
on ratio
(dB)
30
30
30
30
30
30
30
"BA + PA + DCU" indicates that the specifications of the V-64.2b optical interface are
measured when the BA, PA, and DCU are used.
The dispersion coefficient of the G.652 fiber is 17 ps/nm when the transmission wavelength
is 1550.12 nm. Therefore, the dispersion tolerance of the SL64 is 2040 ps/nm when it works
with the BA, PA, and DCU. (The dispersion compensation distance is 80 km.)
Table 10-109 Parameters specified for the optical interfaces of the N4SL64
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit
rate
9953280 kbit/s
Line code type
NRZ
Application
code
I-64.1
S-64.2b
Le-64.2
P1L1-2D
2
V-64.2b (BA + PA +
DCU)
Transmission
distance (km)
0 to 2
2 to 40
35 to 60
40 to 80
80 to 120
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Single-mode LC
Operating
wavelength
range (nm)
1290 to
1330
1530 to
1565
1530 to
1565
1530 to
1565
1550.12
Mean launched
optical power
(dBm)
-6 to -1
-1 to +2
0 to 4
0 to 4
-4 to -1 (without the BA,

PA, or DCU)

13 to 15 (with the BA)
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10 SDH Boards
Parameter
Value
Receiver
sensitivity
(dBm)
-11
Minimum
overload
(dBm)
-1
-1
-8
-7
-1
Minimum
extinction ratio
(dB)
8.2
8.2
8.2
Dispersion
tolerance (ps/
nm)
200
800
1600
1600
2040 (with the DCU)
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
30
30
30
-14
-21
-24
-14 (without the PA, BA,

or DCU)
-26 (with the PA)
"BA + PA + DCU" indicates that the specifications of the V-64.2b optical interface are
measured when the BA, PA, and DCU are used.
The dispersion coefficient of the G.652 fiber is 17 ps/nm when the transmission wavelength
is 1550.12 nm. Therefore, the dispersion tolerance of the SL64 is 2040 ps/nm when it works
with the BA, PA, and DCU. (The dispersion compensation distance is 80 km.)
Table 10-110 lists the parameters specified for the colored optical interfaces of the N1SL64 and
N2SL64.
Table 10-111 and Table 10-112 list the parameters specified for the colored optical interfaces
of the N4SL64.
Table 10-110 Parameters specified for the colored optical interfaces of the N1SL64 and N2SL64
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
40
-4 to -1
192.1 to 196.0

513

Parameter
10 SDH Boards
Value
DWDM
12.5
-14
-1
800
10
0.3
Minimum side mode suppression ratio (dB)
35
22
Table 10-111 CWDM parameters specified for the colored optical interfaces of the N4SL64
Parameter
Value
CWDM
Nominal bit rate
9953280 kbit/s
Type of fiber
Single-mode LC
Transmission distance
(km)
70

range (dBm)
0 to 4
range (nm)
1471 to 1611, in steps of 20
l 1451 to 1551 nm: -23

l 1571 nm: -22
l 1591 to 1611 nm: -21
Issue 03 (2013-02-20)
-9
Maximum allowed
dispersion (ps/nm)
1400

(dB)
8.2

width (nm)
Minimum side mode

30

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10 SDH Boards
Table 10-112 DWDM parameters specified for the colored optical interfaces of the N4SL64
Parameter
Value
DWDM
Nominal bit rate
9953280kbit/s
Type of fiber
Single-mode LC
40
80

range (dBm)
-1 to 2
-1 to 3
192.1 to 196.0
192.1 to 196.0

(GHz)
10
10
-17
-24
-1
-9

(ps/nm)
800
1600

(dB)
9.5
8.2

width (nm)
0.3
0.3
Minimum side mode

35
30
Laser Safety Class

The mechanical specifications of the SL64 are as follows:
l
Weight (kg): 1.1
Power Consumption
Issue 03 (2013-02-20)

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10 SDH Boards
10.22 SLD64

The SLD64 is available in the following functional versions: N1
10.22.2 Application
The SLD64 is a line board. The SLD64 can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SLD64 converts the received optical signals
SLD64 converts the electrical signals sent from the cross-connect side into optical signals and
NE1
NE2
NE4
NE3
Service flow
Line board

The SLD64 receives and transmits 2xSTM-64 optical signals, processes overhead bytes, and
performs the MSP protection.
Table 10-113 describes the functions and features of the SLD64.
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10 SDH Boards

Function and
Feature
SLD64
Basic functions
Provides two optical interfaces to transmit and receive 2xSTM-64

optical signals. Processes 2xSTM-64 standard services or concatenated
services, which are encapsulated in XFP format.
Specifications of

I-64.1 and S-64.2b. The characteristics of the optical interfaces comply
with ITU-T G.691.
Specifications of
the optical module
l Supports the query of the manufacturing information of the optical

module. The SLD64 also reports the performance events that
indicate the performance of the optical module.
l Supports the default off state of the laser, and the setting and query
of the on/off state of the laser.
Service processing

concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.
Overhead
processing

overheads.
l Supports two channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events.
Specifications of
the REG
Protection schemes

l Supports the fiber-shared MSP and processes four sets of K bytes.
A single optical interface can process two sets of K bytes. One
SLD64 supports a maximum of four MSP rings.
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10 SDH Boards
Function and
Feature
SLD64
Maintenance
features

affect services.
services.

The SLD64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
Figure 10-75 shows the functional block diagram of the SLD64.
622 MHz
9.953
Gbit/s
SPI 9.953
E/O
Gbit/s
DEMUX 16x622
Mbit/s
. .
. .
9.953
Gbit/s
O/E
O/E
9.953
SPI Gbit/s
MUX
16x622
Mbit/s
E/O
Backplane
Reference clock
Cross-connect
unit
K1 and K2
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/
DEMUX
O/E
converting
module
622 MHz
PLL
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Power
module
Frame header
Communication
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination
Issue 03 (2013-02-20)

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10 SDH Boards

l
MUX/DEMUX Module
l

l
RST sub-module
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module
Issue 03 (2013-02-20)

519

10 SDH Boards

l
Controls the laser.
units.
Power Module
require.
10.22.5 Front Panel


Issue 03 (2013-02-20)

520

10 SDH Boards
SLD64
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
SLD64
Indicators
l
Interfaces
Issue 03 (2013-02-20)

521

10 SDH Boards

Interface
Type of Interface
Usage
IN1IN2
LC
OUT1OUT2
LC

The SLD64 does not have any jumpers or DIP switches that are used for board settings.
10.22.7 Valid Slots

The SLD64 must be installed in a valid slot in the subrack. Otherwise, the SLD64 fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLD64 vary with the cross-connect capacity of the subrack. The slots
valid for the SLD64 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SLD64 can be installed in slots 7, 8, 11,
and 12.

Table 10-115 describes the relationship between the feature code of the SLD64 and the type of
optical interface.
Table 10-115 Relationship between the feature code of the SLD64 and the type of optical
interface
Board
Feature Code
SSN1SLD6401
01
I-64.1
SSN1SLD6402
02
S-64.2b

Issue 03 (2013-02-20)

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10 SDH Boards

is correct.
----End

Disabled.
TUG structure.
NOTE
----End

----End
Issue 03 (2013-02-20)

523

10 SDH Boards

Boards.
the Current Alarms.
----End

l
J0
J1
J2
C2

Troubleshooting
Table 10-116 lists the faults that occur on the SLD64 frequently and the troubleshooting
methods.
NOTE
The SLD64 uses the XFP optical module. When the SLD64 operates and an abnormal alarm occurs on the
Issue 03 (2013-02-20)

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10 SDH Boards
Table 10-116 Methods used to troubleshoot the faults that occur on the SLD64 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Issue 03 (2013-02-20)

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10 SDH Boards
Fault Symptom
Common Fault
Cause
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLD64, see Replacing an SDH Board.

10.22.12.1 Alarms of N1SLD64
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP8_ECC
BIP_EXC
BIP_SD
CHIP_ABN
C2_PDI
C2_VCAIS
FSELECT_STG
CHIP_FAIL
COMMUN_FAIL
HP_RDI
FPGA_ABN
HP_LOM
HP_TIM
HP_REI
HP_SLM
J0_MM
HP_UNEQ
IN_PWR_ABN
LOOP_ALM
LASER_MOD_ERR
LASER_SHUT
LP_REI_VC12
LP_RDI_VC12
LP_RDI_VC3
LP_SLM_VC3
LP_REI_VC3
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_NO_FITED
LP_UNEQ_VC3
LSR_COOL_ALM
MS_RDI
LSR_WILL_DIE
MS_AIS
R_LOF
MS_REI

526

10 SDH Boards
NO_BD_SOFT
SPARE_PATH_ALM
OH_LOOP
OUT_PWR_ABN
TEM_LA
POWER_ABNORMAL
R_LOC
TF
R_LOS
SLAVE_WORKING
TU_AIS_VC3
T_LOSEX
TEM_HA
W_R_FAIL
TEMP_OVER
TEST_STATUS
PATCH_NOT_CONFIRM
TR_LOC
TU_AIS_VC12
TIME_NOT_SUPPORT
TU_LOP_VC12
TU_LOP_VC3
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
PATCH_ERR
PS
MOD_TYPE_MISMATCH
IN_PWR_LOW
IN_PWR_HIGH
WRG_BD_TYPE
DCN_FAIL

10.22.13.1 Performance Events of N1SLD64
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS

527

10 SDH Boards
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN


Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
9953280 kbit/s
Line code type
NRZ
Application code
I-64.1
S-64.2b
(km)
0 to 2
2 to 40
Type of fiber
Single-mode LC
Single-mode LC
range (nm)
1290 to 1330
1530 to 1565
Mean launched optical

power (dBm)
-6 to -1
-1 to +2
(dBm)
-11
-14
-1
-1

(dB)
8.2
Dispersion tolerance (ps/

nm)
6.6
800
Minimum side mode

30
30

width (nm)

528

10 SDH Boards
Laser Safety Class

The mechanical specifications of the SLD64 are as follows:
l
Weight (kg): 1.2
Power Consumption
10.23 SF64
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
This topic also describes how to configure and commission the SF64.

The SF64 is available in the following functional version: N1.
10.23.2 Application
The SF64 is a line board. The SF64 can be used on the OptiX OSN equipment series to transmit
and receive STM-64 optical signals. The SF64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF64
NE1
NE2
NE4
NE3
Service flow
Line board
Issue 03 (2013-02-20)

529

10 SDH Boards
The SF64 can be interconnected with the WDM equipment.

The SF64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 10-118 describes the functions and features of the SF64.
Table 10-118 Functions and features of the SF64
Function and
Feature
SF64
Basic functions
l Transmits and receives 1xSTM-64 optical signals.

Specifications of

Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the
optical interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with
ITU-T G.692 and can be directly connected to the DWDM
equipment.
l The N1SF64 supports the DWDM colored optical interfaces. The
optical interface uses the LC connector. The DWDM optical
interface supports the transmission distance of 40 km.
Specifications of
the optical module

optical module.
l supports fixed optical modules.
Service processing

Overhead
processing

overheads.
Issue 03 (2013-02-20)
Alarms and
performance events
Specifications of
the REG

530

Function and
Feature
SF64
Protection schemes
10 SDH Boards

l Supports the fiber-shared MSP and processes two sets of K bytes.
One SF64 supports a maximum of two MSP rings.
Maintenance
features

affect services.
services.

The SF64 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, and power module.
Figure 10-78 shows the functional block diagram of the SF64.
Issue 03 (2013-02-20)

531

10 SDH Boards
Figure 10-78 Functional block diagram of the SF64

Backplane
622 MHz
622 MHz
PLL
10.71
Gbit/s
10.71
Gbit/s
O/E
DEMU
X
16x669
Mbit/s
MUX
FEC 16x622
16x669
Mbit/s
Mbit/s
SPI
10.71
Gbit/s
E/O
O/E
converting
module
10.71
Gbit/s
16x622
Mbit/s
622 MHz
PLL
Reference clock
Cross-connect
unit
K1 and K2
Cross-connect
unit
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/DE
MUX
669 MHz
PLL
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Frame header
Communication
Fuse
Power
module
Fuse +3.3 V
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60
V
-48 V/-60 V
+3.3 V backup power

termination

l
MUX/DEMUX Module
l
FEC Module
Issue 03 (2013-02-20)

532

10 SDH Boards

l
RST sub-module
byte.
MST sub-module
writes the B2 byte.
MSA sub-module
justifications.
HPT sub-module

l
Controls the laser.
units.
Issue 03 (2013-02-20)

533

10 SDH Boards
Power Module
require.
10.23.5 Front Panel

The front panel of the SF64 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-79 shows the appearance of the front panel of the SF64.
Figure 10-79 Front panel of the SF64
SF64
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
SF64
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Indicators
l
Interfaces
The front panel of the SF64 has one optical interface. Table 10-119 describes the types and
usage of the optical interfaces of the SF64.
Table 10-119 Optical interfaces of the SF64
Interface
Type of Interface
Usage
IN
LC
OUT
LC

The SF64 does not have any jumpers or DIP switches that are used for board settings.
10.23.7 Valid Slots

The SF64 must be installed in a valid slot in the subrack. Otherwise, the SF64 fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SF64 vary with the cross-connect capacity of the subrack. The slots valid
for the SF64 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the SF64 can be installed in slots 7, 8, 11,
and 12.

The feature code of the SF64 indicates the type of optical interface.
Table 10-120 provides the relationship between the feature code of the SF64 and the type of
optical interface.
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Table 10-120 Relationship between the feature code of the SF64 and the type of optical interface
Board
Feature Code
SSN1SF6400
00
interface
SSN1SF6401
01
Ue-64.2c, Ue-64.2d, and

Ue-64.2e


is correct.
----End

Disabled.
TUG structure.
NOTE
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----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SF64 by using the U2000.
You can set the following parameters for the SF64 by using the U2000:
l
J0
J1
J2
C2

Troubleshooting
Table 10-121 lists the faults that occur on the SF64 frequently and the troubleshooting methods.
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NOTE
The N4SF64 uses the XFP optical module. When the N4SF64 operates and an abnormal alarm occurs on
the optical interface, check whether the optical module is properly installed. To check whether the optical
Table 10-121 Methods used to troubleshoot the faults that occur on the SF64 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
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Fault Symptom
Common Fault
Cause
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SF64, see Replacing an SDH Board.

10.23.12.1 Alarms of N1SF64
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_CMM
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BIP_SD
BEFFEC_EXC
BIP_EXC
C2_VCAIS
BIP8_ECC
C2_PDI
FEC_LOF
CHIP_FAIL
COMMUN_FAIL
FSELECT_STG
FEC_OOF
FPGA_ABN
HP_REI
HP_LOM

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10 SDH Boards
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LASER_MOD_ERR
IN_PWR_ABN
J0_MM
LP_RDI_VC12
LASER_SHUT
LOOP_ALM
LP_REI_VC3
LP_RDI_VC3
LP_REI_VC12
LP_TIM_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LSR_WILL_DIE
LSR_COOL_ALM
LSR_NO_FITED
MS_REI
MS_AIS
MS_RDI
ODU_AIS
NO_BD_SOFT
ODU_OCI
OH_LOOP
ODU_LCK
OTU_LOF
OTU_LOM
OTU_AIS
PM_BIP8_OVER
PM_BDI
OUT_PWR_ABN
POWER_ABNORMAL
PM_BIP8_SD
PM_BEI
R_LOS
R_LOC
PM_TIM
SM_BDI
R_OOF
R_LOF
SM_BIP8_SD
SM_BEI
SLAVE_WORKING
SPARE_PATH_ALM
SM_IAE
SM_BIP8_OVER
TC_EXC
T_LOSEX
SM_TIM
TC_ODI
TC_INCAIS
TC_DEG
TC_REI
TC_OEI
TC_LTC
TEM_HA
TC_TIM
TC_RDI
TF
TEM_LA
TC_UNEQ
TU_AIS_VC3
TR_LOC
TEST_STATUS
W_R_FAIL
TU_LOP_VC12
TU_AIS_VC12
PATCHFILE_NOTEXIST
PATCH_ERR
TU_LOP_VC3
CHIP_ABN
TEMP_OVER
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
PS
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL
MOD_TYPE_MISMATCH
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10.23.13.1 Performance Events of N1SF64

AUPJCHIGH
AUPJCLOW
AUPJCNEW
FEC_AFT_COR_ER
FEC_BEF_COR_ER
FEC_COR_0BIT_CNT
FEC_COR_1BIT_CNT
FEC_COR_BYTE_CNT
FEC_UNCOR_BLOCK_CNT
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
ODU2PMBIP8
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
OTU2SMBIP8
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TCBBE
TCFEBBE
TCOBBE
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

The technical specifications of the SF64 include the parameters specified for optical interfaces,

Table 10-122 lists the parameters specified for the optical interfaces of the SF64.
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Table 10-122 Specifications of optical interfaces of the SF64

Parameter
Value
Nominal bit rate 10709225kbit/s

Line code type
NRZ
Application
code
Ue-64.2c
Ue-64.2d
Ue-64.2e
FEC + BA (14 dB) +

PA + DCU (60 + 80)
FEC + BA (17 dB) + PA +

DCU (80 x 2)
FEC + BA (17 dB) +

RA + PA + DCU (60
x 3)
Operating
wavelength
range (nm)
1550.12
Type of fiber
Single-mode LC
Launched
optical power
range (dBm)
-3 to 2
Receiver
sensitivity
(dBm)
-14
Minimum
overload (dBm)
-1
Minimum
extinction ratio
(dB)
10
Maximum
allowed
dispersion (ps/
nm)
800
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
NOTE
The numbers in the brackets indicate the corresponding parameter values. For example, "BA (14 dB)"
indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA + PA + RA" indicates that
the specifications of the optical interface are measured when the FEC, BA, PA, and Raman amplifier are
used.
The parameters are only for the optical modules. The parameters of the amplifier are not provided.
Table 10-123 lists the parameters specified for the colored optical interfaces of the N1SF64.
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Table 10-123 Parameters specified for the colored optical interfaces of the N1SF64
Parameter
Value
DWDM
Nominal bit rate
10709225 kbit/s
Type of fiber
Single-mode LC
40
-4 to -1
192.1 to 196.0
12.5
-14
-1
800
10
0.3

(dB)
35
With the FEC: 20

Without the FEC: 22
Laser Safety Class

The mechanical specifications of the SF64 are as follows:
l
Weight of the N1SF64 (kg): 1.1
Power Consumption
At room temperature (25C), the maximum power consumption of the N1SF64 is 33 W.
10.24 SF64A
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
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10 SDH Boards

The SF64A is available in one functional version, namely, N1.
10.24.2 Application
The SF64A is a line board. The SF64A can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SF64A converts the received optical signals
SF64A converts the electrical signals sent from the cross-connect side into optical signals and
The SF64A can also be used for interconnecting with the WDM equipment.
NE1
NE2
NE4
NE3
Service flow
Line board
The SF64A can also be used for interconnecting with the WDM equipment.

The SF64A receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 10-124 provides the functions and features of the SF64A.
Table 10-124 Functions and features of the SF64A
Function and
Feature
SF64A
Basic functions
l Transmits and receives 1xSTM-64 optical signals.

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10 SDH Boards
Function and
Feature
SF64A
Specifications of

Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the
optical interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with
ITU-T G.692 and can be directly connected to the DWDM
equipment. Supports the variable-wavelength DWDM.
l Supports the DWDM colored optical interfaces. The optical
interface uses the LC connector. The DWDM optical interface
Specifications of
the optical module

optical module.
Service processing

Overhead
processing

overheads.
Alarms and
performance events
Specifications of
the REG
Protection schemes
l Supports the fiber-shared MSP and SNCP and processes two sets
of K bytes. One SF64A supports a maximum of two MSP protection
rings.
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10 SDH Boards
Function and
Feature
SF64A
Maintenance
features

affect services.
services.

The SF64A consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, power module.
Figure 10-81 shows the functional block diagram of the SF64A.
Figure 10-81 Functional block diagram of the SF64A
Backplane
622 MHz
622 MHz
PLL
10.71
Gbit/s
10.71
Gbit/s
O/E
16x669
Mbit/s
MUX
FEC 16x622
16x669
Mbit/s
Mbit/s
SPI
10.71
Gbit/s
E/O
O/E
converting
module
10.71
Gbit/s
16x622
Mbit/s
DEMU
X
622 MHz
PLL
Reference clock
Cross-connect
unit
K1 and K2
Cross-connect
unit
K1 and K2
High-speed
bus
RST MST MSA HPT
High-speed
bus
DCC
SDH overhead
processing module
MUX/DE
MUX
669 MHz
PLL
IIC
LOS
Laser shutdown
Logic and
control module
+3.3 V
Power
module
Frame header
Communication
Fuse
Power
module
Fuse +3.3 V
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60
V
-48 V/-60 V
+3.3 V backup power

termination

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10 SDH Boards

l
CDR Module
FEC Module
l

l
RST sub-module
byte.
MST sub-module
writes the B2 byte.
l
Issue 03 (2013-02-20)
MSA sub-module
547

10 SDH Boards
justifications.
l
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.24.5 Front Panel

The front panel of the SF64A has indicators, interfaces, a bar code, and a laser safety class label.

Figure 10-82 shows the appearance of the front panel of the SF64A.
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10 SDH Boards
Figure 10-82 Front panel of the SF64A
SF64A
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
SF64A
Indicators
l
Interfaces
The front panel of the SF64A has one optical interface. Table 10-125 describes the types and
usage of the optical interfaces of the SF64A.
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10 SDH Boards
Table 10-125 Optical interfaces of the SF64A

Interface
Type of
Interface
Usage
IN
LC
OUT
LC
10.24.6 Valid Slots

The slots valid for the SF64A vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SF64A are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the SF64A can be installed in slots 7, 8, 11,
and 12.

You can set the parameters for the SF64A by using the U2000.
You can set the following parameters for the SF64A by using the U2000:
l
J0
J1
J2
C2

The technical specifications of the SF64A include the parameters specified for optical interfaces,

Table 10-126 lists the parameters specified for the optical interfaces of the SF64A.
Table 10-126 Specifications of optical interfaces of the SF64A
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
10709225 kbit/s

550

10 SDH Boards
Parameter
Value
Line code type
DRZ
Application code
Ue-64.2c
Ue-64.2d
Ue-64.2e
Meaning of the
code
FEC + BA (14 dB) +

PA + DCU (60 + 80)
FEC + BA (17 dB) +

PA + DCU (80 x 2)
FEC + BA (17 dB) +

RA + PA + DCU (60
x 3)
Operating
wavelength range
(nm)
1550.12
1550.12
1550.12
Type of fiber
Single-mode LC
Launched optical
power range (dBm)
-4 to -1
-4 to -1
-4 to -1
Receiver
sensitivity (dBm)
-14
-14
-14
Minimum overload
(dBm)
-1
-1
-1
Minimum
extinction ratio
(dB)
10
10
10
Dispersion
tolerance (ps/nm)
800
800
800
Maximum -20 dB
spectral width (nm)
Minimum side
mode suppression
ratio (dB)
30
30
30
NOTE
The numbers in the brackets indicate the corresponding parameter values. For example, "BA (14 dB)"
indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA + PA + RA" indicates that
the specifications of the optical interface are measured when the FEC, BA, PA, and Raman amplifier (RA)
are used.
The parameter values are applicable only to the optical modules. The parameter values of the amplifier
and dispersion compensation unit (DCU) are not provided.
Table 10-127 list the parameters specified for the colored optical interfaces of the SF64A.
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10 SDH Boards
Table 10-127 Parameters specified for the colored optical interfaces of the SF64A
Parameter
Value
DWDM
Nominal bit rate
10709225 kbit/s
Type of fiber
Single-mode LC
40
-4 to -1
192.1 to 196.0
12.5
-14
-1
800
10
0.3

(dB)
35
With the FEC: 20

Without the FEC: 22
Laser Safety Class

The mechanical specifications of the SF64A are as follows:
l
Weight (kg): 1.1
Power Consumption
At room temperature (25C), the maximum power consumption of the SF64A is 33 W.
10.25 SLQ41
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board). This topic also
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The SLQ41 is available in one functional version, namely, N3. The SLQ41 supports the autosensing of optical interfaces.
10.25.2 Application
The SLQ41 is a line board. The SLQ41 can be used on the OptiX OSN equipment series to
transmit and receive STM-1/STM-4 optical signals. The SLQ41 converts the received optical
signals into electrical signals and sends the electrical signals to the cross-connect side. In
addition, the SLQ41 converts the electrical signals sent from the cross-connect side into optical
signals and transmits the optical signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SLQ41 transmits and receives STM-1 or STM-4 optical signals, performs O/E conversion
for the STM-1 or STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm
signals on the line.
Issue 03 (2013-02-20)
Function and
Feature
SLQ41
Basic functions
Transmits and receives 4xSTM-1 or 4xSTM-4 optical signals.

553

10 SDH Boards
Function and
Feature
SLQ41
optical interface
The STM-1 optical module or STM-4 optical module can be used.

l When the STM-1 optical module is used, the SLQ41 supports
different types of standard optical interfaces, namely, the I-1,
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-1.2 type comply with the standards defined by Huawei.
l When the STM-4 optical module is used, the SLQ41 supports
different types of standard optical interfaces, namely, the I-4,
interfaces of the I-4, S-4.1, L-4.1, and L-4.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-4.2 type comply with the standards defined by Huawei.
Supports the CWDM and DWDM colored optical interfaces. The
optical interface uses the LC connector. The CWDM optical interface
supports the transmission distance of 80 km, and the DWDM optical
interface supports the transmission distance of 120 km.
optical module

optical module.
Service processing
l When the STM-1 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, and VC-4 services.
l When the STM-4 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
Overhead processing
l Processes the section overheads of the STM-1 signals or STM-4

signals.
overheads.
Alarms and
performance events
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Function and
Feature
SLQ41
Protection schemes
10 SDH Boards

Maintenance
features

affect services.
services.
l Supports the PRBS function in the line direction, cross-connect
direction and Cause by Cross function.

This topic describes the working principle and signal flow of the SLQ41 by describing how to
process STM-1/STM-4 signals.
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155 MHz
PLL
STM-1/
STIM-4
O/E
E/O
O/E
E/O
K1 and K2
High-speed
bus
....
....
STM-1/
STIM-4
K1 and K2
CDR
SPI
Backplane
Reference clock
Cross-connect
unit
RST MST MSA HPT
High-speed
bus
CDR
SPI
DCC
SDH overhead
processing module
O/E converting
module
Frame header
Logic and
control module Communication
IIC
LOS
Laser shutdown
+3.3 V
Power
module
Power
module
Fuse
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse +3.3 V
+3.3 V backup power

termination

l
CDR Module

l
RST sub-module
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10 SDH Boards
MST sub-module
writes the B2 byte.
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.25.5 Front Panel

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10 SDH Boards

SLQ41
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
SLQ41
Indicators
l

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10 SDH Boards
Interfaces
Interface
Type of Interface
Usage
IN1IN4
LC
OUT1OUT4
LC

The SLQ41 does not have any jumpers or DIP switches that are used for board settings.
10.25.7 Valid Slots

The SLQ41 must be installed in a valid slot in the subrack. Otherwise, the SLQ41 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
When the cross-connect capacity is 200 Gbit/s, the slots valid for the SLQ41 are as follows:
The SLQ41 can be installed in slots 14, 15, and 16. In this case, one or two optical
The SLQ41 can be installed in slots 58 and 1114. In this case, one to four optical

optical interface.
Table 10-130 Relationship between the feature code of the SLQ41 and the type of optical
interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN3SLQ414
14
I-4
SSN3SLQ410
10
S-4.1

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10 SDH Boards
Board
Feature Code
SSN3SLQ411
11
L-4.1
SSN3SLQ412
12
L-4.2
SSN3SLQ413
13
Ve-4.2
SSN3SLQ114
14
I-1
SSN3SLQ110
10
S-1.1
SSN3SLQ111
11
L-1.1
SSN3SLQ112
12
L-1.2
SSN3SLQ113
13
Ve-1.2


is correct.
----End

Disabled.
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10 SDH Boards
TUG structure.
NOTE
----End

----End

Boards.
the Current Alarms.
----End

l
J0
J1
J2
C2

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Troubleshooting
Table 10-131 lists the faults that occur on the SLQ41 frequently and the troubleshooting
methods.
NOTE
The SLQ41 uses the SFP optical module. When the SLQ41 operates and an abnormal alarm occurs on the
Table 10-131 Methods used to troubleshoot the faults that occur on the SLQ41 frequently
Fault Symptom
Common Fault
Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
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Fault Symptom
Common Fault
Cause
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
U2000
l A single NE
becomes
unreachable to
the U2000.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the U2000.
l An NE becomes
unreachable to
the U2000
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLQ41, see Replacing an SDH Board.

10.25.12.1 Alarms of N3SLQ41
Issue 03 (2013-02-20)
ALM_ALS
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS

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10 SDH Boards
C2_PDI
BIP_EXC
BIP_SD
COMMUN_FAIL
C2_VCAIS
CHIP_ABN
HP_LOM
FPGA_ABN
FSELECT_STG
HP_SLM
HP_RDI
HP_REI
IN_PWR_ABN
HP_TIM
HP_UNEQ
LASER_SHUT
J0_MM
LASER_MOD_ERR
LP_SLM_VC3
LOOP_ALM
LP_SLM_VC12
LP_UNEQ_VC12
LP_TIM_VC12
LP_TIM_VC3
LSR_NO_FITED
LP_UNEQ_VC3
LSR_COOL_ALM
MS_RDI
LSR_WILL_DIE
MS_AIS
PATCH_ERR
MS_REI
NO_BD_SOFT
R_LOF
OH_LOOP
OUT_PWR_ABN
T_LOSEX
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
POWER_ABNORMAL
PS
R_LOS
SLAVE_WORKING
TEM_LA
TF
TU_AIS_VC12
TEM_HA
DCN_FAIL
TU_LOP_VC3
TEMP_OVER
TEST_STATUS
TR_LOC
TU_AIS_VC3
TU_LOP_VC12
SWDL_PKG_NOBDSOFT
R_LOC
MOD_TYPE_MISMATCH
WRG_BD_TYPE
IN_PWR_HIGH
IN_PWR_LOW

10.25.13.1 Performance Events of N3SLQ41
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES

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10 SDH Boards
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN


The SLQ41 supports the STM-1 and STM-4 optical modules.
Table 10-132 lists the parameters specified for the optical interfaces of the SLQ41 when the
STM-1 optical module is used.
Table 10-132 Parameters specified for the optical interfaces of the SLQ41 when the STM-1 optical module is used
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC
Single-mode LC
Single-mode LC
Operating
wavelength
range (nm)
1260 to 1360
1261 to 1360
1263 to 1360
1480 to 1580
1480 to 1580
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Parameter
Value
Launched
optical power
range (dBm)
-15 to -8
-15 to -8
-5 to 0
-5 to 0
-3 to 0
Receiver
sensitivity
(dBm)
-23
-28
-34
-34
-34
Minimum
overload (dBm)
-8
-8
-10
-10
-10
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Table 10-133 lists the parameters specified for the optical interfaces of the SLQ41 when the
Table 10-133 Parameters specified for the optical interfaces of the SLQ41 when the STM-4
optical module is used
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code pattern
NRZ
Application code
I-4
S-4.1
L-4.1
L-4.2
Ve-4.2
Transmission
distance (km)
0 to 2
2 to 15
15 to 40
40 to 80
80 to 100
Operating
wavelength range
(nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to
1580
Type of fiber
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Singlemode LC
Mean launched
optical power
(dBm)
-15 to -8
-15 to -8
-3 to -2
-3 to -2
-3 to -2

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Parameter
Value
Receiver
sensitivity (dBm)
-23
-28
-28
-28
-34
Minimum
overload (dBm)
-8
-8
-8
-8
-13
Minimum
extinction ratio
(dB)
8.2
8.2
10
10
10.5
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
30
30
Table 10-134 and Table 10-135 lists the parameters specified for the colored optical interfaces
of the SLQ41.
Table 10-134 CWDM parameters specified for the colored optical interfaces of the SLQ41
Parameter
Value
CWDM
Issue 03 (2013-02-20)
Nominal bit rate
155520 kbit/s or 622080 kbit/s
Type of fiber
Single-mode LC
80

(dBm)
0 to 5
1471 to 1611, in steps of 20
-28
-9

nm)
1600
8.2

(nm)

ratio (dB)
30

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10 SDH Boards
Table 10-135 DWDM parameters specified for the colored optical interfaces of the SLQ41
Parameter
Value
DWDM
Nominal bit rate
Type of fiber
Single-mode LC
120

(dBm)
-1 to 3
192.10 to 196.00

(GHz)
10
-28
-9

(ps/nm)
2400
8.2

width (nm)
0.3
Minimum side mode

30
Laser Safety Class

l
Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SLQ41 at room temperature (25C) is 12 W.
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10.26 SLH41
technical specifications of the SLH41 (16xSTM-1/STM-4 optical interface board with the
variable rate). This topic also describes how to configure and commission the SLH41.

The functional version of the SLH41 is N3.
10.26.2 Application
The SLH41 is a line board. The SLH41 can be used on the OptiX OSN equipment series to
transmit and receive STM-1/STM-4 optical signals. The SLH41 converts the received optical
signals into electrical signals and sends the electrical signals to the cross-connect side. In
addition, the SLH41 converts the electrical signals sent from the cross-connect side into optical
signals and transmits the optical signals.
NE1
NE2
NE4
NE3
Service flow
Line board

The SLH41 is used to transmit and receive 16xSTM-1/STM-14 optical signals, to perform O/E
conversion for the STM-1/STM-4 optical signals, to extract or insert overhead bytes, and to
report alarms generated on the line.
Table 10-136 provides the functions and features of the SLH41.
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Table 10-136 Functions and features of the SLH41

Functions and
Features
Value
Basic functions
Transmits and receives 16xSTM-1/STM-4 optical signals.
Specifications of
the optical
interface
The STM-1/STM-4 optical module can be used, which supports the

adaptive modulation (AM) technology.
l When the STM-1 optical module is used, the standard S-1.1 and L-1.1
optical interfaces are supported. The optical interfaces of the S-1.1 and
l When the STM-4 optical module is used, the standard S-4.1 optical
interface is supported. The optical interface of the S-4.1 type complies
with ITU-T G.957.
Supports the CWDM and DWDM colored optical interfaces. The optical
interface uses the LC connector. The CWDM optical interface supports
the transmission distance of 80 km, and the DWDM optical interface
Specifications of
the optical
module
module.
l Supports the usage and detection of the SFP optical module, facilitating
the maintenance of the optical module.
l Provides the ALS function. The optical interface supports the function
of setting the on/off state of a laser.
Service
processing
l When the STM-1 optical module is used, the SLH41 supports VC-12
services, VC-3 services, and VC-4 services.
l When the STM-4 optical module is used, the SLH41 supports VC-12
services, VC-3 services, VC-4 services, and VC-4-4c concatenation
services.
Overhead
processing
l Processes the section overheads of the STM-1/STM-4 signals.

overheads.
l Supports one to sixteen channels of ECC communication. The first
eight optical interfaces support the ECC communication in D1-D12
mode. The last eight optical interfaces support the ECC
communication in D4-D12 mode.
Alarms and
performance
events
Issue 03 (2013-02-20)


570

Functions and
Features
Value
Protection
schemes
10 SDH Boards

Maintenance
features

services.
l Supports the query of the manufacturing information about a board.
l Supports the PRBS function in the line direction and Cause by
Cross function.

The SLH41 consists of the O/E converting module, CDR module, SDH overhead processing
This topic describes the working principle and signal flow of the SLH41 by describing how to
process STM-1/STM-4 signals.
Figure 10-87 shows the functional block diagram of the SLH41.
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Figure 10-87 Functional block diagram of the SLH41

Backplane
Reference clock
Clock unit
155 MHz PLL
STM-1/
STM-4
O/E
E/O
S
P
I
O/E
E/O
S
P
I
K1 and K2
High-speed
bus
....
....
STM-1/
STM-4
Insertion and extraction of

K1 and K2
CDR
RST MST MSA HPT
High-speed
bus
CDR
DCC
SDH OH processing module
O/E
conversion module
IIC
LOS
Logic and
control module
SCC unit
SCC unit
Frame header
Clock unit
Communication
SCC unit
ALS
+3.3V
Power
module
Power
module
Fuse
-48V/-60V
-48V/-60V

termination

l
CDR Module

l
RST sub-module
l
Issue 03 (2013-02-20)
MST sub-module
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10 SDH Boards
writes the B2 byte.
l
MSA sub-module
HPT sub-module

l
Controls the laser.
units.
Power Module
require.
10.26.5 Front Panel

The front panel of the SLH41 has indicators, interfaces, a bar code, and a laser safety class label.
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Figure 10-88 shows the appearance of the front panel of the SLH41.
Figure 10-88 Front panel of the SLH41
SM SFP WORK WITH
G.657B FIBER ONLY
G.657B
SLH41
STAT
ACT
PROG
SRV
RX 1
2 TX
TX 15
16 RX
Indicators
l

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Interfaces
The front panel of the SLH41 has 16 optical interfaces. A silkscreen "16SFP" is marked below
the indicators.
Table 10-137 describes the types and usage of the optical interfaces of the SLH41.
Table 10-137 Description of the optical interfaces of the SLH41
Interface
Type of interface
Usage
RX1-RX16
LC
TX1-TX16
LC
NOTE
The G.657B fiber jumper rather than the G.652D fiber jumper is used if an optical attenuator is inserted
into the transmit port. Otherwise, the cabinet door cannot be closed. Figure 10-89 shows the G.657B fiber
jumper and G.652D fiber jumper.
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10 SDH Boards
Figure 10-89 G.657B fiber jumper and G.652D fiber jumper
G.652D fiber jumper
58.25
50.75
G.657B fiber jumper
42.5

The SLH41 does not have any jumpers or DIP switches that are used for board settings.
10.26.7 Valid Slots

The SLH41 must be installed in a valid slot on the subrack. Otherwise, the SLH41 fails to work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the SLH41 vary with the cross-connect capacity of the equipment. The slots
valid for the SLH41 are as follows:
l
When the cross-connect capacity is 40 Gbit/s or 80 Gbit/s, the SLH41 cannot be installed
on the subrack.
When the cross-connect capacity is 200 Gbit/s, the SLH41 can be installed in any of slots
5-8 and slots 11-14.
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The feature code of the SLH41 indicates the type of optical interface.
Table 10-138 provides the relationship between the feature code of the SLH41 and the type of
optical interface.
Table 10-138 Relationship between the feature code of the SLH41 and the type of optical
interface
Board
Feature Code
SSN3SLH4101
01
12xS-1.1, 4xS-4.1
SSN3SLH4102
02
8xS-1.1, 8xS-4.1
SSN3SLH4103
03
16xS-1.1
SSN3SLH4104
04
4xL-1.1, 12xS-4.1
SSN3SLH4105
05
16xS-4.1
The G.657B fiber jumper is required because the single-mode optical module is used over the
interface.


is correct.
----End

Issue 03 (2013-02-20)

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10 SDH Boards

Disabled.
TUG structure.
NOTE
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SLH41 by using the U2000.
You can set the following parameters for the SLH41 by using the U2000:
l
J0
J1
Issue 03 (2013-02-20)

578

J2
C2
10 SDH Boards

Troubleshooting
Table 10-139 lists the faults that occur on the SLH41 frequently and the troubleshooting
methods.
NOTE
The SLH41 uses the SFP optical module. When the SLH41 operates and an abnormal alarm occurs on the
Table 10-139 Methods used to troubleshoot the faults that occur on the SLH41 frequently
Symptom
Common Cause
l The optical fiber

or connector
becomes
abnormal.

Interruptions.
l An incorrect
operation is
performed.
l The types or
settings of the
boards are
inconsistent.
l The optical power
becomes
abnormal.
Bit error
l The equipment
becomes faulty.
l The clock
configuration is
incorrect.
l The precision of
the external clock
source is very
low.
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Symptom
Common Cause
failure
l The MSP
switching fails.

Faults.
l The SNCP
switching fails.
l The clock
protection
switching fails.
NEs being
unreachable to the
NMS
l A single NE
becomes
unreachable to
the NMS.

Unreachable.
l All the NEs in a

subnet become
unreachable to
the NMS.
l An NE becomes
unreachable to
the NMS
frequently.
Equipment
An SDH overhead
occurs.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SLH41, see Replacing an SDH Board.

10.26.12.1 Alarms of N3SLH41
Issue 03 (2013-02-20)
R_LOS
WRG_BD_TYPE
R_LOF
R_OOF
R_LOC
B1_EXC
B1_SD
J0_MM
B2_EXC
B2_SD
MS_AIS
MS_RDI
MS_REI
TF
IN_PWR_ABN

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10 SDH Boards
OUT_PWR_ABN
LSR_WILL_DIE
LSR_COOL_ALM
TEM_HA
TEM_LA
LASER_SHUT
LSR_NO_FITED
LASER_MOD_ERR
ALM_ALS
SPARE_PATH_ALM
TEST_STATUS
OH_LOOP
FSELECT_STG
NO_BD_SOFT
TR_LOC
T_LOSEX
COMMUN_FAIL
W_R_FAIL
CHIP_FAIL
POWER_ABNORMAL
BIP8_ECC
BD_STATUS
AU_AIS
AU_LOP
HP_TIM
HP_SLM
HP_UNEQ
HP_RDI
HP_REI
B3_EXC
B3_SD
AU_CMM
C2_VCAIS
C2_PDI
FPGA_ABN
SLAVE_WORKING
HP_LOM
PATCHFILE_NOTEXIST
PATCH_ERR
LSR_INVALID
PATCH_NOT_CONFIRM
CHIP_ABN
LOOP_ALM
LP_RDI_VC12
LP_REI_VC12
LP_SLM_VC12
LP_TIM_VC12
LP_UNEQ_VC12
TU_AIS_VC12
TU_LOP_VC12
BIP_SD
BIP_EXC
TEMP_OVER
LP_RDI_VC3
LP_REI_VC3
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
TU_AIS_VC3
TU_LOP_VC3
B3_EXC_VC3
B3_SD_VC3
TIME_NOT_SUPPORT
PS
MOD_TYPE_MISMATCH
IN_PWR_HIGH
IN_PWR_LOW
DCN_FAIL

10.26.13.1 Performance Events of N3SLH41
Issue 03 (2013-02-20)
RSBBE
RSES
RSSES
RSUAS
RSCSES
RSOOF

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RSOFS
MSBBE
MSES
MSUAS
MSCSES
MSSES
MSFEBBE
MSFEES
MSFESES
MSFEUAS
MSFECSES
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES
HPFESES
HPFEUAS
HPFECSES
TLBMAX
TLBMIN
TLBCUR
OSPICCVMAX
OSPICCVMIN
OSPICCVCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
INVOLTMAX
INVOLTMIN
INVOLTCUR

The technical specifications of the SLH41 include the parameters specified for optical interfaces,

Table 10-140 lists the parameters specified for the optical interfaces of the SLH41 when the
Table 10-140 Parameters specified for the optical interfaces of the SLH41 when the STM-1
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
NRZ
Application code
S-1.1
L-1.1
0 to 15
15 to 40
Type of fiber
Single-mode LC
Single-mode LC

582

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Parameter
Value

(nm)
1261 to 1360
1263 to 1360

range (dBm)
-15 to -8
-5 to 0
-28
-34
Overload optical power

(dBm)
-8
-10

(dB)
8.2
10
Table 10-141 lists the parameters specified for the optical interfaces of the SLH41 when the
Table 10-141 Parameters specified for the optical interfaces of the SLH41 when the STM-4
Parameter
Value
Nominal bit rate
622080 kbit/s
Line code pattern
NRZ
Application code
S-4.1
0 to 15

(nm)
1274 to 1356
Type of fiber
Single-mode LC

range (dBm)
-15 to -8
-28
-8

(dB)
8.2
Table 10-142 and Table 10-143 list the parameters specified for the colored optical interfaces
of the SLH41.
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Table 10-142 CWDM parameters specified for the colored optical interfaces of the SLH41
Parameter
Value
CWDM
Nominal bit rate
Type of fiber
Single-mode LC
80

(dBm)
0 to 5
1471 to 1611, in steps of 20
-28
-9

nm)
1600
8.2

(nm)

ratio (dB)
30
Table 10-143 DWDM parameters specified for the colored optical interfaces of the SLH41
Parameter
Value
DWDM
Issue 03 (2013-02-20)
Nominal bit rate
Type of fiber
Single-mode LC
120

(dBm)
-1 to 3
192.10 to 196.00

(GHz)
10
-28
-9

(ps/nm)
2400

584

Parameter
10 SDH Boards
Value
DWDM
8.2

width (nm)
0.3
Minimum side mode

30
Laser Safety Class

The mechanical specifications of the SLH41 are as follows:
l
Weight: 1.5 kg
Power Consumption
The maximum power consumption of the SLH41 at room temperature (25C) is 49 W.
10.27 EU04

The EU04 is available in one functional version, namely, N1.
10.27.2 Application
The EU04 is an STM-1 electrical interface board. The EU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.

The EU04 receives and transmits 4xSTM-1 electrical signals. The EU04 must work with the
SEP.
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The EU04 consists of the interface module, switch matrix module, and power module.
Figure 10-90 shows the functional block diagram of the EU04 by describing how to process
1xSTM-1 signals.
Figure 10-90 Functional block diagram of the EU04
Backplane
Cross-connect board
STM-1 electrical
signal
Interface
module
Switch
matrix
module
STM-1 electrical
signal
+3.3 V
Power
module
Fuse
SEP
TSB4/TSB8
TSB4/TSB8
SEP
+3.3 V power
Interface Module
The interface module receives and transmits the STM-1 electrical signals.
Switch Matrix Module

In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SEP. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the EU04 with the required DC voltages.
10.27.5 Front Panel

The front panel of the EU04 has interfaces and a bar code.

Figure 10-91 shows the appearance of the front panel of the EU04.
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10 SDH Boards
Figure 10-91 Front panel of the EU04
EUO4
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
EUO4
Interfaces
The front panel of the EU04 has four pairs of electrical interfaces.
Table 10-144 describes the types and usage of the interfaces of the EU04.
Table 10-144 Interfaces of the EU04
Issue 03 (2013-02-20)
Interface
Type of Interface
Usage
IN1IN4
SMB
Receives the 1st to the 4th channels of STM-1

electrical signals.
OUT1OUT4
SMB
Transmits the 1st to the 4th channels of STM-1

electrical signals.

587

10 SDH Boards
10.27.6 Valid Slots

The EU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SEP.
Table 10-145 lists the slots valid for the SEP and the corresponding slots for the EU04.
Table 10-145 Slots valid for the SEP and the corresponding slots for the EU04
Slot Valid for the SEP
Corresponding Slot for the EU04
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the EU04 include the parameters specified for electrical

Table 10-146 lists the parameters specified for the electrical interfaces of the EU04.
Table 10-146 Parameters specified for the electrical interfaces of the EU04
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
CMI
Signal bit rate at the output interface
Complies with ITU-T G.703.
Allowed frequency deviation at the input

interface
Allowed attenuation at the input interface
The mechanical specifications of the EU04 are as follows:
Issue 03 (2013-02-20)

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10 SDH Boards
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EU04 at room temperature (25C) is 6 W.
10.28 EU08

The EU08 is available in one functional version, namely, N1.
10.28.2 Application
The EU08 is an STM-1 electrical interface board. The EU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.

The EU08 receives and transmits 8xSTM-1 electrical signals. The EU08 must work with the
SLH1 or SEP1.

The EU08 consists of the interface module, switch matrix module, and power module.
Figure 10-92 shows the functional block diagram of the EU08.
Figure 10-92 Functional block diagram of the EU08
Backplane
Cross-connect board
STM-1 electrical
signal
Interface
module
Switch
matrix
module
STM-1 electrical
signal
+3.3 V
Issue 03 (2013-02-20)
Power
module
Fuse

SEP/SLH1
TSB8
TSB8
SEP/SLH1
+3.3 V power
589

10 SDH Boards
Interface Module
The interface module receives and transmits the STM-1 electrical signals.

module transmits the signal to the SLH1 or SEP. When the TPS is performed, the switch matrix
module transmits the signal to the TSB8 for bridging.
Power Module
The power module provides all the modules of the EU08 with the required DC voltages.
10.28.5 Front Panel

The front panel of the EU08 has interfaces and a bar code.

Figure 10-93 shows the appearance of the front panel of the EU08.
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10 SDH Boards
Figure 10-93 Front panel of the EU08
EUO8
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
OUT7
IN7
OUT8
IN8
EUO8
Interfaces
The front panel of the EU08 has eight pairs of electrical interfaces.
Table 10-147 describes the types and usage of the interfaces of the EU08.
Table 10-147 Interfaces of the EU08
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
IN1IN8
SMB
Receives the 1st to the 8th channels of STM-1

electrical signals.
OUT1OUT8
SMB
Transmits the 1st to the 8th channels of STM-1

electrical signals.

591

10 SDH Boards
10.28.6 Valid Slots

The slots valid for the EU08 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the EU08 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the EU08 can be installed in slots 19-26
and 29-36.
Table 10-148 lists the slots valid for the SLH1 and the corresponding slots for the EU08. The
EU08 installed in the slot with a smaller number transmits/receives the 1st to the 8th channels
of STM-1 electrical signals. The EU08 installed in the slot with a larger number transmits/
receives the 9th to the 16th channels of STM-1 electrical signals.
Table 10-148 Slots valid for the SLH1 and the corresponding slots for the EU08
Slot Valid for the SLH1
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
Table 10-149 lists the slots valid for the SEP and the corresponding slots for the EU08.
Table 10-149 Slots valid for the SEP and the corresponding slots for the EU08
Issue 03 (2013-02-20)
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
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10 SDH Boards
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the EU08 include the parameters specified for electrical

Table 10-150 lists the parameters specified for the electrical interfaces of the EU08.
Table 10-150 Parameters specified for the electrical interfaces of the EU08
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
CMI
Allowed frequency deviation at the

input interface
interface
The mechanical specifications of the EU08 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EU08 at room temperature (25C) is 11 W.
10.29 OU08
technical specifications of the OU08 (8xSTM-1 optical interface board).
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The OU08 is available in the following functional versions: N1 and N2. The difference between
the two versions is with regard to the connector type for the optical interfaces and whether the
optical module is swappable.
Table 10-151 describes the versions of the OU08.
Table 10-151 Versions of the OU08
Item
Description
Functional versions
The OU08 is available in two functional versions, namely, N1 and N2.
Common points
The working principle of the N1OU08 is the same as the working

principle of the N2OU08.
Differences
The optical interface of the N1OU08 uses the LC connector, whereas

the optical interface of the N2OU08 uses the SC connector.
The N1OU08 uses the swappable optical module, whereas the
N2OU08 does not use the swappable optical module.
The N1OU08 supports optical power query when using pluggable
optical modules, whereas the N2OU08 does not.
Substitution
None
10.29.2 Application
The OU08 is an STM-1 optical interface board. The OU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 optical processing board.

The OU08 receives and transmits 8xSTM-1 optical signals. The OU08 must work with the SLH1
or SEP1.

The OU08 consists of the interface module and power module.
Figure 10-94 shows the functional block diagram of the OU08.
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Figure 10-94 Functional block diagram of the OU08

Backplane
STM-1 optical
signal
SEP/SLH1
Interface
module
STM-1 optical
signal
SEP/SLH1
+3.3 V
Power
module
Fuse
+3.3 V power
Interface Module
In the receive direction, the interface module performs O/E conversion for the STM-1 signals
and transmits the signals to the SLH1 or SEP.
In the transmit direction, the interface module performs E/O conversion for the STM-1 signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the OU08 with the required DC voltages.
10.29.5 Front Panel

The front panel of the OU08 has interfaces and a bar code.

Figure 10-95 shows the appearance of the front panel of the N1OU08. Figure 10-96 shows the
appearance of the front panel of the N2OU08.
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Figure 10-95 Front panel of the N1OU08
OU08
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT
OU08
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Figure 10-96 Front panel of the N2OU08
OU08
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
OUT7
IN7
OUT8
IN8
OU08
Interfaces
The front panel of the N1OU08/N2OU08 has eight optical interfaces.
Table 10-152 describes the types and usage of the interfaces of the N1OU08. Table 10-153
describes the types and usage of the interfaces of the N2OU08.
Table 10-152 Interfaces of the N1OU08
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
IN1IN8
LC
Receives the first to the eighth channels of STM-1

optical signals.

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Interface
Type of
Interface
Usage
OUT1OUT8
LC
Transmits the first to the eight channels of STM-1

optical signals.
Table 10-153 Interfaces of the N2OU08

Interface
Type of
Interface
Usage
IN1IN8
SC
Receives the first to the eighth channels of STM-1

optical signals.
OUT1OUT8
SC
Transmits the first to the eighth channels of STM-1

optical signals.
10.29.6 Valid Slots

The slots valid for the OU08 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
When the cross-connect capacity is 200 Gbit/s, the OU08 can be installed in slots 1926
and 2936.
Table 10-154 lists the slots valid for the SLH1 and the corresponding slots for the OU08. The
OU08 installed in the slot with a smaller number transmits/receives the 1st to the 8th channels
of STM-1 optical signals. The OU08 installed in the slot with a larger number transmits/receives
the 9th to the 16th channels of STM-1 optical signals.
Table 10-154 Slots valid for the SLH1 and the corresponding slots for the OU08
Issue 03 (2013-02-20)
Corresponding Slot for the OU08
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
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Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
Table 10-155 lists the slots valid for the SEP1 and the corresponding slots for the OU08.
Table 10-155 Slots valid for the SEP1 and the corresponding slots for the OU08
Slot Valid for the SEP1
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the OU08 include the parameters specified for optical interfaces,

Table 10-156 lists the parameters specified for the optical interfaces of the OU08.
Table 10-156 Parameters specified for the optical interfaces of the OU08
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
155520 kbit/s
Line code pattern
NRZ
Application code
S-1.1
range (nm)
N1OU08: 1260-1360
Type of fiber
Single-mode LC
N2OU08: 1261-1360

599

Parameter
Value

power (dBm)
-15 to -8
(dBm)
-28
10 SDH Boards
Laser Safety Class

The mechanical specifications of the OU08 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the OU08 at room temperature (25C) is 6 W.
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11
PDH Boards
About This Chapter

The PDH boards include the PDH service interface boards and PDH service processing boards,
to transmit/receive and process E1/T1 signals, E3/T3 signals, E4/STM-1 electrical signals, and
DDN signals.
11.1 PQ1
technical specifications of the PQ1 (63xE1 service processing board). This topic also describes
how to configure and commission the PQ1.
11.2 PQM
technical specifications of the PQM (63xE1/T1 service processing board). This topic also
describes how to configure and commission the PQM.
11.3 PFL1
technical specifications of the PFL1 (8xE1 optical processing board). This topic also describes
how to configure and commission the PFL1.
11.4 PL3
technical specifications of the PL3 (3xE3/T3 service processing board). This topic also describes
how to configure and commission the PL3.
11.5 PL3A
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel). This topic also describes how to configure and commission the PL3A.
11.6 PD3
technical specifications of the PD3 (6xE3/T3 service processing board).
11.7 PQ3
technical specifications of the PQ3 (12xE3/T3 service processing board).
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11.8 DX1
technical specifications of the DX1 (DDN service accessing and converging board). This topic
also describes how to configure and commission the DX1.
11.9 DXA
technical specifications of the DXA (DDN service converging and processing board).
11.10 SPQ4
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board). This topic also
describes how to configure and commission the SPQ4.
11.11 D12B
technical specifications of the D12B (32xE1/T1 access board).
11.12 D12S
technical specifications of the D12S (32xE1/T1 switching access board).
11.13 D75S
technical specifications of the D75S (32xE1 switching access board).
11.14 D34S
11.15 C34S
technical specifications of the C34S (3xE3/T3 switching access board).
11.16 MU04
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).
11.17 DM12
technical specifications of the DM12 (DDN service interface board).
11.18 TSB4
technical specifications of the TSB4 (4-channel electrical interface protection switching board).
11.19 TSB8
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11.1 PQ1
technical specifications of the PQ1 (63xE1 service processing board). This topic also describes
how to configure and commission the PQ1.

The PQ1 is available in the following functional versions: N1 and N2. The functions provided
by the functional versions are different. The N1PQ1 is discontinued.
NOTE
Depending on the port impedance, the PQ1 is available in PQ1A (75 ohms) and PQ1B (120 ohms). Except
this, the two boards are the same in function and feature. When the port impedance does not need to be
present, the PQ1A and PQ1B are referred to as the PQ1.
Table 11-1 describes the versions of the PQ1.

Table 11-1 Versions of the PQ1
Item
Description
Functional versions
The PQ1 is available in the following functional versions: N1 and N2.
Differences
l Service processing: E13 function.

l Maintenance features: CRC function, PRBS test.
Substitution
When the tributary re-timing function is not required, the N1PQ1A

can be replaced with the N2PQ1A.
When the tributary re-timing function is not required, the N1PQ1B
can be replaced with the N2PQ1B.
Note: The PQ1 boards are classified into the PQ1A boards (75 ohms) and PQ1B boards (120
ohms) according to the interface impedance. When the interface impedance is not considered,
the PQ1A and PQ1B are called PQ1 hereafter.
11.1.2 Application
The PQ1 is a PDH processing board. The PQ1 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To transmit/receive and process 63xE1 signals, the PQ1 must be
used with the interface board.
Figure 11-1 shows the application of the PDH processing boards. The PDH processing boards
add tributary signals to line signals and drops tributary signals to line signals.
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Figure 11-1 Networking and application of the PDH processing boards
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PQ1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
Table 11-2 provides the functions and features of the PQ1.
Table 11-2 Functions and features of the PQ1
Issue 03 (2013-02-20)
Function
and
Feature
PQ1
N1PQ1
N2PQ1
Basic
functions
Processes 63xE1
signals.
Processes 63xE1 signals.
Service
processing
Processes 63xE1
electrical signals
when working with
the interface board.
l Processes 63xE1 electrical signals when working

with the interface board.
l Supports the E13 function, which is used to
converge E1 services into E3 services.
Overhead
processing
Supports the processing of the path overheads at the VC-12 level, such as the
J2 byte.
Alarms and
performanc
e events


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Function
and
Feature
PQ1
Maintenan
ce features
l Supports inloops and outloops at electrical interfaces.
N1PQ1
N2PQ1
services.
l The N1PQ1 supports the PRBS test in the tributary direction and in the
cross-connect direction.
l The N2PQ1:
Supports the PRBS test in the tributary direction and in the cross-connect
direction in the normal mode.
Does not support the PRBS test in the MUX mode or Server mode.
l The N1PQ1 does not support the CRC function, but the N2PQ1 supports
the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board.
l The N1PQ1 supports hybrid protection. When the working board is the
N1PQ1, the protection board can be the N1PQ1, N2PQ1, or N1PQM.
l The N2PQ1 does not support hybrid protection. When the working board
is the N2PQ1, the protection board can only be the N2PQ1.

The PQ1 consists of the interface module, mapping/demapping module, interface converting
Figure 11-2 shows the functional block diagram of the PQ1.
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Figure 11-2 Functional block diagram of the PQ1

Backplane
155 MHz
PLL
2 MHz
OSC
E1
63x2 Mbit/s
LIU
PPI
E1
LIU
Mapping/
Demapping
module
63x2 Mbit/s
155 Mbit/s
155 Mbit/s
Reference
clock
Cross-connect
unit
High-speed
bus
Cross-connect
unit A
Interface
converting
module High-speed
bus
Cross-connect
unit B
Interface
module
LOS
Outloop/Inloop
control
Cross-connect
unit
Frame header
Communication
Logic and
control module
+3.3 V
Power
module
Power
module
SCC unit
Fuse
-48 V/-60 V
-48V/-60V
Fuse
+3.3 V backup power
LIU: logic interface unit
PPI: PDH physical interface
OSC: oscillator
Figure 11-3 shows the functional block diagram of the mapping/demapping module.
Figure 11-3 Functional block diagram of the mapping/demapping module
Mapping/demapping module
E1
LPA
LPT
PDH AIS
detector
E1
LPA
LPOH(V5/J2/N2/
K4) insertion
LPOH(V5/J2/N2/
K4) extraction
LPT
HPA
HPT
STM-1
TU-AIS/TULOP detector
HPA
HPT
STM-1
Interface Module
The interface module consists of LIUs and provides the inloop and outloop functions. The
interface module performs the following functions:
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Encodes and decodes signals.
Restores the data signal and the clock signal.
Processes the PDH LOS signals.
11 PDH Boards
Mapping/Demapping Module
l
LPA sub-module
The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.
LPT sub-module
The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C-12 container and POH. The POH contains nine octets equally distributed within the frame
bytes for VC-12, namely, V5, J2, N2, and K4.
HPA sub-module
The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TU-12s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2>TUG3->VC-4
HPT sub-module
C4 container and POH.
MST sub-module and RST sub-module

These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.
Interface Converting Module

The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.

l
units.
Control the indicators on the board.
Power Module
require.
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11.1.5 Front Panel

The front panel of the PQ1 has indicators.

Figure 11-4 shows the appearance of the front panel of the PQ1.
Figure 11-4 Front panel of the PQ1
PQ1
STAT
ACT
PROG
SRV
PQ1
Indicators
l
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Interfaces
The front panel of the PQ1 does not have an interface.
The D75S, D12S, and D12B provide 75-ohm or 120-ohm E1 interfaces for the PQ1. For details,
see the topics that describe the D75S, D12S, and D12B.

The PQ1 does not have any jumpers or DIP switches that are used for board settings.
11.1.7 Valid Slots

The PQ1 must be installed in a valid slot in the subrack. Otherwise, the PQ1 fails to work
normally.
The PQ1 can be installed in slots 15 and 1316 in the main subrack.
Table 11-3 lists the slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and
D12B in the main subrack.
Table 11-3 Slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and D12B
in the main subrack
Slot Valid for the PQ1
Corresponding Slots for the D75S, D12S,

and D12B
Slot 1
Without an interface board
Slot 2
Slot 19 (132 channels of services)

Slot 3

Slot 4

Slot 5

Slot 13

Slot 14

Slot 15

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11 PDH Boards
Corresponding Slots for the D75S, D12S,

and D12B
Slot 16

NOTE
l Slot 1 can house a protection board for the TPS protection. The board in slot 1 protects the boards in
slots 25 and 1316.
l If the interface board for the boards in slots 25 and 1316 is the D12B, the boards in slots 25 and
1316 cannot be protected by the TPS protection scheme.
11.1.8 Feature Code

The feature code of the PQ1 indicates the type of interface impedance.
Table 11-4 provides the relationship between the feature code of the PQ1 and the type of
interface impedance.
Table 11-4 Relationship between the feature code of the PQ1 and the type of interface impedance
Board
Feature Code
Type of Interface Impedance
SSN1PQ1A01 and SSN2PQ1A01
A01
75-ohm
SSN1PQ1B01 and SSN2PQ1B01
B01
120-ohm

The PQ1 supports the 1:N TPS protection.
The PQ1 boards work with the D75S or D12S boards to realize one 1:N (N8) TPS protection
group.
Figure 11-5 shows the TPS protection provided by the PQ1. When the cross-connect and timing
board detects that a working PQ1 is faulty, the cross-connect and timing board issues a service
switching command to control the interface board to switch the services from the faulty PQ1 to
the protection PQ1, which realizes the protection of the services.
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11 PDH Boards
Figure 11-5 TPS protection provided by the PQ1

Service signal
Service signal
Switching
control bus
Interface board
Protection bus
Protection bus
Crossconnect and
timing board
Interface board
Interface board
Interface board
Interface board
Interface board
Working board N
Working board
Working board 1
Protection board
Failed
NOTE
Table 11-5 shows the slot configuration for the 1:8 TPS protection of the PQ1.
Table 11-5 Slot configuration for the 1:8 TPS protection of the PQ1
Issue 03 (2013-02-20)
Working Board
Protection Board
Slot Configuration
PQ1A (75-ohm)
PQ1A (75-ohm)
PQ1B (120-ohm)
PQ1B (120-ohm) or PQM
Slot 1 can house a protection board.

The board in slot 1 protects the boards
in slots 2-5 and 13-16. Figure 11-6
shows the slot configuration for the 1:8
TPS protection of the PQ1.

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11 PDH Boards
D12S
D12S
D12S
D12S
D12S
D12S
PIU
PIU
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
1
0
XCS
XCS
S
L
O
T
1
1
S
L
O
T
1
2
S
L
O
T
3
6
S
L
O
T
3
7
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working
S
L
O
T
9
Working
S S S S
L L L L
O O O O
T T T T
5 6 7 8
S
L
O
T
3
5
FAN
Working
S
L
O
T
4
Working
FAN
Working
Working
Working
Protection
S S S
L L L
O O O
T T T
1 2 3
S
L
O
T
3
0
AUX
D12S
FAN
S
L
O
T
2
9
GSCC
S
L
O
T
2
8
D12S
S
L
O
T
2
7
S
L
O
T
2
4
Working
S
L
O
T
2
6
S
L
O
T
2
3
D12S
D12S
S
L
O
T
2
5
S
L
O
T
2
2
D12S
D12S
D12S
S
L
O
T
2
1
D12S
S
L
O
T
2
0
D12S
S
L
O
T
1
9
D12S
Figure 11-6 Slot configuration for the 1:8 TPS protection of the PQ1
Fiber routing area


impedance of the cable matches the impedance of the board.
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11 PDH Boards
is correct.
----End

Step 2 Required: Set the PDH interface.
Generally, use the default value. The default value of the J2 to be sent is HuaWei SBS and
the default value of the J2 to be received is Disabled.
l V5 byte: The setting of the V5 byte on the interconnected equipment must be consistent.
Generally, use the default value. The default value of the V5 byte is Asynchronous.
l Service load indication: When a service channel does not process its carried services, select
Non-Loaded. When the service channel processes its carried services, select Load.
Step 3 Optional: Create the protection. For details, see Creating a TPS Protection Group for Boards.
NOTE
Before you configure services, learn the type of protection subnet configured for the ring network. For the
method for querying the protection subnet, see 28.1 Querying the Protection Subnet.
Step 5 Set parameters on the U2000. For the parameters to be set, see 27.6 PDH Boards.
----End

Step 1 Required: Test the connection between the cable and the service interface. For details, see
Testing Connection Between the Cables and the PDH Service Interfaces.
Step 2 Optional: Test the TPS of the electrical interface. For details, see Testing the TPS of the
Electrical Interfaces.
----End

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11 PDH Boards
Boards.
the Current Alarms.
----End

You can set parameters for the PQ1 by using the U2000.
You can set the following parameters for the PQ1 by using the U2000:
l
J2 byte
V5 byte
Tributary loopback
Service loading indication

Troubleshooting
Table 11-6 lists the faults that occur on the PQ1 frequently and the troubleshooting methods.
Table 11-6 Methods used to troubleshoot the faults that occur on the PQ1 frequently
Fault
Symptom
Common Fault Cause
Service
interruption
l The cable or connector

becomes abnormal.

Interruptions.
performed.
l The types or settings of
the boards are
inconsistent.
Bit error
The equipment becomes

faulty.
Pointer
justification
l The clock configuration

is incorrect.
l The precision of the

external clock source is
very low.
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11 PDH Boards
Fault
Symptom
Common Fault Cause
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PQ1, see Replacing a PDH Board.

11.1.13.1 Alarms of N1PQ1

BD_STATUS
BIP_EXC
BIP_SD
CHIP_FAIL
COMMUN_FAIL
DOWN_E1_AIS
E1_LOC
LOOP_ALM
LP_RDI
LP_REI
LP_RFI
LP_SIZE_ERR
LP_SLM
LP_TIM
LP_UNEQ
NO_BD_SOFT
SWDL_PKG_NOBDSOFT
POWER_ABNORMAL
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
T_ALOS
T_LOSEX
TEST_STATUS
TPS_ALM
TR_LOC
TU_AIS
TU_LOP
UP_E1_AIS
V5_VCAIS
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
WRG_BD_TYPE
11.1.13.2 Alarms of N2PQ1
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B3_EXC
B3_SD
BD_STATUS
BIP_EXC
BIP_SD
C2_VCAIS

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11 PDH Boards
CHIP_ABN
CHIP_FAIL
COMMUN_FAIL
CRC4_ERR_OVER
DOWN_E1_AIS
LFA
LMFA
LOOP_ALM
LP_RDI
LP_REI
LP_RFI
LP_SLM
LP_UNEQ
NO_BD_SOFT
P_AIS
P_LOF
P_RAI
LP_TIM
POWER_ABNORMAL
SLAVE_WORKING
SUBCARD_ABN
T_ALOS
T_LOSEX
TEMP_OVER
TEST_STATUS
TPS_ALM
TR_LOC
TU_AIS
TU_LOP
UP_E1_AIS
V5_VCAIS
PATCH_ERR
SWDL_PKG_NOBDSOFT
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
WRG_BD_TYPE

11.1.14.1 Performance Events of N1PQ1

LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
TUPJCHIGH
TUPJCLOW
11.1.14.2 Performance Events of N2PQ1
Issue 03 (2013-02-20)
CRC4_ERR
E1_LCV_SDH
E1_LES_SDH
E1_LLOSS_SDH
E1_LSES_SDH
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
TUPJCHIGH
TUPJCLOW
VC3BBE

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11 PDH Boards
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS

The technical specifications of the PQ1 include the parameters specified for electrical interfaces,

The D75S, D12S, or D12B provides electrical interfaces for the PQ1. For the parameters
specified for the electrical interfaces, see Technical Specifications of the D75S, Technical
Specifications of the D12S and Technical Specifications of the D12B.
The mechanical specifications of the PQ1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1PQ1 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PQ1 at room temperature (25C) is 13 W.
11.2 PQM
technical specifications of the PQM (63xE1/T1 service processing board). This topic also
describes how to configure and commission the PQM.

The PQM is available in one functional version, namely, N1.
11.2.2 Application
The PQM is a PDH processing board. The PQM can be used on the OptiX OSN equipment series
to add and drop PDH signals. To transmit/receive and process 63xE1/T1 signals, the PQM must
be used with the interface board.
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NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PQM processes E1/T1 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 11-7 provides the functions and features of the PQM.
Table 11-7 Functions and features of the PQM
Issue 03 (2013-02-20)
Function
and Feature
PQM
Basic
functions
Processes 63xE1/T1 signals.
Service
processing
Transmits/Receives and processes 63xE1/T1 electrical signals when

working with the interface board. Each channel can be configured as E1 or
T1.
Overhead
processing
Supports the processing of the path overheads at the VC-12 level, such as
the J2 byte.
Alarms and
performance
events


618

Function
and Feature
PQM
Maintenance
features
11 PDH Boards
services.
l Supports the PRBS test in the tributary direction and in the cross-connect
direction.
l Supports the CRC function.
Protection
schemes
Supports the TPS Protection when working with the interface board.
l When the working board is the N1PQ1, the protection board can be the
N1PQ1, N2PQ1 or N1PQM. In this case, the hybrid protection is
provided.
l When the working board is the N1PQM, the protection board can only
be the N1PQM.

The PQM consists of the interface module, mapping/demapping module, interface converting
Figure 11-8 shows the functional block diagram of the PQM.
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Figure 11-8 Functional block diagram of the PQM

Backplane
155 MHz
PLL
1.5 MHz/2 MHz

OSC
E1/T1
63x1.5 Mbit/s
63x2 Mbit/s
LIU
PPI
E1/T1
LIU
Mapping/
Demapping
63x1.5 Mbit/s
module
63x2 Mbit/s
155 Mbit/s
155 Mbit/s
Reference
clock
Cross-connect
unit
High-speed
bus
Cross-connect
unit A
Interface
converting
module High-speed
bus
Cross-connect
unit B
Interface
module
LOS
Outloop/Inloop
control
Cross-connect
unit
Frame header
Communication
Logic and
control module
+3.3 V
Power
module
Power
module
SCC unit
Fuse
-48 V/-60 V
-48V/-60V
Fuse
+3.3 V backup power
OSC: oscillator
E1/T1
LPA
LPT
PDH AIS
detector
LPOH(V5/J2/N2/
K4) insertion
LPOH(V5/J2/N2/
K4) extraction
E1/T1
LPA
LPT
HPA
HPT
STM-1
HPA
HPT
STM-1
Interface Module
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l
LPA sub-module
The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.
LPT sub-module
bytes for VC-12, namely, V5, J2, N2, and K4.
HPA sub-module
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TU-12s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2>TUG3->VC-4
HPT sub-module

These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.


l
units.
Control the indicators on the board.
Power Module
require.
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11.2.5 Front Panel

The front panel of the PQM has indicators.

Figure 11-10 shows the appearance of the front panel of the PQM.
Figure 11-10 Front panel of the PQM
PQM
STAT
ACT
PROG
SRV
PQM
Indicators
l
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11 PDH Boards
Interfaces
The front panel of the PQM does not have an interface. The D12S and D12B provide 120-ohm
E1 interfaces or 100-ohm T1 interfaces for the PQM. For details, see the topics that describe the
D12S and D12B.

The PQM does not have any jumpers or DIP switches that are used for board settings.
11.2.7 Valid Slots

The PQM must be used with the D12S or D12B. In addition, the PQM must be installed in a
valid slot in the subrack. Otherwise, the PQM fails to work normally.
The PQM board can be installed in slots 15 and 1316 in the main subrack.
Table 11-8 lists the slots valid for the PQM and the corresponding slots for the D12S and D12B
in the main subrack.
Table 11-8 Slots valid for the PQM and the corresponding slots for the D12S and D12B in the
main subrack
Slot Valid for the PQM
Corresponding Slots for the D12S and

D12B
Slot 1
Slot 2

Slot 3

Slot 4

Slot 5

Slot 13

Slot 14

Slot 15

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11 PDH Boards
Slot Valid for the PQM
Corresponding Slots for the D12S and

D12B
Slot 16

NOTE
slots 25 and 1316.
l If the interface board for the boards in slots 25 and 1316 is the D12B, the boards in slots 25 and
1316 cannot be protected by the TPS protection scheme.
11.2.8 Feature Code

The PQM does not have a feature code.

The PQM supports the 1:N TPS protection.
The PQM boards can work with the D12S boards to realize one 1:N (N8) TPS protection group.
Figure 11-11 shows the TPS protection provided by the PQM.
Figure 11-11 TPS protection provided by the PQM (E1 services are provided as an example)
Service signal
Service signal
Switching
control bus
Interface board
Protection bus
Protection bus
Crossconnect and
timing board
Interface board
Interface board
Interface board
Interface board
Interface board
Working board N
Working board
Working board 1
Protection board
Failed
When the cross-connect and timing board detects that a working PQM is faulty, the cross-connect
and timing board issues a service switching command. Then, the interface board switches the
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11 PDH Boards
services from the faulty PQM to the protection PQM, which realizes the protection of the
services.
NOTE
Table 11-9 shows the slot configuration for the 1:8 TPS protection of the PQM.
Table 11-9 Slot configuration for the 1:8 TPS protection of the PQM
Working
Board
Protection Board
Slot Configuration
PQM (E1)
PQM (E1)
PQM (T1)
PQM (T1)
Slot 1 can house a protection board. The board

in slot 1 protects the boards in slots 2-5 and
13-16. Figure 11-12 shows the slot
configuration for the 1:8 TPS protection of the
PQM.
S
L
O
T
3
1
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
3
6
S
L
O
T
3
7
S
L
O
T
1
0
Protection
Working
Working
XCS
XCS
S
L
O
T
1
1
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working
Working
S
L
O
T
9
Working
S S S S
L L L L
O O O O
T T T T
5 6 7 8
FAN
Working
S
L
O
T
4
Working
S
L
O
T
3
3
FAN
S S S
L L L
O O O
T T T
1 2 3
Working
S
L
O
T
3
2
AUX
S
L
O
T
3
0
GSCC
FAN
S
L
O
T
2
9
D12S
S
L
O
T
2
8
D12S
D12S
S
L
O
T
2
7
D12S
D12S
D12S
S
L
O
T
2
6
D12S
S
L
O
T
2
5
S
L
O
T
2
4
D12S
D12S
D12S
D12S
S
L
O
T
2
3
PIU
D12S
S
L
O
T
2
2
PIU
S
L
O
T
2
1
D12S
S
L
O
T
2
0
D12S
D12S
S
L
O
T
1
9
D12S
Figure 11-12 Slot configuration for the 1:8 TPS protection of the PQM
Fiber routing area
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11 PDH Boards


is correct.
----End

NOTE
----End
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11 PDH Boards

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the PQM by using the U2000.
You can set the following parameters for the PQM by using the U2000:
l
J2 byte
V5 byte
Tributary loopback

Troubleshooting
Table 11-10 lists the faults that occur on the PQM frequently and the troubleshooting methods.
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Table 11-10 Methods used to troubleshoot the faults that occur on the PQM frequently
Fault
Symptom
Common Fault Cause
Service
interruption

becomes abnormal.

Interruptions.
performed.
the boards are
inconsistent.
Bit error

faulty.
Pointer
justification

is incorrect.

very low.
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PQM, see Replacing a PDH Board.

11.2.13.1 Alarms of N1PQM
Issue 03 (2013-02-20)
BIP_EXC
BD_STATUS
BIP_SD
CHIP_FAIL
COMMUN_FAIL
CRC4_ERR_OVER
CRC6_ERR_OVER
DOWN_E1_AIS
DOWN_T1_AIS
E1_LOC
LFA
LMFA
LOOP_ALM
LP_RDI
LP_REI
LP_SIZE_ERR
LP_SLM
LP_RFI

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11 PDH Boards
LP_TIM
LP_UNEQ
NO_BD_SOFT
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
RMFA
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
T_ALOS
T_LOSEX
TEST_STATUS
TPS_ALM
TR_LOC
TS16_AIS
TU_AIS
TU_LOP
UP_E1_AIS
UP_T1AIS
V5_VCAIS
RFA
SWDL_PKG_NOBDSOFT
POWER_ABNORMAL
WRG_BD_TYPE

11.2.14.1 Performance Events of N1PQM

CRC4_ERR
CRC6_ERR
E1_LCV_SDH
E1_LES_SDH
E1_LSES_SDH
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
T1_LCV_SDH
T1_LES_SDH
T1_LSES_SDH
TUPJCHIGH
TUPJCLOW

The technical specifications of the PQM include the parameters specified for electrical

The D12S or D12B provides electrical interfaces for the PQM. For the parameters specified for
the electrical interfaces, see Technical Specifications of the D12S and Technical Specifications
of the D12B.
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11 PDH Boards
The mechanical specifications of the PQM are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the PQM at room temperature (25C) is 22 W.
11.3 PFL1
technical specifications of the PFL1 (8xE1 optical processing board). This topic also describes
how to configure and commission the PFL1.

The PFL1 is available in one functional version, N1.
11.3.2 Application
The PFL1 is a PDH processing board. The PFL1 can be used on the OptiX OSN equipment
series to receive/transmit and process 8xE1 optical signals.
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board
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11 PDH Boards

The PFL1 processes E1 optical signals and overheads, and supports alarms, performance events,
and maintenance features.
Table 11-11 provides the functions and features of the PFL1.
Table 11-11 Functions and features of the PFL1
Function and
Feature
PFL1
Basic functions
Processes 8xE1 optical signals.
Service
processing
Receives/Transmits and processes 8xE1 optical signals.
Optical port
specifications
Supports I-2M optical ports, which comply with standards defined by

Huawei.
Optical module
specifications
l Supports the detection and query of information about an optical

module.
l Allows setting the on/off state of a laser and supports the automatic laser
shutdown (ALS) function.
l Supports the usage and monitoring of eSFP optical modules, facilitating
optical module maintenance.
Overhead
processing
Processes path overheads at the VC-12 level, such as J2 bytes.
Alarms and
performance
events
Provides various alarms and performance events, facilitating equipment

management and maintenance.
Maintenance
features
l Supports inloops and outloops at optical ports.

l Supports warm resets and cold resets. Warm resets do not affect ongoing
services.
l Supports the query of board manufacturer information.
l Supports in-service FPGA loading.
l Supports board software upgrades without affecting ongoing services.
l Supports the PRBS test in the tributary direction and in the crossconnect direction.
Protection
scheme
TPS protection is not supported.

The PFL1 consists of the client-side receive/transmit module, mapping/demapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-14 shows the functional block diagram of the PFL1.
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11 PDH Boards
Figure 11-14 Functional block diagram of the PFL1

Backplane
E1
Clientside
interface
module
Interface
converting
module
Mapping/Demappi
ng module
Cross-connect
unit A/B
Communication
Logic and control module
32 MHz
38 MHz
58 MHz
66 MHz
Cross-connect
unit A/B
Clock
module
Reference clock and frame header
+3.3 V
Power
module
Power
module
Fuse
Fuse
SCC unit
Cross-connect
unit A/B
-48 V/-60 V
-48 V/-60 V
+3.3 V backup
power
Client-Side Receive/Transmit Module

The client-side receive/transmit module performs the following functions:
l
In the receive direction, converts received optical signals into electrical signals.
In the transmit direction, converts received electrical signals into E1 optical signals.
Detects the T_ALOS alarm and provides the ALS function.
The mapping/demapping module maps 8xE1 signals into VC-4 signals or demaps VC-4 signals
into 8xE1 signals by using asynchronous mapping.

The interface converting module converts the signal bus into a parallel bus. The interface
converting module connects the high-rate backplane interface to the low-rate interface chip of
the transmit system.

The logic control module collects and reports information about board status. This module
contains basic logic units and performs the following functions:
l
Recovers clock signals from an optical module.
Realizes inter-board communication using internal Ethernet interfaces.
Selects and traces clock signals from the active and standby cross-connect units.
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Selects clock signals and frame header signals from the active and standby cross-connect
units.
Controls board indicators.
Clock Module
The clock module provides the desired reference clock to boards.
Power Module
The power module converts the -48 V/-60 V power supply into required DC voltages.
11.3.5 Front Panel

The front panel of the PFL1 has indicators.

Figure 11-15 shows the front panel of the PFL1.
Figure 11-15 Front panel of the PFL1
PFL1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
TX1 RX1
TX2 RX2
TX3 RX3
TX4 RX4
TX5 RX5
TX6 RX6
TX7 RX7
TX8 RX8
PFL1
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11 PDH Boards
Indicators
l
Interfaces
The front panel of the PFL1 has eight optical interfaces. Table 11-12 describes the types and
usage of the optical interfaces on the PFL1.
Table 11-12 Electrical ports on the PFL1
Port
Port Type
Usage
RX1-RX8
LC
TX1-TX8
LC

The PFL1 does not have any jumpers or DIP switches for board settings.
11.3.7 Valid Slots

The PFL1 must be installed in a valid slot in the subrack. Otherwise, the PFL1 fails to work
properly.
The PFL1 can be installed in slots 1-8 and slots 11-16.
11.3.8 Feature Code

The PFL1 does not have a feature code.

tasks need to be performed: checking the board hardware, configuring the board, commissioning
the board, and checking the operation of the board.
Checking the Board Hardware

Step 1 Required: Check the board hardware.
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11 PDH Boards
l The labels on the front panel of the board are correct and clear.
l The daughter board of the board is properly installed.
l All the components on both surfaces of the board are available and intact.
Step 2 Required: Verify that cables match the board.
Step 3 Required: Insert the board. For details, see Replacing Boards Onsite. Ensure that the board is
in proper contact with the bottom of the subrack and the front panel of the board is properly
locked.
Step 4 Required: Verify that the version of the board software matches the version of the NE software
and the version of the U2000 software.
----End

Step 1 Required: Add a logical board. For details, see Adding Boards.
Step 2 Required: Set the PDH port.
l J2 byte: The settings of the J2 byte on the interconnected equipment must be consistent.
l V5 byte: The settings of the V5 byte on the interconnected equipment must be consistent.
l Service load indication: If a service channel does not process its carried services, select NonLoaded. If a service channel processes its carried services, select Load.
Step 4 Optional: Set parameters on the U2000. For details, see 27.6 PDH Boards.
----End

Step 1 Required: Test the optical port specifications. For details, see Testing Specifications of Optical
Interfaces.
----End

Boards.
Issue 03 (2013-02-20)

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11 PDH Boards
the Current Alarms.
----End

You can set parameters for the PFL1 by using the U2000.
You can set the following parameters for the PFL1 by using the U2000:
l
J2 byte
V5 byte
Tributary loopback

Troubleshooting
Table 11-13 lists the faults that occur on the PFL1 frequently and the troubleshooting methods.
NOTE
The PFL1 uses an SFP optical module. If the PFL1 operates and an abnormal alarm occurs on the optical
interface, check whether the optical module is properly installed. To check whether the optical module is
properly installed, you can reseat the optical module.
Table 11-13 Methods used to rectify the faults that occur on the PFL1 frequently
Fault
Symptom
Common Fault Cause
Service
interruption
l The optical fiber or

connector is faulty.

Interruptions.
performed.
the boards are
inconsistent.
Bit error
l The equipment becomes

faulty.
l The optical power

becomes abnormal.
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11 PDH Boards
Fault
Symptom
Common Fault Cause
Pointer
justification

is incorrect.

very low.
Replacing the Board

NOTE
replace the board.
For information about how to replace the PFL1, see Replacing a PDH Board.

11.3.12.1 Alarms of N1PFL1

T_ALOS
LP_SIZE_ERR
UP_E1_AIS
BIP_EXC
BIP_SD
LP_RFI
TU_AIS
TU_LOP
LP_UNEQ
LP_TIM
LP_SLM
LP_RDI
LP_REI
LOOP_ALM
CHIP_FAIL
NO_BD_SOFT
POWER_ABNORMAL
TEST_STATUS
T_LOSEX
TR_LOC
V5_VCAIS
SLAVE_WORKING
DOWN_E1_AIS
COMMUN_FAIL
BD_STATUS
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
TF
IN_PWR_ABN
OUT_PWR_ABN
LSR_WILL_DIE
LSR_COOL_ALM
TEM_HA
TEM_LA
LASER_SHUT
LSR_NO_FITED
LASER_MOD_ERR
ALM_ALS
WRG_BD_TYPE
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11.3.13.1 Performance Events of N1PFL1

LPBBE
LPES
LPUAS
LPCSES
LPSES
LPFEBBE
LPFEES
LPFESES
LPFEUAS
LPFECSES
TUPJCHIGH
TUPJCLOW
TLBMAX
TLBMIN
TLBCUR
OSPICCVMAX
OSPICCVMIN
OSPICCVCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR

The technical specifications of the PFL1 include the parameters specified for optical interfaces,

Table 11-14 lists the parameters specified for the optical interfaces of the PFL1.
Table 11-14 Parameters specified for the optical interfaces of the PFL1
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
2048 kbit/s
Line code type
NRZ
Type of optical interface
I-2M
0 to 2

(nm)
1260 to 1360
Type of fiber
Single-mode LC
Launched optical power (dBm)
-15 to -8

638

Parameter
Value
Optical receiver sensitivity

(dBm)
-23
-8
8.2

width (nm)
Side mode suppression ratio

(dB)
11 PDH Boards
Laser Safety Class

The mechanical specifications of the PFL1 are as follows:
l
Weight (kg): 1.0
Power consumption
The maximum power consumption of the PFL1 at room temperature (25C) is 17 W.
11.4 PL3
technical specifications of the PL3 (3xE3/T3 service processing board). This topic also describes
how to configure and commission the PL3.

The PL3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PL3 is discontinued.
Table 11-15 describes the versions of the PL3.
Table 11-15 Versions of the PL3
Issue 03 (2013-02-20)
Item
Description
Functional versions
The PL3 is available in two functional versions, namely, N1 and N2.

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11 PDH Boards
Item
Description
Differences
l Service processing: E13 function and M13 function.

l Maintenance features: PRBS test and CRC function.
Substitution
The N2PL3 can replace the N1PL3.
11.4.2 Application
The PL3 is a PDH processing board. The PL3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To transmit/receive and process 3xE3/T3 signals, the PL3 must
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PL3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
Table 11-16 provides the functions and features of the PL3.
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11 PDH Boards
Table 11-16 Functions and features of the PL3

Function and
Feature
PL3
Basic functions
Service processing
Transmits/Receives and processes 3xE3/T3 electrical signals.

The N2PL3 supports the E13 function, which is used to converge E1
services into E3 services.
The N2PL3 supports the M13 function, which is used to converge T1
services into T3 services.
Overhead
processing
Supports the setting and query of all the path overhead bytes at the VC-3
level.
Alarms and
performance
events

Maintenance
features

services.
services.
l The N1PL3 supports the PRBS test in only the tributary direction.
l The N2PL3:
Supports the PRBS test in the tributary direction and in the crossconnect direction in the normal mode.
Does not support the PRBS test in the Server mode.
Support the PRBS test in the electrical interface direction in the
MUX mode.
l The N1PL3 does not support the CRC function, but the N2PL3
supports the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board
and the switching and bridging board.

The PL3 consists of the interface module, mapping/demapping module, interface converting
Figure 11-17 shows the functional block diagram of the PL3.
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11 PDH Boards
Figure 11-17 Functional block diagram of the PL3

Backplane
155 MHz
PLL
34 MHz/45 MHz
OSC
E3/T3
3x34 Mbit/s
3x45 Mbit/s
LIU
PPI
E3/T3
LIU
2x155 Mbit/s
Mapping/
Demapping
3x34 Mbit/s
2x155 Mbit/s
module
3x45 Mbit/s
Reference
clock
High-speed
bus
Interface
converting
module High-speed
bus
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
Interface
module
LOS
Outloop/Inloop
control
Cross-connect
unit
Frame header
Communication
Logic and
control module
+3.3 V
Power
module
Power
module
SCC unit
Fuse
-48 V/-60 V
-48V/-60V
Fuse
+3.3 V backup power
OSC: oscillator
E3/T3
LPA
LPT
PDH AIS
detector
E3/T3
LPA
LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction
LPT
HPA
HPT
STM-1
HPA
HPT
STM-1
LPA: low order path adaptation
LPT: low order path termination
HPA: high order path adaptation
HPT: high order path termination
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11 PDH Boards
Interface Module
l
Processes the P_LOS alarm.
l
LPA sub-module
The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so that the stream can be transported to the synchronous network.
LPT sub-module
bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
HPA sub-module
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4
HPT sub-module

These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.


l
units.
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11 PDH Boards
Power Module
require.
11.4.5 Front Panel

The front panel of the PL3 has indicators.

Figure 11-19 shows the appearance of the front panel of the PL3.
Figure 11-19 Front panel of the PL3
PL3
STAT
ACT
PROG
SRV
PL3
Indicators
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11 PDH Boards
Interfaces
The front panel of the PL3 does not have an interface.
The C34S provides E3/T3 interfaces for the PL3. For details, see the topic that describes the
C34S.

The PL3 does not have any jumpers or DIP switches that are used for board settings.
11.4.7 Valid Slots

The PL3 must be used with the C34S. In addition, the PL3 must be installed in a valid slot in
the subrack. Otherwise, the PL3 cannot work normally.
The PL3 can be installed in slots 25 and 1316 in the main subrack.
The PL3 must be used with the C34S.
Table 11-17 lists the slots valid for the PL3 and the corresponding slots for the C34S in the main
subrack.
Table 11-17 Slots valid for the PL3 and the corresponding slots for the C34S in the main subrack
Slot Valid for the PL3
Corresponding Slot for the C34S
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35
11.4.8 Feature Code

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11 PDH Boards

The PL3 supports the 1:N TPS protection.
The PL3 can be configured into two 1:N (N3) TPS protection groups when the PL3 works with
the C34S and TSB8/TSB4.
Figure 11-20 shows the TPS protection provided by the PL3.
Figure 11-20 TPS protection provided by the PL3 in the OptiX OSN 1500B subrack
Service signal
Service signal
Switching
control bus
Crossconnect and
timing board
Interface board N
Interface board
Working board N
Working board
Working board 1
Protection board
Interface board 1
Protection
switching board
Failed
Normal state
board.
Switching state
NOTE
Table 11-18 shows the slot configuration for the 1:3 TPS protection of the PL3.
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Table 11-18 Slot configuration for the 1:3 TPS protection of the PL3
Working
Board
Protection Board
Slot Configuration
PL3 (E3)
PL3 (E3)/PD3 (E3)
PL3 (T3)
PL3 (T3)/PD3 (T3)
If the working board is the PL3, the PD3

can be the protection board. Figure 11-21
shows the slot configuration for the 1:3 TPS
protection of the PL3.
FAN
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
1
0
Working 1
Working 1
XCS
XCS
S
L
O
T
1
1
S
L
O
T
1
2
S
L
O
T
3
6
S
L
O
T
3
7
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working 2
S
L
O
T
9
Working 2
S S S S
L L L L
O O O O
T T T T
5 6 7 8
S
L
O
T
3
5
FAN
Working 2
S
L
O
T
4
Protection 1
FAN
S S S
L L L
O O O
T T T
1 2 3
Working 1
S
L
O
T
3
0
AUX
S
L
O
T
2
9
GSCC
S
L
O
T
2
8
TSB8/TSB4
S
L
O
T
2
7
Protection 2
S
L
O
T
2
6
C34S
S
L
O
T
2
5
C34S
S
L
O
T
2
4
C34S
S
L
O
T
2
3
PIU
C34S
S
L
O
T
2
2
C34S
S
L
O
T
2
1
C34S
S
L
O
T
2
0
TSB8/TSB4
S
L
O
T
1
9
PIU
Figure 11-21 Slot configuration for the two 1:3 TPS protection groups of the PL3
Fiber routing area
Table 11-19 lists the slots for the PL3, C34S, and TSB8/TSB4.
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11 PDH Boards
Table 11-19 Slots for the PL3, C34S, and TSB8/TSB4

Board
Protection Group 1
Protection Group 2
PL3 (working board)
Slots 3, 4, and 5
PL3 (protection board)
Slot 2
Slot 16
TSB8/TSB4
Slot 19
Slot 35
C34S


is correct.
----End

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11 PDH Boards
NOTE
----End

----End

Boards.
the Current Alarms.
----End

You can set the parameters for the PL3 by using the U2000.
You can set the following parameters for the PL3 by using the U2000:
l
J1 byte
C2 byte
Tributary loopback
Path service type

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11 PDH Boards

Troubleshooting
Table 11-20 lists the faults that occur on the PL3 frequently and the troubleshooting methods.
Table 11-20 Methods used to troubleshoot the faults that occur on the PL3 frequently
Fault
Symptom
Common Fault Cause
Service
interruption

becomes abnormal.

Interruptions.
performed.
the boards are
inconsistent.
Bit error

faulty.
Pointer
justification

is incorrect.

very low.
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PL3, see Replacing a PDH Board.

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11.4.13.1 Alarms of N1PL3

A_LOC
B3_EXC
B3_SD
BD_STATUS
BDID_ERROR
C2_VCAIS
CHIP_FAIL
COMMUN_FAIL
FPGA_ABN
LOOP_ALM
LP_R_FIFO
LP_RDI
LP_REI
LP_SLM
LP_T_FIFO
LP_TIM
LP_UNEQ
NO_BD_SOFT
P_AIS
P_LOS
PLL_FAIL
POWER_ABNORMAL
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
T_LOSEX
TEST_STATUS
TPS_ALM
TR_LOC
TU_AIS
TU_LOP
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
11.4.13.2 Alarms of N2PL3
Issue 03 (2013-02-20)
B3_EXC
B3_SD
BD_STATUS
BIP_EXC
BIP_SD
C2_VCAIS
CHIP_ABN
CHIP_FAIL
COMMUN_FAIL
CRC6_ERR_OVER
DOWN_E1_AIS
DOWN_T1_AIS
DS3_IDLE
CRC4_ERR_OVER
LFA
LMFA
LOOP_ALM
LP_RFI
LP_RDI
LP_REI
LP_TIM
LP_SLM
NO_BD_SOFT
P_AIS
LP_UNEQ
P_LOF
P_LOS
P_RAI
SUBCARD_ABN
POWER_ABNORMAL
SLAVE_WORKING
TEST_STATUS
T_LOSEX
TEMP_OVER
TU_AIS
TPS_ALM
TR_LOC
UP_T1AIS
TU_LOP
UP_E1_AIS
PATCH_NOT_CONFIRM
V5_VCAIS

651

PATCH_ERR
SWDL_PKG_NOBDSOFT
P_FFM
WRG_BD_TYPE
11 PDH Boards
PATCHFILE_NOTEXIST

11.4.14.1 Performance Events of N1PL3

E3_LCV_SDH
E3_LES_SDH
E3_LSES_SDH
T3_LCV_SDH
T3_LES_SDH
T3_LSES_SDH
TUPJCHIGH
TUPJCLOW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
11.4.14.2 Performance Events of N2PL3

CRC4_ERR
CRC6_ERR
E3_LCV_SDH
E3_LES_SDH
E3_LSES_SDH
LPBBE
LPES
LPFEBBE
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
T3_LCV_SDH
T3_LES_SDH
T3_LSES_SDH
TUPJCHIGH
TUPJCLOW
TUPJCNEW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
VC3FECSES
LPCSES
LPFECSES
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The technical specifications of the PL3 include the parameters specified for electrical interfaces,

The C34S provides electrical interfaces for the PL3. For the parameters specified for the
electrical interfaces, see Technical Specifications of the C34S.
The mechanical specifications of the PL3 are as follows:
l
Weight of the N1PL3 (kg): 1.0
Weight of the N2PL3 (kg): 0.9
Power Consumption
The maximum power consumption of the N1PL3 at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3 at room temperature (25C) is 12 W.
11.5 PL3A
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel). This topic also describes how to configure and commission the PL3A.

The PL3A is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PL3A is
discontinued.
Table 11-21 describes the versions of the PL3A.
Table 11-21 Versions of the PL3A
Item
Description
Functional versions
The PL3A is available in two functional versions, namely, N1 and

N2.
Differences

l Maintenance features: PRBS test and CRC function.
Substitution
Issue 03 (2013-02-20)
The N2PL3A can replace the N1PL3A.

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11 PDH Boards
11.5.2 Application
The PL3A is a PDH processing board. The PL3A can be used on the OptiX OSN equipment
series to add and drop PDH signals. To transmit/receive and process 3xE3/T3 signals, the PL3A
uses the interfaces on its front panel.
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PL3A processes E3/T3 signals, processes overhead bytes, reports alarms and performance
Table 11-22 provides the functions and features of the PL3A.
Table 11-22 Functions and features of the PL3A
Function and
Feature
PL3A
Basic functions
Service processing
Transmits/Receives and processes 3xE3/T3 electrical signals.

The N2PL3A supports the E13 function, which is used to converge E1
The N2PL3A supports the M13 function, which is used to converge
T1 services into T3 services.
Overhead
processing
Issue 03 (2013-02-20)
Supports the setting and query of all the path overhead bytes at the
VC-3 level.
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11 PDH Boards
Function and
Feature
PL3A
Alarms and
performance events

Maintenance
features

affect services.
services.
l The N1PL3A supports the PRBS test in only the tributary direction.
l The N2PL3A:
Supports the PRBS test in the tributary direction and in the
cross-connect direction in the normal mode.
MUX mode.
l The N1PLS3A does not support the CRC function, but the N2PL3A
supports the CRC function.

The PL3A consists of the interface module, mapping/demapping module, interface converting
Figure 11-23 shows the functional block diagram of the PL3A.
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11 PDH Boards
Figure 11-23 Functional block diagram of the PL3A

Backplane
155 MHz
PLL
34 MHz/45 MHz
OSC
E3/T3
3x34 Mbit/s
3x45 Mbit/s
LIU
PPI
E3/T3
LIU
2x155 Mbit/s
Mapping/
Demapping
3x34 Mbit/s
2x155 Mbit/s
module
3x45 Mbit/s
Reference
clock
High-speed
bus
Interface
converting
module High-speed
bus
Cross-connect
unit
Cross-connect
unit A
Cross-connect
unit B
Interface
module
LOS
Outloop/Inloop
control
Cross-connect
unit
Frame header
Communication
Logic and
control module
+3.3 V
Power
module
Power
module
SCC unit
Fuse
-48 V/-60 V
-48V/-60V
Fuse
+3.3 V backup power
OSC: oscillator
E3/T3
LPA
LPT
PDH AIS
detector
E3/T3
LPA
LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction
LPT
HPA
HPT
STM-1
HPA
HPT
STM-1
LPA: low order path adaptation
LPT: low order path termination
HPA: high order path adaptation
HPT: high order path termination
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11 PDH Boards
Interface Module
l
l
LPA sub-module
LPT sub-module
bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
HPA sub-module
HPT sub-module



l
units.
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11 PDH Boards
Power Module
require.
11.5.5 Front Panel

The front panel of the PL3A has indicators and interfaces.

Figure 11-25 shows the appearance of the front panel of the PL3A.
Figure 11-25 Front panel of the PL3A
PL3A
STAT
ACT
PROG
SRV
OUT1
IN1
OUT2
IN2
OUT3
IN3
PL3A
Indicators
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11 PDH Boards
Interfaces
The front panel of the PL3A has three pairs of 75-ohm unbalanced interfaces, which are of the
SMB type.

The PL3A does not have any jumpers or DIP switches that are used for board settings.
11.5.7 Valid Slots

The PL3A must be installed in a valid slot in the subrack. Otherwise, the PL3A cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the PL3A vary with the cross-connect capacity of the subrack. The slots valid
for the PL3A are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the PL3A can be installed in slots 18 and
1117 in the main subrack.
11.5.8 Feature Code



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11 PDH Boards
is correct.
----End

NOTE
----End

----End

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11 PDH Boards
Boards.
the Current Alarms.
----End

You can set the parameters for the PL3A by using the U2000.
You can set the following parameters for the PL3A by using the U2000:
l
J1 byte
C2 byte
Tributary loopback
Path service type

Troubleshooting
Table 11-23 lists the faults that occur on the PL3A frequently and the troubleshooting methods.
Table 11-23 Methods used to troubleshoot the faults that occur on the PL3A frequently
Fault
Symptom
Common Fault Cause
Service
interruption

becomes abnormal.

Interruptions.
performed.
the boards are
inconsistent.
Bit error
Issue 03 (2013-02-20)

faulty.

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11 PDH Boards
Fault
Symptom
Common Fault Cause
Pointer
justification

is incorrect.

very low.
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the PL3A, see Replacing a PDH Board.

11.5.12.1 Alarms of N1PL3A

A_LOC
B3_EXC
B3_SD
BD_STATUS
BDID_ERROR
C2_VCAIS
CHIP_FAIL
COMMUN_FAIL
FPGA_ABN
LOOP_ALM
LP_R_FIFO
LP_RDI
LP_REI
LP_SLM
LP_T_FIFO
LP_TIM
LP_UNEQ
NO_BD_SOFT
P_AIS
P_LOS
PLL_FAIL
POWER_ABNORMAL
SLAVE_WORKING
T_LOSEX
TEST_STATUS
TR_LOC
TU_AIS
TU_LOP
W_R_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
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11 PDH Boards
11.5.12.2 Alarms of N2PL3A

BD_STATUS
B3_EXC
B3_SD
BIP_SD
C2_VCAIS
BIP_EXC
CHIP_FAIL
COMMUN_FAIL
CHIP_ABN
CRC6_ERR_OVER
DOWN_E1_AIS
CRC4_ERR_OVER
DS3_IDLE
LOOP_ALM
DOWN_T1_AIS
LMFA
LP_REI
LFA
LP_RDI
NO_BD_SOFT
LP_RFI
LP_SLM
P_LOF
LP_TIM
LP_UNEQ
P_AIS
P_FFM
P_RAI
TPS_ALM
UP_E1_AIS
SLAVE_WORKING
SUBCARD_ABN
P_LOS
TEMP_OVER
TEST_STATUS
POWER_ABNORMAL
TU_AIS
TU_LOP
T_LOSEX
V5_VCAIS
PATCH_ERR
TR_LOC
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
UP_T1AIS
PATCH_NOT_CONFIRM
WRG_BD_TYPE

11.5.13.1 Performance Events of N1PL3A

E3_LCV_SDH
E3_LES_SDH
E3_LSES_SDH
T3_LCV_SDH
T3_LES_SDH
T3_LSES_SDH
TUPJCHIGH
TUPJCLOW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
TUPJCNEW
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11 PDH Boards
11.5.13.2 Performance Events of N2PL3A

CRC4_ERR
CRC6_ERR
E3_LCV_SDH
E3_LES_SDH
E3_LSES_SDH
LPBBE
LPES
LPFEBBE
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
T3_LCV_SDH
T3_LES_SDH
T3_LSES_SDH
TUPJCHIGH
TUPJCLOW
TUPJCNEW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
VC3FECSES
LPCSES
LPFECSES

The technical specifications of the PL3A include the parameters specified for electrical

Table 11-24 lists the parameters specified for the electrical interfaces of the PL3A.
Table 11-24 Parameters specified for the electrical interfaces of the PL3A
Nominal bit rate
34368 kbit/s
44736 kbit/s
Line code pattern
HDB3
B3ZS
Waveform at the output

interface
Signal bit rate at the output

interface
interface
Issue 03 (2013-02-20)
Allowed frequency deviation at

the input interface
Complies with ITU-T G.

823.


824.
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11 PDH Boards
Nominal bit rate
34368 kbit/s
44736 kbit/s
Anti-interference capability at
the input interface

703.
Reflection attenuation at the

input/output interface
Output jitter
Complies with ITU-T G.823 and G.824.
Mapping jitter
Combined jitter
Jitter transfer function

751.
The mechanical specifications of the PL3A are as follows:
l
Weight of the N1PL3A (kg): 1.0
Weight of the N2PL3A (kg): 0.9
Power Consumption
The maximum power consumption of the N1PL3A at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3A at room temperature (25C) is 12 W.
11.6 PD3
technical specifications of the PD3 (6xE3/T3 service processing board).

The PD3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PD3 is
no longer manufactured.
Table 11-25 describes the versions of the PD3.
Table 11-25 Versions of the PD3
Issue 03 (2013-02-20)
Item
Description
Functional
versions
The PD3 is available in two functional versions, namely, N1 and N2.

665

11 PDH Boards
Item
Description
Differences

l Maintenance features: CRC function, PRBS test.
Substitution
The N2PD3 can replace the N1PD3.
11.6.2 Application
The PD3 is a PDH processing board. The PD3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To transmit/receive and process 6xE3/T3 signals, the PD3 must
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PD3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
Table 11-26 provides the functions and features of the PD3.
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11 PDH Boards
Table 11-26 Functions and features of the PD3

Function
and Feature
PD3
Basic
functions
Service
processing
l Transmits/Receives and processes 6xE3/T3 electrical signals.

l The N2PD3 supports the E13 function, which is used to converge E1
l The N2PD3 supports the M13 function, which is used to converge T1
services into T3 services.
Overhead
processing
level.
Alarms and
performance
events

Maintenance
features

services.
l The N1PD3 supports the PRBS test in only the tributary direction.
l The N2PD3:
Does not support the PRBS test in the MUX mode or Server mode.
l The N1PD3 does not support the CRC function, but the N2PD3 supports
the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board and the
switching and bridging board.

The PD3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 11-27 shows the functional block diagram of the PD3.
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11 PDH Boards
Figure 11-27 Functional block diagram of the PD3

34 MHz/
45 MHz
OSC
E3/T3
E3/T3
LIU
LIU
P
I
155 MHz
PLL
6x34 Mbit/s/
6x45 Mbit/s
2x155 Mbit/s
E3/T3
Interface
mapping/
converting
6x34 Mbit/s/
demapping
module
2x155 Mbit/s
6x45 Mbit/s
module
LOS
Outloop/Inloop
control
Cross-connect unit
Highspeed bus
Highspeed bus
Frame header
Communication
Logic and
control module
+3.3 V
DC/DC
converter
OSC: Oscillator
Reference
clock
DC/DC
converter
Cross-connect unit
SCC Unit
Fuse
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power
Figure 11-28 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 11-28 Functional block diagram of the E3/T3 mapping/demapping module
E3/T3
LPA
HPA
LPT
PDH AIS
detector
E3/T3
LPA
LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction
HPT
STM-1
HPA
LPT
HPT
STM-1
LPA: Low order path adaptation
LPT: Low order path termination
HPA: High order path adaptation
HPT: High order path termination

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PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l
E3/T3 Mapping/Demapping Module

l
LPA sub-module

LPT sub-module
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
HPA sub-module
HPT sub-module


l
units.
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11 PDH Boards
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
11.6.5 Front Panel

The front panel of the PD3 has indicators.

Figure 11-29 shows the appearance of the front panel of the PD3.
Figure 11-29 Front panel of the PD3
PD3
STAT
ACT
PROG
SRV
PD3
Indicators
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Interfaces
The front panel of the PD3 does not have an interface.
The D34S provides E3/T3 interfaces for the PD3. For details, see the topic that describes the
D34S.
11.6.6 Valid Slots

The PD3 must be used with the D34S.
The PD3 can be installed in slots 25 and 1316 in the main subrack.
Table 11-27 lists the slots valid for the PD3 and the corresponding slots for the D34S in the
main subrack.
Table 11-27 Slots valid for the PD3 and the corresponding slots for the D34S in the main subrack
Slot Valid for the PD3
Corresponding Slot for the D34S
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The PD3 supports the 1:N TPS protection.
The PD3 can be configured into two 1:N (N3) TPS protection groups when the PD3 works
with the D34S and TSB8. Figure 11-30 shows the TPS protection provided by the PD3.
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11 PDH Boards
Figure 11-30 TPS protection provided by the PD3

6xE3/T3
TSB8
6xE3/T3
D34S
6xE3/T3
Sw itching
control
D34S
signal
D34S
Crossconnect
and timing
board
Slot 9/10
Protection
PD3
Working
PD3
Working
PD3
Working
PD3
Failed
Slot 2
Slot 3
Slot 4
Slot 5
Normal state
the PD3 through position 1 of the control switch on the D34S.
Switching state
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.
NOTE
Table 11-28 shows the slot configuration for the 1:3 TPS protection of the PD3.
Table 11-28 Slot configuration for the 1:3 TPS protection of the PD3
Issue 03 (2013-02-20)
Working
Board
Protection Board
Slot Configuration
PD3 (E3)
PD3 (E3)
PD3 (T3)
PD3 (T3)
Figure 11-31 shows the slot configuration for

the 1:3 TPS protection of the PD3.

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11 PDH Boards
FAN
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working 2
Working 1
S
L
O
T
1
1
Working 2
Working 1
S
L
O
T
1
0
S
L
O
T
3
7
FAN
Working 2
Protection 1
S
L
O
T
9
XCS
S S S S
L L L L
O O O O
T T T T
5 6 7 8
XCS
S
L
O
T
4
S
L
O
T
3
6
AUX
S
L
O
T
3
0
FAN
S S S
L L L
O O O
T T T
1 2 3
Working 1
S
L
O
T
2
9
GSCC
S
L
O
T
2
8
TSB8
S
L
O
T
2
7
Protection 2
S
L
O
T
2
6
D34S
S
L
O
T
2
5
D34S
S
L
O
T
2
4
D34S
S
L
O
T
2
3
PIU
D34S
S
L
O
T
2
2
D34S
S
L
O
T
2
1
D34S
S
L
O
T
2
0
TSB8
S
L
O
T
1
9
PIU
Figure 11-31 Slot configuration for the 1:3 TPS protection of the PD3
Fiber routing area
Table 11-29 lists the slots for the PD3, D34S, and TSB8.
Table 11-29 Slots for the PD3, D34S, and TSB8
Issue 03 (2013-02-20)
Board
Protection Group 1
Protection Group 2
PD3 (working board)
Slots 3-5
Slots 13-15
PD3 (protection board)
Slot 2
Slot 16
TSB8
Slot 19
Slot 35
D34S

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You can set the parameters for the PD3 by using the U2000.
You can set the following parameters for the PD3 by using the U2000:
l
J1 byte
C2 byte
Tributary loopback
Path service type

The technical specifications of the PD3 include the parameters specified for electrical interfaces,

The C34S provides electrical interfaces for the PD3. For the parameters specified for the
electrical interfaces, see Technical Specifications of the D34S.
The mechanical specifications of the PD3 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the N1PD3 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PD3 at room temperature (25C) is 12 W.
11.7 PQ3
technical specifications of the PQ3 (12xE3/T3 service processing board).

The PQ3 is available in one functional version, namely, N2.
11.7.2 Application
The PQ3 is a PDH processing board. The PQ3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To transmit/receive and process 12xE3/T3 signals, the PQ3 must
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11 PDH Boards
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The PQ3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
Table 11-30 provides the functions and features of the PQ3.
Table 11-30 Functions and features of the PQ3
Function and
Feature
PQ3
Basic functions
Service
processing
l Transmits/Receives and processes 12xE3/T3 electrical signals.

l Supports the E13 function, which is used to converge E1 services into
E3 services.
l Supports the M13 function, which is used to converge T1 services into
T3 services.
Issue 03 (2013-02-20)
Overhead
processing
level.
Alarms and
performance
events


675

Function and
Feature
PQ3
Maintenance
features
11 PDH Boards
services.
l PRBS function:
MUX mode.
Protection
schemes
Supports the TPS protection when working with the interface board and the
switching and bridging board.

The PQ3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 11-33 shows the functional block diagram of the PQ3.
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Figure 11-33 Functional block diagram of the PQ3

34 MHz/
45 MHz
OSC
E3/T3
E3/T3
LIU
LIU
P
I
155 MHz
PLL
12x34 Mbit/s/
12x45 Mbit/s
2x155 Mbit/s
E3/T3
Interface
mapping/
converting
12x34 Mbit/s/
demapping
module
2x155 Mbit/s
12x45 Mbit/s
module
LOS
Outloop/Inloop
control
Cross-connect unit
Highspeed bus
Highspeed bus
Frame header
Communication
Logic and
control module
+3.3 V
DC/DC
converter
OSC: Oscillator
Reference
clock
DC/DC
converter
Cross-connect unit
SCC Unit
Fuse
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power
Figure 11-34 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 11-34 Functional block diagram of the E3/T3 mapping/demapping module
E3/T3
LPA
HPA
LPT
PDH AIS
detector
E3/T3
LPA
LPOH (J1/C2/
B3) insertion
LPOH (J1/C2/
B3) extraction
HPT
STM-1
HPA
LPT
HPT
STM-1
LPA: Low order path adaptation
LPT: Low order path termination
HPA: High order path adaptation
HPT: High order path termination
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PPI Module
l
E3/T3 Mapping/Demapping Module

l
LPA sub-module

LPT sub-module
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
HPA sub-module
HPT sub-module


l
units.
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DC/DC Converter
require.
11.7.5 Front Panel

The front panel of the PQ3 has indicators.

Figure 11-35 shows the appearance of the front panel of the PQ3.
Figure 11-35 Front panel of the PQ3
PQ3
STAT
ACT
PROG
SRV
PQ3
Indicators
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11 PDH Boards
Interfaces
The front panel of the PQ3 does not have an interface.
The D34S provides E3/T3 interfaces for the PQ3. For details, see the topic that describes the
D34S.
11.7.6 Valid Slots

The PQ3 can be installed in slots 25 and 1316, and must be used with the D34S.
Table 11-31 lists the slots valid for the PQ3 and the corresponding slots for the D34S.
Table 11-31 Slots valid for the PQ3 and the corresponding slots for the D34S
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The PQ3 supports the 1:N TPS protection.
The PQ3 boards can be configured into two 1:N (N3) TPS protection groups when the PQ3
boards work with two D34S boards and two TSB8 boards. Figure 11-36 shows the TPS
protection provided by the PQ3.
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Figure 11-36 TPS protection provided by the PQ3

12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3 12xE3/T3
TSB8
TSB8
3 2
D34S
D34S
D34S
D34S
Sw itching
control
D34S signal
D34S
Crossconnect
and timing
board
Slot 9/10
Protection
Working
PQ3
PQ3
Slot 2
Slot 3
Working
PQ3
Failed
Slot 4
Working
PQ3
Slot 5
Normal state
the PQ3 through position 1 of the control switch on the D34S.
Switching state
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.
NOTE
NOTE
When you configure the N2PQ3 as the TPS protection board, two TSB8 boards are required.
Table 11-32 shows the slot configuration for the 1:3 TPS protection of the PQ3.
Table 11-32 Slot configuration for the 1:3 TPS protection of the PQ3
Issue 03 (2013-02-20)
Working
Board
Protection Board
Slot Configuration
PQ3 (E3)
PQ3 (E3)
PQ3 (T3)
PQ3 (T3)
Figure 11-37 shows the slot configuration for

the 1:3 TPS protection of the PQ3.

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11 PDH Boards
D34S
D34S
D34S
D34S
D34S
D34S
PIU
PIU
S
L
O
T
3
5
S
L
O
T
3
6
S
L
O
T
3
7
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
1
0
XCS
XCS
S
L
O
T
1
1
S
L
O
T
1
2
S
L
O
T
1
3
S S S S S
L L L L L
O O O O O
T T T T T
1 1 1 1 1
4 5 6 7 8
Working 2
S
L
O
T
9
FAN
Working 2
S S S S
L L L L
O O O O
T T T T
5 6 7 8
Working 1
Working 1
Working 1
S
L
O
T
3
1
AUX
TSB8
Protection 1
S
L
O
T
3
0
FAN
FAN
S S S S
L L L L
O O O O
T T T T
1 2 3 4
S
L
O
T
2
9
GSCC
S
L
O
T
2
8
TSB8
S
L
O
T
2
7
S
L
O
T
2
4
Protection 2
S
L
O
T
2
6
S
L
O
T
2
3
Working 2
S
L
O
T
2
5
S
L
O
T
2
2
D34S
D34S
D34S
D34S
TSB8
S
L
O
T
2
1
D34S
S
L
O
T
2
0
D34S
S
L
O
T
1
9
TSB8
Figure 11-37 Slot configuration for the two 1:3 TPS protection groups of the PQ3
Fiber routing area
Table 11-33 lists the slots for the PQ3, D34S, and TSB8.
Table 11-33 Slots for the PQ3, D34S, and TSB8
Board
Protection Group 1
Protection Group 2
PQ3 (working board)
Slots 3-5
Slots 13-15
PQ3 (protection board)
Slot 2
Slot 16
TSB8
Slots 19 and 20
Slots 35 and 36
D34S
Slots 21-26
Slots 29-34

You can set the parameters for the PQ3 by using the U2000.
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11 PDH Boards
You can set the following parameters for the PQ3 by using the U2000:
l
J1 byte
C2 byte
Tributary loopback
Path service type

The technical specifications of the PQ3 include the parameters specified for electrical interfaces,

The D34S provides electrical interfaces for the PQ3. For the parameters specified for the
electrical interfaces, see Technical Specifications of the D34S.
The mechanical specifications of the PQ3 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the PQ3 at room temperature (25C) is 13 W.
11.8 DX1
technical specifications of the DX1 (DDN service accessing and converging board). This topic
also describes how to configure and commission the DX1.

The DX1 is available in one functional version, namely, N1.
11.8.2 Application
The DX1 is a DDN service processing board. The DX1 can be used on the OptiX OSN equipment
series to add and converge the DDN services. To receive eight channels of Nx64 kbit/s signals
and eight channels of framed E1 services and to cross-connect the 48 channels of Nx64 kbit/s
signals on the system side, the DX1 must be used with the interface board.
Figure 11-38 shows the application of the DDN service processing boards. The DDN service
processing boards add DDN service signals to line signals and drops line signals to DDN service
signals.
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11 PDH Boards
Figure 11-38 Networking and application of the DDN service processing boards
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The DX1 cross-connects 48xE1 signals at the 64 kbit/s level on the system side.
Table 11-34 provides the functions and features of the DX1.
Table 11-34 Functions and features of the DX1
Function
and
Feature
DX1
Basic
functions
l Processes eight channels of Nx64 kbit/s services and eight channels of

framed E1 services.
l Cross-connects 48 channels of Nx64 kbit/s signals on the system side.
Service
processing
l Transmits/Receives eight channels of Nx64 kbit/s and eight channels of

framed E1 services and realizes the 1:N TPS protection when working with
the DM12.
l One DX1 board needs to work with two DM12 boards.
Alarms and
performance
events

Maintenance
features

l Supports the PRBS test in the cross-connect direction and in the electrical
interface direction.
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11 PDH Boards
Function
and
Feature
DX1
Connectors
The DB28 connectors and DB44 connectors are present on the front panel of
the DM12. The DB28 connector is used for the Nx64 kbit/s signals, and the
DB44 connector is used for the framed E1 signals.
Protection
schemes
Supports the TPS protection when working with the interface board.

The DX1 consists of the interface and frame processing module, encoding/decoding module,
timeslot cross-connect module, framing/deframing module, mapping/demapping module, logic
and control module, and power module.
Figure 11-39 shows the functional block diagram of the DX1.
Figure 11-39 Functional block diagram of the DX1
Backplane
DM12
8xFrame E1
Framed E1
interface
module
4xNx64 kbit/s
Nx64 kbit/s
interface
module
Power
DM12
4xNx64 kbit/s
Nx64 kbit/s
interface
module
Backplane
DX1 Framed E1
encoding/
decoding and
frame processing
module
Nx64 kbit/s
interface
and frame
processing
module
64 kbit/s
timeslot
cross-connect
module
Framing/
Deframing
module
Logic and
control module
Power
Framed E1
interface
module
+3.3 V
Power
module
Power
module
Mapping/
Demapping
module for
48 channels
of signals
Cross-connect
unit
SCC unit
Fuse
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power
In the Transmit Direction

The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module crossconnects and grooms the signals at the 64 kbit/s granularity, and transmits the signals that need
to be dropped on the local NE to the interface module.
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In the Receive Direction

The DX1 transmits/receives eight channels of framed E1 signals from the framed E1 interface
module of the DM12 and eight channels of Nx64 kbit/s signals from the Nx64 kbit/s interface
module of the DM12. In addition, the DX1 restores the data signal and clock signal.
In the case of the framed E1 signals, the DX1 decodes the signals and processes the frames. In
the case of the Nx64 kbit/s signals, the DX1 converts the signals and processes the frames. Then,
the DX1 transmits the signals to the 64 kbit/s timeslot cross-connect module. The timeslot crossconnect module cross-connects and grooms the signals at the 64 kbit/s granularity, and transmits
the signals to the framing/deframing module. Finally, the framing/deframing module maps the
signals into VC-4s and transmits the signals to the SDH cross-connect unit.

The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.
Power Module
The power module provides all the modules of the DX1 with the required DC voltages.
11.8.5 Front Panel

The front panel of the DX1 has indicators.

Figure 11-40 shows the appearance of the front panel of the DX1.
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11 PDH Boards
Figure 11-40 Front panel of the DX1
DX1
STAT
ACT
PROG
SRV
DX1
Indicators
l
Interfaces
The front panel of the DX1 does not have an interface.
One DX1 board needs to work with two DM12 boards to receive and transmit the framed E1
signals and Nx64 kbit/s signals. For details, see the topic that describes the DM12.
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11 PDH Boards

The DX1 does not have any jumpers or DIP switches that are used for board settings.
11.8.7 Valid Slots

The DX1 must be used with the DM12. In addition, the DX1 must be installed in a valid slot in
the subrack. Otherwise, the DX1 cannot work normally.
The DX1 can be installed in slots 15 and 1316.
Table 11-35 lists the slots valid for the DX1 and the corresponding slots for the DM12.
Table 11-35 Slots valid for the DX1 and the corresponding slots for the DM12
Slot Valid for the DX1
Corresponding Slot for the DM12
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
NOTE
slots 25 and 1316.
l One DX1 needs to work with two DM12 boards to transmit/receive eight channels of Nx64 kbit/s
signals. The DM12 in the slot with a smaller slot number is used to transmit/receive eight channels of
framed E1 signals and four channels of Nx64 kbit/s signals. The DM12 in the slot with a larger slot
number is used to transmit/receive four channels of Nx64 kbit/s signals.
11.8.8 Feature Code

The feature code of the DX1 indicates the type of interface impedance.
Table 11-36 provides the relationship between the feature code of the DX1 and the type of
interface impedance.
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Table 11-36 Relationship between the feature code of the DX1 and the type of interface
impedance
Board
Feature Code
Type of Interface Impedance
SSN1DX1A01
A01
75-ohm
SSN1DX1B01
B01
120-ohm

The DX1 supports the 1:N TPS protection.
The DX1 can be configured into one 1:N (N8) TPS protection group when the DX1 works with
the DM12.
Figure 11-41 shows the TPS protection provided by the DX1.
Figure 11-41 TPS protection provided by the DX1
Service signal
Service signal
Switching
control bus
Interface board
Protection bus
Protection bus
Crossconnect and
timing board
Interface board
Interface board
Interface board
Interface board
Interface board
Working board N
Working board
Working board 1
Protection board
Failed
When the cross-connect and timing board detects that a working DX1 is faulty, the cross-connect
and timing board issues a service switching command to control the interface board to switch
the services from the faulty board to the protection board, which realizes the protection of the
services.
Figure 11-42 shows the slot configuration for the 1:8 TPS protection of the DX1.
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11 PDH Boards
DM12
DM12
PIU
PIU
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
3
6
S
L
O
T
3
3
Working
S
L
O
T
1
1
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working
Working
S
L
O
T
1
0
Working
Protection
S
L
O
T
9
S
L
O
T
3
7
FAN
Working
S S S S
L L L L
O O O O
T T T T
5 6 7 8
XCS
S
L
O
T
4
XCS
S S S
L L L
O O O
T T T
1 2 3
Working
S
L
O
T
3
2
AUX
DM12
DM12
DM12
DM12
DM12
S
L
O
T
3
1
S
L
O
T
2
9
FAN
FAN
Working
S
L
O
T
3
0
DM12
S
L
O
T
2
8
GSCC
S
L
O
T
2
7
DM12
S
L
O
T
2
6
S
L
O
T
2
3
Working
S
L
O
T
2
5
S
L
O
T
2
2
DM12
DM12
DM12
S
L
O
T
2
4
S
L
O
T
2
1
DM12
S
L
O
T
2
0
DM12
DM12
S
L
O
T
1
9
DM12
Figure 11-42 Slot configuration for the 1:8 TPS protection of the DX1
Fiber routing area
In Figure 11-42, the board in slot 1 protects the boards in slots 25 and 1316.
Table 11-37 lists the slots for the DX1 and DM12.
Table 11-37 Slots for the DX1 and DM12
Issue 03 (2013-02-20)
Board
Protection Group
DX1 (working board)
Slots 25 and 1316
DX1 (protection board)
Slot 1
DM12
Slots 1926 and 2936

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is correct.
----End

NOTE
----End
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----End

Boards.
the Current Alarms.
----End

You can set the parameters for the DX1 by using the U2000.
You can set the following parameters for the DX1 by using the U2000:
l
J2 byte
Tributary loopback
Protocol mode of serial ports
DDN clock source management

Troubleshooting
Table 11-38 lists the faults that occur on the DX1 frequently and the troubleshooting methods.
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Table 11-38 Methods used to troubleshoot the faults that occur on the DX1 frequently
Fault
Symptom
Common Fault Cause
Service
interruption

becomes abnormal.

Interruptions.
performed.
the boards are
inconsistent.
Bit error

faulty.
Pointer
justification

is incorrect.

very low.
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the DX1, see Replacing a PDH Board.

11.8.13.1 Alarms of N1DX1
Issue 03 (2013-02-20)
BD_STATUS
BDID_ERROR
BIP_EXC
BIP_SD
CHIP_ABN
CHIP_FAIL
COMMUN_FAIL
CRC4_ERR_OVER
CTS
DCD
DDN_AIS
DDN_ALOS
DDN_CRC4_ERR_OVER
DDN_LFA
DDN_LMFA
DDN_LOOP_ALM
DDN_RFA
DDN_RMFA

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DOWN_E1_AIS
DSR
DTR
E1_LOC
FPGA_ABN
LFA
LMFA
LOOP_ALM
LP_R_FIFO
LP_RDI
LP_REI
LP_RFI
LP_SLM
LP_T_FIFO
LP_TIM
LP_UNEQ
NO_BD_SOFT
PLL_FAIL
POWER_ABNORMAL
R_FIFO_E
RFA
RMFA
RTS
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
TEMP_OVER
T_FIFO_E
T_LOSEX
TR_LOC
TEST_STATUS
TPS_ALM
UP_E1_AIS
TU_AIS
TU_LOP
PATCH_NOT_CONFIRM
V5_VCAIS
PATCH_ERR
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

11.8.14.1 Performance Events of N1DX1

LPBBE
LPCSES
LPFECSES
LPFEUAS
LPES
LPSES
LPUAS
LPFEBBE
LPFEES
LPFESES
TUPJCHIGH
TUPJCLOW
CRC4_ERR
DDN_CRC4_ERR

The technical specifications of the DX1 include the parameters specified for electrical interfaces,
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The DM12 provides electrical interfaces for the DX1. For the parameters specified for the
electrical interfaces, see Technical Specifications of the DM12.
The mechanical specifications of the DX1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the DX1 at room temperature (25C) is 15 W.
11.9 DXA
technical specifications of the DXA (DDN service converging and processing board).

The DXA is available in one functional version, namely, N1.
11.9.2 Application
The DXA is a DDN service processing board. The DXA can be used on the OptiX OSN
equipment series to transmit/receive and converge DDN services. To cross-connect the 63
channels of Nx64 kbit/s signals and framed E1 signals on the system side.
Figure 11-43 shows the application of the DDN service processing boards. The DDN service
processing boards add DDN service signals to line signals and drops line signals to DDN service
signals.
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Figure 11-43 Networking and application of the DDN service processing boards
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The DXA cross-connects 63xE1 signals at the 64 kbit/s level on the system side.
Table 11-39 provides the functions and features of the DXA.
Table 11-39 Functions and features of the DXA
Function and
Feature
DXA
Basic functions
Cross-connects 63 channels of framed E1 signals.
Alarms and
performance events

Maintenance
features
Supports inloops and outloops.

Supports the CRC function.

The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/
demapping module, logic and control module, and power module.
Figure 11-44 shows the functional block diagram of the DXA.
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Figure 11-44 Functional block diagram of the DXA

Backplane
64 kbit/s
timeslot
crossconnect
module
Framing/
Deframing
module
Signal
mapping/
demapping
module
Logic and
control module
+3.3 V
Power
module
Power
module
Crossconnect unit
SCC unit
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V
+3.3 V
backup power

The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module crossconnects and grooms the signals at the 64 kbit/s granularity.

The timeslot cross-connect module cross-connects and grooms the signals at the 64 kbit/s
granularity, and transmits the signals to the framing/deframing module. Then, the framing/
deframing module maps the signals into VC-4s and transmits the signals to the SDH crossconnect unit.

The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.
Power Module
The power module provides all the modules of the DX1 with the required DC voltages.
11.9.5 Front Panel

The front panel of the DXA has indicators.
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Figure 11-45 shows the appearance of the front panel of the DXA.
Figure 11-45 Front panel of the DXA
DXA
STAT
ACT
PROG
SRV
DXA
Indicators
l

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Interfaces
The front panel of the DXA does not have an interface.
11.9.6 Valid Slots

The slots valid for the DXA vary with the cross-connect capacity of the subrack.
The slots valid for the DXA are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the DXA can be installed in slots 18 and
1117.

You can set the parameters for the DXA by using the U2000.
You can set the following parameters for the DXA by using the U2000:
l
J2 byte
Tributary loopback
Protocol mode of serial ports
DDN clock source management

The technical specifications of the DXA include the mechanical specifications and power
consumption.
The mechanical specifications of the DXA are as follows:
l
Weight (kg): 0.8
Power Consumption
The maximum power consumption of the DXA at room temperature (25C) is 10 W.
11.10 SPQ4
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board). This topic also
describes how to configure and commission the SPQ4.

The SPQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1SPQ4 is discontinued.
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Table 11-40 describes the versions of the SPQ4.

Table 11-40 Versions of the SPQ4
Item
Description
Functional versions
The SPQ4 is available in two functional versions, namely, N1 and N2.
Differences
The equipment of the V100R001 and V100R002 versions supports

the N1SPQ4. The equipment of the V100R003 and later versions
supports the N2SPQ2.
Substitution
The N1SPQ4 can be replaced with the N2SPQ4. When the N1SPQ4
is replaced with the N2SPQ4, the NE software needs to be upgraded.
11.10.2 Application
The SPQ4 is a PDH processing board. The SPQ4 can be used on the OptiX OSN equipment
series to transmit and receive E4/STM-1 electrical signals. To transmit/receive and process
4xE4/STM-1 electrical signals, the SPQ4 must be used with the interface board.
NE1
NE2
NE4
NE3
Service flow
Line board
Tributary board

The SPQ4 processes 4xE4/STM-1 electrical signals, processes overhead bytes, reports alarms
and performance events, provides maintenance features, and supports protection schemes.
Table 11-41 provides the functions and features of the SPQ4.
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Table 11-41 Functions and features of the SPQ4

Function and
Feature
SPQ4
Basic functions
Processes 4xSTM-1/E4 signals.
Service
processing
Transmits/Receives and processes 4xE4/STM-1 electrical signals. The

E4 signals and STM-1 signals are compatible on each channel. Supports
the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals, such as B1,

B2, K1, K2, M1, F1, and D1D12.
overhead bytes including J1, B3, C2, G1, and H4.
l Supports the setting and query of the J0, J1, and C2 bytes.
Alarms and
performance
events

Maintenance
features

services.
l Does not support the CRC function.
Protection
schemes
l Supports the TPS protection when working with the interface board
and the switching and bridging board.

The SPQ4 consists of the interface module, mapping/demapping module, SDH overhead
processing module, interface converting module, logic and control module, and power module.
Figure 11-47 shows the functional block diagram of the SPQ4. Figure 11-48 shows the
functional block diagram of the mapping/demapping module. Figure 11-49 shows the functional
block diagram of the SDH overhead processing module.
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Figure 11-47 Functional block diagram of the SPQ4

155 MHz
PLL
34 MHz
OSC
LIU
LIU
PPI/SPI
E4/STM-1
Mapping/
4x139 Mbit/s Demapping 4x155 Mbit/s
module
4x155 Mbit/s
Interface
module
SDH
overhead
processing
module
EN 140 Mbit/s/155 Mbit/s

LOS
4x155 Mbit/s
High-speed
bus
Interface
converting
module High-speed
bus
DCC
K1 and K2
Logic and
control module
Outloop/Inloop control
Backplane
Reference
Cross-connect
clock
unit
+3.3 V
Power
module
Cross-connect
unit A
Cross-connect
unit B
SCC unit
Cross-connect
unit
Frame header
Communication
Cross-connect
unit
SCC unit
Power
module
Fuse
Fuse
OSC: oscillator
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power

139 Mbit/s
155 Mbit/s
LPA
PDH AIS E4 AIS

detector insertion
139 Mbit/s
Issue 03 (2013-02-20)
SIPO
HPT
PG
J1/C2/B3
E4 AIS
insertion
LPA
HPT

MST
RST
MST
RST
155 Mbit/s
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Figure 11-49 Functional block diagram of the SDH overhead processing module
K1 and K2 insertion/
extraction
Cross-connect unit
155 Mbit/s
155 Mbit/s
155 Mbit/s
RST
MST
MSA
HPT
155 Mbit/s
DCC
SCC unit
Interface Module
l
The SPI module consists of LIUs and provides the inloop and outloop functions. The SPI module
l
Processes the R_LOS signals.
SDH Overhead Processing Module (155 Mbit/s SDH Signals)

The SDH overhead processing module performs the functions that are required to manage 155
Mbit/s SDH signals.
l
RST Sub-Module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), restores the regenerator section trace byte (J0), detects a J0 mismatch, and counts
BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, and performs BIP-8 calculation and byte insertion.
MST Sub-Module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI and MS_AIS.
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In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1 byte and K2 byte.
l
MSA Sub-Module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
AU-4 pointer and the AU_AIS.
HPT Sub-Module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Mapping/Demapping Module (140 Mbit/s PDH Signals)

The mapping/demapping module performs the functions that are required to manage 140 Mbit/
s PDH signals.
l
LPA Sub-Module
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so that
the stream can be transported to the synchronous network. The PDH AIS is monitored and
the E4 AIS in inserted.
HPT Sub-Module
C4 container and POH. The POH contains nine octets equally distributed within the frame.
The following overhead bytes can be extracted: J1, B3. C2, G1, F2, H4, F3, K3, and N1.
The E4 AIS can be inserted in the downstream direction.
Pointer generator (PG)

A fixed pointer value is inserted into the SOH to structure the AU-4 signal.
MST Sub-Module and RST Sub-Module

converting module can be connected. In the receive direction, these sub-modules detect the
frame alignment bytes (A1 and A2).


l
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the GSCC cannot be detected.
units.
Power Module
require.
11.10.5 Front Panel

The front panel of the SPQ4 has indicators.

Figure 11-50 shows the appearance of the front panel of the SPQ4.
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Figure 11-50 Front panel of the SPQ4
SPQ4
STAT
ACT
PROG
SRV
SPQ4
Indicators
l
Interfaces
The front panel of the SPQ4 does not have an interface. Hence, the SPQ4 needs to work with
the MU04 to receive and transmit the E4/STM-1 signals. For details, see the topic that describes
the MU04.
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The SPQ4 does not have any jumpers or DIP switches that are used for board settings.
11.10.7 Valid Slots

The SPQ4 must be used with the MU04. In addition, the SPQ4 must be installed in a valid slot
in the subrack. Otherwise, the SPQ4 fails to work normally.
The SPQ4 can be installed in slots 25 and 1316.
Table 11-42 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 11-42 Slots valid for the SPQ4 and the corresponding slots for the MU04
Slot Valid for the SPQ4
Corresponding Slot for the MU04
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The SPQ4 does not have a feature code.

The SPQ4 supports the 1:N TPS protection.
The SPQ4 can be configured into two 1:N (N3) TPS protection groups when the SPQ4 works
with the MU04 and TSB8/TSB4.
Figure 11-51 shows the TPS protection provided by the SPQ4.
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Figure 11-51 TPS protection provided by the SPQ4

Service signal
Service signal
Switching
control bus
Crossconnect and
timing board
Interface board N
Interface board
Working board N
Working board
Working board 1
Protection board
Interface board 1
Protection
switching board
Failed
Normal state
the working board through position 1 of the control switch on the interface board.
Switching state
NOTE
Figure 11-52 shows the slot configuration for the 1:3 TPS protection of the SPQ4.
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S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
5
S
L
O
T
3
4
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
GSCC
Working 1
S
L
O
T
1
1
Working 2
Working 1
S
L
O
T
1
0
Working 2
Protection 1
S
L
O
T
9
S
L
O
T
3
7
FAN
Working 2
S S S S
L L L L
O O O O
T T T T
5 6 7 8
XCS
S
L
O
T
4
XCS
S S S
L L L
O O O
T T T
1 2 3
S
L
O
T
3
6
AUX
S
L
O
T
3
0
FAN
FAN
Working 1
S
L
O
T
2
9
TSB8/TSB4
S
L
O
T
2
8
Protection 2
S
L
O
T
2
7
MU04
S
L
O
T
2
6
MU04
S
L
O
T
2
5
MU04
S
L
O
T
2
4
PIU
S
L
O
T
2
3
MU04
S
L
O
T
2
2
MU04
S
L
O
T
2
1
MU04
S
L
O
T
2
0
TSB8/TSB4
S
L
O
T
1
9
PIU
Figure 11-52 Slot configuration for the two 1:3 TPS protection groups of the SPQ4
Fiber routing area
Table 11-43 lists the slots for the SPQ4, MU04, and TSB8/TSB4.
Table 11-43 Slots for the SPQ4, MU04, and TSB8/TSB4
Issue 03 (2013-02-20)
Board
Protection Group 1
Protection Group 2
SPQ4 (working
board)
Slots 3-5
Slots 13-15
SPQ4 (protection
board)
Slot 2
Slot 16
MU04
TSB8/TSB4
Slot 19
Slot 35

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is correct.
----End

NOTE
----End
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----End

Boards.
the Current Alarms.
----End

You can set the parameters for the SPQ4 by using the U2000.
You can set the following parameters for the SPQ4 by using the U2000:
l
J1 byte
C2 byte

Troubleshooting
Table 11-44 lists the faults that occur on the SPQ4 frequently and the troubleshooting methods.
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Table 11-44 Methods used to troubleshoot the faults that occur on the SPQ4 frequently
Fault
Symptom
Common Fault Cause
Service
interruption

becomes abnormal.

Interruptions.
performed.
the boards are
inconsistent.
Bit error

faulty.
Pointer
justification

is incorrect.

very low.
Protection
switching
failure
The TPS fails.

Faults.
Replacing the Board

NOTE
replace the board.
For information on how to replace the SPQ4, see Replacing a PDH Board.

11.10.13.1 Alarms of N1SPQ4
Issue 03 (2013-02-20)
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BDID_ERROR
BIP_EXC
BIP_SD
BIP8_ECC
C4_R_LAISD
C4_T_LAISD
CHIP_FAIL

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COMMUN_FAIL
EXT_LOS
FPGA_ABN
FSELECT_STG
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
J0_MM
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OH_LOOP
PLL_FAIL
POWER_ABNORMAL
R_LOC
R_LOF
R_LOS
R_OOF
RELAY_FAIL
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
T_LOSEX
TEST_STATUS
TPS_ALM
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
BDID_ERROR
BIP_EXC
BIP_SD
BIP8_ECC
C4_R_LAISD
C4_T_LAISD
CHIP_FAIL
COMMUN_FAIL
EXT_LOS
FPGA_ABN
FSELECT_STG
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
J0_MM
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
11.10.13.2 Alarms of N2SPQ4
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LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OH_LOOP
PLL_FAIL
POWER_ABNORMAL
R_LOC
R_LOF
R_LOS
R_OOF
RELAY_FAIL
SLAVE_WORKING
SPARE_PATH_ALM
SUBCARD_ABN
T_LOSEX
TEST_STATUS
TPS_ALM
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
PS
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

11.10.14.1 Performance Events of N1SPQ4
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSOFS
RSSES
RSUAS

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11.10.14.2 Performance Events of N2SPQ4

AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSOFS
RSSES
RSUAS

The technical specifications of the SPQ4 include the parameters specified for electrical

The MU04 provides electrical interfaces for the SPQ4. For the parameters specified for the
electrical interfaces, see Technical Specifications of the MU04.
The mechanical specifications of the SPQ4 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the SPQ4 at room temperature (25C) is 24 W.
11.11 D12B
technical specifications of the D12B (32xE1/T1 access board).

The D12B is available in one functional version, namely, N1.
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11.11.2 Application
The D12B is a PDH interface board. The D12B can be used on the OptiX OSN equipment series
to transmit and receive signals for the PDH processing board. To transmit/receive and process
signals, the interface board must be used with its corresponding processing board.

The D12B receives and transmits 32xE1/T1 electrical signals. The D12B must work with the
PQ1, or PQM.

The D12B has the interface module.
Figure 11-53 shows the functional block diagram of the D12B by describing how to process
1xE1/T1 signals.
Figure 11-53 Functional block diagram of the D12B
Backplane
PQ1/PQM/PO1
E1/T1 electrical signal

Interface
module
E1/T1 electrical signal
PQ1/PQM/PO1
Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
11.11.5 Front Panel

The front panel of the D12B has interfaces and a bar code.

Figure 11-54 shows the appearance of the front panel of the D12B.
Issue 03 (2013-02-20)

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11 PDH Boards
Figure 11-54 Front panel of the D12B
D12B
1~8
9~16
17~24
25~32
D12B
Interfaces
The front panel of the D12B has four DB44 interfaces. Table 11-45 describes the types and
usage of the interfaces of the D12B.
Table 11-45 Interfaces of the D12B
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
18
DB44
Receives the 1st to the 8th channels of E1/T1

signals.
916
DB44
Receives the 9th to the 16th channels of E1/T1

signals.

717

11 PDH Boards
Interface
Type of
Interface
Usage
1724
DB44

signals.
2532
DB44
Receives the 25th to the 32nd channels of E1/T1

signals.
Table 11-46 provides the pin assignments of the DB44 interface.

Table 11-46 Pin assignments of the DB44 interface
Front View
30
15
44
Pin
Usage
Pin
Usage
38
Receives the 1st

channel of signals
(R1).
34
Receives the 5th

channel of signals
(R5).
Receives the 2nd

channel of signals
(R2).
33
Receives the 3rd

channel of signals
(R3).
32
Receives the 4th

channel of signals
(R4).
31
Transmits the 1st

channel of signals
(T1).
11
Transmits the 2nd

channel of signals
(T2).
10
Transmits the 3rd

channel of signals
(T3).
Transmits the 4th

channel of signals
(T4).
23
37
22
36
21
35
31
16
20
15
30
14
29
13
28
12
27
19
18
17
16
26
25
24
Receives the 6th

channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).
Transmits the 7th
channel of signals
(T7).
Transmits the 8th
channel of signals
(T8).
11.11.6 Valid Slots

The D12B can work as the interface board of the PQ1, or PQM.
The D12B can be installed in slots 1926 and 2936 in the main subrack.
Issue 03 (2013-02-20)

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11 PDH Boards
Table 11-47 lists the slots valid for the PQ1/PQM and the corresponding slots for the D12B.
The D12B installed in the slot with a smaller number transmits/receives the 1st to the 32nd
channels of E1/T1 electrical signals. The D12B installed in the slot with a larger number
transmits/receives the 33rd to the 63rd channels of E1/T1 electrical signals.
Table 11-47 Slots valid for the PQ1/PQM and the corresponding slots for the D12B
Slot Valid for the PQ1/PQM
Corresponding Slot for the D12B
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the D12B include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.

Table 11-48 Parameters specified for the electrical interfaces of the D12B
Nominal bit rate
1544 kbit/s
2048 kbit/s
Line code pattern
B8ZS and AMI
HDB3

interface

interface
interface
Issue 03 (2013-02-20)

the input interface

824.


823.
719

11 PDH Boards
Nominal bit rate
1544 kbit/s
2048 kbit/s
the input interface

703.

Output jitter
Mapping jitter
Combined jitter

742.
The mechanical specifications of the D12B are as follows:
l
Weight (kg): 0.3
Power Consumption
The maximum power consumption of the D12B at room temperature (25C) is 0 W.
11.12 D12S

The D12S is available in one functional version, namely, N1.
11.12.2 Application
The D12S is a PDH interface switching board. The D12S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.

The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must work with the
PQ1, or PQM.
Issue 03 (2013-02-20)

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11 PDH Boards

The D12S consists of the interface module, switch matrix module, and power access circuit.
Figure 11-55 shows the functional block diagram of the D12S by describing how to process
1xE1/T1 signals.
Figure 11-55 Functional block diagram of the D12S
Backplane
Cross-connect board
E1/T1 electrical
signal
Interface
module
Switch
matrix
module
E1/T1 electrical
signal
PQ1/PQM/PO1
PQ1/PQM/PO1
+3.3 V
Fuse
+3.3 V power
Interface Module

module transmits the signal to the PQ1 or PQM. When the TPS is performed, the switch matrix
module transmits the signal to the protection board for bridging.
Power Access Circuit

The power access circuit provides all the modules of the D12S with the required DC voltages.
11.12.5 Front Panel

The front panel of the D12S has interfaces and a bar code.

Figure 11-56 shows the appearance of the front panel of the D12S.
Issue 03 (2013-02-20)

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11 PDH Boards
Figure 11-56 Front panel of the D12S
D12S
1~8
9~16
17~24
25~32
D12S
Interfaces
The front panel of the D12S has four DB44 interfaces. Table 11-49 describes the types and
usage of the interfaces of the D12S.
Table 11-49 Interfaces of the D12S
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
18
DB44
Receives the 1st to the 8th channels of E1/T1 signals.
916
DB44

signals.

722

11 PDH Boards
Interface
Type of
Interface
Usage
1724
DB44

signals.
2532
DB44
Receives the 25th to the 32nd channels of E1/T1

signals.

Front View
30
15
44
Pin
Usage
Pin
Usage
38
Receives the 1st

channel of signals
(R1).
34
Receives the 5th

channel of signals
(R5).
Receives the 2nd

channel of signals
(R2).
33
Receives the 3rd

channel of signals
(R3).
32
Receives the 4th

channel of signals
(R4).
31
Transmits the 1st

channel of signals
(T1).
11
Transmits the 2nd

channel of signals
(T2).
10
Transmits the 3rd

channel of signals
(T3).
Transmits the 4th

channel of signals
(T4).
23
37
22
36
21
35
31
16
20
15
30
14
29
13
28
12
27
19
18
17
16
26
25
24
Receives the 6th

channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).
Transmits the 7th
channel of signals
(T7).
Transmits the 8th
channel of signals
(T8).
11.12.6 Valid Slots

The D12S can be installed in slots 1926 and 2936 in the main subrack. The D12S works as
the interface board of the PQ1, or PQM.
Issue 03 (2013-02-20)

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11 PDH Boards
Table 11-51 lists the slots valid for the PQ1/PQM and the corresponding slots for the D12S.
The D12S installed in the slot with a smaller number transmits/receives the 1st to the 32nd
channels of E1/T1 electrical signals. The D12S installed in the slot with a larger number
transmits/receives the 33rd to the 63rd channels of E1/T1 electrical signals.
Table 11-51 Slots valid for the PQ1/PQM and the corresponding slots for the D12S
Slot Valid for the PQ1/PQM
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the D12S include the parameters specified for the electrical

Table 11-52 Parameters specified for the electrical interfaces of the D12S
Nominal bit rate
1544 kbit/s
2048 kbit/s
Line code pattern
B8ZS and AMI
HDB3

interface

interface
interface
Issue 03 (2013-02-20)

the input interface

824.


823.
724

11 PDH Boards
Nominal bit rate
1544 kbit/s
2048 kbit/s
the input interface

703.

Output jitter
Mapping jitter
Combined jitter

742.
The mechanical specifications of the D12S are as follows:
l
Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the D12S is 0 W.
11.13 D75S
technical specifications of the D75S (32xE1 switching access board).

11.13.2 Application

The D75S receives and transmits 32xE1 electrical signals. The D75S must work with the PQ1.
Issue 03 (2013-02-20)

725

11 PDH Boards

1xE1 signals.
Backplane
Cross-connect board
E1 electrical signal
Interface
module
Switch
matrix
module
PQ1/PD1
PQ1/PD1
+3.3 V
Fuse
+3.3 V power
Backplane
Cross-connect board
Interface
module
Switch
matrix
module
PQ1
PQ1
+3.3 V
Fuse
+3.3 V power
Interface Module
The interface module receives and transmits the E1 electrical signals.

module transmits the signal to the PQ1. When the TPS is performed, the switch matrix module
transmits the signal to the protection board for bridging.
Issue 03 (2013-02-20)

726

11 PDH Boards

11.13.5 Front Panel


D75S
1~8
9~16
17~24
25~32
D75S
Issue 03 (2013-02-20)

727

11 PDH Boards
Interfaces
The front panel of the D75S has four DB44 interfaces. Table 11-53 describes the types and
usage of the interfaces of the D75S.
Interface
Type of
Interface
Usage
18
DB44
Receives the 1st to the 8th channels of E1 signals.
916
DB44
Receives the 9th to the 16th channels of E1 signals.
1724
DB44
Receives the 17th to the 24th channels of E1 signals.
2532
DB44
Receives the 25th to the 32nd channels of E1 signals.

Front View
30
15
44
Pin
Usage
Pin
Usage
38
Receives the 1st

channel of signals
(R1).
34
Receives the 5th

channel of signals
(R5).
Receives the 2nd

channel of signals
(R2).
33
Receives the 3rd

channel of signals
(R3).
32
Receives the 4th

channel of signals
(R4).
31
Transmits the 1st

channel of signals
(T1).
11
Transmits the 2nd

channel of signals
(T2).
10
Transmits the 3rd

channel of signals
(T3).
23
37
22
36
21
35
31
16
20
15
30
14
29
13
28
Issue 03 (2013-02-20)

19
18
17
16
26
25
24
Receives the 6th

channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Transmits the 5th
channel of signals
(T5).
Transmits the 6th
channel of signals
(T6).
Transmits the 7th
channel of signals
(T7).
728

Front View
11 PDH Boards
Pin
Usage
Pin
Usage
12
Transmits the 4th

channel of signals
(T4).
Transmits the 8th

channel of signals
(T8).
27
11.13.6 Valid Slots

The D75S can work as the interface board of the PQ1.
The D75S can be installed in slots 1926 and 2936 in the main subrack.
Table 11-55 lists the slots valid for the PQ1 and the corresponding slots for the D75S. The D75S
installed in the slot with a smaller number transmits/receives the 1st to the 32nd channels of E1
electrical signals. The D75S installed in the slot with a larger number transmits/receives the 33rd
to the 63rd channels of E1 electrical signals.
Table 11-55 Slots valid for the PQ1 and the corresponding slots for the D75S
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the D75S include the parameters specified for the electrical

Issue 03 (2013-02-20)
Nominal bit rate
2048 kbit/s
Line code pattern
HDB3
Waveform at the output interface

729

Nominal bit rate
11 PDH Boards
2048 kbit/s

Allowed attenuation at the input interface
Allowed frequency deviation at the input
interface

Anti-interference capability at the input
interface
Reflection attenuation at the input/output

interface
Output jitter
Mapping jitter
Combined jitter
l
Weight (kg): 0.4
Power Consumption
11.14 D34S

11.14.2 Application
Issue 03 (2013-02-20)

730

11 PDH Boards

The D34S receives and transmits 6xE3/T3 electrical signals. The D34S must work with the PD3
or PQ3.

1xE3/T3 signals.
Backplane
Cross-connect board
E3/T3 electrical
signal
Interface
module
Switch
matrix
module
+3.3 V
Fuse
E3/T3 electrical
signal
PD3/PQ3
TSB8
TSB8
PD3/PQ3
+3.3 V power
Interface Module

module transmits the signal to the PD3 or PQ3. When the TPS is performed, the switch matrix
module transmits the signal to the TSB8 for bridging.

11.14.5 Front Panel

Issue 03 (2013-02-20)

731

11 PDH Boards

D34S
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
OUT5
IN5
OUT6
IN6
D34S
Interfaces
The front panel of the D34S has six pairs of electrical interfaces.
Table 11-57 describes the types and usage of the interfaces of the D34S.
Issue 03 (2013-02-20)

732

11 PDH Boards

Interface
Type of
Interface
Usage
IN1IN6
SMB
Receives the 1st to the 6th channels of E3/T3

electrical signals.
OUT1OUT6
SMB
Transmits the 1st to the 6th channels of E3/T3

electrical signals.
11.14.6 Valid Slots

The D34S can be installed in slots 1926 and 2936 in the subrack.

The technical specifications of the D34S include the parameters specified for electrical

Table 11-58 lists the parameters specified for the electrical interfaces of the D34S.
Nominal bit rate
34368 kbit/s
44736 kbit/s
Line code pattern
HDB3
B3ZS

interface

interface
interface
the input interface

823.
the input interface

703.

Output jitter
Issue 03 (2013-02-20)

733

11 PDH Boards
Nominal bit rate
34368 kbit/s
44736 kbit/s
Mapping jitter
Combined jitter

751.
l
Weight (kg): 0.4
Power Consumption
11.15 C34S
technical specifications of the C34S (3xE3/T3 switching access board).

The C34S is available in one functional version, namely, N1.
11.15.2 Application
The C34S is a PDH interface switching board. The C34S can be used on the OptiX OSN

The C34S receives and transmits 3xE3/T3 electrical signals. The C34S must work with the PL3.

The C34S consists of the interface module, switch matrix module, and power access circuit.
Figure 11-61 shows the functional block diagram of the C34S by describing how to process
1xE3/T3 signals.
Issue 03 (2013-02-20)

734

11 PDH Boards
Figure 11-61 Functional block diagram of the C34S

Backplane
Cross-connect board
E3/T3 electrical
signal
Interface
module
Switch
matrix
module
E3/T3 electrical
signal
+3.3 V
Fuse
PL3
TSB4/TSB8
TSB4/TSB8
PL3
+3.3 V power
Interface Module

module transmits the signal to the PL3. When the TPS is performed, the switch matrix module

The power access circuit provides all the modules of the C34S with the required DC voltages.
11.15.5 Front Panel

The front panel of the C34S has interfaces and a bar code.

Figure 11-62 shows the appearance of the front panel of the C34S.
Issue 03 (2013-02-20)

735

11 PDH Boards
Figure 11-62 Front panel of the C34S
C34S
OUT1
IN1
OUT2
IN2
OUT3
IN3
C34S
Interfaces
The front panel of the C34S has three pairs of electrical interfaces.
Table 11-59 describes the type and usage of the interface of the C34S.
Table 11-59 Interfaces of the C34S
Issue 03 (2013-02-20)
Interface
Type of Interface
Usage
IN1IN3
SMB
Receives the 1st to the 3rd channels of E3/T3

electrical signals.
OUT1OUT3
SMB
Transmits the 1st to the 3rd channels of E3/T3

electrical signals.

736

11 PDH Boards
11.15.6 Valid Slots

The C34S can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the main subrack.
Table 11-60 lists the slots valid for the PL3 and the corresponding slots for the C34S.
Table 11-60 Slots valid for the PL3 and the corresponding slots for the C34S
Corresponding Slot for the C34S
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the C34S include the parameters specified for electrical

Table 11-61 lists the parameters specified for the electrical interfaces of the C34S.
Table 11-61 Parameters specified for the electrical interfaces of the C34S
Nominal bit rate
34368 kbit/s
44736 kbit/s
Line code pattern
HDB3
B3ZS

interface

interface
interface
Issue 03 (2013-02-20)

the input interface

823.

737

11 PDH Boards
Nominal bit rate
34368 kbit/s
44736 kbit/s
the input interface

703.

Output jitter
Mapping jitter
Combined jitter

751.
The mechanical specifications of the C34S are as follows:
l
Weight (kg): 0.3
Power Consumption
At room temperature (25C), the maximum power consumption of the C34S is 0 W.
11.16 MU04
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).

The MU04 is available in one functional version, namely, N1.
11.16.2 Application
The MU04 is an E4/STM-1 electrical interface board. The MU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the E4/STM-1 electrical processing board.

The MU04 receives and transmits 4xE4/STM-1 electrical signals. The MU04 must work with
the SPQ4.

The MU04 consists of the interface module, switch matrix module, and power module.
Issue 03 (2013-02-20)

738

11 PDH Boards
Figure 11-63 shows the functional block diagram of the MU04 by describing how to process
1xE4/STM-1 signals.
Figure 11-63 Functional block diagram of the MU04
Backplane
Cross-connect board
E4/STM-1 electrical
signal
Interface
module
E4/STM-1 electrical
signal
+3.3 V
Switch
matrix
module
Power
module
Fuse
SPQ4
TSB4/TSB8
TSB4/TSB8
SPQ4
+3.3 V power
Interface Module
The interface module receives and transmits the E4/STM-1 electrical signals.

module transmits the signal to the SPQ4. When the TPS is performed, the switch matrix module
Power Module
The power module provides all the modules of the MU04 with the required DC voltages.
11.16.5 Front Panel

The front panel of the MU04 has interfaces and a bar code.

Figure 11-64 shows the appearance of the front panel of the MU04.
Issue 03 (2013-02-20)

739

11 PDH Boards
Figure 11-64 Front panel of the MU04
MUO4
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
MUO4
Interfaces
The front panel of the MU04 has four pairs of electrical interfaces.
Table 11-62 describes the types and usage of the interfaces of the MU04.
Table 11-62 Interfaces of the MU04
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
IN1IN4
SMB
Receives the 1st to the 4th channels of E4/STM-1

electrical signals.
OUT1OUT4
SMB
Transmits the 1st to the 4th channels of E4/STM-1

electrical signals.

740

11 PDH Boards
11.16.6 Valid Slots

The MU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SPQ4.
Table 11-63 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 11-63 Slots valid for the SPQ4 and the corresponding slots for the MU04
Corresponding Slot for the MU04
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the MU04 include the parameters specified for electrical

Table 11-64 lists the parameters specified for the electrical interfaces of the MU04.
Table 11-64 Parameters specified for the electrical interfaces of the MU04
Nominal bit rate
139264 kbit/s
155520 kbit/s
Line code pattern
CMI
CMI

interface

interface
Allowed attenuation at the
input interface
Allowed frequency deviation
at the input interface
Issue 03 (2013-02-20)

741

11 PDH Boards
Nominal bit rate
139264 kbit/s
155520 kbit/s

823.
the input interface

Output jitter
Mapping jitter

783.

751.
Combined jitter
The mechanical specifications of the MU04 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the MU04 at room temperature (25C) is 2 W.
11.17 DM12
technical specifications of the DM12 (DDN service interface board).

The DM12 is available in one functional version, namely, N1.
11.17.2 Application
The DM12 is a DDN service interface board. The DM12 can be used on the OptiX OSN
equipment series to transmit and receive electrical signals of the DDN service.

The DM12 receives and transmits four channels of Nx64 kbit/s signals and eight channels of
framed E1 electrical signals. The DM12 must work with the DX1.
Issue 03 (2013-02-20)

742

11 PDH Boards

The DM12 consists of the interface module, switch matrix module, and power module.
Figure 11-65 shows the functional block diagram of the DM12 by describing how to process
one channel of Nx64 kbit/s or framed E1 electrical signals.
Figure 11-65 Functional block diagram of the DM12
Backplane
Cross-connect board
Nx64 kbit/s/
Framed E1
electrical signal
Switch
matrix
module
Interface
module
Nx64 kbit/s/
Framed E1
electrical signal
+3.3 V
Power
module
Fuse
DX1
DX1
+3.3 V backup power
Interface Module
The interface module receives and transmits the Nx64 kbit/s or framed E1 electrical signals.

module transmits the signal to the DX1. When the TPS is performed, the switch matrix module
transmits the signal to the protection DX1 for bridging.
Power Module
The power module provides all the modules of the DM12 with the required DC voltages.
11.17.5 Front Panel

The front panel of the DM12 has interfaces and a bar code.

Figure 11-66 shows the appearance of the front panel of the DM12.
Issue 03 (2013-02-20)

743

11 PDH Boards
Figure 11-66 Front panel of the DM12
DM12
E1(1-8)
DDN1
DDN2
DDN3
DDN4
DM12
Interfaces
The front panel of the DM12 has DB44 and DB28 interfaces. Table 11-65 describes the types
and usage of the interfaces of the DM12.
Table 11-65 Interfaces of the DM12
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
E1 (18)
DB44
Transmits/Receives eight channels of framed E1

signals.
DDN1DDN4
DB28
Transmits/Receives the 1st to the 4th channels of

Nx64 kbit/s signals.

744

11 PDH Boards

Front View
30
15
Pin
Usage
Pin
Usage
30
Transmits the
1st channel of
signals (T1).
Transmits the 8th

channel of signals
(T8).
Transmits the
2nd channel of
signals (T2).
36
Transmits the
3rd channel of
signals (T3).
35
Transmits the
4th channel of
signals (T4).
34
Transmits the
5th channel of
signals (T5).
33
Transmits the
6th channel of
signals (T6).
32
Transmits the
7th channel of
signals (T7).
31
Receives the 1st

channel of
signals (R1).
4439 and
61
15
44
29
14
28
13
27
31
16
12
26
11
25
10
24
9
38
23
37
22
21
20
19
18
17
16
Receives the 3rd

channel of signals
(R3).
Receives the 4th
channel of signals
(R4).
Receives the 5th
channel of signals
(R5).
Receives the 6th
channel of signals
(R6).
Receives the 7th
channel of signals
(R7).
Receives the 8th
channel of signals
(R8).
Grounding
Receives the
2nd channel of
signals (R2).
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11 PDH Boards

Front View
28
Pin
Usage
Pin
Usage
Transmits data
signals.
19
Receives data signals.
Transmits
clock signals.
21
Grounding
22
Receives the
loopback control
signal.
Detects the
carrier.
23
Permits the
transmission.
Requests for
transmission.
25
Receives the
clock to be used
in the transmit
direction from
the external
equipment.
27
Receives clock
signals.
2
3
4
11
12
1
13
14
15
16
17
18
20
24
26
28
Receives the DCE

ready signal.
Transmits the DTE
ready signal.
11.17.6 Valid Slots

The DM12 can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the DX1.
Table 11-68 lists the slots valid for the DX1 and the corresponding slots for the DM12. The
DM12 installed in the slot with a smaller number transmits/receives eight channels of framed
E1 signals and four channels of Nx64 kbit/s signals. The DM12 installed in the slot with a larger
number transmits/receives only four channels of Nx64 kbit/s signals.
Table 11-68 Slots valid for the DX1 and the corresponding slots for the DM12
Issue 03 (2013-02-20)
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
746

11 PDH Boards
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the DM12 include the parameters specified for electrical

Table 11-69 lists the parameters specified for the electrical interfaces of the DM12.
Table 11-69 Parameters specified for the electrical interfaces of the DM12
Interface Type
Description of the Interface
Specification of the Interface
Framed E1
interface (DB44)
Framed E1 signals
The physical and electrical

characteristics of the interface
comply with ITU-T G.703. The
frame structure of the interface
complies with ITU-T G.704.
NX64 kbit/s
interface (DB28)
V.35 interface
Complies with ITU-T V.35.
V.24 interface
Complies with ITU-T V.24.
X.21 interface
Complies with ITU-T X.21.
RS-449 interface
Complies with EIA RS-449

(RS-423A and RS-422A).
RS-530 interface
Complies with EIA RS-530.
RS-530A interface
Complies with EIA RS-530A.
The mechanical specifications of the DM12 are as follows:
l
Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the DM12 is 0 W.
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11.18 TSB4

The TSB4 is available in one functional version, namely, N1.
11.18.2 Application
The TSB4 is a PDH electrical interface protection switching board. The TSB4 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.

The TSB4 is used to provide the TPS protection.
The TSB4 can work with the MU04, C34S, or EU04 to realize the TPS protection on different
processing boards.
l
The TSB4 can work with the MU04 to realize the TPS protection on the SPQ4.
The TSB4 can work with the C34S to realize the TPS protection on the PL3.
The TSB4 can work with the EU04 to realize the TPS protection on the SEP.

The TSB4 consists of the switch matrix module and power module.
Figure 11-67 shows the functional block diagram of the TSB4.
Figure 11-67 Functional block diagram of the TSB4
Backplane
Backplane
Cross-connect board
Interface board 1
Interface board 2
Standby processing board
Interface board 3
Switch matrix
module
+3.3 V
Issue 03 (2013-02-20)
Power
module
Fuse
+3.3 V backup power

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11 PDH Boards

In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
Power Module
The power module provides all the modules of the TSB4 with the required DC voltages.
11.18.5 Front Panel

The front panel of the TSB4 has a bar code.

Figure 11-68 shows the appearance of the front panel of the TSB4.
Figure 11-68 Front panel of the TSB4
TSB4
TSB4
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11 PDH Boards
11.18.6 Valid Slots

When the TSB4 works with different processing boards and interface boards to realize the TPS
protection, the TSB4 can be installed in different slots.
The TSB4 can be installed in slots 19 and 35 in the main subrack.
Table 11-70 lists the slots valid for the TSB4 and the corresponding slots for the SPQ4 and
MU04.
Table 11-70 Slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04
Slot Valid for the TSB4

MU04
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 35
Table 11-71 lists the slots valid for the TSB4 and the corresponding slots for the SEP1 and
EU04.
Table 11-71 Slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04
Corresponding Slot for

the EU04
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 6
Slot 29
Slot 13
Slot 31
Slot 14
Slot 33
Slot 35
NOTE
The SEP1 is displayed as SEP or SEP1 on the U2000. When the interfaces are available on the front panel
of the SEP1, the SEP1 is displayed as SEP1 on the U2000. When the SEP1 works with the interface board
to realize the TPS protection, the SEP1 is displayed as SEP on the U2000.
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11 PDH Boards
Table 11-72 lists the slots valid for the TSB4 and the corresponding slots for the PL3 and C34S.
Table 11-72 Slots valid for the TSB4 and the corresponding slots for the PL3 and C34S

the C34S
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 35

The technical specifications of the TSB4 include the mechanical specifications and power
consumption.
The mechanical specifications of the TSB4 are as follows:
l
Weight (kg): 0.3
Power Consumption
The maximum power consumption of the TSB4 at room temperature (25C) is 3 W.
11.19 TSB8

The TSB8 is available in one functional version, namely, N1.
11.19.2 Application
The TSB8 is a PDH electrical interface protection switching board. The TSB8 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.
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11 PDH Boards

The TSB8 is used to provide the TPS protection.
The TSB8 can work with the C34S, EU04, EU08, ETS8, MU04 and D34S to realize the TPS
protection on different processing boards.
l
The TSB8 can work with the MU04 to realize the TPS protection on the SPQ4.
The TSB8 can work with the C34S to realize the TPS protection on the PL3.
The TSB8 can work with the D34S to realize the TPS protection on the PD3.
The TSB8 can work with the D34S to realize the TPS protection on the PQ3.
The TSB8 can work with the EU04 to realize the TPS protection on the SEP1.
The TSB8 can work with the EU08 to realize the TPS protection on the SLH1/SEP1.
The TSB8 can work with the ETS8 to realize the TPS protection on the EFS0.
The TSB8 can work with the ETS8 to realize the TPS protection on the EFS0A.

The TSB8 consists of the switch matrix module and power module.
Figure 11-69 shows the functional block diagram of the TSB8 by describing how to process
one channel of signals.
Figure 11-69 Functional block diagram of the TSB8
Backplane
Backplane
Cross-connect board
Interface board 1
Interface board 2
Standby processing board
Interface board 3
Switch matrix
module
+3.3 V
Power
module
Fuse
+3.3 V backup power

In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
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11 PDH Boards
Power Module
The power module provides all the modules of the TSB8 with the required DC voltages.
11.19.5 Front Panel

The front panel of the TSB8 has a bar code.

Figure 11-70 shows the appearance of the front panel of the TSB8.
Figure 11-70 Front panel of the TSB8
TSB8
TSB8
11.19.6 Valid Slots

The TSB8 can be installed in slots 19, 20, 35, and 36 in the main subrack.
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11 PDH Boards
Table 11-73 lists the slots valid for the TSB8 and the corresponding slots for the SPQ4 and
MU04.
Table 11-73 Slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04

MU04
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 35
Table 11-74 lists the slots valid for the TSB8 and the corresponding slots for the PL3 and C34S.
Table 11-74 Slots valid for the TSB8 and the corresponding slots for the PL3 and C34S

the C34S
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 35
Table 11-75 lists the slots valid for the TSB8 and the corresponding slots for the PD3 and D34S.
Table 11-75 Slots valid for the TSB8 and the corresponding slots for the PD3 and D34S

the D34S
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 35
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11 PDH Boards

the D34S
Slot 14
Slot 31
Slot 15
Slot 33
Table 11-76 lists the slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S.
Table 11-76 Slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S

D34S
Slots 19 and 20
Slots 25
Slots 2126
Slots 35 and 36
Slots 1316
Slots 2934
EU04.

the EU04
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 35
EU08.
Issue 03 (2013-02-20)

the EU08
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23

755

Slot 35
11 PDH Boards

the EU08
Slot 5
Slot 25
Slot 6
Slot 29
Slot 13
Slot 31
Slot 14
Slot 33
Table 11-79 lists the slots valid for the TSB8 and the corresponding slots for the SLH1 and
EU08.
Table 11-79 Slots valid for the TSB8 and the corresponding slots for the SLH1 and EU08

the EU08
Slot 19 and 20
Slot 3
Slot 21 and 22
Slot 4
Slot 23 and 24
Slot 5
Slot 25 and 26
Slot 6
Slot 29 and 30
Slot 13
Slot 31 and 32
Slot 14
Slot 33 and 34
Slot 35 and 36
NOTE
The SEP1 is displayed as SEP or SEP1 on the U2000. When the interfaces are available on the front panel
of the SEP1, the SEP1 is displayed as SEP1 on the U2000. When the SEP1 works with the interface board
to realize the TPS protection, the SEP1 is displayed as SEP on the U2000.
Table 11-80 lists the slots valid for the TSB8 and the corresponding slots for the EFS0 and
ETS8.
Table 11-80 Slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8
Slot Valid for the EFS0

the ETS8
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 6
Slot 29
Slot 13
Slot 31
Slot 35
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the ETS8
Slot 14
Slot 33
Table 11-81 lists the slots valid for the TSB8 and the corresponding slots for the EFS0A and
ETS8.
Table 11-81 Slots valid for the TSB8 and the corresponding slots for the EFS0A and ETS8
Slot Valid for the EFS0A

the ETS8
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 6
Slot 29
Slot 13
Slot 31
Slot 14
Slot 33
Slot 35

The technical specifications of the TSB8 include the mechanical specifications and power
consumption.
The mechanical specifications of the TSB8 are as follows:
l
Weight (kg): 0.3
Power Consumption
At room temperature (25C), the maximum power consumption of the TSB8 is 0 W.
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12
EoS Boards
About This Chapter

The EoS boards include the interface boards and processing boards for FE and GE services.
12.1 EFT8
technical specifications of the EFT8 (8xFE/16xFE transparent transmission board). This topic
also describes how to configure and commission the EFT8.
12.2 EFT8A
technical specifications of the EFT8A (8xFE transparent transmission board). This topic also
describes how to configure and commission the EFT8A.
12.3 EGT2
technical specifications of the EGT2 (2xGE transparent transmission board). This topic also
describes how to configure and commission the EGT2.
12.4 EFS0
technical specifications of the EFS0 (8xFE switching and processing board). This topic also
describes how to configure and commission the EFS0.
12.5 EFS0A
technical specifications of the EFS0A (16xFE switching and processing board). This topic also
describes how to configure and commission the EFS0A.
12.6 EFS4
12.7 EGS2
technical specifications of the EGS2 (2xGE switching and processing board). This topic also
describes how to configure and commission the EGS2.
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12.8 EMS2
technical specifications of the EMS2 (2xGE and 16xFE switching and processing board). This
topic also describes how to configure and commission the EMS2.
12.9 EMS4
12.10 EGS4
12.11 EAS2
technical specifications of the EAS2 (2-port 10xGE switching and processing board). This topic
also describes how to configure and commission the EAS2.
12.12 EFF8
technical specifications of the EFF8 (8x100M Ethernet optical interface board).
12.13 EFF8A
technical specifications of the EFF8A (8x100M Ethernet optical interface board).
12.14 ETF8
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).
12.15 ETF8A
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).
12.16 ETS8
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
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12 EoS Boards
12.1 EFT8
technical specifications of the EFT8 (8xFE/16xFE transparent transmission board). This topic
also describes how to configure and commission the EFT8.

The EFT8 is available in the following functional version: N1.
12.1.2 Application
The EFT8 is used to transmit/receive Ethernet services, manage bandwidths, and converge
Ethernet services.
Figure 12-1 shows the typical networking and application of the Ethernet transparent
transmission board. The Ethernet transparent transmission board realizes point-to-point
transparent transmission of Ethernet services. The Ethernet transparent transmission board
provides the following functions by using the interfaces on the board: data receipt, data
transmission, data mapping, and traffic control. In addition, the Ethernet transparent
transmission board performs port-based point-to-point transparent transmission, encapsulation/
decapsulation, overhead bytes and pointers processing, virtual concatenation, SDH mapping/
demapping, and LCAS function.
Figure 12-1 Networking and application of the Ethernet transparent transmission board
NMS
User A2
NE1
PORT 1
NE2
MSP ring
PORT 2
NE4
NE3
User B2
Service flow
Line board
PORT 1
PORT 2
Data board
Cross-connect and
timing board
Issue 03 (2013-02-20)
User B1
User A1

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12 EoS Boards

The EFT8 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 12-1 provides the functions and features of the EFT8.
Table 12-1 Functions and features of the EFT8
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Transparently transmits 8xFE or 16xFE services.
Interfa
ce
types
l Supports 10BASE-T/100BASE-TX signals. The electrical ports comply with

IEEE 802.3u.
l Supports 10BASE-T/100BASE-TX signals when the EFT8 is used with the
ETF8.
l Supports 100BASE-FX/100BASE-LX signals when the EFT8 is used with the
EFF8. The optical interfaces comply with IEEE 802.3u.
Functi
ons
when
being
used
with
an
interfa
ce
board
l Receives/Transmits 16 Ethernet signals through the electrical interface when the

EFT8 is used with the ETF8.
Interfa
ce
charac
teristic
s
Working
modes
100M full-duplex, 10M full-duplex, auto-negotiation
Traffic
control at
ports
Auto-negotiation mode
Not supported
Non-autonegotiation mode
Supported
l Receives/Transmits 8 Ethernet optical signals and 8 Ethernet electrical signals

when the EFT8 is used with the EFF8.
Query/
Supported
Setting of
port
status
Query of
interface
types
Issue 03 (2013-02-20)
Supported

761

Funct
ion
and
Featu
re
12 EoS Boards
Description
Setting of Not supported

optical
power
threshold
s
Pluggabl
e optical
module
Issue 03 (2013-02-20)
Not supported
EPL
servic
e
Supports the PORT-based transparent transmission.
Servic
e
specifi
cation
s
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1q TAG
Supported
Frame
length
range
l Supports the setting of the packet length, which ranges from 1518
bytes to 1535 bytes. Ports 1-4 and 9-12 on the board support a jumbo
frame with a maximum length of 6144 bytes, whereas ports 5-8 and
13-16 support a jumbo frame with a maximum length of 9600 bytes.
Bound
bandwidt
h
24xVC-3, or 126xVC-12 + 18xVC-3
Mapping
granularit
ies
Supports VC-12, VC-3, VC-12-Xv (X 63), and VC-3-Xv (X 3)

granularities.
Encapsul
ation
formats
HDLC
Supported
LAPS
Supported
GFP-F
Supported
MPLS
technolo
gy
Does not support the MPLS.
VLAN
technolo
gy
Supports VLAN transparent transmission.

762

Funct
ion
and
Featu
re
12 EoS Boards
Description
Maximu
m uplink
bandwidt
h
The maximum uplink bandwidth is 1.25 Gbit/s. The EFT8 can adapt to
the bandwidth of the slot.
VCTRU
NK
specificat
ions
Number of supported VCTRUNKs: 16

Configuration principles are as follows:
l A VCTRUNK can be bound with the VC-12 path or VC-3 path at
one time. A VCTRUNK should not be bound with VC-12 and VC-3
paths at the same time.
l A VCTRUNK can be bound with a maximum of three VC-3s or a
maximum of 63 VC-12s.
l VCTRUNK 1-VCTRUNK 8 can be bound with VC-3s 1-12 or
VC-12s 1-63.
l VCTRUNK 9-VCTRUNK 16 can be bound with VC-3s 13-24 or
VC-12s 64-126.
l A VCTRUNK cannot be bound with VC-12s numbered 1-63 and
VC-3s numbered 10-12 at the same time. In addition, a VCTRUNK
cannot be bound with VC-12s numbered 64-126 and VC-3s
numbered 22-24 at the same time.
l VC-4s numbered 4 and 8 support the binding of VC-3 and VC-12
paths. The other VC-4s support the binding of VC-3 paths only.
l In the case of the configuration of cross-connection, VC-12s
numbered 163 should be configured into the fourth VC-4, and
VC-12s numbered 64126 should be configured into the eighth
VC-4.
Protec
tion
schem
es
Issue 03 (2013-02-20)
TPS
Not supported
LCAS

LPT
Supports P2P LPT, which comply with ITU-T G.7042.
LAG
Not supported
Clock
synchr
onizati
on
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
Maint
enanc
ETH
OAM
Does not support the ETH OAM function.

763

12 EoS Boards
Funct
ion
and
Featu
re
Description
e
featur
es
Test
Frame
Supports test frames in GFP bearer mode.
Response
to ping
Not supported
Port
mirroring
Does not support the port mirroring function.
Loopbac
k
capabilit
y
PHY layer at Ethernet ports
Inloops
MAC layer at Ethernet ports
Inloops
VC-4 level
Not supported
VC-3 level
VC-12 level
Not supported
RMON
Supports Ethernet performance monitoring at the port level.
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events

QoS
Does not support the QoS function.
Traffi
c
contro
l
Supports the FE port-based traffic control function that complies with IEEE 802.3x.

The EFT8 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 12-2 shows the functional block diagram of the EFT8 by describing how to process 1xFE
signals.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-2 Functional block diagram of the EFT8

Backplane
FE
Ethernet
access
module
Cross-connect unit
ENCP
Interface
converting
module
VCP
DENCP
Cross-connect unit
Mapping module
Laser
shutdown
LOS
Logic and
control module
Communication
+3.3 V
Clock module
50 77 125 155
MHz MHz MHz MHz
Power
module
ENCP: data encapsulation module
Power
module
SCC unit
SCC unit
Fuse
-48 V/-60 V
-48 V/-60 V
+3.3 V
+3.3 V backup power
Fuse
DENCP: decapsulation module
VCP: virtual concatenation processing module
Ethernet Access Module

In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
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The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
l
Manages and configures other modules of the board.
The control module also contains basic logic units. This module performs the following
functions:
l
Writes and reads the register.
Provides interfaces for the CPU.
Checks and selects the clock.
Performs phase discrimination and frequency division on the clock.
Checks the in-service state of the cross-connect, SCC, and line boards.
Controls the shutting down of the optical module.
Implements communication.
Controls indicators.
Clock Module
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
require.
12.1.5 Front Panel

The front panel of the EFT8 has indicators, interfaces, and a bar code.

Figure 12-3 shows the appearance of the front panel of the EFT8.
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12 EoS Boards
Figure 12-3 Front panel of the EFT8
EFT8
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8
Indicators
l
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12 EoS Boards
Interfaces
The front panel of the EFT8 has eight FE interfaces. Table 12-2 describes the types and usage
of the interfaces of the EFT8. For information about the cables connected to the interfaces, see
23.4.6 Straight-Through Cable and 23.4.7 Crossover Cable.
Table 12-2 Interfaces of the EFT8
Interface
Type of
Interface
Usage
FE1
RJ-45
Transmits and receives 10BASE-T/100BASE-TX

signals.
FE2
RJ-45

signals.
FE3
RJ-45

signals.
FE4
RJ-45

signals.
FE5
RJ-45

signals.
FE6
RJ-45

signals.
FE7
RJ-45

signals.
FE8
RJ-45

signals.
Table 12-3 describes the pins of the RJ45 connector.

Table 12-3 Pins of the RJ45 connector
Issue 03 (2013-02-20)
Pin
Description
Positive data transmit end
Negative data transmit end
Positive data receive end
Grounding
Grounding
Negative data receive end
Grounding

768

Pin
Description
Grounding
12 EoS Boards

The EFT8 does not have any jumpers or DIP switches that are used for board settings.
NOTE
The daughter board of the EFT8 has only one push-button switch, which is used for resetting the EFT8.
When the EFT8 operates normally, do not push the switch. Otherwise, a cold reset is performed on the
EFT8 and the services may be lost.
12.1.7 Valid Slots

The EFT8 must be installed in a valid slot in the subrack. Otherwise, the EFT8 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the EFT8 vary with the cross-connect capacity of the subrack and whether
the EFT8 works with an interface board.
The slots valid for the EFT8 are as follows:
l
When the EFT8 does not work with an interface board:

The EFT8 can be installed in slots 16 and 1316. In this case, the bandwidth is 622 Mbit/
s.
When the EFT8 works with an interface board:

When the cross-connect capacity is 200 Gbit/s, the EFT8 can be installed in slots 25
and 1316. In this case, the bandwidth is 1.25 Gbit/s.
12.1.8 Feature Code

The EFT8 does not have the feature code.


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12 EoS Boards
Step 3 Required: Check whether the interface board and cable match the board. Ensure that the cable
matches the board.
is correct.
----End

Step 2 Required: Configure services. For details, see Configuring EPL Services on Ethernet
Transparent Transmission Board.
Step 3 Required: Set the Ethernet interface.
l Set the overhead byte as follows:
J1/J2 byte: The setting of the J1/J2 byte on the interconnected equipment must be
consistent. Generally, use the default value. The default mode of the J1/J2 to be sent is
16-Byte CRC Mode and the default value of the J1/J2 to be sent is HuaWei SBS ; the
default mode of the J1/J2 to be received is Single-Byte Mode and the default value of
the J1/J2 to be received is 0x00.
l Set the Ethernet interface as follows:
Port enabled/disabled: When you configure services on a port of the Ethernet board, the
port must be set to Enabled.
Working mode: Generally, the Ethernet interfaces of the interconnected equipment are
required to work in the same working mode. If the working modes on two sides do not
match, packets may be lost or the bit rate may decrease. In the case of large volume of
traffic, services may be completely interrupted.
NOTE
For more information about the parameters of the board, see 27.4.2 Ethernet Parameters.
Step 4 Optional: Configure the test frame. For details, see Configuring Test Frames.
----End

----End
Issue 03 (2013-02-20)

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12 EoS Boards

Boards.
the Current Alarms.
----End

The EFT8 supports multiple Ethernet functions and features such as LCAS and LPT. Configure
the functions according to actual requirements.
You can configure the following Ethernet functions for the EFT8 by using the U2000:
l
LCAS
LPT
Test Frame

You can set parameters for the EFT8 by using the U2000.
You can set the following main parameters for the EFT8 by using the U2000:
l
Working mode
LCAS
Mapping protocol
For information about more parameters and the description of each parameter, see 27 Parameter
Settings.

Troubleshooting
Table 12-4 lists the faults that occur on the EFT8 frequently and the troubleshooting methods.
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Table 12-4 Methods used to troubleshoot the faults that occur on the EFT8 frequently
Fault Symptom
Common Fault Cause
Service
interruption
l The services on a VCTRUNK

port are interrupted.

Interruptions.
l The services on a single

Ethernet port are interrupted.
l The services on all the Ethernet
ports are interrupted.
Transient service
interruption

port are transiently interrupted.
See Troubleshooting Transient

Service Interruptions.

Ethernet port are transiently
interrupted.
l The protocol becomes
abnormal.
l The negotiated working mode
of the Ethernet ports is the halfduplex mode.
Packet loss
See Troubleshooting Service

Packet Loss.
l Bit errors occur on the line side.

Interconnection
fault
l The interconnection fault

occurs on a single Ethernet port.


occurs on the VCG port.
l The LCAS interconnection
fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EFT8, see Replacing an EOS Board.

12.1.13.1 Alarms of N1EFT8
Issue 03 (2013-02-20)
ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BDID_ERROR
BIP_EXC

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12 EoS Boards
BIP_SD
BOOTROM_BAD
COMMUN_FAIL
ETH_LOS
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FPGA_ABN
HARD_BAD
HP_LOM
LCAS_BAND_DECREASED
LASER_MOD_ERR
LCAS_PLCR
LCAS_FOPR
LCAS_FOPT
LCAS_TLCT
LCAS_PLCT
LCAS_TLCR
LP_RDI_VC3
LOOP_ALM
LP_RDI_VC12
LP_SLM_VC12
LP_REI_VC12
LP_REI_VC3
LP_TIM_VC3
LP_SLM_VC3
LP_TIM_VC12
LP_UNEQ_VC12
LP_UNEQ_VC3
LPT_INEFFECT
LPT_RFI
LSR_NO_FITED
MSSW_DIFFERENT
NO_BD_SOFT
SLAVE_WORKING
SUBCARD_ABN
TEST_STATUS
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
W_R_FAIL
TR_LOC
T_LOSEX
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

12.1.14.1 Performance Events of N1EFT8

Table 12-5 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS

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12 EoS Boards
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPSES
LPUAS
DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors
Table 12-6 RMON alarm

Multicast Packets Received
(packets)
Undersize Packets
Received(packets)
Oversize Packets Received

(packets)
Fragments(packets)
Packets Received and

Transmitted(64 Octets in
Length)(packets)
Packets Received(65~127
Octets in Length)(packets)
Packets Received
(512~1023 Octets in
Length)(packets)
Broadcast Packets Received

(packets)
Issue 03 (2013-02-20)
Packets Transmitted(64
Packets Transmitted(65~127
Packets Transmitted
(128~255 Octets in Length)
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(1024~1518 Octets in
Length)(packets)

Length)(packets)

Transmitted(65~127 Octets in
Length)(packets)

Transmitted(128~255

Transmitted(256~511

Transmitted(512~1023 Octets
in Length)(packets)

Transmitted(1024~1518
Unicast Packets Received

(packets)
Unicast Packets Transmitted

(packets)
Pause Frames Received

(frames)

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12 EoS Boards
Pause Frames Transmitted

(frames)
Multicast Packets Transmitted

(packets)
Broadcast Packets
Transmitted(packets)
Good Octets Received

(Byte)
Good Octets Transmitted

(Byte)
Bad Octets Received(Byte)
Bad Octets Transmitted

(Byte)
FCS Errors(frames)

The technical specifications of the EFT8 include the Ethernet performance specifications,

Table 12-9 lists the parameters specified for the electrical interfaces of the EFT8.
Table 12-9 Parameters specified for the optical interfaces of the EFT8
Parameter
Value
Nominal bit rate
10 Mbit/s or 100 Mbit/s
Line code pattern
Manchester encoding signal (10M) or MLT-3 encoding signal

(100M)
interface
Ethernet Performance Specifications

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFT8 board of the N1 version.
Figure 12-4 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EFT8.
Figure 12-4 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Port 1
Tested
equipment 1
Tested
equipment 2
Port 2
Port 1
Port 2
Data network
performance
analyzer
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12 EoS Boards
Figure 12-5 shows the connection for testing the back-to-back specifications of the EFT8.
Figure 12-5 Connection for testing the back-to-back specifications
Tested
equipment 1
Port 1
Port 2
Data network
performance
analyzer
Table 12-10 lists the throughput specifications of the EFT8. Table 12-11 lists the packet loss
ratio in the case of overloading of the EFT8. Table 12-12 lists the latency specifications of the
EFT8. Table 12-13 lists the back-to-back specifications of the EFT8.
NOTE
The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 63 VC-12s are bound on the FE port.
The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 12-10 lists the throughput specifications of the EFT8. The values are obtained when the
SmartApplication is set as follows:
l
The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
The test duration is set to 60 seconds.
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12 EoS Boards
Table 12-10 Throughput specifications of the EFT8

Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64
100.00
148810
148810
297620
128
100.00
84459
84459
168918
256
100.00
45290
45290
90580
512
100.00
23496
23496
46992
1024
100.00
11973
11973
23946
1280
100.00
9615
9615
19230
1518
100.00
8127
8127
16254
Table 12-11 lists the packet loss ratio in the case of overloading of the EFT8. The values are
obtained when the SmartApplication is set as follows:
l
The tested traffic starts from the throughput and increases to 100% in 10% steps.
Table 12-11 Packet loss ratio in the case of overloading of the EFT8
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64
100.00
0.000
0.000
0.000
128
100.00
0.000
0.000
0.000
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000
Table 12-12 lists the latency specifications of the EFT8. The values are obtained when the
l
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12 EoS Boards
The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
Table 12-12 Latency specifications of the EFT8

Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
506.4
506.4
501.2
501.2
128
100.00
518.8
518.8
508.5
508.5
256
100.00
536.2
536.2
515.8
515.8
512
100.00
578.9
578.9
538.0
538.0
1024
100.00
653.4
653.4
571.4
571.4
1280
100.00
688.1
688.1
585.6
585.6
1518
100.00
720.6
720.6
599.1
599.1
Table 12-13 lists the back-to-back specifications of the EFT8. The values are obtained when
the SmartApplication is set as follows:
l
The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
The tested traffic is set to the wire speed.
Table 12-13 Back-to-back specifications of the EFT8
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
297620
297620
595240
128
100.00
168918
168918
337836
256
100.00
90580
90580
181160

778

12 EoS Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
512
100.00
46992
46992
93984
1024
100.00
23946
23946
47892
1280
100.00
19230
19230
38460
1518
100.00
16254
16254
32508
The mechanical specifications of the EFT8 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the EFT8 at room temperature (25C) is 26 W.
12.2 EFT8A
technical specifications of the EFT8A (8xFE transparent transmission board). This topic also
describes how to configure and commission the EFT8A.

The EFT8A is available in the following functional version: N1.
12.2.2 Application
The EFT8A is used to transmit/receive Ethernet services, manage bandwidths, and converge
Ethernet services.
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12 EoS Boards
NMS
User A2
NE1
PORT 1
NE2
MSP ring
PORT 2
NE4
NE3
User B2
Service flow
Line board
PORT 1
PORT 2
Data board
Cross-connect and
timing board
User B1
User A1

The EFT8A supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 12-14 provides the functions and features of the EFT8A.
Table 12-14 Functions and features of the EFT8A
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Transparently transmits 8xFE services.
Interfa
ce
types
l Supports 10BASE-T/100BASE-TX signals.

l The optical interfaces comply with IEEE 802.3u.

780

12 EoS Boards
Funct
ion
and
Featu
re
Description
Functi
ons
when
being
used
with
an
interfa
ce
board
Receives/Transmits 8xFE signals by providing interfaces on the front panel.
Interfa
ce
charac
teristic
s
Working
modes
100M full-duplex, 10M full-duplex, and auto-negotiation
Traffic
control at
ports
Not supported
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported

optical
power
threshold
s
Pluggabl
e optical
module
Issue 03 (2013-02-20)
Not supported
EPL
servic
e
Servic
e
specifi
cation
s
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1q TAG
Supported

781

Funct
ion
and
Featu
re
Issue 03 (2013-02-20)
12 EoS Boards
Description
Frame
length
range
l Supports the setting of the method used for processing frames with
less than 64 bytes or error frames.
Bound
bandwidt
h
12xVC-3, or 63xVC-12 + 9xVC-3
Mapping
granularit
ies

granularities.
Encapsul
ation
formats
HDLC
Supported
LAPS
Supported
GFP-F
Supported
bytes to 1535 bytes. The first four ports support a jumbo frame with
a maximum length of 6144 bytes, whereas the last four ports support
a jumbo frame with a maximum length of 9600 bytes.
MPLS
technolo
gy
Does not support the MPLS.
VLAN
technolo
gy
Supports VLAN transparent transmission.
Maximu
m uplink
bandwidt
h
622 Mbit/s

782

Funct
ion
and
Featu
re
12 EoS Boards
Description
VCTRU
NK
specificat
ions

l A VCTRUNK can be bound with a maximum of three VC-3s or a
l A VCTRUNK cannot be bound with VC-12s numbered 163 and
VC-3s numbered 1012 at the same time.
l VC-4 numbered 4 supports the binding of VC-3 and VC-12 paths.
The other VC-4s support the binding of VC-3 paths only.
l VCTRUNK 1VCTRUNK 8 can be bound with VC-3s numbered
112 or VC-12s numbered 163.
TPS
Not supported
LCAS

LPT
Supports P2P LPT in compliance with ITU-T G.7042.
LAG
Not supported
Clock
synchr
onizati
on
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
Maint
enanc
e
featur
es
ETH
OAM
Not supported
Test
Frame
Response
to ping
Not supported
Port
mirroring
Does not support the port mirroring function.
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported
Protec
tion
schem
es
Issue 03 (2013-02-20)

783

Funct
ion
and
Featu
re
12 EoS Boards
Description
VC-3 level
VC-12 level
Not supported
RMON
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events

QoS
Does not support the QoS function.
Traffi
c
contro
l
Supports the FE interface-based traffic control function that complies with IEEE
802.3x.

The EFT8A consists of the Ethernet access module, mapping module, interface converting
Figure 12-7 shows the functional block diagram of the EFT8A by describing how to process
1xFE signals.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-7 Functional block diagram of the EFT8A

Backplane
FE
Ethernet
access
module
ENCP
Interface
converting
module
VCP
DENCP
Cross-connect unit
Cross-connect unit
Mapping module
LOS
Logic and
control module
Communication
+3.3 V
Clock
module
Power
module
Power
module
Fuse
-48 V/-60 V
-48 V/-60 V
+3.3 V
Fuse
50 77 125 155
MHz MHz MHz MHz
SCC unit
SCC unit
+3.3 V backup power

In the receive direction, the Ethernet access module receives the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
signals are encoded.
Mapping Module
signals.

Issue 03 (2013-02-20)

785

12 EoS Boards

l
functions:
l
Clock Module
Power Module
require.
12.2.5 Front Panel

The front panel of the EFT8A has indicators, interfaces, and a bar code.

Figure 12-8 shows the appearance of the front panel of the EFT8A.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-8 Front panel of the EFT8A
EFT8A
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
EFT8A
Indicators
l
Issue 03 (2013-02-20)

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12 EoS Boards
Interfaces
The front panel of the EFT8A has eight FE interfaces. Table 12-15 describes the types and usage
of the interfaces of the EFT8A. For information about the cables connected to the interfaces, see
Table 12-15 Interfaces of the EFT8A
Interface
Type of
Interface
Usage
FE1
RJ-45

signals.
FE2
RJ-45

signals.
FE3
RJ-45

signals.
FE4
RJ-45

signals.
FE5
RJ-45

signals.
FE6
RJ-45

signals.
FE7
RJ-45

signals.
FE8
RJ-45

signals.

Issue 03 (2013-02-20)
Pin
Description
Grounding
Grounding
Grounding

788

Pin
Description
Grounding
12 EoS Boards

The EFT8A does not have any jumpers or DIP switches that are used for board settings.
NOTE
The daughter board of the EFT8A has only one push-button switch, which is used for resetting the EFT8A.
When the EFT8A operates normally, do not push the switch. Otherwise, a cold reset is performed on the
EFT8A and the services may be lost.
12.2.7 Valid Slots

The EFT8A must be installed in a valid slot in the subrack. Otherwise, the EFT8A cannot work
normally.
The EFT8A can be installed in slots 18 and 1116 in the subrack. In this case, the bandwidth
is 622 Mbit/s.
12.2.8 Feature Code

The EFT8A does not have the feature code.


matches the board.
is correct.
----End
Issue 03 (2013-02-20)

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12 EoS Boards

NOTE
----End

----End

Boards.
the Current Alarms.
----End

The EFT8A supports multiple Ethernet functions and features such as LCAS and LPT. Configure
Issue 03 (2013-02-20)

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12 EoS Boards
You can configure the following Ethernet functions for the EFT8A by using the U2000:
l
LCAS
LPT
Test Frame

You can set parameters for the EFT8A by using the U2000.
You can set the following main parameters for the EFT8A by using the U2000:
l
Working mode
LCAS
Mapping protocol
Byte packet
CRC error frame
Settings.

Troubleshooting
Table 12-17 lists the faults that occur on the EFT8A frequently and the troubleshooting methods.
Table 12-17 Methods used to troubleshoot the faults that occur on the EFT8A frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Issue 03 (2013-02-20)

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12 EoS Boards
Fault Symptom
Common Fault Cause
Packet loss


Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EFT8A, see Replacing an EOS Board.

12.2.13.1 Alarms of N1EFT8A
Issue 03 (2013-02-20)
ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BDID_ERROR
BIP_EXC
BIP_SD
BOOTROM_BAD
COMMUN_FAIL
ETH_LOS
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNFL
CT
FCS_ERR
FPGA_ABN
HARD_BAD
HP_LOM
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12

792

12 EoS Boards
LP_UNEQ_VC3
LPT_INEFFECT
LPT_RFI
NO_BD_SOFT
SLAVE_WORKING
TEST_STATUS
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
W_R_FAIL
TR_LOC
T_LOSEX
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

12.2.14.1 Performance Events of N1EFT8A

Table 12-18 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPSES
LPUAS
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPSES
LPUAS
Table 12-19 SDH
Issue 03 (2013-02-20)

793

12 EoS Boards

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

(packets)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)

Length)(packets)
Packets Received
(512~1023 Octets in
Length)(packets)

(packets)
Issue 03 (2013-02-20)
Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
Length)(packets)

Length)(packets)

Length)(packets)

Transmitted(128~255

Transmitted(256~511

in Length)(packets)


(packets)

(packets)

(frames)

(frames)

(packets)
Broadcast Packets

(Byte)

(Byte)
Bad Octets Received(Byte)
Bad Octets Transmitted

(Byte)
FCS Errors(frames)

794

12 EoS Boards

The technical specifications of the EFT8A include the Ethernet performance specifications,

Table 12-23 lists the parameters specified for the electrical interfaces of the EFT8A.
Table 12-23 Parameters specified for the optical interfaces of the EFT8A
Parameter
Value
Nominal bit rate
Line code pattern

(100M)
interface

NOTE
specifications, and back-to-back specifications of the EFT8A board of the N1 version.
the case of overloading, and latency specifications of the EFTA.
of overloading, and latency specifications
Port 1
Tested
equipment 1
Tested
equipment 2
Port 2
Port 1
Port 2
Data network
performance
analyzer
Figure 12-10 shows the connection for testing the back-to-back specifications of the EFT8A.
Issue 03 (2013-02-20)

795

12 EoS Boards
Figure 12-10 Connection for testing the back-to-back specifications

Tested
equipment 1
Port 1
Port 2
Data network
performance
analyzer
Table 12-24 lists the throughput specifications of the EFT8A. Table 12-25 lists the packet loss
ratio in the case of overloading of the EFT8A. Table 12-26 lists the latency specifications of the
EFT8A. Table 12-27 lists the back-to-back specifications of the EFT8A.
NOTE
are used.
configured and 63 VC-12s are bound on the FE port.
Table 12-24 lists the throughput specifications of the EFT8A. The values are obtained when the
l
Table 12-24 Throughput specifications of the EFT8A
Issue 03 (2013-02-20)
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64
100.00
148810
148810
297620
128
100.00
84459
84459
168918

796

12 EoS Boards
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
256
100.00
45290
45290
90580
512
100.00
23496
23496
46992
1024
100.00
11973
11973
23946
1280
100.00
9615
9615
19230
1518
100.00
8127
8127
16254
Table 12-25 lists the packet loss ratio in the case of overloading of the EFT8A. The values are
l
Table 12-25 Packet loss ratio in the case of overloading of the EFT8A
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64
100.00
0.000
0.000
0.000
128
100.00
0.000
0.000
0.000
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000
Table 12-26 lists the latency specifications of the EFT8A. The values are obtained when the
l
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-26 Latency specifications of the EFT8A
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
506.4
506.4
501.2
501.2
128
100.00
518.8
518.8
508.5
508.5
256
100.00
536.2
536.2
515.8
515.8
512
100.00
578.9
578.9
538.0
538.0
1024
100.00
653.4
653.4
571.4
571.4
1280
100.00
688.1
688.1
585.6
585.6
1518
100.00
720.6
720.6
599.1
599.1
Table 12-27 lists the back-to-back specifications of the EFT8A. The values are obtained when
l
Table 12-27 Back-to-back specifications of the EFT8A
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
297620
297620
595240
128
100.00
168918
168918
337836
256
100.00
90580
90580
181160
512
100.00
46992
46992
93984
1024
100.00
23946
23946
47892
1280
100.00
19230
19230
38460

798

12 EoS Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
1518
100.00
16254
16254
32508
The mechanical specifications of the EFT8A are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the EFT8A at room temperature (25C) is 26 W.
12.3 EGT2
technical specifications of the EGT2 (2xGE transparent transmission board). This topic also
describes how to configure and commission the EGT2.

The EGT2 is available in two functional versions, namely, N1 and N2.
Table 12-28 describes the versions of the EGT2.
Table 12-28 Versions of the EGT2
Item
Description
Functional versions
The EGT2 is available in two functional versions, namely, N1 and

N2.
Differences
l Regarding interface specifications: interface types, interface

characteristics
l Regarding service specifications: MTU, VCTRUNK
specifications, Mapping granularities
l Regarding maintenance features: ETH OAM
Substitution
Issue 03 (2013-02-20)
The N2EGT2 can substitute for the N1EGT2.

799

12 EoS Boards
12.3.2 Application
The EGT2 is used to transmit/receive Ethernet services, manage bandwidths, and converge
Ethernet services.
NMS
User A2
NE1
PORT 1
NE2
MSP ring
PORT 2
NE4
NE3
User B2
Service flow
Line board
PORT 1
PORT 2
Data board
Cross-connect and
timing board
User B1
User A1

The EGT2 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 12-29 provides the functions and features of the EGT2.
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12 EoS Boards
Table 12-29 Functions and features of the EGT2

Funct
ion
and
Featu
re
Description
Basic
functi
ons
Transparently transmits 2xGE services.
Interfa
ce
types
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical interfaces. The optical

interfaces support the auto-negotiation function in compliance with IEEE 802.3z.
The optical interfaces use the SFP optical module and support hot swapping.
When the multi-mode optical fiber is used, the maximum transmission distance
is 550 m. When the single-mode optical fiber is used, the maximum transmission
distance is 10 km. The optical modules that can meet different requirements for
the transmission distance such as 40 km and 80 km can also be used.
l The N2EGT2 also supports the 1000BASE-T RJ-45 Ethernet electrical interface.
The electrical interface supports the 1000M full-duplex working mode. The
N2EGT2 uses the SFP electrical interface and supports hot swapping. The
maximum transmission distance is 100 m.
Functi
ons
when
being
used
with
an
interfa
ce
board
Provides interfaces on the front panel.
Interfa
ce
charac
teristic
s
Working
modes
1000M full-duplex and auto-negotiation
Traffic
control at
ports
Not supported
Supported
Query/
Supported
Setting of
port
status
Issue 03 (2013-02-20)
Query of
interface
types
Supported
RMON
measure
ment
Supported

801

Funct
ion
and
Featu
re
12 EoS Boards
Description

optical
power
threshold
s
Pluggabl
e optical
module
Issue 03 (2013-02-20)
Supports SFP optical modules.
EPL
servic
e
Servic
e
specifi
cation
s
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1q TAG
Supported
Frame
length
range
bytes to 9600 bytes.
Bound
bandwidt
h
16xVC-4, or 48xVC-3
Mapping
granularit
ies

granularities.
Encapsul
ation
formats
HDLC
Supported
LAPS
Supported
GFP-F
Supported
l Supports a jumbo frame with a length less than 9600 bytes.
MPLS
technolo
gy
Not supported
VLAN
technolo
gy
Supports the VLAN transparent transmission.
Maximu
m uplink
bandwidt
h
The maximum uplink bandwidth is 2.5 Gbit/s. The EGT2 can adapt to

802

Funct
ion
and
Featu
re
12 EoS Boards
Description
VCTRU
NK
specificat
ions

l A VCTRUNK can be bound with a maximum of 8 VC-4s or a
maximum of 24 VC-3s. A VCTRUNK can be bound with VC-4s
numbered 1-16 or VC-3s numbered 1-48.
l The virtual concatenation modes of the two VCTRUNKs of the
board should be the same. That is, the two VCTRUNKs should be
of the VC-4 virtual concatenation or of the VC-3 virtual
concatenation.
Protec
tion
schem
es
Clock
synchr
onizati
on
Maint
enanc
e
featur
es
Issue 03 (2013-02-20)
TPS
Not supported
LCAS

LPT
Supports the P2P LPT in GFP bearer mode.
LAG
Not supported
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
l The N1EGT2 does not support the ETH OAM function.
l The N2EGT2 supports CC, LB test, and LT test. The ETH OAM
function complies with IEEE 802.1ag.
Test
Frame
Response
to ping
Not supported
Port
mirroring
Not supported
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported
VC-3 level
Not supported
VC-12 level
Not supported

803

Funct
ion
and
Featu
re
12 EoS Boards
Description
RMON
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events

QoS
Not supported
Traffi
c
contro
l
Supports the GE port-based traffic control function that complies with IEEE 802.3x.

The EGT2 consists of the Ethernet access module, mapping module, interface converting
Figure 12-12 shows the functional block diagram of the EGT2 by describing how to process
1xGE signals.
Issue 03 (2013-02-20)

804

12 EoS Boards
Figure 12-12 Functional block diagram of the EGT2

Backplane
GE
Ethernet
access
module
ENCP
VCP
DENCP
Interface
converting
module
Cross-connect unit
Cross-connect unit
Mapping module
Laser
shutdown
LOS
Logic and
control module
Communication
+3.3 V
Clock module
Power
module
50 77 125 155
MHz MHz MHz MHz
Power
module
SCC unit
SCC unit
Fuse
-48 V/-60 V
-48 V/-60 V
+3.3 V
+3.3 V backup power
Fuse

Mapping Module
signals.
Issue 03 (2013-02-20)

805

12 EoS Boards


l
functions:
l
Clock Module
Power Module
require.
12.3.5 Front Panel

The front panel of the EGT2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-13 shows the appearance of the front panel of the N1EGT2/N2EGT2 that has the GE
optical interface.
Issue 03 (2013-02-20)

806

12 EoS Boards
Figure 12-13 Front panel of the N1EGT2/N2EGT2 that has the GE optical interface
EGT2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
EGT2
The N2EGT2 can also be installed with the GE electrical interface. Figure 12-14 shows the
appearance of the front panel of the N2EGT2 that has the GE electrical interface.
Issue 03 (2013-02-20)

807

12 EoS Boards
Figure 12-14 Front panel of the N2EGT2 that has the GE electrical interface
EGT2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
OUT1
IN1
OUT2
IN2
EGT2
Indicators
l
Issue 03 (2013-02-20)

808

12 EoS Boards
Interfaces
The front panel of the N1EGT2/N2EGT2 has two GE optical interfaces. Table 12-30 describes
the types and usage of the optical interfaces of the N1EGT2/N2EGT2.
Table 12-30 Optical interfaces of the N1EGT2/N2EGT2
Interface
Type of Interface
Usage
IN1/OUT1
LC (swappable)
Transmits and receives 1000BASE-SX/LX/ZX/

VX signals.
IN2/OUT2
LC (swappable)

VX signals.
The two GE electrical interfaces of the N2EGT2 are of the same type and have the same usage.
Table 12-31 describes the types and usage of the electrical interfaces of the N2EGT2.
Table 12-31 Electrical interfaces of the N2EGT2
Interface
Type of Interface
Usage
GE
RJ-45 (swappable)
Transmits and receives 1000BASE-T signals.
Table 12-32 provides the pin assignments of the RJ-45 interface of the N2EGT2.
Table 12-32 Pin assignments of the RJ-45 interface of the N2EGT2
Pin
Description
BI_DA+
BI_DA
BI_DB+
BI_DC+
BI_DC
BI_DB
BI_DD+
BI_DD

The EGT2 does not have any jumpers or DIP switches that are used for board settings.
Issue 03 (2013-02-20)

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12 EoS Boards
12.3.7 Valid Slots

The EGT2 must be installed in a valid slot in the subrack. Otherwise, the EGT2 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EGT2 can be installed in slots 18 and 1116 in the subrack.

l
When the cross-connect capacity is 200 Gbit/s, the slots valid for the EGT2 are as follows:
The N1EGT2 can be installed in slots 14, 58, 1114, and 1516. When the N1EGT2
is installed in slots 14 and 1516, the bandwidth is 1.25 Gbit/s. When the N1EGT2 is
installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
The N2EGT2 can be installed in slots 18 and 1116. In this case, the bandwidth is 2.5
Gbit/s.
12.3.8 Feature Code

The feature code of the EGT2 indicates the type of interface.
Table 12-33 provides the relationship between the feature code of the EGT2 and the type of
interface.
Table 12-33 Relationship between the feature code of the EGT2 and the type of interface
Board
Feature Code
Type of Interface
SSN1EGT210 and
SSN2EGT210
10
1000BASE-SX (0.5 km)
SSN1EGT211 and
SSN2EGT211
11
1000BASE-LX (10 km)
SSN1EGT212 and
SSN2EGT212
12
1000BASE-VX (40 km)
SSN1EGT213 and
SSN2EGT213
13
1000BASE-ZX (80 km)
SSN2EGT214
14
1000BASE-T (100 m)

Issue 03 (2013-02-20)

810

12 EoS Boards

matches the board.
is correct.
----End

NOTE
----End
Issue 03 (2013-02-20)

811

12 EoS Boards

----End

Boards.
the Current Alarms.
----End

The EGT2 supports multiple Ethernet functions and features such as LCAS and LPT. Configure
You can configure the following Ethernet functions for the EGT2 by using the U2000:
l
LCAS
LPT
Test Frame

You can set parameters for the EGT2 by using the U2000.
You can set the following main parameters for the EGT2 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Troubleshooting
Table 12-34 lists the faults that occur on the EGT2 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

812

12 EoS Boards
Table 12-34 Methods used to troubleshoot the faults that occur on the EGT2 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EGT2, see Replacing an EOS Board.

12.3.13.1 Alarms of N1EGT2
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC3

813

12 EoS Boards
B3_SD_VC4
BD_STATUS
BDID_ERROR
COMMUN_FAIL
ETH_LOS
FPGA_ABN
HARD_BAD
HP_RDI
HP_SLM
HP_TIM
HP_UNEQ
LASER_MOD_ERR
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_RDI_VC3
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
LPT_RFI
LSR_NO_FITED
NO_BD_SOFT
TEST_STATUS
TU_AIS_VC3
TU_LOP_VC3
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
T_LOSEX
TR_LOC
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
12.3.13.2 Alarms of N2EGT2
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
AU_LOP
B3_SD_VC3
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC4
BD_STATUS
COMMUN_FAIL
ETH_CFM_RDI
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_UNEXPERI
ETH_LOS
ETH_NO_FLOW
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_RDI
HP_SLM
HP_TIM
HP_UNEQ
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_RDI_VC3
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
LPT_RFI

814

12 EoS Boards
LSR_NO_FITED
LSR_WILL_DIE
LTEMP_OVER
MOD_TYPE_MISMATCH
NO_BD_SOFT
PORT_MODULE_OFFLINE
SUM_INPWR_HI
SUM_INPWR_LOW
SUM_OUTPWR_HI
SUM_OUTPWR_LOW
T_LOSEX
TD
TEMP_OVER
TF
TR_LOC
TU_AIS_VC3
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC3
VCAT_LOM_VC4
VCAT_SQM_VC3
VCAT_SQM_VC4
VCTRUNK_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

12.3.14.1 Performance Events of N1EGT2

Table 12-35 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFECSES
LPFEES
LPFESES
LPSES
DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
FCSErrors
LPUAS
Issue 03 (2013-02-20)

815

12 EoS Boards

Packets Received(64
Octets in Length)
(packets/s)
Octets in Length)(packets/
s)
Packets Received(128~255 Octets

in Length)(packets/s)
Packets Received
(256~511 Octets in
Length)(packets/s)
Packets Received
(512~1023 Octets in
Length)(packets/s)
Octets in Length)(packets/s)
Multicast Packets
Received(packets/s)
Broadcast Packets
Received(packets/s)
Drop Events(times/s)
Undersize Packets
Received(packets/s)

(packets/s)
Fragments(packets/s)
Jabbers(packets/s)
Octets Received(Byte/s)
Packets Received(packets/s)

Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(512~1023 Octets in
Length)(packets/s)
Packets Transmitted
(packets/s)

(packets/s)
Unicast Packets
Transmitted(packets/s)

(packets/s)
Broadcast Packets

(frames/s)

(frames/s)
FCS Errors(frames/s)

Length)(packets/s)

Length)(packets/s)


Transmitted(256~511
s)


12.3.14.2 Performance Events of N2EGT2

Table 12-39 SDH
HPBBE
Issue 03 (2013-02-20)
HPCSES
HPES
816

12 EoS Boards
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
FCSErrors

Packets Received(64
Octets in Length)
(packets/s)
s)
Packets Received(128~255 Octets

Packets Received
(256~511 Octets in
Length)(packets/s)
Packets Received
(512~1023 Octets in
Length)(packets/s)
Multicast Packets
Received(packets/s)
Broadcast Packets
Received(packets/s)
Undersize Packets
Received(packets/s)

(packets/s)
Jabbers(packets/s)

Issue 03 (2013-02-20)
Packets Transmitted
(packets/s)

817

12 EoS Boards
Packets Transmitted
(packets/s)
Packets Transmitted
(512~1023 Octets in
Length)(packets/s)
Packets Transmitted
(packets/s)

(packets/s)
Unicast Packets

(packets/s)
Broadcast Packets

(frames/s)

(frames/s)

Length)(packets/s)

Length)(packets/s)


Transmitted(256~511
s)



The technical specifications of the EGT2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.

Table 12-43 lists the parameters specified for the optical interfaces of the EGT2.
Table 12-43 Parameters specified for the optical interfaces of the EGT2
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
1000BASEZX (80 km)
1000BASE-VX
(40 km)
1000BASELX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched
optical power
range (dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength
range (nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3

818

12 EoS Boards
Parameter
Value
Receiver
sensitivity
(dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Ethernet Electrical Interfaces

Table 12-44 lists the parameters specified for the electrical interfaces of the EGT2.
Table 12-44 Parameters specified for the electrical interfaces of the EGT2
Type of Interface
Code Type
1000BASE-T, RJ-45
4D-PAM5
NOTE
Only the EGT2 boards of the N2 version supports the GE electrical interfaces.

NOTE
specifications, and back-to-back specifications of the EGT2 board of the N1 version.
Figure 12-15 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, and latency specifications of the N1EGT2.
Issue 03 (2013-02-20)

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12 EoS Boards
of overloading, and latency specifications of the N1EGT2
Port 1
Tested
equipment 1
Tested
equipment 2
Port 2
Port 1
Port 2
Data network
performance
analyzer
Figure 12-16 shows the connection for testing the back-to-back specifications of the N1EGT2.
Figure 12-16 Connection for testing the back-to-back specifications of the N1EGT2
Tested
equipment 1
Port 1
Port 2
Data network
performance
analyzer
Table 12-45 lists the throughput specifications of the N1EGT2. Table 12-46 lists the packet
loss ratio in the case of overloading of the N1EGT2. Table 12-47 lists the latency specifications
of the N1EGT2. Table 12-48 lists the back-to-back specifications of the N1EGT2.
Issue 03 (2013-02-20)

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12 EoS Boards
NOTE
are used.
configured and 24 VC-3s are bound on the GE port.
Table 12-45 lists the throughput specifications of the N1EGT2. The values are obtained when
l
Table 12-45 Throughput specifications of the N1EGT2

Frame Size
(Byte)
Passed Rate
(%)
(01,02,01) to
(01,02,02) (pks/
sec)
(01,02,02) to
(01,02,01) (pks/
sec)
Total (pks/
sec)
64
100.00
1488095
1488095
2976190
128
100.00
844595
844595
1689190
256
100.00
452899
452899
905798
512
100.00
234962
234962
469924
1024
100.00
119732
119732
239464
1280
100.00
96154
96154
192308
1518
100.00
81274
81274
162548
Table 12-46 lists the packet loss ratio in the case of overloading of the N1EGT2. The values are
l
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-46 Packet loss ratio in the case of overloading of the N1EGT2
Frame Size
(Byte)
Rate Tested
(%)
(01,02,01) to
(01,02,02) (%)
(01,02,02) to
(01,02,01) (%)
Average (%)
64
100.00
0.000
0.000
0.000
128
100.00
0.000
0.000
0.000
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000
Table 12-47 lists the latency specifications of the N1EGT2. The values are obtained when the
l
Table 12-47 Latency specifications of the N1EGT2
Issue 03 (2013-02-20)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,01) to
(01,02,02) (us)CT (us)
Average
(CT) (us)
(01,02,02) to
(01,02,01)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
35.7
35.7
35.2
35.2
128
100.00
37.1
37.1
36.1
36.1
256
100.00
39.5
39.5
37.4
37.4
512
100.00
44.1
44.1
40.1
40.1
1024
100.00
53.2
53.2
45.1
45.1
1280
100.00
57.6
57.6
47.4
47.4
1518
100.00
61.9
61.9
49.7
49.7

822

12 EoS Boards
Table 12-48 lists the back-to-back specifications of the N1EGT2. The values are obtained when
l
Table 12-48 Back-to-back specifications of the N1EGT2

Frame Size
(Byte)
Rate Tested
(%)
(01,02,01) to
(01,02,02) Burst
Size (Number of
Frames)
(01,02,02) to
(01,02,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
2976190
2976190
5952380
128
100.00
1689190
1689190
3378380
256
100.00
905798
905798
1811596
512
100.00
469924
469924
939848
1024
100.00
239464
239464
478928
1280
100.00
192308
192308
384616
1518
100.00
162548
162548
325096
NOTE
specifications, and back-to-back specifications of the EGT2 board of the N2 version.
in the case of overloading, latency specifications, and back-to-back specifications of the
N2EGT2.
of overloading, latency specifications, and back-to-back specifications of the N2EGT2
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-49 lists the throughput specifications of the N2EGT2. Table 12-50 lists the packet
loss ratio in the case of overloading of the N2EGT2. Table 12-51 lists the latency specifications
of the N2EGT2. Table 12-52 lists the back-to-back specifications of the N2EGT2.
NOTE
are used.
configured and two VC-3s are bound on the GE port.
Table 12-49 lists the throughput specifications of the N2EGT2. The values are obtained when
l
Minimum frame size (byte): 64
Maximum frame size (byte): 1518
Step frame size (byte): Custom
Number of pairs: 1
Initial rate (%): 15
Maximum rate (%): 15
Mode: Uni-directional
Table 12-49 Throughput specifications of the N2EGT2
Issue 03 (2013-02-20)
Frame Size
(byte)
Passed Rate (%)
(01,05,02) to (01,05,01)
(pks/sec)
Total (pks/sec)
64
11.23
167112
334224
128
10.48
88527
177054
256
9.75
44138
88276
512
9.74
22894
45788
1024
9.75
11674
23348
1280
9.75
9373
18746
1518
9.75
7922
15844

824

12 EoS Boards
Table 12-50 lists the packet loss ratio in the case of overloading of the N2EGT2. The values are
l
Number of pairs: 1
Initial rate (%): 11.23
Maximum rate (%): 10.00
Resolution rate (%): None
Table 12-50 Packet loss ratio in the case of overloading of the N2EGT2
Frame Size
(byte)
Rate Tested (%)
(01,05,02) to (01,05,01)
(%)
Average (%)
64
11.23
0.000
0.000
128
10.48
0.000
0.000
256
9.75
0.000
0.000
512
9.74
0.000
0.000
1024
9.75
0.000
0.000
1280
9.75
0.000
0.000
1518
9.75
0.000
0.000
Table 12-51 lists the latency specifications of the N2EGT2. The values are obtained when the
l
Issue 03 (2013-02-20)

825

12 EoS Boards
l
Measure on one receiving card only
Number of pairs: 1
Table 12-51 Latency specifications of the N2EGT2

Frame
Size
(byte)
Rate
Tested
(%)
(01,05,02) to
(01,05,01) (us)CT (us)
Average
(CT) (us)
(01,05,02) to
(01,05,01)
(us)-S&F (us)
Average
(S&F) (us)
64
11.23
92.7
92.7
92.1
92.1
128
10.48
97.7
97.7
96.6
96.6
256
9.75
109.5
109.5
107.5
107.5
512
9.74
133.1
133.1
129.0
129.0
1024
9.75
178.8
178.8
170.6
170.6
1280
9.75
204.1
204.1
193.9
193.9
1518
9.75
224.0
224.0
211.9
211.9
Table 12-52 lists the back-to-back specifications of the N2EGT2. The values are obtained when
l
a value more than 1 on the SmartApplication.
Number of pairs: 1
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-52 Back-to-back specifications of the N2EGT2

Frame Size
(byte)
Rate Tested (%)
(01,05,02) to (01,05,01)
Burst Size (frames)
Total (frames)
64
11.23
334224
668448
128
10.48
177054
354108
256
9.75
88276
176552
512
9.74
45754
91508
1024
9.75
23348
46696
1280
9.75
18752
37504
1518
9.75
15848
31696
Laser Safety Class

The mechanical specifications of the EGT2 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the N1EGT2 at room temperature (25C) is 29 W.
The maximum power consumption of the N2EGT2 at room temperature (25C) is 15 W.
12.4 EFS0

The EFS0 is available in several functional versions. Select a functional board according to
actual requirements.
The EFS0 is available in the following functional versions: N1, N2, N4, and N5. The
N2EFS0/N1EFS0 is discontinued.
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-53 describes the versions of the EFS0.

Table 12-53 Versions of the EFS0
Item
Description
Functional
versions
The EFS0 is available in the following functional versions: N1, N2, N4,
and N5.
Differences
l Regarding interface specifications: interface types, functions when

being used with an interface board
l Regarding service specifications: MTU, bound bandwidth,
maximum uplink bandwidth, VCTRUNK specifications
l Regarding protection schemes: TPS, LCAS, LPT, LAG
l Regarding maintenance features: ETH OAM, test frame, , port
mirroring, loopback capability, warm resets
l QoS
Substitution
The N2EFS0 supports the board version replacement function and can
replace the N1EFS0.
replace the N2EFS0/N1EFS0.
replace the N4EFS0/N2EFS0/N1EFS0.
12.4.2 Application
The EFS0 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
2 switching of Ethernet services.
Figure 12-18 shows the typical networking and application of the Ethernet switching board. the
Ethernet switching board accesses and converges Ethernet services, and provides the Ethernet
data with the following data features: Layer 2 switching, port isolation, flow classification, traffic
control, VLAN management, and priority configuration. In addition, the Ethernet switching
board performs encapsulation/decapsulation, virtual concatenation, and SDH mapping/
demapping for data. The Ethernet switching board can be interconnected with the bandwidth
access equipment and the data communication equipment at the same time, thus to provide a
network-level solution.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-18 Networking and application of the Ethernet switching board
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EFS0 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 12-54 provides the functions and features of the EFS0.
Table 12-54 Functions and features of the EFS0
Function and
Feature
Description
Basic functions
Processes 8xFE services.
Interface types
l Supports 10BASE-T/100BASE-TX signals when the EFS0 is used

with the ETF8.
l Supports 100BASE-FX/LX/VX/ZX signals when the EFS0 is used
with the EFF8. The optical interfaces comply with IEEE 802.3u.
l The N5EFS0 supports 10BASE-T/100BASE-TX signals when it is
used with the ETF8A.
l The N5EFS0 supports 100BASE-FX/LX signals when it is used
with the EFF8A. The optical interfaces comply with IEEE 802.3u.
Issue 03 (2013-02-20)

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12 EoS Boards
Function and
Feature
Description
Functions when
being used with an
interface board
l Receives/Transmits 8xFE signals through the electrical interface

when the EFS0 is used with the ETF8.
l Receives/Transmits 8xFE signals through the optical interface when
the EFS0 is used with the EFF8.
l Provides the TPS protection for the 8xFE signals through the
electrical interface when the EFS0 is used with the ETS8 and TSB8.
l The N5EFS0 can receive/transmit 8xFE signals through the
electrical interface when it is used with the ETF8A.
l The N5EFS0 can receive/transmit 8xFE signals through the optical
interface when it is used with the EFF8A.
Workin
g
modes
Interface
characteristics
l FE electrical port: auto-negotiation, 100M full-duplex,

100M half-duplex, 10M full-duplex, and 10M halfduplex
l FE optical port: 100M full-duplex
l An N5EFS0 board supports only the auto-negotiation and
100M full-duplex working mode when working with an
EFF8A board.
Service categories
Issue 03 (2013-02-20)
Traffic
control
at ports
Supported (Not supported by

FE optical ports)
Supported (not supported if

an EFS0 board works with an
EFF8 board)
Query/
Setting
of port
status
Supported
Query
of
interfac
e types
Supported
Setting
of
optical
power
thresho
lds
Not supported
Plugga
ble
optical
module
Not supported
EPL
service

830

Function and
Feature
12 EoS Boards
Description
EVPL
service
l Supports PORT-shared EVPL services.

l Supports VCTRUNK-shared EVPL services.
The services are isolated by VLAN tags.
The services are isolated by MPLS tags.
The services are isolated by QinQ tags.
l Supports a maximum of 4096 links.
EPLA
N
service
N4EFS0/N5EFS0 boards support the EPLAN services that

are based on the IEEE 802.1d MAC bridge.
l Supports the blacklist that can contain 2K records and
also the static MAC address table that can contain 2K
records. The sum of the number of records in the blacklist
and the number of addresses in the static MAC address
table must not exceed 2K. The blacklist function of
N5EFS0 boards supports verification of destination
MAC addresses only.
l Supports the self-learning of the source MAC address.
The capacity of the MAC address table is 16K. The aging
time of the MAC address can be set and queried.
l Supports the configuration of static MAC routes.
l N4EFS0/N5EFS0 boards support the query of dynamic
MAC addresses.
l The maximum number of supported VBs is 16. The
maximum number of logical ports for each VB is 30.
l Queries the number of actually learned MAC addresses
based on VB+VLAN or VB+LP.
Service
specifications
Issue 03 (2013-02-20)
EVPL
AN
service
s
l Supports data isolation based on VB+VLAN.
Format
s of
Etherne
t data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1 q/p
Supported
Frame
length
range
l Supports the setting of the frame length to a value ranging

from 1518 bytes to 9600 bytes.
l Supports the setting of a maximum of 4096 VLAN

services.
l Supports the EVPLAN services that are based on the
IEEE 802.1q virtual bridge.
l Supports a jumbo frame with a maximum length of 9600

bytes.

831

Function and
Feature
12 EoS Boards
Description
Bound
bandwi
dth
N1EFS0: 12xVC-3, or 63xVC-12 + 9xVC-3
Mappin
g
granula
rities
Supports VC-12, VC-3, VC-12-Xv (X 63), and VC-3-Xv

(X 12) granularities.
Encaps
ulation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
N2EFS0/N4EFS0/N5EFS0: 24xVC-3, or 126xVC-12 +

18xVC-3
MPLS
technol
ogy
Supports the MPLS.
VLAN
technol
ogy
Supports 4094 VLANs. The VLAN technology complies

with IEEE 802.1q/p.
Maxim
um
uplink
bandwi
dth
l The maximum uplink bandwidth of the N1EFS0 is 622

Mbit/s.
VCTR
UNK
specific
ations
The number of supported VCTRUNKs is as follows:
l The maximum uplink bandwidth of the N2EFS0/

N4EFS0/N5EFS0 is 1.25 Gbit/s.
l The EFS0 can adapt to the bandwidth of the slot.
l The number of VCTRUNKs supported by the N1EFS0

is 12.
l The number of VCTRUNKs supported by the N2EFS0/
N4EFS0/N5EFS0 is 24.
l VCTRUNK 1VCTRUNK 12 can be bound with VC-4s
numbered 14 only. VCTRUNK 13VCTRUNK 24 can
be bound with VC-4s numbered 58 only.
l VC-4s numbered 4 and 8 support the binding of VC-3
and VC-12 paths. The other VC-4s support the binding
of VC-3 paths only.
l A VCTRUNK can be bound with the VC-12 path or VC-3
path at one time. A VCTRUNK should not be bound with
VC-12 and VC-3 paths at the same time.
Protection schemes
Issue 03 (2013-02-20)
TPS
Not supported by the N1EFS0 but supported by the N2EFS0/

N4EFS0/N5EFS0.

832

Function and
Feature
12 EoS Boards
Description
BPS
Not supported
PPS
Not supported
DLAG
Not supported
LAG
The N1EFS0 does not support link aggregation, but the

N2EFS0/N4EFS0/N5EFS0 supports manual link
aggregation and the load sharing mode that comply with
IEEE 802.3ad and IEEE 802.1AX.
LCAS
Not supported by the N1EFS0/N2EFS0

Dynamically increases or decreases the bandwidth and
protects the bandwidth in compliance with ITU-T G.7042.
This protection scheme is supported by the N4EFS0/
N5EFS0.
Clock
synchronization
LPT
The N1EFS0/N2EFS0 supports the P2P LPT. The N4EFS0/

N5EFS0 supports the P2P LPT and P2MP LPT.
STP/
RSTP
Supports the broadcast packet suppression function and

RSTP that comply with IEEE 802.1w.
MSTP
Not supported
Synchr
onous
Etherne
t
Not supported
IEEE
1588v2
Not supported
l The N1EFS0 and N2EFS0 do not support the ETH OAM
function.
Maintenance
features
l N4EFS0 and N5EFS0 boards support CC, LB tests, and

LT tests in compliance with IEEE 802.1ag, LM and DM
in compliance with ITU-T Y.1731, and OAM ping in
compliance with Huawei proprietary protocol.
l N4EFS0 and N5EFS0 boards support OAM autodiscovery, remote loopbacks, fault detection, and link
performance detection in compliance with IEEE 802.3ah,
and selfloop detection in compliance with Huawei
proprietary protocol.
Test
Frame
l The N1EFS0/N2EFS0 supports test frames in Ethernet

bearer mode.
l The N4EFS0/N5EFS0 supports test frames in Ethernet/
GFP bearer mode.
Issue 03 (2013-02-20)

833

Function and
Feature
12 EoS Boards
Description
Respon
se to
ping
Not supported
Port
mirrori
ng
The N1EFS0/N2EFS0/N4EFS0 does not supports port

mirroring. The N5EFS0 supports ingress mirroring.
Loopba
ck
capabili
ty
Inloops
Inloops
VC-4 level
Not supported
VC-3 level
The N1EFS0/N2EFS0/
N4EFS0 supports inloops
and outloops. The N5EFS0
does not support inloops or
outloops.
VC-12 level
Not supported
RMON
Warm
resets
N1EFS0/N2EFS0/N4EFS0/N5EFS0 boards support warm

resets. If a warm reset is performed on an N1EFS0/N2EFS0
board, traffic on the board is interrupted, whereas if a warm
reset is performed on an N4EFS0/N5EFS0 board, traffic on
the board is not interrupted. If an N4EFS0/N5EFS0 board
substitutes for an N1EFS0/N2EFS0 board, traffic on the
N4EFS0/N5EFS0 board is not interrupted.
Cold
resets
Supported
Alarms
and
perfor
mance
events
Reports various alarms and performance events, which

facilitates the management and maintenance of the
equipment.
l Supports the CAR. The granularity is 64 kbit/s.
QoS
l The N1EFS0 supports the service classification based on PORT,

PORT+VLAN ID, or PORT+VLAN PRI.
l The N2EFS0, N4EFS0, and N5EFS0 support the flow classification
based on PORT, PORT++VLAN ID, or PORT+VLAN ID+VLAN
PRI.
IGMP snooping
Issue 03 (2013-02-20)
Protoco
l
enablin
g
Supported

834

Function and
Feature
Traffic control
12 EoS Boards
Description
Port
aging
time
Supported
Fast
leave
Not supported by N1EFS0/N2EFS0/N4EFS0 boards
Discard
ing of
unkno
wn
broadca
st
packets
Not supported by N1EFS0/N2EFS0/N4EFS0 boards
Static
broadca
st entry
Not supported
Supported by N5EFS0 boards
Supported by N5EFS0 boards
Supports the port-based traffic control function that complies with IEEE
802.3x.

The EFS0 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-19 shows the functional block diagram of the EFS0 by describing how to process
1xFE signals.
Issue 03 (2013-02-20)

835

12 EoS Boards
Figure 12-19 Functional block diagram of the EFS0

Backplane
Control
Switch
fabric
Data
Cross-connect unit
Cross-connect unit
Mapping module
Network processor module

Laser
shutdown
Interface
converting
module
VCP
Network
processor
DENCP
Ethernet
access
module
ENCP
FE
LOS
Communication
Logic and
control module
+3.3 V
Clock module
Power Fuse
module
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
50 77 125 155
MHz MHz MHz MHz
SCC unit
SCC unit
Fuse

Network Processor Module

The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l
Multi-protocol label switching (MPLS)
L2 MPLS VPN
Ethernet/VLAN
Issue 03 (2013-02-20)

836

12 EoS Boards
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l
Flow sense and flow classification
Unicast, multicast, and broadcast of the flow
Setting of data priorities
Weighted fair queuing (WFQ)
Four classes of service (CoSs)
Mapping Module
In the upstream direction, this module first encapsulates Ethernet signals in GFP format. The
concatenation is performed. Then, the Ethernet signals are converted into SDH signals.


l
functions:
l
Issue 03 (2013-02-20)

837

12 EoS Boards
Clock Module
Power Module
require.
12.4.5 Front Panel

The front panel of the EFS0 has indicators and a bar code.

Figure 12-20 shows the appearance of the front panel of the EFS0.
Figure 12-20 Front panel of the EFS0
EFS0
STAT
ACT
PROG
SRV
EFS0
Issue 03 (2013-02-20)

838

12 EoS Boards
Indicators
l
Interfaces
The front panel of the EFS0 has no interfaces. The interfaces are available on the ETF8 or on
the EFF8. When the N5EFS0 is used with the ETF8A or EFF8A, the interfaces are available on
the ETF8A or on the EFF8A.

The EFS0 does not have any jumpers or DIP switches that are used for board settings.
12.4.7 Valid Slots

The EFS0 must be installed in a valid slot in the subrack. Otherwise, the EFS0 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EFS0 must be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0, ETS8, and
TSB8 when the EFS0 works with the ETS8 and TSB8, see 12.4.9 Board Protection.
The N5EFS0 can be used with the ETF8A and EFF8A. When the N5EFS0 works with the ETF8A
or EFF8A, the slots valid for the N5EFS0 are the same as the slots valid for the N5EFS0 when
the N5EFS0 works with the ETF8 or EFF8.
The slots valid for the EFS0 vary with the version of the board and the cross-connect capacity
of the subrack. The slots valid for the board are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the N1EFS0 can be installed in slots 25
and 1316. In this case, the bandwidth is 622 Mbit/s.
When the cross-connect capacity is 200 Gbit/s, the N2EFS0, N4EFS0, and N5EFS0 can
be installed in slots 25 and 1316. In this case, the bandwidth is 1.25 Gbit/s.
Table 12-55 lists the slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8.
Issue 03 (2013-02-20)

839

12 EoS Boards
Table 12-55 Slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8
Corresponding Slot for the ETF8 and EFF8
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35
12.4.8 Feature Code

The EFS0 does not have the feature code.

The EFS0 supports the 1:1 TPS protection.
NOTE
Figure 12-21 shows the slot configuration for the 1:1 TPS protection for the EFS0.
Issue 03 (2013-02-20)

840

12 EoS Boards
S
L
O
T
2
7
S
L
O
T
2
8
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
5
S
L
O
T
3
4
S
L
O
T
1
0
XCS
S
L
O
T
3
6
S
L
O
T
3
7
FAN
S
L
O
T
1
1
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
Working 2
S
L
O
T
9
XCS
S S S S
L L L L
O O O O
T T T T
5 6 7 8
Working 1
Protection 1
S
L
O
T
4
S
L
O
T
3
0
FAN
FAN
S S S
L L L
O O O
T T T
1 2 3
S
L
O
T
2
9
AUX
S
L
O
T
2
6
GSCC
S
L
O
T
2
5
TSB8
S
L
O
T
2
4
Protection 2
S
L
O
T
2
3
ETS8
S
L
O
T
2
2
ETS8
S
L
O
T
2
1
PIU
S
L
O
T
2
0
TSB8
S
L
O
T
1
9
PIU
Figure 12-21 Slot configuration for the 1:1 TPS protection for the EFS0
Fiber routing area
In Figure 12-21, the board in slot 2 protects the board in slot 3 and the board in slot 16 protects
the board in slot 15. The ETS8 is used with the working EFS0 and the TSB8 is used with the
protection EFS0. Table 12-56 lists the slots for the EFS0, ETS8, and TSB8.
Table 12-56 Slots for the EFS0, ETS8, and TSB8
Issue 03 (2013-02-20)
Board
Protection Group 1
Protection Group 2
EFS0 (protection)
Slot 2
Slot 16
EFS0 (working)
Slot 3
Slot 15
TSB8
Slot 19
Slot 35
ETS8
Slot 21
Slot 33

841

12 EoS Boards


matches the board.
is correct.
----End

Step 2 Required: Configure services. For details, see Configuring Ethernet Services.
J2 byte: The setting of the J2 byte on the interconnected equipment must be consistent.
Generally, use the default value. The default value of the J2 to be sent is HuaWei SBS
and the default value of the J2 to be received is Disabled.
NOTE
Step 4 Optional: Configure the Layer 2 switching management service, including the following tasks:
l Enabling the IGMP Snooping Protocol
Issue 03 (2013-02-20)

842

12 EoS Boards
l Configuring the Spanning Tree

l Setting the Aging Time for the Multicast Router Port
Step 5 Optional: Configure the QoS. For details, see Configuring QoS.
Step 6 Optional: Configure the link aggregation function on the Ethernet port. For details, see Creating
a LAG.
----End

----End

Boards.
the Current Alarms.
----End

The EFS0 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
and QoS. Configure the functions according to actual requirements.
You can configure the following Ethernet functions for the EFS0 by using the U2000:
l
LCAS
QoS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EFS0 by using the U2000.
You can set the following main parameters for the EFS0 by using the U2000:
Issue 03 (2013-02-20)

843

Working mode
LCAS
Mapping protocol
12 EoS Boards
Settings.

Troubleshooting
Table 12-57 lists the faults that occur on the EFS0 frequently and the troubleshooting methods.
Table 12-57 Methods used to troubleshoot the faults that occur on the EFS0 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Issue 03 (2013-02-20)

844

12 EoS Boards
Replacing the Board

NOTE
replace the board.
For information on how to replace the EFS0, see Replacing an EOS Board.

12.4.14.1 Alarms of N1EFS0

ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
LCAS_BAND_DECREASED
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_RFI
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LSR_NO_FITED
NO_BD_SOFT
SUBCARD_ABN
TEMP_OVER
T_LOS
TU_LOP_VC12
TU_AIS_VC12
TU_AIS_VC3
VCAT_LOM_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_SQM_VC3
VCAT_LOM_VC3
VCAT_SQM_VC12
W_R_FAIL
PROTOCOL_MM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD

845

12 EoS Boards
LAG_FAIL
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LSR_NO_FITED
NO_BD_SOFT
SLAVE_WORKING
SUBCARD_ABN
T_LOS
TPS_ALM
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
ETHOAM_DISCOVER_FAI
L
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_LOO
P
FLOW_OVER
FPGA_ABN
FCS_ERR
HP_LOM
LAG_FAIL
HARD_BAD
LCAS_PLCR
LASER_MOD_ERR
LCAS_FOPT
LCAS_TLCT
LCAS_FOPR
LCAS_TLCR
LP_REI_VC12
LCAS_PLCT
LOOP_ALM
LP_SLM_VC3
LP_RDI_VC12
LINK_ERR
LP_UNEQ_VC12
LP_REI_VC3
LP_RDI_VC3
LSR_NO_FITED
LP_TIM_VC12
LP_SLM_VC12
NO_BD_SOFT
LP_UNEQ_VC3
LP_TIM_VC3

846

12 EoS Boards
SUM_INPWR_HI
LSR_WILL_DIE
LPT_RFI
SUM_OUTPWR_LOW
SLAVE_WORKING
LTEMP_OVER
TF
SUM_INPWR_LOW
SUBCARD_ABN
TU_AIS_VC3
T_LOS
SUM_OUTPWR_HI
VCAT_LOA
TPS_ALM
TD
VCAT_LOM_VC3
TU_LOP_VC12
TU_AIS_VC12
TR_LOC
VCAT_LOM_VC12
TU_LOP_VC3
T_LOSEX
EX_ETHOAM_CC_LO
S
EX_ETHOAM_MPID_CNFL
CT
PATCH_NOT_CONFIRM
ALM_GFP_dCSF
PATCH_ERR
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETH_LOS
ETH_NO_FLOW
ETHOAM_DISCOVER_FA
IL
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_LOM
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12

847

12 EoS Boards
LP_UNEQ_VC3
LPT_RFI
LSR_NO_FITED
LSR_WILL_DIE
LTEMP_OVER
NO_BD_SOFT
SUBCARD_ABN
SUM_INPWR_HI
SUM_INPWR_LOW
SUM_OUTPWR_HI
SUM_OUTPWR_LOW
T_LOSEX
TD
TEMP_OVER
TF
TPS_ALM
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
VCTRUNK_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

12.4.15.1 Performance Events of N1EFS0

Table 12-58 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
Issue 03 (2013-02-20)
DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

848

12 EoS Boards

Packets Received(64
Octets in Length)
(packets)
Packets Received
(256~511 Octets in
Length)(packets)
Multicast Packets
Received(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Octets Received(Byte)
Packets Received
(packets)

Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
Packets Transmitted
(512~1023 Octets in Length) (1024~1518 Octets in Length)
(packets)
(packets)

(packets)

(packets)

(packets)
Broadcast Packets

(Byte)
Alignment Errors(frames)
FCS Errors(frames)
Good Full Frame Speed

Received(Byte/s)
Good Full Frame Octets

Transmitted(Byte)

Received(Byte)

Transmitted(Byte/s)

Table 12-62 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES

849

12 EoS Boards
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64
Octets in Length)
(packets)
Packets Received
(256~511 Octets in
Length)(packets)
Multicast Packets
Received(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Packets Received
(packets)
Issue 03 (2013-02-20)
Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
Packets Transmitted
(packets)
(packets)

(packets)

(packets)


(packets)
850

12 EoS Boards
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte)

Received(Byte)

Transmitted(Byte/s)

Table 12-66 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors
Issue 03 (2013-02-20)
Packets Received(64
Octets in Length)
(packets)
Packets Received
(256~511 Octets in
Length)(packets)
Multicast Packets
Received(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)

851

Jabbers(packets)
Collisions(times)
12 EoS Boards
Packets Received
(packets)

Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
Packets Transmitted
(packets)
(packets)

(packets)

(packets)

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte)

Received(Byte)

Transmitted(Byte/s)

Table 12-70 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

852

12 EoS Boards

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64

(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Packets Received(packets)

Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(512~1023 Octets in
Length)(packets)
Packets Transmitted
(packets)

(packets)
Unicast Packets

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Received(Byte)

Transmitted(Byte)

The technical specifications of the EFS0 include the dimensions, weight, and power
consumption.
Issue 03 (2013-02-20)

853

12 EoS Boards

NOTE
specifications, and back-to-back specifications of the EFS0 board of the N4 version.
N4EFS0.
of overloading, latency specifications, and back-to-back specifications of the N4EFS0
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-74 lists the throughput specifications of the N4EFS0. Table 12-75 lists the packet loss
ratio in the case of overloading of the N4EFS0. Table 12-76 lists the latency specifications of
the N4EFS0. Table 12-77 lists the back-to-back specifications of the N4EFS0.
NOTE
l The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
l The specific test results depend on the settings on the SmartApplication. The values listed in the
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
Table 12-74 lists the throughput specifications of the N4EFS0. The values are obtained when
l
Issue 03 (2013-02-20)

854

Step frame size (byte): custom
Number of pairs: 1
Mode: bidirectional
12 EoS Boards
Table 12-74 Throughput specifications of the N4EFS0

Frame Size
(Byte)
Passed Rate
(%)
(01,02,03) to
(01,02,05) (pks/
sec)
(01,02,05) to
(01,02,03) (pks/
sec)
Total (pks/
sec)
64
11.48
17088
17088
34176
128
11.25
9502
9502
19004
256
11.13
5042
5042
10084
512
11.12
2613
2613
5226
1024
11.07
1326
1326
2652
1280
11.10
1067
1067
2134
1518
11.12
904
904
1808
Table 12-75 lists the packet loss ratio in the case of overloading of the N4EFS0. The values are
l
Number of pairs: 1
Resolution rate (%): none
Mode: bidirectional
Table 12-75 Packet loss ratio in the case of overloading of the N4EFS0
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) (%)
(01,02,05) to
(01,02,03) (%)
Average (%)
64
100.00
88.507
88.507
88.507

855

12 EoS Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) (%)
(01,02,05) to
(01,02,03) (%)
Average (%)
128
100.00
88.730
88.745
88.737
256
100.00
88.851
88.831
88.841
512
100.00
88.876
88.846
88.861
1024
100.00
88.901
88.890
88.895
1280
100.00
88.878
88.878
88.878
1518
100.00
88.850
88.844
88.847
Table 12-76 lists the latency specifications of the N4EFS0. The values are obtained when the
l
CT: cut through or FIFO; S&F: store forward or LIFO
Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
Number of pairs: 1
Mode: bidirectional
Table 12-76 Latency specifications of the N4EFS0
Issue 03 (2013-02-20)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,03) to
(01,02,05) (us)CT (us)
Average
(CT) (us)
(01,02,03) to
(01,02,05)
(us)-S&F (us)
Average
(S&F) (us)
64
10.00
561.4
561.4
556.2
556.2

856

12 EoS Boards
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,03) to
(01,02,05) (us)CT (us)
Average
(CT) (us)
(01,02,03) to
(01,02,05)
(us)-S&F (us)
Average
(S&F) (us)
128
10.00
644.4
644.4
634.2
634.2
256
10.00
738.4
738.4
718.0
718.0
512
10.00
948.8
948.8
907.9
907.9
1024
10.00
1371.5
1371.5
1289.6
1289.6
1280
10.00
1604.1
1604.1
1501.7
1501.7
1518
10.00
1790.4
1790.4
1669.0
1669.0
Table 12-77 lists the back-to-back specifications of the N4EFS0. The values are obtained when
l
Number of pairs: 1
Mode: bidirectional
Table 12-77 Back-to-back specifications of the N4EFS0
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)
(01,02,05) to
(01,02,03)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
1333
1335
2668
128
100.00
848
850
1698
256
100.00
586
587
1173
512
100.00
445
447
892

857

12 EoS Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)
(01,02,05) to
(01,02,03)
(Number of
Frames)
Total
(Number of
Frames)
1024
100.00
224
224
448
1280
100.00
211
212
423
1518
100.00
201
201
402
NOTE
N5EFS0.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-78 lists the throughput specifications of the N5EFS0. Table 12-79 lists the packet loss
ratio in the case of overloading of the N5EFS0. Table 12-80 lists the latency specifications of
the N5EFS0. Table 12-81 lists the back-to-back specifications of the N5EFS0.
Issue 03 (2013-02-20)

858

12 EoS Boards
NOTE
are used.
configured 3 VC-3s are bound on the FE port.
l
The permitted packet loss ratio is set to 0% and the resolution rate is set to 1%.
Number of pairs: 1
Maximum rate (%): None

Frame Size
(byte)
Passed Rate (%)
(01,06,01) to (01,06,02)
(pks/sec)
Total (pks/sec)
64
100.00
148810
148810
128
100.00
84459
84459
256
100.00
45290
45290
512
100.00
23496
23496
1024
100.00
11973
11973
1280
100.00
9615
9615
1518
100.00
8127
8127
Table 12-79 lists the packet loss ratio in the case of overloading of the N5EFS0. The values are
Issue 03 (2013-02-20)

859

12 EoS Boards
Number of pairs: 1
Frame Size
(byte)
Rate Tested (%)
(01,06,01) to (01,06,02)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
l
CT: Cut Through (or FIFO),S&F: Store & Forward (or LIFO)
Measure on one receiving card only, Mode: SmartMetrics Comp. Mode
Issue 03 (2013-02-20)

860

Number of pairs: 1
12 EoS Boards

Frame
Size
(byte)
Rate
Tested
(%)
(01,06,01) to
(01,06,02) (us)CT (us)
Average
(CT) (us)
(01,06,01) to
(01,06,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
124.3
124.3
119.2
119.2
128
100.00
137.4
137.4
127.2
127.2
256
100.00
169.6
169.6
149.2
149.2
512
100.00
211.5
211.5
170.6
170.6
1024
100.00
294.4
294.4
212.4
212.4
1280
100.00
334.5
334.5
232.1
232.1
1518
100.00
368.7
368.7
247.3
247.3
l
Number of pairs: 1
Issue 03 (2013-02-20)

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12 EoS Boards

Frame Size
(byte)
Rate Tested (%)
(01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64
100.00
297620
297620
128
100.00
168918
168918
256
100.00
90580
90580
512
100.00
46992
46992
1024
100.00
23946
23946
1280
100.00
19230
19230
1518
100.00
16254
16254
The mechanical specifications of the EFS0 are as follows:
l
Weight of the N1EFS0 (kg): 1.0
Power Consumption
The maximum power consumption of the N1EFS0 at room temperature (25C) is 35 W.
12.5 EFS0A
technical specifications of the EFS0A (16xFE switching and processing board). This topic also
describes how to configure and commission the EFS0A.

The EFS0A is available in one functional version, namely, N1.
Issue 03 (2013-02-20)

862

12 EoS Boards
12.5.2 Application
The EFS0A is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EFS0A supports the Layer 2 switching, MPLS, and broadcast functions.
Table 12-82 provides the functions and features of the EFS0A.
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863

12 EoS Boards
Table 12-82 Functions and features of the EFS0A

Funct
ion
and
Featu
re
Description
Basic
functi
ons
Interfa
ce
types
l Supports 10BASE-T/100BASE-TX signals when the EFS0A is used with the

ETF8.
Functi
ons
when
being
used
with
an
interfa
ce
board
l Receives/Transmits 16xFE signals through the electrical interface when the

EFS0A is used with the ETF8.
Interfa
ce
charac
teristic
s
Working
modes
l Supports 100BASE-FX/LX signals when the EFS0A is used with the EFF8. The
optical interfaces comply with IEEE 802.3u.
l Receives/Transmits 16xFE signals through the optical interface when the EFS0A
is used with the EFF8.
l Receives/Transmits 8xFE signals through the electrical interface and 8xFE
signals through the optical interface when the EFS0A is used with the ETF8 and
EFF8.
l Provides the TPS protection for the 16xFE signals through the electrical interface
when the EFS0A is used with the ETS8 and TSB8.
l FE electrical port: auto-negotiation, 100M full-duplex, 100M halfduplex, 10M full-duplex, and 10M half-duplex
l FE optical port: 100M full-duplex
Traffic
control at
ports
Supported (Not supported by FE

optical ports)
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported
RMON
measure
ment
Supported

optical
power
threshold
s
Issue 03 (2013-02-20)

864

Funct
ion
and
Featu
re
Servic
e
catego
ries
12 EoS Boards
Description
Pluggabl
e optical
module
Not supported
EPL
service
EVPL
service

EPLAN
service
l Supports the blacklist that can contain 2K records and also the static
MAC address table that can contain 2K records. The sum of the
number of records in the blacklist and the number of addresses in
the static MAC address table must not exceed 2K. The blacklist
function supports verification of destination MAC addresses only.
l Supports the self-learning of the source MAC address. The capacity
of the MAC address table is 16K. The aging time of the MAC
address can be set and queried.
l N1EFS0, N2EFS0, and N5EFS0 boards support the query of
dynamic MAC addresses.
l Supports the query of dynamic MAC addresses.
l The maximum number of supported VBs is 16. The maximum
number of logical ports for each VB is 48.
l Queries the number of actually learned MAC addresses based on
VB+VLAN or VB+LP.
l Supports the EPLAN services that are based on the IEEE 802.1d
MAC bridge.
EVPLA
N service

l Supports the setting of a maximum of 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge.
virtual bridge and IEEE 802.1ad provider bridge.
Servic
e
specifi
Issue 03 (2013-02-20)
Formats
of
Ethernet
IEEE 802.3
Supported
Ethernet II
Supported

865

12 EoS Boards
Funct
ion
and
Featu
re
Description
cation
s
data
frames
IEEE 802.1 q/p
Frame
length
range
l Supports the setting of the frame length to a value ranging from 1518
Bound
bandwidt
h
48xVC-3, or 252xVC-12 + 36xVC-3
Mapping
granularit
ies

granularities.
Encapsul
ation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
Supported
l Supports a jumbo frame with a maximum length of 9600 bytes.
MPLS
technolo
gy
Supports the MPLS.
VLAN
technolo
gy
Supports 4094 VLANs. The VLAN technology complies with IEEE

802.1q/p.
Maximu
m uplink
bandwidt
h
The maximum uplink bandwidth is 2.5 Gbit/s.
VCTRU
NK
specificat
ions
The EFS0A can adapt to the bandwidth of the slot.

l VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3 and
VC-12 paths. The other VC-4s support the binding of VC-3 paths
only.
Protec
tion
schem
es
Issue 03 (2013-02-20)
TPS
Supported
BPS
Not supported
PPS
Not supported

866

Funct
ion
and
Featu
re
Clock
synchr
onizati
on
Description
DLAG
Not supported
LAG
Supports manual link aggregation and the load sharing mode that
comply with IEEE 802.3ad and IEEE 802.1AX.
LCAS

LPT
Supports the P2P LPT and P2MP LPT.
STP/
RSTP
Supports the broadcast packet suppression function and RSTP that

comply with IEEE 802.1w.
MSTP
Not supported
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
l Supports CC, LB tests, and LT tests in compliance with IEEE
802.1ag, LM and DM in compliance with ITU-T Y.1731, and OAM
ping in compliance with Huawei proprietary protocol.
Maint
enanc
e
featur
es
l Supports OAM auto-discovery, remote loopbacks, fault detection,

and link performance detection in compliance with IEEE 802.3ah,
and selfloop detection in compliance with Huawei proprietary
protocol.
Test
Frame
Supports test frames in ETH and GFP bearer modes.
Response
to ping
Not supported
Port
mirroring
Supports ingress mirroring.
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported
VC-3 level
Not supported
VC-12 level
Not supported
RMON
Issue 03 (2013-02-20)
12 EoS Boards
Supports RMON of the Ethernet performance of Ethernet ports .

867

Funct
ion
and
Featu
re
QoS
12 EoS Boards
Description
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events


l Supports the flow classification based on PORT, PORT+VLAN ID, or PORT
+VLAN ID+VLAN PRI.
IGMP
snoopi
ng
Traffi
c
contro
l
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Not supported
Discardin
g of
unknown
broadcast
packets
Not supported
Static
broadcast
entry
Not supported
Supports the port-based traffic control function that complies with IEEE 802.3x.

The EFS0A consists of the Ethernet access module, network processor module, mapping
module, interface converting module, logic and control module, clock module, and power
module.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-25 shows the functional block diagram of the EFS0A by describing how to process
1xFE signals.
Figure 12-25 Functional block diagram of the EFS0A
Backplane
Control
Switch
fabric
Data
Laser
shutdown
Interface
converting
module
VCP
Network
processor
DENCP
Ethernet
access
module
ENCP
FE
Cross-connect unit
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
Power Fuse
module
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
50 77 125 155
MHz MHz MHz MHz
SCC unit
SCC unit
Fuse


l
MPLS
L2 MPLS VPN
Issue 03 (2013-02-20)

869

12 EoS Boards
Ethernet/VLAN
l
WFQ
Four CoSs
Mapping Module
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.


l
functions:
l
Issue 03 (2013-02-20)

870

12 EoS Boards
Clock Module
Power Module
require.
12.5.5 Front Panel

The front panel of the EFS0A has indicators and a bar code.

Figure 12-26 shows the appearance of the front panel of the EFS0A.
Figure 12-26 Front panel of the EFS0A
EFS0A
STAT
ACT
PROG
SRV
EFS0A
Issue 03 (2013-02-20)

871

12 EoS Boards
Indicators
l
Interfaces
The front panel of the EFS0A has no interfaces. The interfaces are available on the ETF8 board
or on the EFF8 board.

The EFS0A does not have any jumpers or DIP switches that are used for board settings.
12.5.7 Valid Slots

The EFS0A must be installed in a valid slot in the subrack. Otherwise, the EFS0A cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EFS0A can be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0A, ETS8,
and TSB8 when the EFS0A works with the ETS8 and TSB8, see 12.5.9 Board Protection.
The slots valid for the EFS0A vary with the cross-connect capacity of the subrack. The slots
valid for the EFS0A are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the EFS0A can be installed in slots 25 and
1316 in the subrack. In this case, the bandwidth is 2.5 Gbit/s.
Table 12-83 lists the slots valid for the EFS0A and the corresponding slots for the ETF8 and
EFF8.
Table 12-83 Slots valid for the EFS0A and the corresponding slots for the ETF8 and EFF8
Issue 03 (2013-02-20)
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
872

12 EoS Boards
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
12.5.8 Feature Code

The EFS0A does not have the feature code.

The EFS0A supports the 1:1 TPS protection.
NOTE
Figure 12-27 shows the slot configuration for the 1:1 TPS protection for the EFS0A.
Issue 03 (2013-02-20)

873

12 EoS Boards
S
L
O
T
2
8
S
L
O
T
9
S
L
O
T
1
0
XCS
XCS
S S S S
L L L L
O O O O
T T T T
5 6 7 8
Working 1
Protection 1
S
L
O
T
4
S
L
O
T
3
0
S
L
O
T
3
1
S
L
O
T
3
2
S
L
O
T
3
3
S
L
O
T
3
4
S
L
O
T
3
5
S
L
O
T
3
6
S
L
O
T
3
7
FAN
FAN
S S S
L L L
O O O
T T T
1 2 3
S
L
O
T
2
9
AUX
S
L
O
T
2
7
FAN
S
L
O
T
1
1
S
L
O
T
1
2
S S S S S S
L L L L L L
O O O O O O
T T T T T T
1 1 1 1 1 1
3 4 5 6 7 8
GSCC
S
L
O
T
2
6
TSB8
S
L
O
T
2
5
Protection 2
S
L
O
T
2
4
ETS8
TSB8
S
L
O
T
2
3
Working 2
S
L
O
T
2
2
ETS8
TSB8
ETS8
ETS8
S
L
O
T
2
1
PIU
S
L
O
T
2
0
PIU
S
L
O
T
1
9
TSB8
Figure 12-27 Slot configuration for the 1:1 TPS protection for the EFS0A
Fiber routing area
The board in slot 2 protects the board in slots 3 and the board in slot 16 protects the board in slot
15. The ETS8 is used with the working EFS0A and the TSB8 is used with the protection EFS0A.
Table 12-84 lists the slots for the EFS0A, ETS8, and TSB8.
Table 12-84 Slots for the EFS0A, ETS8, and TSB8
Issue 03 (2013-02-20)
Board
Protection Group 1
Protection Group 2
EFS0A (protection)
Slot 2
Slot 16
EFS0A (working)
Slot 3
Slot 15
TSB8
Slots 19 and 20
Slots 35 and 36
ETS8
Slots 21 and 22
Slots 33 and 34

874

12 EoS Boards


matches the board.
is correct.
----End

NOTE
Issue 03 (2013-02-20)

875

12 EoS Boards

a LAG.
----End

----End

Boards.
the Current Alarms.
----End

The EFS0A supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
You can configure the following Ethernet functions for the EFS0A by using the U2000:
l
LCAS
QoS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EFS0A by using the U2000.
You can set the following main parameters for the EFS0A by using the U2000:
Issue 03 (2013-02-20)

876

Working mode
LCAS
Mapping protocol
12 EoS Boards
Settings.

Troubleshooting
Table 12-85 lists the faults that occur on the EFS0A frequently and the troubleshooting methods.
Table 12-85 Methods used to troubleshoot the faults that occur on the EFS0A frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Issue 03 (2013-02-20)

877

12 EoS Boards
Replacing the Board

NOTE
replace the board.
For information on how to replace the EFS0A, see Replacing an EOS Board.

12.5.14.1 Alarms of N1EFS0A
Issue 03 (2013-02-20)
ALM_GFP_dLFD
ALM_GFP_dCSF
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
HP_LOM
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LPT_RFI
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LSR_NO_FITED
NO_BD_SOFT
TEMP_OVER
TD
T_LOSEX
TU_LOP_VC12
TU_AIS_VC12
TU_AIS_VC3
VCAT_LOM_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_SQM_VC3
VCAT_LOM_VC3
VCAT_SQM_VC12
VCTRUNK_NO_FLOW
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETH_NO_FLOW
ETHOAM_DISCOVER_FA
IL
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FLOW_OVER
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR

878

12 EoS Boards
LCAS_TLCT
LINK_ERR
LSR_WILL_DIE
LTEMP_OVER
IN_PWR_HIGH
IN_PWR_LOW
OUT_PWR_HIGH
OUT_PWR_LOW
SUBCARD_ABN
TF
TPS_ALM
TR_LOC
WRG_BD_TYPE

12.5.15.1 Performance Events of N1EFS0A

Table 12-86 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN
Issue 03 (2013-02-20)
DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

879

12 EoS Boards

Packets Received(64

(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)

Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(512~1023 Octets in
Length)(packets)
Packets Transmitted
(packets)

(packets)
Unicast Packets

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Received(Byte)

Transmitted(Byte)

The technical specifications of the EFS0A include the dimensions, weight, and power
consumption.

NOTE
specifications, and back-to-back specifications of the EFS0A board of the N1 version.
in the case of overloading, latency specifications, and back-to-back specifications of the EFS0A.
Issue 03 (2013-02-20)

880

12 EoS Boards
of overloading, latency specifications, and back-to-back specifications
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-90 lists the throughput specifications of the EFS0A. Table 12-91 lists the packet loss
ratio in the case of overloading of the EFS0A. Table 12-92 lists the latency specifications of the
EFS0A. Table 12-93 lists the back-to-back specifications of the EFS0A.
NOTE
The specifications vary according to the configuration and networking of the test environment, port
configured, one VC-3 is bound on the FE port, and the MAC port is set to auto-negotiation mode.
Table 12-90 lists the throughput specifications of the EFS0A. The values are obtained when the
l
Test duration (sec): 3
Number of pairs: 1
Resolution rate (%): 0.01
Mode: bidirectional
Issue 03 (2013-02-20)

881

12 EoS Boards
Table 12-90 Throughput specifications of the EFS0A

Frame Size
(Byte)
Passed Rate
(%)
(01,11,01) to
(01,11,02) (pks/
sec)
(01,11,02) to
(01,11,01) (pks/
sec)
Total (pks/
sec)
64
53.50
79618
79618
159236
128
51.21
43253
43253
86506
256
49.95
22624
22624
45248
512
49.31
11585
11585
23170
1024
49.14
5884
5884
11768
1280
49.15
4726
4726
9452
1518
49.19
3998
3998
7996
Table 12-91 lists the packet loss ratio in the case of overloading of the EFS0A. The values are
l
Number of pairs: 1
Mode: bidirectional
Table 12-91 Packet loss ratio in the case of overloading of the EFS0A
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,11,01) to
(01,11,02) (%)
(01,11,02) to
(01,11,01) (%)
Average (%)
64
100.00
46.497
46.497
46.497
128
100.00
48.820
48.820
48.820
256
100.00
50.127
50.127
50.127
512
100.00
50.804
50.804
50.804
1024
100.00
51.115
51.115
51.115
1280
100.00
51.159
51.159
51.159
1518
100.00
51.176
51.176
51.176

882

12 EoS Boards
Table 12-92 lists the latency specifications of the EFS0A. The values are obtained when the
l
Number of pairs: 1
Mode: bidirectional
Table 12-92 Latency specifications of the EFS0A

Frame
Size
(Byte)
Rate
Tested
(%)
(01,11,01) to
(01,11,02) (us)CT (us)
Average
(CT) (us)
(01,11,01) to
(01,11,02)
(us)-S&F (us)
Average
(S&F) (us)
64
40.00
164.3
164.3
159.2
159.2
128
40.00
199.0
199.0
188.8
188.8
256
40.00
247.0
247.0
226.6
226.6
512
40.00
357.6
357.6
357.6
357.6
1024
40.00
514.8
514.8
432.9
432.9
1280
40.00
613.1
613.1
510.7
510.7
1518
40.00
699.4
699.4
578.0
578.0
Table 12-93 lists the back-to-back specifications of the EFS0A. The values are obtained when
l
Issue 03 (2013-02-20)

883

Number of pairs: 1
Mode: bidirectional
12 EoS Boards
Table 12-93 Back-to-back specifications of the EFS0A

Frame Size
(Byte)
Rate Tested
(%)
(01,11,01) to
(01,11,02) Burst
Size (Number of
Frames)
(01,11,02) to
(01,11,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
353
353
706
128
100.00
342
342
684
256
100.00
380
380
761
512
100.00
368
368
736
1024
100.00
282
282
564
1280
100.00
279
279
559
1518
100.00
291
291
582
The mechanical specifications of the EFS0A are as follows:
l
Weight (kg): 0.7
Power Consumption
The maximum power consumption of the EFS0A at room temperature (25C) is 32 W.
12.6 EFS4
Issue 03 (2013-02-20)

884

12 EoS Boards

The EFS4 is available in three functional versions, namely, N1, N2 and N3. The difference
between the three versions is their different maximum uplink bandwidths. The N1EFS4 is
discontinued.
Table 12-94 describes the versions of the EFS4.
Table 12-94 Versions of the EFS4
Item
Description
Functional versions
The EFS4 is available in three functional versions, namely, N1, N2

and N3.
Differences
l Regarding service specifications: MTU, bound bandwidth,

maximum uplink bandwidth, VCTRUNK specifications
l Regarding protection schemes: LCAS, LPT, LAG
l Regarding maintenance features: ETH OAM, test frame, port
mirroring, loopback capability, warm resets
l QoS
Substitution
l The N2EFS4 can substitute for the N1EFS4.

l The N3EFS4 can substitute for the N2EFS4 and N1EFS4.
12.6.2 Application
The EFS4 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
Issue 03 (2013-02-20)

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12 EoS Boards
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EFS4 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 12-95 provides the functions and features of the EFS4.
Table 12-95 Functions and features of the EFS4
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Interfa
ce
types
Supports 10BASE-T/100BASE-TX signals. The optical interfaces comply with

IEEE 802.3u.

886

12 EoS Boards
Funct
ion
and
Featu
re
Description
Functi
ons
when
being
used
with
an
interfa
ce
board
Receives/Transmits 4xFE signals by providing interfaces on the front panel.
Interfa
ce
charac
teristic
s
Working
modes
Auto-negotiation, 100M full-duplex, 100M half-duplex, 10M fullduplex, and 10M half-duplex
Traffic
control at
ports
Supported
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported

optical
power
threshold
s
Servic
e
catego
ries
Pluggabl
e optical
module
Not supported
EPL
service
EVPL
service

Issue 03 (2013-02-20)

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Funct
ion
and
Featu
re
12 EoS Boards
Description
EPLAN
service
The N2EFS4 and N3EFS4 support the EPLAN services that are based
on the IEEE 802.1d MAC bridge.
l Supports switching on the client and SDH sides.
function of N3EFS4 boards supports verification of destination
MAC addresses only.
l N2EFS4 and N3EFS4 boards support the query of dynamic MAC
addresses.
l N1EFS4 boards do not support the query of dynamic MAC
addresses.
VB+VLAN or VB+LP.
Servic
e
specifi
cation
s
Issue 03 (2013-02-20)
EVPLA
N
services
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1 q/p
Supported

virtual bridge.
Frame
length
range
Bound
bandwidt
h
l N1EFS4: 12xVC-3, or 63xVC-12 + 9xVC-3
Mapping
granularit
ies

granularities.
l N2EFS4/N3EFS4: 24xVC-3 or 126xVC-12 + 18xVC-3

888

Funct
ion
and
Featu
re
12 EoS Boards
Description
Encapsul
ation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
MPLS
technolo
gy
Supports the MPLS.
VLAN
technolo
gy

802.1q/p.
Maximu
m uplink
bandwidt
h
l The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.
VCTRU
NK
specificat
ions
l The number of VCTRUNKs supported by the N1EFS4 is 12.
l The maximum uplink bandwidth of the N2EFS4 and N3EFS4 is 1.25

Gbit/s.
l The EFS4 can adapt to the bandwidth of the slot.
l The number of VCTRUNKs supported by the N2EFS4 and N3EFS4

is 24.
14 only. VCTRUNK 13VCTRUNK 24 can be bound with VC-4s
numbered 58 only.
l VC-4s numbered 4 and 8 support the binding of VC-3 and VC-12
paths. The other VC-4s support the binding of VC-3 paths only.
Protec
tion
schem
es
TPS
Not supported
BPS
Not supported
PPS
Not supported
DLAG
Not supported
LCAS
Not supported by the N1EFS4

bandwidth in compliance with ITU-T G.7042. This protection scheme
is supported by the N2EFS4/N3EFS4.
Issue 03 (2013-02-20)

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Funct
ion
and
Featu
re
12 EoS Boards
Description
l The N1EFS4 supports the P2P LPT.
LPT
l The N2EFS4 and N3EFS4 support the P2P LPT and P2MP LPT.
l LPT complies with ITU-T G.7042.
Clock
synchr
onizati
on
STP/
RSTP

MSTP
Not supported
LAG
The N1EFS4 does not support this protection scheme. The N2EFS4/
N3EFS4 supports manual link aggregation and the load sharing mode
that comply with IEEE 802.3ad and IEEE 802.1AX.
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Does not support the high-precision time.

l The N1EFS4 does not support the ETH OAM function.
Maint
enanc
e
featur
es
l N2EFS4 and N3EFS4 boards support CC, LB tests, and LT tests in

compliance with IEEE 802.1ag, LM and DM in compliance with
ITU-T Y.1731, and OAM ping in compliance with Huawei
l N2EFS4 and N3EFS4 boards support OAM auto-discovery, remote
loopbacks, fault detection, and link performance detection in
compliance with IEEE 802.3ah, and selfloop detection in
compliance with Huawei proprietary protocol.
Issue 03 (2013-02-20)
Test
Frame
l The N1EFS4 supports test frames in Ethernet bearer mode.
Response
to ping
Not supported
Port
mirroring
The N3EFS4 supports ingress mirroring.
Loopbac
k
capabilit
y
Supports inloops
Supports inloops
VC-4 level
Not supported
VC-3 level
The N1EFS4/N2EFS4 supports

inloops and outloops.
l The N2EFS4/N3EFS4 supports test frames in Ethernet/GFP bearer

mode.

890

Funct
ion
and
Featu
re
Description
VC-12 level
QoS
12 EoS Boards
Not supported
RMON
Warm
resets
N1EFS4/N2EFS4/N3EFS4 boards support warm resets. If a warm reset

is performed on an N1EFS4 board, traffic on the board is interrupted,
whereas if a warm reset is performed on an N2EFS4/N3EFS4 board,
traffic on the board is not interrupted. If an N2EFS4/N3EFS4 board
substitutes for an N1EFS4 board, traffic on the N2EFS4/N3EFS4 board
is not interrupted.
Cold
resets
Supported
Alarms
and
performa
nce
events


l The N1EFS4 supports the service classification based on PORT, PORT+VLAN
ID, or PORT+VLAN PRI.
l The N2EFS4 and N3EFS4 support the flow classification based on PORT, PORT
++VLAN ID, or PORT+VLAN ID+VLAN PRI.
IGMP
snoopi
ng
Issue 03 (2013-02-20)
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Not supported
Discardin
g of
unknown
broadcast
packets
Not supported
Static
broadcast
entry
Not supported

891

12 EoS Boards
Funct
ion
and
Featu
re
Description
Traffi
c
contro
l

The EFS4 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-30 shows the functional block diagram of the EFS4 by describing how to process
1xFE signals.
Figure 12-30 Functional block diagram of the EFS4
Backplane
Control
Switch
fabric
Data
Interface
converting
module
VCP
Network
processor
DENCP
Ethernet
access
module
ENCP
FE
Cross-connect unit
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
Power Fuse
module
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
50 77 125 155
MHz MHz MHz MHz
SCC unit
SCC unit
Fuse

In the receive direction, the Ethernet access module receives the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
Issue 03 (2013-02-20)

892

12 EoS Boards
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
signals are encoded.

l
MPLS
L2 MPLS VPN
Ethernet/VLAN
l
WFQ
Four CoSs
Mapping Module


Issue 03 (2013-02-20)

893

12 EoS Boards
functions:
l
Clock Module
Power Module
require.
12.6.5 Front Panel

The front panel of the EFS4 has indicators, interfaces, and a bar code.

Figure 12-31 shows the appearance of the front panel of the EFS4.
Issue 03 (2013-02-20)

894

12 EoS Boards
Figure 12-31 Front panel of the EFS4
EFS4
STAT
ACT
PROG
SRV
FE1
FE2
FE3
FE4
EFS4
Indicators
l
Issue 03 (2013-02-20)

895

12 EoS Boards
Interfaces
The front panel of the EFS4 has four FE interfaces. Table 12-96 describes the types and usage
of the interfaces of the EFS4. For information about the cables connected to the interfaces, see
Table 12-96 Interfaces of the EFS4
Interface
Type of
Interface
Usage
FE1
RJ-45

signals.
FE2
RJ-45

signals.
FE3
RJ-45

signals.
FE4
RJ-45

signals.

Pin
Description
Grounding
Grounding
Grounding
Grounding

The EFS4 does not have any jumpers or DIP switches that are used for board settings.
Issue 03 (2013-02-20)

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12 EoS Boards
12.6.7 Valid Slots

The EFS4 must be installed in a valid slot in the subrack. Otherwise, the EFS4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the EFS4 vary with the cross-connect capacity of the subrack.
The relationship between the slots valid for the EFS4 and the bandwidth is as follows:
l
When the cross-connect capacity is 200 Gbit/s, the EFS4 can be installed in slots 18 and
1117.
When the N1EFS4 is installed in slots 18 and 1117, the bandwidth is 622 Mbit/s.
When the N2EFS4 or N3EFS4 is installed in slots 18 and 1117, the bandwidth is 1.25
Gbit/s.
12.6.8 Feature Code

The EFS4 does not have the feature code.


matches the board.
is correct.
----End
Issue 03 (2013-02-20)

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12 EoS Boards

NOTE
Step 4 Optional: Configure the L2 switching management service. Perform the following tasks:
Step 5 Optional: Configure the aggregation function for the Ethernet port. For details, see Creating a
LAG.
----End

----End

Boards.
Issue 03 (2013-02-20)

898

12 EoS Boards
the Current Alarms.
----End

The EFS4 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
You can configure the following Ethernet functions for the EFS4 by using the U2000:
l
LCAS
QoS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EFS4 by using the U2000.
You can set the following main parameters for the EFS4 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Troubleshooting
Table 12-98 lists the faults that occur on the EFS4 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-98 Methods used to troubleshoot the faults that occur on the EFS4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EFS4, see Replacing an EOS Board.

Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC

900

12 EoS Boards
BIP_SD
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_RFI
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
TU_AIS_VC12
NO_BD_SOFT
TU_LOP_VC12
TU_LOP_VC3
T_LOS
VCAT_LOM_VC12
VCAT_LOM_VC3
TU_AIS_VC3
VCAT_SQM_VC3
W_R_FAIL
VCAT_LOA
PATCH_ERR
PATCHFILE_NOTEXIST
VCAT_SQM_VC12
PATCH_NOT_CONFIRM
PROTOCOL_MM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
ETHOAM_DISCOVER_F
AIL
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_RMT_CRIT_F
AULT
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNFL
CT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_LOM
LAG_FAIL
LCAS_FOPT
LCAS_PLCR
LCAS_FOPR
LCAS_TLCR
LCAS_TLCT
LCAS_PLCT
LP_RDI_VC12
LP_RDI_VC3
LOOP_ALM
LP_REI_VC3

901

12 EoS Boards
LP_SLM_VC12
LP_REI_VC12
LP_TIM_VC12
LP_TIM_VC3
LP_SLM_VC3
LP_UNEQ_VC3
LPT_RFI
LP_UNEQ_VC12
NO_BD_SOFT
SLAVE_WORKING
TU_AIS_VC3
T_LOS
TU_AIS_VC12
VCAT_LOA
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOM_VC3
VCAT_LOM_VC12
TR_LOC
T_LOSEX
ALM_GFP_dCSF
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETH_LOS
ETH_NO_FLOW
ETHOAM_DISCOVER_F
AIL
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_LOM
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LPT_RFI
NO_BD_SOFT
T_LOSEX
TEMP_OVER

902

12 EoS Boards
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
VCTRUNK_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE


Table 12-99 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64
Octets in Length)
(packets)
Issue 03 (2013-02-20)

903

12 EoS Boards
Packets Received
(256~511 Octets in
Length)(packets)
Multicast Packets
Received(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Packets Received
(packets)

Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
Packets Transmitted
(packets)
(packets)

(packets)

(packets)

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte)

Received(Byte)

Transmitted(Byte/s)

Table 12-103 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS

904

LPSES
12 EoS Boards
LPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64
Octets in Length)
(packets)
Packets Received
(256~511 Octets in
Length)(packets)
Multicast Packets
Received(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Packets Received
(packets)
Issue 03 (2013-02-20)
Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
Packets Transmitted
(packets)
(packets)

(packets)

(packets)

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte)

905


Received(Byte)
12 EoS Boards

Transmitted(Byte/s)

Table 12-107 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64

(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)
Issue 03 (2013-02-20)

906

12 EoS Boards

Packets Transmitted
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(512~1023 Octets in
Length)(packets)
Packets Transmitted
(packets)

(packets)
Unicast Packets

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Received(Byte)

Transmitted(Byte)

The technical specifications of the EFS4 include the dimensions, weight, and power
consumption.

Table 12-111 lists the parameters specified for the electrical interfaces of the EFS4.
Table 12-111 Parameters specified for the optical interfaces of the EFS4
Parameter
Value
Nominal bit rate
Line code pattern

(100M)
interface

NOTE
N2EFS4.
Issue 03 (2013-02-20)

907

12 EoS Boards
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-112 lists the throughput specifications of the N2EFS4. Table 12-113 lists the packet
loss ratio in the case of overloading of the N2EFS4. Table 12-114 lists the latency specifications
of the N2EFS4. Table 12-115 lists the back-to-back specifications of the N2EFS4.
NOTE
The specifications vary according to the configuration and networking of the test environment, port
configured and five VC-12s are bound on the FE port.
l
Number of pairs: 1
Mode: bidirectional
Issue 03 (2013-02-20)

908

12 EoS Boards

Frame Size
(Byte)
Passed Rate
(%)
(01,02,03) to
(01,02,05) (pks/
sec)
(01,02,05) to
(01,02,03) (pks/
sec)
Total (pks/
sec)
64
11.41
16984
16984
33968
128
11.18
9441
9441
18882
256
11.10
5026
5026
10052
512
11.09
2605
2605
5210
1024
11.00
1317
1317
2634
1280
11.09
1066
1066
2132
1518
11.07
900
900
1800
Table 12-113 lists the packet loss ratio in the case of overloading of the N2EFS4. The values
are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Mode: bidirectional
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) (%)
(01,02,05) to
(01,02,03) (%)
Average (%)
64
100.00
88.510
88.513
88.512
128
100.00
88.724
88.729
88.726
256
100.00
88.858
88.859
88.859
512
100.00
88.858
88.861
88.859
1024
100.00
88.888
88.914
88.901
1280
100.00
88.895
88.875
88.885
1518
100.00
88.870
88.871
88.870

909

12 EoS Boards
l
Number of pairs: 1
Mode: bidirectional

Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,03) to
(01,02,05) (us)CT (us)
Average
(CT) (us)
(01,02,03) to
(01,02,05)
(us)-S&F (us)
Average
(S&F) (us)
64
10.00
586.1
586.1
581.0
581.0
128
10.00
644.4
644.4
634.2
634.2
256
10.00
726.3
726.3
705.9
705.9
512
10.00
969.0
969.0
928.1
928.1
1024
10.00
1382.6
1382.6
1300.6
1300.6
1280
10.00
1609.0
1609.0
1506.6
1506.6
1518
10.00
1804.9
1804.9
1683.4
1683.4
l
Issue 03 (2013-02-20)

910

Number of pairs: 1
Mode: bidirectional
12 EoS Boards

Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)
(01,02,05) to
(01,02,03)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
1337
1339
2676
128
100.00
852
852
1704
256
100.00
583
583
1166
512
100.00
441
441
882
1024
100.00
225
228
453
1280
100.00
210
210
420
1518
100.00
200
200
400
NOTE
N3EFS4.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Issue 03 (2013-02-20)

911

12 EoS Boards
Table 12-116 lists the throughput specifications of the N3EFS4. Table 12-117 lists the packet
loss ratio in the case of overloading of the N3EFS4. Table 12-118 lists the latency specifications
of the N3EFS4. Table 12-119 lists the back-to-back specifications of the N3EFS4.
NOTE
are used.
configured and three VC-3s are bound on the FE port.
l
Number of pairs: 1
Maximum rate (%): None
Issue 03 (2013-02-20)
Frame Size
(byte)
Passed Rate (%)
(01,04,01) to (01,04,02)
(pks/sec)
Total (pks/sec)
64
100.00
148810
148810
128
100.00
84459
84459
256
100.00
45290
45290
512
100.00
23496
23496
1024
100.00
11973
11973
1280
100.00
9615
9615
1518
100.00
8127
8127

912

12 EoS Boards
Table 12-117 lists the packet loss ratio in the case of overloading of the N3EFS4. The values
l
Number of pairs: 1
Frame Size
(byte)
Rate Tested (%)
(01,04,01) to (01,04,02)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
l
Issue 03 (2013-02-20)

913

12 EoS Boards
l
Measure on one receiving card only
Number of pairs: 1

Frame
Size
(byte)
Rate
Tested
(%)
(01,04,01) to
(01,04,02) (us)CT (us)
Average
(CT) (us)
(01,04,01) to
(01,04,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
129.3
129.3
124.2
124.2
128
100.00
142.6
142.6
132.4
132.4
256
100.00
171.1
171.1
150.6
150.6
512
100.00
215.7
215.7
174.7
174.7
1024
100.00
298.4
298.4
216.5
216.5
1280
100.00
339.8
339.8
237.4
237.4
1518
100.00
374.7
374.7
253.3
253.3
l
Number of pairs: 1
Issue 03 (2013-02-20)

914

12 EoS Boards

Frame Size
(byte)
Rate Tested (%)
(01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64
100.00
297620
297620
128
100.00
168918
168918
256
100.00
90580
90580
512
100.00
46992
46992
1024
100.00
23946
23946
1280
100.00
19230
19230
1518
100.00
16254
16254
The mechanical specifications of the EFS4 are as follows:
l
Power Consumption
12.7 EGS2

The EGS2 is available in two functional versions, namely, N2 and N3.
Table 12-120 describes the versions of the EGS2.
Issue 03 (2013-02-20)

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12 EoS Boards
Table 12-120 Versions of the EGS2

Item
Description
Functional version
The EGS2 is available in two functional versions, namely, N2 and N3.
Difference
l Regarding interface specifications: interface types

l Regarding protection schemes: , LPT
l Regarding maintenance features: ETH OAM, , , port mirroring,
loopback capability, warm resets
l IGMP snooping
Substitution
The N3EGS2 can substitute for the N2EGS2.
12.7.2 Application
The EGS2 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
Issue 03 (2013-02-20)
User A1

916

12 EoS Boards
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set to the 1000M full-duplex mode or auto-negotiation mode, the VLAN of the convergence service is
variable, and the binding granularity can be at the VC-3 or VC-12 level.

The EGS2 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 12-121 provides the functions and features of the EGS2.
Table 12-121 Functions and features of the EGS2
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Processes 2xGE services.
Interfa
ce
types

The optical interfaces use the SFP optical module and support hot swapping.
When the multi-mode optical fiber is used, the maximum transmission distance
is 550 m. When the single-mode optical fiber is used, the maximum transmission
distance is 10 km. The optical modules that can meet different requirements for
the transmission distance such as 40 km and 80 km can also be used.
l The N3EGS2 also supports the 1000BASE-T RJ-45 Ethernet electrical interface.
The electrical interface supports the auto-negotiation function. The negotiated
rate can be 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. The N3EGS2 uses the SFP
electrical interface and supports hot swapping. The maximum transmission
distance is 100 m.
Issue 03 (2013-02-20)
Functi
ons
when
being
used
with
an
interfa
ce
board
Interfa
ce
charac
teristic
s
Working
modes
l GE electrical port: auto-negotiation, 1000M full-duplex, 100M fullduplex, and 10M full-duplex (only N3EGS2 boards support GE
electrical port.)
l GE optical port: auto-negotiation and 1000M full-duplex

917

Funct
ion
and
Featu
re
12 EoS Boards
Description
Traffic
control at
ports
Supported
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported

optical
power
threshold
s
Servic
e
catego
ries
Pluggabl
e optical
module
EPL
service
EVPL
service

Issue 03 (2013-02-20)

918

Funct
ion
and
Featu
re
12 EoS Boards
Description
EPLAN
service
function of N3EGS2 boards supports verification of destination
MAC addresses only.
l N3EGS2 supports the EPLAN services that are based on the IEEE
802.1d MAC bridge.
EVPLA
N service

virtual bridge.
Servic
e
specifi
cation
s
Formats
of
Ethernet
data
frames
Supported
Ethernet II
Supported
IEEE 802.1 q/p
Supported
Frame
length
range
Bound
bandwidt
h
48xVC-3, or 252xVC-12 + 36xVC-3
Mapping
granularit
ies
VC-12, VC-3, VC-12-Xv (X 63), VC-3-Xv (X 12).
Encapsul
ation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
MPLS
technolo
gy
Issue 03 (2013-02-20)
IEEE 802.3
Supported

919

Funct
ion
and
Featu
re
12 EoS Boards
Description
VLAN
technolo
gy

802.1q/p.
Maximu
m uplink
bandwidt
h
The maximum uplink bandwidth is 2.5 Gbit/s. The EGS2 can adapt to
VCTRU
NK
specificat
ions

14 only. VCTRUNK13VCTRUNK 24 can be bound with VC-4s
numbered 58 only. VCTRUNK 25VCTRUNK 36 can be bound
with VC-4s numbered 912 only. VCTRUNK 37VCTRUNK 48
can be bound with VC-4s numbered 1316 only.
only.
Protec
tion
schem
es
TPS
Not supported
BPS
Not supported
PPS
Not supported
DLAG
Not supported
LAG
Supports manual link aggregation and the load sharing mode that
comply with IEEE 802.3ad and IEEE 802.1AX.
LCAS

LPT
l The N2EGS2 supports the P2P LPT.

l The N3EGS2 supports the P2P LPT and P2MP LPT.
l Complies with ITU-T G.7042.
Issue 03 (2013-02-20)
STP/
RSTP

MSTP
Not supported

920

Funct
ion
and
Featu
re
Description
Clock
synchr
onizati
on
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
l The N2EGS2 does not support the ETH OAM function.
Maint
enanc
e
featur
es
Issue 03 (2013-02-20)
12 EoS Boards
l N3EGS2 boards support CC, LB tests, and LT tests in compliance

with IEEE 802.1ag, LM and DM in compliance with ITU-T Y.1731,
and OAM ping in compliance with Huawei proprietary protocol.
l N3EGS2 boards support OAM auto-discovery, remote loopbacks,
fault detection, and link performance detection in compliance with
IEEE 802.3ah, and selfloop detection in compliance with Huawei
Test
Frame
Supports test frames in Ethernet bearer mode.
Response
to ping
Not supported
Port
mirroring
The N3EGS2 supports ingress mirroring.
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported
VC-3 level
The N2EGS2 supports inloops

and outloops. The N3EGS2 does
not support inloops or outloops.
VC-12 level
Not supported
RMON
Warm
resets
N2EGS2/N3EGS2 boards support warm resets. If a warm reset is

performed on an N2EGS2 board, traffic on the board is interrupted,
whereas if a warm reset is performed on an N3EGS2 board, traffic on
the board is not interrupted. If an N3EGS2 board substitutes for an
N2EGS2 board, traffic on the N3EGS2 board is not interrupted.
Cold
resets
Supported

921

Funct
ion
and
Featu
re
Description
Alarms
and
performa
nce
events
QoS
12 EoS Boards


l Supports the flow classification based on PORT, PORT+VLAN ID, or PORT
+VLAN ID+VLAN PRI.
IGMP
snoopi
ng
Traffi
c
contro
l
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Supported by N3EGS2 boards
Discardin
g of
unknown
broadcast
packets
Static
broadcast
entry
NOTE
N3EGS2 boards support the IGMP snooping fast-leave function when they
substitute for N2EGS2 boards using the board version replacement function.

The EGS2 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-35 shows the functional block diagram of the EGS2 by describing how to process
1xGE signals.
Issue 03 (2013-02-20)

922

12 EoS Boards
Figure 12-35 Functional block diagram of the EGS2

Backplane
Cross-connect unit
Interface
converting
module
VCP
Laser
shutdown
DENCP
ENCP
Network Control Switch

processor
fabric
Data
GE Ethernet
access
module
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
50
77
MHz MHz
Power
module
Power
module
SCC unit
-48 V/-60 V
-48 V/-60 V
Fuse
+3.3 V backup power
125 155
MHz MHz
Fuse
SCC unit


l
MPLS
L2 MPLS VPN
Issue 03 (2013-02-20)

923

12 EoS Boards
Ethernet/VLAN
l
WFQ
Four CoSs
Mapping Module


l
functions:
l
Issue 03 (2013-02-20)

924

12 EoS Boards
Clock Module
Power Module
require.
12.7.5 Front Panel

The front panel of the EGS2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-36 shows the appearance of the front panel of the N2EGS2/N3EGS2 that has the GE
optical interface.
Figure 12-36 Front panel of the N2EGS2/N3EGS2 that has the GE optical interface
EGS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
EGS2
Issue 03 (2013-02-20)

925

12 EoS Boards
The N3EGS2 can also be installed with the GE electrical interface. Figure 12-37 shows the
appearance of the front panel of the N3EGS2 that has the GE electrical interface.
Figure 12-37 Front panel of the N3EGS2 that has the GE electrical interface
EGS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
OUT1
IN1
OUT2
IN2
EGS2
Indicators
l
Issue 03 (2013-02-20)

926

12 EoS Boards
Interfaces
The front panel of the N2EGS2/N3EGS2 has two GE optical interfaces. Table 12-122 describes
the types and usage of the optical interfaces of the N2EGS2/N3EGS2.
Table 12-122 Optical interfaces of the N2EGS2/N3EGS2
Interface
Type of Interface
Usage
OUT1/IN1
LC (swappable)

VX signals.
OUT2/IN2
LC (swappable)

VX signals.
When the N3EGS2 has the electrical interfaces, the two GE electrical interfaces are of the same
type and have the same usage. Table 12-123 describes the types and usage of the electrical
interfaces of the N3EGS2.
Table 12-123 Electrical interfaces of the N3EGS2
Interface
Type of Interface
Usage
GE
RJ-45 (swappable)
Table 12-124 provides the pin assignments of the RJ-45 interface of the N3EGS2.
Table 12-124 Pin assignments of the RJ-45 interface of the N3EGS2
Issue 03 (2013-02-20)
Pin
Description
BI_DA+
BI_DA
BI_DB+
BI_DC+
BI_DC
BI_DB
BI_DD+
BI_DD

927

12 EoS Boards

The EGS2 does not have any jumpers or DIP switches that are used for board settings.
12.7.7 Valid Slots

The EGS2 must be installed in a valid slot in the subrack. Otherwise, the EGS2 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the EGS2 and the bandwidth of the EGS2 vary with the cross-connect capacity
of the subrack and the version of the board. The slots valid for the EGS2 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the slots valid for the EGS2 are as follows:
The N2EGS2 can be installed in slots 18 and 1116. When the N2EGS2 is installed
in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s. When the N2EGS2 is installed in
slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
The N3EGS2 can be installed in slots 18 and 1116. In this case, the bandwidth is 2.5
Gbit/s.
12.7.8 Feature Code

The feature code of the EGS2 indicates the type of interface.
Table 12-125 provides the relationship between the feature code of the EGS2 and the type of
interface.
Table 12-125 Relationship between the feature code of the EGS2 and the type of interface
Issue 03 (2013-02-20)
Board
Feature Code
Type of Interface
SSN2EGS210 and
SSN2EGS310
10
SSN2EGS211 and
SSN2EGS311
11
1000BASE-LX (10 km)
SSN2EGS212 and
SSN2EGS312
12
1000BASE-VX (40 km)
SSN2EGS213 and
SSN2EGS213
13
1000BASE-ZX (80 km)
SSN3EGS214
14
1000BASE-T (100 m)

928

12 EoS Boards


matches the board.
is correct.
----End

NOTE
Issue 03 (2013-02-20)

929

12 EoS Boards

a LAG.
----End

----End

Boards.
the Current Alarms.
----End

The EGS2 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
You can configure the following Ethernet functions for the EGS2 by using the U2000:
l
LCAS
QoS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EGS2 by using the U2000.
You can set the following main parameters for the EGS2 by using the U2000:
Issue 03 (2013-02-20)

930

Working mode
LCAS
Mapping protocol
12 EoS Boards
Settings.

Troubleshooting
Table 12-126 lists the faults that occur on the EGS2 frequently and the troubleshooting methods.
Table 12-126 Methods used to troubleshoot the faults that occur on the EGS2 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Issue 03 (2013-02-20)

931

12 EoS Boards
Replacing the Board

NOTE
replace the board.
For information on how to replace the EGS2, see Replacing an EOS Board.

12.7.13.1 Alarms of N2EGS2
Issue 03 (2013-02-20)
ALM_GFP_dLFD
AU_AIS
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
HP_LOM
LAG_FAIL
LASER_MOD_ERR
LCAS_FOPR
LCAS_PLCT
LCAS_FOPT
LCAS_PLCR
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC3
LP_REI_VC12
LP_RDI_VC12
LP_SLM_VC12
LP_SLM_VC3
LP_REI_VC3
LP_TIM_VC3
LP_UNEQ_VC12
LP_TIM_VC12
LSR_NO_FITED
NO_BD_SOFT
LP_UNEQ_VC3
SUBCARD_ABN
T_LOS
SLAVE_WORKING
TU_AIS_VC12
TU_AIS_VC3
TPS_ALM
TU_LOP_VC3
VCAT_LOA
TU_LOP_VC12
VCAT_LOM_VC3
PATCHFILE_NOTEXIST
VCAT_LOM_VC12
PATCH_NOT_CONFIRM
TR_LOC
PATCH_ERR
T_LOSEX
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

932

12 EoS Boards

ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETH_LOS
ETH_NO_FLOW
ETHOAM_DISCOVER_F
AIL
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_LOM
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_RDI_VC12
LP_RDI_VC3
LP_REI_VC12
LP_REI_VC3
LP_SLM_VC12
LP_SLM_VC3
LP_TIM_VC12
LP_TIM_VC3
LP_UNEQ_VC12
LP_UNEQ_VC3
LPT_RFI
LSR_NO_FITED
LSR_WILL_DIE
LTEMP_OVER
MOD_TYPE_MISMATCH
NO_BD_SOFT
PORT_MODULE_OFFLINE
SUM_INPWR_HI
SUM_INPWR_LOW
SUM_OUTPWR_HI
SUM_OUTPWR_LOW
T_LOSEX
TD
TEMP_OVER
TF
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_SQM_VC12
VCAT_SQM_VC3
VCTRUNK_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

Issue 03 (2013-02-20)

933

12 EoS Boards
12.7.14.1 Performance Events of N2EGS2

Table 12-127 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments Jabbers
AlignmentErrors
FCSErrors
AlignmentErrors
Issue 03 (2013-02-20)
Packets Received(64 Octets

s)
s)
Packets Received
(512~1023 Octets in
Length)(packets/s)

(packets/s)
Broadcast Packets
Received(packets/s)
Undersize Packets
Received(packets/s)

(packets/s)
Jabbers(packets/s)

934

12 EoS Boards

s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(512~1023 Octets in
Length)(packets/s)
Packets Transmitted
(packets/s)

(packets/s)
Unicast Packets

(packets/s)
Broadcast Packets

(Byte/s)
Alignment Errors(frames/s)

Table 12-131 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
RPLMAX
RPLMIN
RPLCUR
TPLMAX
TPLMIN
TPLCUR
TLBMAX
TLBMIN
TLBCUR
XCSTMPMAX
XCSTMPMIN
XCSTMPCUR

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
AlignmentErrors
FCSErrors
Issue 03 (2013-02-20)

935

12 EoS Boards

s)
s)
Packets Received
(512~1023 Octets in
Length)(packets/s)

(packets/s)
Broadcast Packets
Received(packets/s)
Undersize Packets
Received(packets/s)

(packets/s)
Jabbers(packets/s)

s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(512~1023 Octets in
Length)(packets/s)
Packets Transmitted
(packets/s)

(packets/s)
Unicast Packets

(packets/s)
Broadcast Packets

(Byte/s)

The technical specifications of the EGS2 include the parameters specified for optical interfaces,
consumption.
Parameter Specified for Optical Interfaces

Table 12-135 lists the parameters specified for the optical interfaces of the EGS2.
Issue 03 (2013-02-20)

936

12 EoS Boards
Table 12-135 Parameters specified for the optical interfaces of the EGS2
Parameter
Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASEVX (40 km)
1000BASELX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength range
(nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3
Receiver
sensitivity (dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)
Maximum -20 dB
spectral width
(nm)
30
Minimum side
30
mode suppression
ratio (dB)

Table 12-136 lists the parameters specified for the electrical interfaces of the EGS2.
Table 12-136 Parameters specified for the electrical interfaces of the EGS2
Type of Interface
Code Type
1000BASE-T, RJ-45
4D-PAM5
NOTE
Only the EGS2 boards of the N3 version supports the GE electrical interfaces.
Issue 03 (2013-02-20)

937

12 EoS Boards
Laser Safety Class


NOTE
specifications, and back-to-back specifications of the EGS2 board of the N2 version.
N2EGS2.
of overloading, latency specifications, and back-to-back specifications of the N2EGS2
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-137 lists the throughput specifications of the N2EGS2. Table 12-138 lists the packet
loss ratio in the case of overloading of the N2EGS2. Table 12-139 lists the latency specifications
of the N2EGS2. Table 12-140 lists the back-to-back specifications of the N2EGS2.
NOTE
are used.
configured and five VC-12s are bound on the GE port.
Table 12-137 lists the throughput specifications of the N2EGS2. The values are obtained when
l
Issue 03 (2013-02-20)

938

Number of pairs: 1
Mode: bidirectional
12 EoS Boards
Table 12-137 Throughput specifications of the N2EGS2

Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64
1.15
17086
17086
34172
128
1.12
9501
9501
19002
256
1.12
5094
5094
10188
512
1.13
2660
2660
5320
1024
1.12
1346
1346
2692
1280
1.13
1088
1088
2176
1518
1.14
925
925
1850
Table 12-138 lists the packet loss ratio in the case of overloading of the N2EGS2. The values
l
Number of pairs: 1
Mode: bidirectional
Table 12-138 Packet loss ratio in the case of overloading of the N2EGS2
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64
100.00
98.846
98.846
98.846
128
100.00
98.869
98.868
98.868

939

12 EoS Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
256
100.00
98.874
98.875
98.874
512
100.00
98.866
98.863
98.865
1024
100.00
98.870
98.870
98.870
1280
100.00
98.863
98.861
98.862
1518
100.00
98.855
98.855
98.855
Table 12-139 lists the latency specifications of the N2EGS2. The values are obtained when the
l
Number of pairs: 1
Mode: bidirectional
Table 12-139 Latency specifications of the N2EGS2
Issue 03 (2013-02-20)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64
1.00
555.8
555.8
555.3
555.3
128
1.00
615.2
615.2
614.2
614.2
256
1.00
734.6
734.6
732.6
732.6

940

12 EoS Boards
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
512
1.00
914.0
914.0
909.9
909.9
1024
1.00
1313.7
1313.7
1305.6
1305.6
1280
1.00
1523.1
1523.1
1512.9
1512.9
1518
1.00
1706.6
1706.6
1694.4
1694.4
Table 12-140 lists the back-to-back specifications of the N2EGS2. The values are obtained when
l
Number of pairs: 1
Mode: bidirectional
Table 12-140 Back-to-back specifications of the N2EGS2

Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
1236
1236
2472
128
100.00
1321
1323
2644
256
100.00
1070
1070
2140
512
100.00
934
934
1868
1024
100.00
468
468
936
1280
100.00
458
458
916
1518
100.00
450
453
903
NOTE
Issue 03 (2013-02-20)

941

12 EoS Boards
N3EGS2.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
NOTE
are used.
configured and 12 VC-3s are bound on the GE port.
l
Number of pairs: 1
Maximum rate (%): 65
Issue 03 (2013-02-20)

942

12 EoS Boards

Frame Size
(byte)
Passed Rate (%)
(01,04,01) to (01,04,02)
(pks/sec)
Total (pks/sec)
64
60.00
892857
892857
128
58.73
496032
496032
256
57.98
262605
262605
512
58.08
136463
136463
1024
58.00
69444
69444
1280
58.04
55804
55804
1518
58.04
47170
47170
l
Number of pairs: 1
Issue 03 (2013-02-20)
Frame Size
(byte)
Rate Tested (%)
(01,04,01) to (01,04,02)
(%)
Average (%)
64
100.00
39.033
39.033
128
100.00
40.323
40.323
256
100.00
41.081
41.081
512
100.00
41.492
41.492
1024
100.00
41.703
41.703

943

12 EoS Boards
Frame Size
(byte)
Rate Tested (%)
(01,04,01) to (01,04,02)
(%)
Average (%)
1280
100.00
41.744
41.744
1518
100.00
41.769
41.769
l
Number of pairs: 1
Step rate (%): 10.00
Issue 03 (2013-02-20)
Frame
Size
(byte)
Rate
Tested
(%)
(01,04,01) to
(01,04,02) (us)CT (us)
Average
(CT) (us)
(01,04,01) to
(01,04,02)
(us)-S&F (us)
Average
(S&F) (us)
64
60.00
89.9
89.9
89.4
89.4
128
58.73
94.8
94.8
93.8
93.8
256
57.98
97.4
97.4
95.3
95.3
512
58.08
108.9
108.9
104.9
104.9

944

12 EoS Boards
Frame
Size
(byte)
Rate
Tested
(%)
(01,04,01) to
(01,04,02) (us)CT (us)
Average
(CT) (us)
(01,04,01) to
(01,04,02)
(us)-S&F (us)
Average
(S&F) (us)
1024
58.00
123.4
123.4
115.3
115.3
1280
58.04
129.2
129.2
119.0
119.0
1518
58.04
138.0
138.0
125.8
125.8
l
Number of pairs: 1
Issue 03 (2013-02-20)
Frame Size
(byte)
Rate Tested (%)
(01,04,01) to (01,04,02)
Burst Size (frames)
Total (frames)
64
60.00
1785714
1785714
128
58.73
992064
992064
256
57.98
525210
525210
512
58.08
272926
272926
1024
58.00
138888
138888
1280
58.04
111608
111608
1518
58.04
94340
94340

945

12 EoS Boards
The mechanical specifications of the EGS2 are as follows:
l
Weight of the N2EGS2 (kg): 1.0
Power Consumption
The maximum power consumption of the N2EGS2 at room temperature (25C) is 43 W.
12.8 EMS2

The EMS2 is available in one functional version, namely, N1.
12.8.2 Application
The EMS2 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
Issue 03 (2013-02-20)

946

12 EoS Boards
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1
NOTE
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.

The EMS2 supports the Layer 2 switching, link convergence, and multicast functions.
Table 12-145 provides the functions and features of the EMS2.
Table 12-145 Functions and features of the EMS2
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 2xGE and 16xFE services.

947

12 EoS Boards
Funct
ion
and
Featu
re
Description
Interfa
ce
types

The optical interfaces use pluggable SFP optical modules. When the multi-mode
optical fiber is used, the maximum transmission distance is 550 m. When the
single-mode optical fiber is used, the maximum transmission distance is 10 km.
The optical modules that can meet different requirements for the transmission
distance such as 40 km and 80 km can also be used.
l Supports the 1000BASE-T RJ-45 Ethernet electrical interface. The electrical
interface supports the auto-negotiation function. The negotiated rate can be 10
Mbit/s, 100 Mbit/s, or 1000 Mbit/s. The board uses the SFP electrical interface
and supports hot swapping. The maximum transmission distance is 100 m.
l Supports 10BASE-T/100BASE-TX signals when the EMS2 is used with the
ETF8 and supports 100BASE-FX signals when the EMS2 is used with the EFF8.
Functi
ons
when
being
used
with
an
interfa
ce
board

EMS2 is used with the ETF8.
Interfa
ce
charac
teristic
s
Working
modes
l Receives/Transmits 16xFE signals through the optical interface when the EMS2
signals through the optical interface when the EMS2 is used with the ETF8 and
EFF8.
l GE electrical port: auto-negotiation, 1000M full-duplex, 100M fullduplex, and 10M full-duplex
l GE optical port: auto-negotiation and 1000M full-duplex
l FE electrical port: auto-negotiation, 100M full-duplex, 100M halfduplex, 10M full-duplex, and 10M half-duplex (This working mode
is supported only when the EMS2 board works with the ETF8
board.)
l FE optical port: 100M full-duplex (This working mode is supported
only when the EMS2 board works with the EFF8 board.)
Traffic
control at
ports
Supported (Not supported by FE

optical ports)
Supported
Query/
Supported
Setting of
port
status
Issue 03 (2013-02-20)

948

Funct
ion
and
Featu
re
12 EoS Boards
Description
Query of
interface
types
Supported

optical
power
threshold
s
Servic
e
catego
ries
Pluggabl
e optical
module
EPL
service
Supports PORT-based transparent transmission.
EVPL
service

EPLAN
service
MAC bridge.
EVPLA
N service

l Supports the configuration of up to 4096 VLAN services.
virtual bridge.
Issue 03 (2013-02-20)

949

Funct
ion
and
Featu
re
Description
Servic
e
specifi
cation
s
Formats
of
Ethernet
data
frames
12 EoS Boards
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1q/p
Supported
Frame
length
range
Bound
bandwidt
h
48xVC-3, or 252xVC-12 + 36xVC-3
Mapping
granularit
ies
VC-3, VC-12-Xv (X 63), VC-3-Xv (X 12).
Encapsul
ation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
MPLS
technolo
gy
Not supported
VLAN
technolo
gy
Supports a total number of 4094 VLANs, which comply with IEEE

802.1q/p.
Maximu
m uplink
bandwidt
h
2.5 Gbit/s
VCTRU
NK
specificat
ions

only.
Issue 03 (2013-02-20)

950

Funct
ion
and
Featu
re
Description
Protec
tion
schem
es
TPS
Not supported
BPS
Not supported
PPS
Not supported
DLAG
Not supported
LAG
Supports manual link aggregation and load sharing link aggregation in

compliance with IEEE 802.3ad and IEEE 802.1AX.
LCAS

LPT
Supports the P2P LPT and P2MP LPT in compliance with ITU-T G.
7042.
STP/
RSTP
Supports the broadcast packet suppression function and RSTP, which

complies with IEEE 802.1w.
MSTP
Not supported
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
Clock
synchr
onizati
on

Maint
enanc
e
featur
es
Issue 03 (2013-02-20)
12 EoS Boards

protocol.
Test
Frame
Supports test frames in Ethernet/GFP bearer mode.
Response
to ping
Not supported
Port
mirroring
Supports ingress mirroring.
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported

951

Funct
ion
and
Featu
re
QoS
12 EoS Boards
Description
VC-3 level
Not supported
VC-12 level
Not supported
RMON
Supports RMON of the Ethernet performance of Ethernet ports and

VCTRUNKs.
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events


l Supports the flow classification based on PORT, PORT+VLAN, PORT
+SVLAN, and PORT+VLAN+PRI.
IGMP
snoopi
ng
Traffi
c
contro
l
Issue 03 (2013-02-20)
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Supported
Discardin
g of
unknown
broadcast
packets
Supported
Static
broadcast
entry
Supported

952

12 EoS Boards

The EMS2 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-41 shows the functional block diagram of the EMS2 by describing how to process
1xGE/FE signals.
Figure 12-41 Functional block diagram of the EMS2
Backplane
Cross-connect unit
Interface
converting
module
VCP
Laser
shutdown
DENCP
ENCP

processor
fabric
Data
GE/FE Ethernet
access
module
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
77
50
MHz MHz
Power
module
Power
module
Fuse
SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V
125 155
MHz MHz


Issue 03 (2013-02-20)

953

12 EoS Boards
decapsulated. The Ethernet/VLAN format is supported.
l
WFQ
Four CoSs
Mapping Module
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.


l
functions:
l
Issue 03 (2013-02-20)

954

12 EoS Boards
Clock Module
Power Module
require.
12.8.5 Front Panel

The front panel of the EMS2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-42 shows the appearance of the front panel of the EMS2 that has the GE optical
interface.
Figure 12-42 Front panel of the EMS2 that has the GE optical interface
EMS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
EMS2
Issue 03 (2013-02-20)

955

12 EoS Boards
Figure 12-43 shows the appearance of the front panel of the EMS2 that has the GE electrical
interface.
Figure 12-43 Front panel of the EMS2 that has the GE electrical interface
EMS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
OUT1
IN1
OUT2
IN2
EMS2
Indicators
l
Issue 03 (2013-02-20)

956

12 EoS Boards
Interfaces
The front panel of the EMS2 has two interfaces. Table 12-146 describes the types and usage of
the interfaces of the EMS2 when the EMS2 has the optical interfaces. When the EMS2 has the
electrical interfaces, the two GE electrical interfaces are of the same type and have the same
usage. Table 12-147 describes the types and usage of the electrical interfaces of the EMS2.
Table 12-146 Optical interfaces of the EMS2
Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)
Transmits and receives 1000BASE-SX/LX/ZX/VX

signals.
OUT2/IN2
LC (swappable)

signals.
Table 12-147 Electrical interfaces of the EMS2

Interface
Type of
Interface
Usage
GE
RJ-45
(swappable)
Table 12-148 provides the pin assignments of the RJ-45 interface of the EMS2.
Table 12-148 Pin assignments of the RJ-45 interface of the EMS2
Issue 03 (2013-02-20)
Pin
Description
BI_DA+
BI_DA
BI_DB+
BI_DC+
BI_DC
BI_DB
BI_DD+
BI_DD

957

12 EoS Boards

The EMS2 does not have any jumpers or DIP switches that are used for board settings.
12.8.7 Valid Slots

The EMS2 must be installed in a valid slot in the subrack. Otherwise, the EMS2 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EMS2 can be used with the ETF8 and EFF8.

The EMS2 can be installed in slots 16 and 1316 in the subrack. The slots valid for the EMS2
vary with the bandwidth and the cross-connect capacity of the subrack.
l
When the cross-connect capacity is 200 Gbit/s, the EMS2 can be installed in slots 16 and
1316. In this case, the bandwidth is 2.5 Gbit/s.
Table 12-149 lists the slots valid for the EMS2 and the corresponding slots for the ETF8 and
EFF8.
Table 12-149 Slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMS2
Corresponding Slots for the ETF8 and EFF8
Slot 1
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 6
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36
12.8.8 Feature Code

The feature code of the EMS2 indicates the type of interface.
Issue 03 (2013-02-20)

958

12 EoS Boards
Table 12-150 provides the relationship between the feature code of the EMS2 and the type of
interface.
Table 12-150 Relationship between the feature code of the EMS2 and the type of interface
Board
Feature Code
Type of Interface
SSN1EMS210
10
1000BASE-ZX (80 km)
SSN1EMS211
11
SSN1EMS212
12
1000BASE-LX (10 km)
SSN1EMS213
13
1000BASE-VX (40 km)
SSN1EMS214
14
1000BASE-T (100 m)


matches the board.
is correct.
----End

Issue 03 (2013-02-20)

959

12 EoS Boards
NOTE
a LAG.
----End

----End

Boards.
the Current Alarms.
----End

The EMS2 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
and LPT. Configure the functions according to actual requirements.
Issue 03 (2013-02-20)

960

12 EoS Boards
You can configure the following Ethernet functions for the EMS2 by using the U2000:
l
LCAS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EMS2 by using the U2000.
You can use set the following main parameters for the EMS2 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Troubleshooting
Table 12-151 lists the faults that occur on the EMS2 frequently and the troubleshooting methods.
Table 12-151 Methods used to troubleshoot the faults that occur on the EMS2 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Issue 03 (2013-02-20)

961

12 EoS Boards
Fault Symptom
Common Fault Cause
Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EMS2, see Replacing an EOS Board.

12.8.13.1 Alarms of N1EMS2
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
B3_EXC_VC3
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
COMMUN_FAIL
ETH_LOS
ETH_NO_FLOW
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETHOAM_RMT_LOOP
ETHOAM_DISCOVER_FA
IL
ETHOAM_RMT_CRIT_FA
ULT
EX_ETHOAM_CC_LOS

962

12 EoS Boards
EX_ETHOAM_MPID_CNF
LCT
ETHOAM_RMT_SD
FPGA_ABN
HARD_BAD
FLOW_OVER
HP_LOM
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_RDI_VC3
LP_RDI_VC12
LP_REI_VC3
LP_REI_VC12
LP_SLM_VC3
LP_SLM_VC12
LP_TIM_VC3
LP_TIM_VC12
LP_UNEQ_VC3
LP_UNEQ_VC12
LPT_RFI
LSR_NO_FITED
LTEMP_OVER
MOD_TYPE_MISMATCH
NO_BD_SOFT
PORT_MODULE_OFFLINE
SUBCARD_ABN
SUM_INPWR_HI
SUM_INPWR_LOW
SUM_OUTPWR_HI
SUM_OUTPWR_LOW
T_LOSEX
TD
TEMP_OVER
TF
TR_LOC
TU_AIS_VC12
TU_AIS_VC3
TU_LOP_VC12
TU_LOP_VC3
LSR_WILL_DIE
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_LOA
VCAT_SQM_VC12
VCAT_SQM_VC3
VCTRUNK_NO_FLOW
FCS_ERR
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_LO
OP
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

12.8.14.1 Performance Events of N1EMS2

Table 12-152 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES

963

12 EoS Boards
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors

Packets Received(64

(packets)

(packets)
Drop Events(times)
Undersize Packets
Received(packets)

(packets)
Fragments(packets)
Jabbers(packets)
Collisions(times)

Issue 03 (2013-02-20)
Packets Transmitted
(packets)

964

12 EoS Boards
Packets Transmitted
(packets)
Packets Transmitted
(512~1023 Octets in
Length)(packets)
Packets Transmitted
(packets)

(packets)
Unicast Packets

(packets)
Broadcast Packets

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Received(Byte)

Transmitted(Byte)

The technical specifications of the EMS2 include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.

Table 12-156 lists the parameters specified for the optical interfaces of the EMS2.
Table 12-156 Parameters specified for the optical interfaces of the EMS2
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASEVX (40 km)
1000BASELX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength range
(nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3
Receiver
sensitivity (dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)

965

Parameter
Value
Maximum -20 dB
spectral width
(nm)
12 EoS Boards
Minimum side
30
mode suppression
ratio (dB)
30

Table 12-157 lists the parameters specified for the electrical interfaces of the EMS2.
Table 12-157 Parameters specified for the electrical interfaces of the EMS2
Type of Interface
Code Type
1000BASE-T, RJ-45
4D-PAM5

NOTE
specifications, and back-to-back specifications of the EMS2 board of the N1 version.
in the case of overloading, latency specifications, and back-to-back specifications of the EMS2.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-158 and Table 12-159 list the throughput specifications of the EMS2. Table 12-160
and Table 12-161 list the packet loss ratio in the case of overloading of the EMS2. Table
12-162 and Table 12-163 list the latency specifications of the EMS2. Table 12-164 and Table
12-165 list the back-to-back specifications of the EMS2.
Issue 03 (2013-02-20)

966

12 EoS Boards
NOTE
are used.
configured and three VC-3s is bound on the FE port, or EPL services are configured and 48 VC-12s
are bound on the GE port.
Table 12-158 lists the throughput specifications of the EMS2 (three VC-3s is bound on the FE
port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Maximum rate (%): none
Table 12-158 Throughput specifications of the EMS2 (three VC-3s is bound on the FE port)
Frame Size
(byte)
Passed Rate (%)
(01,09,01) to (01,09,02)
(pks/sec)
Total (pks/sec)
64
100.00
148810
148810
128
100.00
84459
84459
256
100.00
45290
45290
512
100.00
23496
23496
1024
100.00
11973
11973
1280
100.00
9615
9615
1518
100.00
8127
8127
Table 12-159 lists the throughput specifications of the EMS2 (48 VC-12s are bound on the GE
Issue 03 (2013-02-20)

967

12 EoS Boards
Number of pairs: 1
Table 12-159 Throughput specifications of the EMS2 (48 VC-12s are bound on the GE port)
Frame Size
(byte)
Passed Rate (%)
(01,05,01) to (01,05,02)
(pks/sec)
Total (pks/sec)
64
11.41
169837
339674
128
10.82
91374
182748
256
10.19
46160
92320
512
10.20
23965
47930
1024
10.20
12212
24424
1280
10.20
9809
19618
1518
10.20
8288
16576
Table 12-160 lists the packet loss ratio in the case of overloading of the EMS2 (three VC-3s is
bound on the FE port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Issue 03 (2013-02-20)

968

12 EoS Boards
Table 12-160 Packet loss ratio in the case of overloading of the EMS2 (three VC-3s is bound
on the FE port)
Frame Size
(byte)
Rate Tested (%)
(01,09,01) to (01,09,02)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
Table 12-161 lists the packet loss ratio in the case of overloading of the EMS2 (48 VC-12s are
bound on the GE port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Table 12-161 Packet loss ratio in the case of overloading of the EMS2 (48 VC-12s are bound
on the GE port)
Issue 03 (2013-02-20)
Frame Size
(byte)
Rate Tested (%)
(01,05,01) to (01,05,02)
(%)
Average (%)
64
11.41
0.000
0.000
128
10.82
0.000
0.000
256
10.19
0.000
0.000
512
10.20
0.000
0.000
1024
10.20
0.000
0.000

969

12 EoS Boards
Frame Size
(byte)
Rate Tested (%)
(01,05,01) to (01,05,02)
(%)
Average (%)
1280
10.20
0.000
0.000
1518
10.20
0.000
0.000
Table 12-162 lists the latency specifications of the EMS2 (three VC-3s is bound on the FE port).
The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Table 12-162 Latency specifications of the EMS2 (three VC-3s is bound on the FE port)
Issue 03 (2013-02-20)
Frame
Size
(byte)
Rate
Tested
(%)
(01,09,01) to
(01,09,02) (us)CT (us)
Average
(CT) (us)
(01,09,01) to
(01,09,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
127.1
127.1
121.9
121.9
128
100.00
144.1
144.1
133.9
133.9
256
100.00
172.2
172.2
151.8
151.8
512
100.00
215.3
215.3
174.4
174.4
1024
100.00
299.8
299.8
217.8
217.8

970

12 EoS Boards
Frame
Size
(byte)
Rate
Tested
(%)
(01,09,01) to
(01,09,02) (us)CT (us)
Average
(CT) (us)
(01,09,01) to
(01,09,02)
(us)-S&F (us)
Average
(S&F) (us)
1280
100.00
341.7
341.7
239.3
239.3
1518
100.00
377.1
377.1
255.7
255.7
Table 12-163 lists the latency specifications of the EMS2 (48 VC-12s are bound on the GE
l
Number of pairs: 1
Table 12-163 Latency specifications of the EMS2 (48 VC-12s are bound on the GE port)
Issue 03 (2013-02-20)
Frame
Size
(byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64
11.41
657.9
657.9
657.4
657.4
128
10.82
663.9
663.9
662.8
662.8
256
10.19
683.6
683.6
681.6
681.6
512
10.20
717.3
717.3
713.3
713.3
1024
10.20
789.6
789.6
781.5
781.5

971

12 EoS Boards
Frame
Size
(byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
1280
10.20
822.1
822.1
811.9
811.9
1518
10.20
846.9
846.9
834.8
834.8
Table 12-164 lists the back-to-back specifications of the EMS2 (three VC-3s is bound on the
FE port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Table 12-164 Back-to-back specifications of the EMS2 (three VC-3s is bound on the FE port)
Frame Size
(byte)
Rate Tested (%)
(01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64
100.00
297620
297620
128
100.00
168918
168918
256
100.00
90580
90580
512
100.00
46992
46992
1024
100.00
23946
23946
1280
100.00
19230
19230
1518
100.00
16254
16254
Table 12-165 lists the back-to-back specifications of the EMS2 (48 VC-12s are bound on the
GE port). The values are obtained when the SmartApplication is set as follows:
Issue 03 (2013-02-20)

972

12 EoS Boards
Number of pairs: 1
Table 12-165 Back-to-back specifications of the EMS2 (48 VC-12s are bound on the GE port)
Frame Size
(byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
Burst Size (frames)
Total (frames)
64
11.41
339674
679348
128
10.82
182748
365496
256
10.19
92320
184640
512
10.20
47930
95860
1024
10.20
24424
48848
1280
10.20
19610
39220
1518
10.20
16576
33152
Laser Safety Class

The mechanical specifications of the EMS2 are as follows:
l
Weight (kg): 0.8
Power Consumption
The maximum power consumption of the EMS2 at room temperature (25C) is 40 W.
Issue 03 (2013-02-20)

973

12 EoS Boards
12.9 EMS4

The EMS4 is available in one functional version, namely, N1.
12.9.2 Application
The EMS4 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
Issue 03 (2013-02-20)
User A1

974

12 EoS Boards
NOTE

The EMS4 supports the Layer 2 switching, link convergence, and multicast functions.
Table 12-166 provides the functions and features of the EMS4.
Table 12-166 Functions and features of the EMS4
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 4xGE and 16xFE services
Interfa
ce
types

The optical interfaces use the SFP optical modules. When the multi-mode optical
fiber is used, the maximum transmission distance is 550 m. When the singlemode optical fiber is used, the maximum transmission distance is 10 km. The
optical modules that can meet different requirements for the transmission
l Supports the 1000BASE-T RJ-45 Ethernet electrical interface. The electrical
interface supports the auto-negotiation function. The negotiated rate can be 10
Mbit/s, 100 Mbit/s, or. 1000 Mbit/s. The EMS4 uses the SFP electrical interface
and supports hot swapping. The maximum transmission distance is 100 m.
l Supports 10BASE-T/100BASE-TX signals when the EMS4 is used with the
ETF8 and supports 100BASE-FX signals when the EMS4 is used with the EFF8.
Issue 03 (2013-02-20)
Functi
ons
when
being
used
with
an
interfa
ce
board

EMS4 is used with the ETF8.
Interfa
ce
charac
Working
modes
l Receives/Transmits 16xFE signals through the optical interface when the EMS4
signals through the optical interface when the EMS4 is used with the ETF8 and
EFF8.
1000M full-duplex

975

Funct
ion
and
Featu
re
Description
teristic
s
Traffic
control at
ports
12 EoS Boards
Supported
Not supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported

optical
power
threshold
s
Servic
e
catego
ries
Pluggabl
e optical
module
EPL
service
EVPL
service

EPLAN
service
l Supports the blacklist that can contain 512 records and also the static
MAC address table that can contain 512 records. The blacklist
MAC bridge.
Issue 03 (2013-02-20)

976

Funct
ion
and
Featu
re
12 EoS Boards
Description
EVPLA
N service

Servic
e
specifi
cation
s
Issue 03 (2013-02-20)
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1 q/p
Supported
Frame
length
range
Bound
bandwidt
h
16xVC-4, or 48xVC-3, or 1008xVC-12
Mapping
granularit
ies
VC-12, VC-3, VC-4, VC-12-Xv (X 64), VC-3-Xv (X 24), and

VC-4-Xv (X 8).
Encapsul
ation
formats
HDLC
Supported
LAPS
Supported
GFP-F
Supported
MPLS
technolo
gy
Not supported
VLAN
technolo
gy

802.1q/p.
Maximu
m uplink
bandwidt
h
2.5 Gbit/s.

977

Funct
ion
and
Featu
re
12 EoS Boards
Description
VCTRU
NK
specificat
ions
Number of VCTRUNKs: 64
Notes for configuration:
l The maximum bandwidth of a VCTRUNK is 1.25 Gbit/s. A
VCTRUNK can be bound to a maximum of eight VC-4s, 24 VC-3s,
or 63 VC-12s.
Protec
tion
schem
es
TPS
Not supported
BPS
Supported
PPS
Supported
DLAG
Supported
LAG
Supports manual link aggregation and static link aggregation.

Supports the load sharing mode and load non-sharing mode.
Complies with IEEE 802.3ad and IEEE 802.1AX.
Clock
synchr
onizati
on
Maint
enanc
e
featur
es
Issue 03 (2013-02-20)
LCAS

LPT
Supports P2P LPT and P2MP LPT in compliance with ITU-T G.7042.
STP/
RSTP
Supports the broadcast packet suppression function and RSTP, which

MSTP
Does not support the MSTP.
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
protocol.

978

Funct
ion
and
Featu
re
QoS
12 EoS Boards
Description
Test
Frame
Response
to ping
Not supported
Port
mirroring
Not supported
Loopbac
k
capabilit
y
Inloops
Not supported
VC-4 level
Not supported
VC-3 level
Not supported
VC-12 level
Not supported
RMON

VCTRUNKs.
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events
Reports various alarms and performance events, which facilitates


l Supports the flow classification based on PORT, PORT+VLAN, or PORT
+SVLAN.
IGMP
snoopi
ng
Issue 03 (2013-02-20)
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Supported

979

Funct
ion
and
Featu
re
Traffi
c
contro
l
12 EoS Boards
Description
Discardin
g of
unknown
broadcast
packets
Supported
Static
broadcast
entry
Supported

The EMS4 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-46 shows the functional block diagram of the EMS4 by describing how to process
1xGE/FE signals.
Issue 03 (2013-02-20)

980

12 EoS Boards
Figure 12-46 Functional block diagram of the EMS4

Backplane
Cross-connect unit
Interface
converting
module
VCP
Laser
shutdown
DENCP
ENCP

processor
fabric
Data
GE/FE Ethernet
access
module
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
77
50
MHz MHz
Power
module
Power
module
Fuse
SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V
125 155
MHz MHz


l
Issue 03 (2013-02-20)

981

WFQ
Four CoSs
12 EoS Boards
Mapping Module
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the


l
functions:
l
Clock Module
Issue 03 (2013-02-20)

982

12 EoS Boards
Power Module
require.
12.9.5 Front Panel

The front panel of the EMS4 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-47 shows the appearance of the front panel of the EMS4 that has the GE optical
interface.
Figure 12-47 Front panel of the EMS4 that has the GE optical interface
EMS4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4
EMS4
Figure 12-48 shows the appearance of the front panel of the EMS4 that has the GE electrical
interface.
Issue 03 (2013-02-20)

983

12 EoS Boards
Figure 12-48 Front panel of the EMS4 that has the GE electrical interface
EMS4
STAT
ACT
PROG
SRV
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4
EMS4
Indicators
l
Issue 03 (2013-02-20)

984

12 EoS Boards
Interfaces
The front panel of the EMS4 has four interfaces. Table 12-167 describes the types and usage of
the optical interfaces of the EMS4. When the EMS4 has the electrical interfaces, the four GE
electrical interfaces are of the same type and have the same usage. Table 12-168 describes the
types and usage of the electrical interfaces of the EMS4.
Table 12-167 Optical interfaces of the EMS4
Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)

signals.
OUT2/IN2
LC (swappable)

signals.
OUT3/IN3
LC (swappable)

signals.
OUT4/IN4
LC (swappable)

signals.
Table 12-168 Electrical interfaces of the EMS4

Interface
Type of
Interface
Usage
GE
RJ-45
(swappable)
Table 12-169 provides the pin assignments of the RJ-45 interface of the EMS4.
Table 12-169 Pin assignments of the RJ-45 interface of the EMS4
Issue 03 (2013-02-20)
Pin
Description
BI_DA+
BI_DA
BI_DB+
BI_DC+
BI_DC
BI_DB
BI_DD+
BI_DD
985

12 EoS Boards

The EMS4 does not have any jumpers or DIP switches that are used for board settings.
12.9.7 Valid Slots

The EMS4 must be installed in a valid slot in the subrack. Otherwise, the EMS4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EMS4 can be used with the ETF8 and EFF8.

The EMS4 can be installed in slots 16 and 1316 in the subrack. The slots valid for the EMS4
vary with the bandwidth and cross-connect capacity of the subrack.
l
When the cross-connect capacity is 200 Gbit/s, the EMS4 can be installed in slots 16 and
1316. When the EMS4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EMS4 is installed in slots 5, 6, 13, and 14, the bandwidth is 2.5 Gbit/s.
Table 12-170 lists the slots valid for the EMS4 and the corresponding slots for the ETF8 and
EFF8.
Table 12-170 Slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8
Issue 03 (2013-02-20)
Slot Valid for the EMS4
Corresponding Slots for the ETF8 and EFF8
Slot 1
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 6
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

986

12 EoS Boards
12.9.8 Feature Code

The feature code of the EMS4 indicates the type of interface.
Table 12-171 provides the relationship between the feature code of the EMS4 and the type of
interface.
Table 12-171 Relationship between the feature code of the EMS4 and the type of interface
Board
Feature Code
Type of Interface
SSN1EMS410
10
1000BASE-LX (0.5 km)
SSN1EMS411
11
1000BASE-SX (10 km)
SSN1EMS412
12
1000BASE-VX (40 km)
SSN1EMS413
13
1000BASE-ZX (80 km)
SSN1EMS414
14
1000BASE-T (100 m)

The EMS4 supports the BPS, PPS, and distributed link aggregation group (DLAG) protection.
When the BPS protection is provided for the EMS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EMS4 has four GE ports and 16 FE ports
and hence may be connected to many sets of communication equipment. Normally, the active
board is working and services are transmitted in two directions of the active link. On the standby
link, the EMS4 disables the transmission of all ports. In this case, the ports of the opposite board
are in the link-down state. In addition, the opposite board enables the transmission but does not
transmit services. In this manner, the receive ports of the standby EMS4 are not in the link-down
state. The solid lines in Figure 12-49 show how the EMS4 normally works.
Issue 03 (2013-02-20)

987

12 EoS Boards
Figure 12-49 Normal working of the EMS4
No.1
Active
EMS4
Active
communication
equipment
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EMS4
No.3
Active
communication
equipment
Standby
communication
equipment
BPS Protection
When the BPS protection is provided, if the active board detects the link-down state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
12-50 show how the BPS protection functions. The services numbered 1, 2 and 3 are all switched
to the standby EMS4 and the corresponding communication equipment.
Issue 03 (2013-02-20)

988

12 EoS Boards
Figure 12-50 Principle of the BPS protection for the EMS4
No.1
Active
EMS4
Active
communication
equipment
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EMS4
No.3
Active
communication
equipment
Standby
communication
equipment
PPS Protection
When the PPS protection is provided, if the active board detects the link-down state of any link,
the cross-connect board switches all the services to the standby board. In this manner, services
are protected. The solid lines in Figure 12-51 show how the PPS protection functions. Only the
service numbered 1 is switched to the standby EMS4 and the standby communication equipment.
Issue 03 (2013-02-20)

989

12 EoS Boards
Figure 12-51 Principle of the PPS protection for the EMS4
No.1
Active
communication
equipment
Active
EMS4
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EMS4
No.3
Active
communication
equipment
Standby
communication
equipment
NOTE
In the case of the PPS, when a link failure occurs on a port, only the link services on the port are switched
generally. If the services of two ports are associated, for example, the services of port IP1 and port IP2 are
converged into the same VCTRUNK, port IP1 and port IP2 are defined as associated ports. When one port
of the associated ports is faulty, the services of the entire associated port group are switched.
DLAG Protection
The DLAG is a group where the two mapping ports on two identical boards are aggregated to
from a protection group, providing 1+1 protection for the ports. By default, the port on the active
board is working, and the port on the standby board is protecting the working port.
When the DLAG is configured, the cross-connect board switches all services from the active
board to the standby board if the active board detects a link failure on a port, a board offline
event, or a board hardware failure. As shown in Figure 12-52, the services carried on port 1 are
switched to port 1 of the standby EMS4 and the associated equipment.
Issue 03 (2013-02-20)

990

12 EoS Boards
Figure 12-52 Principle of the DLAG protection for the EMS4

PORT1
Active
PORT2
EMS4
PORT3
Active
communication
equipment
1#
A
2#
Standby
communication
equipment
VCG
3#
XCS
1#
Active
communication
equipment
Standby
communication
equipment
VCG
2#
PORT1
Standby
EMS4
PORT2
PORT3
3#
Active
communication
equipment
Standby
communication
equipment
WARNING
When the board-level BPS/PPS protection is performed, the FE ports support only the 100M
full-duplex mode and the GE optical ports support the auto-negotiation and 1000M full-duplex
mode.
Board Configuration
Two EMS4 boards should be configured on an NE to provide the board-level protection. One
EMS4 is the active board and the other is the standby board. When you configure the EMS4
board protection, ensure that the access capacity of the slot that houses the standby board must
not be less than the access capacity of the slot that houses the active board.


Issue 03 (2013-02-20)

991

12 EoS Boards
matches the board.
is correct.
----End

NOTE
a LAG.
----End
Issue 03 (2013-02-20)

992

12 EoS Boards

----End

Boards.
the Current Alarms.
----End

The EMS4 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
You can configure the following Ethernet functions for the EMS4 by using the U2000:
l
LCAS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EMS4 by using the U2000.
You can set the following main parameters for the EMS4 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Issue 03 (2013-02-20)

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12 EoS Boards
Troubleshooting
Table 12-172 lists the faults that occur on the EMS4 frequently and the troubleshooting methods.
Table 12-172 Methods used to troubleshoot the faults that occur on the EMS4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EMS4, see Replacing an EOS Board.

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12 EoS Boards
12.9.14.1 Alarms of N1EMS4
Issue 03 (2013-02-20)
B3_SD_VC4
ALM_GFP_dCSF
ALM_GFP_dLFD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC3
BD_STATUS
BIP_EXC
BIP_SD
BOOTROM_BAD
COMMUN_FAIL
ETH_LOS
ETHOAM_RMT_LOOP
ETHOAM_DISCOVER_FA
IL
ETHOAM_RMT_CRIT_FA
ULT
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
ETHOAM_RMT_SD
FPGA_ABN
HARD_BAD
FLOW_OVER
HP_LOM
HP_RDI
HP_CROSSTR
HP_SLM
HP_TIM
HP_REI
LASER_MOD_ERR
LCAS_PLCR
HP_UNEQ
LCAS_TLCR
LCAS_TLCT
LCAS_PLCT
LOOP_ALM
LP_CROSSTR
LINK_ERR
LP_RDI_VC3
LP_REI
LP_RDI
LP_SLM
LP_SLM_VC3
LP_REI_VC3
LP_TIM_VC3
LP_UNEQ
LP_TIM
LPT_RFI
LSR_NO_FITED
LP_UNEQ_VC3
LTEMP_OVER
NO_BD_SOFT
LSR_WILL_DIE
SUBCARD_ABN
LAG_PORT_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
TD
TEMP_OVER
TF
TU_AIS
TU_AIS_VC3
TU_LOP
TU_LOP_VC3
VC3_CROSSTR
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_LOM_VC4
VCAT_SQM_VC12
VCAT_SQM_VC3
VCAT_SQM_VC4
ETH_NO_FLOW
VCTRUNK_NO_FLOW
W_R_FAIL
TR_LOC
T_LOSEX
PORTMODE_MISMATCH
ETHOAM_VCG_SELF_LO
OP
DLAG_PROTECT_FAIL
ETHOAM_SELF_LOOP
MOD_TYPE_MISMATCH
PORT_MODULE_OFFLINE

995

12 EoS Boards
IN_PWR_HIGH
IN_PWR_LOW
OUT_PWR_HIGH
OUT_PWR_LOW
SWDL_PKG_NOBDSOFT
ETH_CFM_MISMERGE
ETH_CFM_UNEXPERI
ETH_CFM_LOC
ETH_CFM_RDI
WRG_BD_TYPE

12.9.15.1 Performance Events of N1EMS4

Table 12-173 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
TPLCUR
RPLMAX
RPLMIN
RPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN
Issue 03 (2013-02-20)
UndersizePkts
OversizePkts
LateCollisions
DeferredTransmissions

FCSErrors
996

12 EoS Boards

Broadcast Packets
Received(packets)

(packets)
Undersize Packets Received

(packets)

(packets)

(packets)
Unicast Packets
Pause Frames Received(frames)

(frames)
Multicast Packets
Broadcast Packets Transmitted

(packets)

(Byte)

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)
Table 12-177 Statistics of RMON VCG performance

Octets Transmitted(Byte)
Packets Transmitted
(packets)
Good Packets Received

(packets)
Good Packets Transmitted

(packets)
Full Frame Speed

Received(Byte/s)
Full Frame Speed

Transmitted(Byte/s)

The technical specifications of the EMS4 include the parameters specified for optical interfaces,
consumption.

Table 12-178 lists the parameters specified for the optical interfaces of the EMS4.
Table 12-178 Parameters specified for the optical interfaces of the EMS4
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASEVX (40 km)
1000BASELX (10 km)

1000BASE-SX
(0.5 km)
997

12 EoS Boards
Parameter
Value
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength range
(nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3
Receiver
sensitivity (dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)
Maximum -20 dB
spectral width
(nm)
30
Minimum side
30
mode suppression
ratio (dB)

Table 12-179 lists the parameters specified for the electrical interfaces of the EMS4.
Table 12-179 Parameters specified for the electrical interfaces of the EMS4
Type of Interface
Code Type
1000BASE-T, RJ-45
4D-PAM5
Laser Safety Class


NOTE
specifications, and back-to-back specifications of the EMS4 board of the N1 version.
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12 EoS Boards
in the case of overloading, latency specifications, and back-to-back specifications of the EMS4.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-180 and Table 12-181 list the throughput specifications of the EMS4. Table 12-182
and Table 12-183 list the packet loss ratio in the case of overloading of the EMS4. Table
12-184 and Table 12-185 list the latency specifications of the EMS4. Table 12-186 and Table
12-187 list the back-to-back specifications of the EMS4.
NOTE
are used.
configured and one VC-4 is bound on the FE port, or EPL services are configured and 24 VC-3s are
bound on the GE port.
Table 12-180 lists the throughput specifications of the EMS4 (one VC-4 is bound on the FE
l
Number of pairs: 1
Issue 03 (2013-02-20)

999

Maximum rate (%): none
12 EoS Boards
Table 12-180 Throughput specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)
Passed Rate (%)
(01,01,03) to (01,01,06)
(pks/sec)
Total (pks/sec)
64
100.00
148810
148810
128
100.00
84459
84459
256
100.00
45290
45290
512
100.00
23496
23496
1024
100.00
11973
11973
1280
100.00
9615
9615
1518
100.00
8127
8127
Table 12-181 lists the throughput specifications of the EMS4 (24 VC-3s are bound on the GE
l
Number of pairs: 1
Table 12-181 Throughput specifications of the EMS4 (24 VC-3s are bound on the GE port)
Issue 03 (2013-02-20)
Frame Size
(Byte)
Passed Rate (%)
(01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
64
100.00
1488095
1488095
128
100.00
844595
844595
256
100.00
452899
452899
512
100.00
234962
234962

1000

12 EoS Boards
Frame Size
(Byte)
Passed Rate (%)
(01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
1024
100.00
119732
119732
1280
100.00
96154
96154
1518
100.00
81274
81274
Table 12-182 lists the packet loss ratio in the case of overloading of the EMS4 (one VC-4 is
l
Number of pairs: 1
Table 12-182 Packet loss ratio in the case of overloading of the EMS4 (one VC-4 is bound on
the FE port)
Frame Size
(Byte)
Rate Tested (%)
(01,01,03) to (01,01,06)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
Table 12-183 lists the packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are
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1001

12 EoS Boards
Number of pairs: 1
Table 12-183 Packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are bound on
the GE port)
Frame Size
(Byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
Table 12-184 lists the latency specifications of the EMS4 (one VC-4 is bound on the FE port).
l
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12 EoS Boards
Number of pairs: 1
Table 12-184 Latency specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,03) to
(01,01,06) (us)CT (us)
Average
(CT) (us)
(01,01,03) to
(01,01,06)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
110.6
110.6
105.5
105.5
128
100.00
123.8
123.8
113.6
113.6
256
100.00
149.2
149.2
128.8
128.8
512
100.00
195.5
195.5
154.6
154.6
1024
100.00
285.6
285.6
203.7
203.7
1280
100.00
344.6
344.6
240.5
240.5
1518
100.00
373.1
373.1
251.7
251.7
Table 12-185 lists the latency specifications of the EMS4 (24 VC-3s are bound on the GE port).
l
Issue 03 (2013-02-20)

1003

Number of pairs: 1
12 EoS Boards
Table 12-185 Latency specifications of the EMS4 (24 VC-3s are bound on the GE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
80.9
80.9
80.4
80.4
128
100.00
83.0
83.0
82.0
82.0
256
100.00
86.9
86.9
84.9
84.9
512
100.00
94.9
94.9
90.9
90.9
1024
100.00
108.8
108.8
100.7
100.7
1280
100.00
115.2
115.2
105.0
105.0
1518
100.00
120.7
120.7
108.6
108.6
Table 12-186 lists the back-to-back specifications of the EMS4 (one VC-4 is bound on the FE
l
Number of pairs: 1
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1004

12 EoS Boards
Table 12-186 Back-to-back specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)
Rate Tested (%)
(01,01,03) to (01,01,06)
Burst Size (Number of
Frames)
Total (Number of
Frames)
64
100.00
1488100
1488100
128
100.00
844590
844590
256
100.00
452900
452900
512
100.00
234960
234960
1024
100.00
119730
119730
1280
100.00
96150
96150
1518
100.00
81270
81270
Table 12-187 lists the back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE
l
Number of pairs: 1
Table 12-187 Back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE port)
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
Frames)
Total (Number of
Frames)
64
100.00
2976190
2976190
128
100.00
1689190
1689190
256
100.00
905798
905798

1005

12 EoS Boards
Frame Size
(Byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
Frames)
Total (Number of
Frames)
512
100.00
469924
469924
1024
100.00
239464
239464
1280
100.00
192308
192308
1518
100.00
162548
162548
The mechanical specifications of the EMS4 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the EMS4 at room temperature (25C) is 65 W.
12.10 EGS4

The EGS4 is available in three functional versions, namely, N1, N3 and N4. The N3EGS4 is
discontinued.
Table 12-188 describes the versions of the EGS4.
Table 12-188 Versions of the EGS4
Item
Description
Functional versions
The EGS4 is available in three functional versions, namely, N1, N3

and N4.
Differences
l Regarding interface specifications: interface types

l Regarding service specifications: bound bandwidth,
VCTRUNK specifications
l Regarding maintenance features: ETH OAM
l QoS
Substitution
Issue 03 (2013-02-20)
The N4EGS4 can substitute for the N3EGS4.

1006

12 EoS Boards
12.10.2 Application
The EGS4 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1
NOTE

The EGS4 supports the Layer 2 switching, link aggregation, and multicast functions.
Table 12-189 provides the functions and features of the EGS4.
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12 EoS Boards
Table 12-189 Functions and features of the EGS4

Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits and processes 4xGE services.
Interfa
ce
types

The optical interfaces use the SFP optical modules. When the multi-mode optical
fiber is used, the maximum transmission distance is 550 m. When the singlemode optical fiber is used, the maximum transmission distance is 10 km. The
optical modules that can meet different requirements for the transmission
l The N1EGS4 and N4EGS4 also support GE electrical interfaces using RJ45
connectors, whose specifications comply with IEEE 802.3 1000BASE-T. The
GE electrical interfaces on the N1EGS4 can adapt to 1000 Mbit/s, and those on
the N4EGS4 can adapt to 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s automatically.
The GE electrical interfaces using hot-swapping electrical SFP modules support
signal transmission over a maximum distance of 100 meters.
Functi
ons
when
being
used
with
an
interfa
ce
board
Interfa
ce
charac
teristic
s
Working
modes
l GE electrical port (available only on N1EGS4 and N4EGS4

boards): auto-negotiation, 1000M full-duplex, 100M full-duplex,
and 10M full-duplex.
l GE optical port: auto-negotiation and 1000M full-duplex.
Traffic
control at
ports
Supported
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Issue 03 (2013-02-20)
Supported

1008

Funct
ion
and
Featu
re
12 EoS Boards
Description

optical
power
threshold
s
Servic
e
catego
ries
Pluggabl
e optical
module
EPL
service
EVPL
service

EPLAN
service
l Supports switching on the client and SDH sides.

MAC address table that can contain 512 records. The blacklist
l Supports a maximum of two VBs. The maximum number of logical
ports for each VB is 68.
VB+VLAN or VB+LP.
MAC bridge.
EVPLA
N service

Servic
e
specifi
Issue 03 (2013-02-20)
Formats
of
Ethernet
IEEE 802.3
Supported
Ethernet II
Supported

1009

Issue 03 (2013-02-20)
12 EoS Boards
Funct
ion
and
Featu
re
Description
cation
s
data
frames
IEEE 802.1 q/p
Frame
length
range
Bound
bandwidt
h
l N1EGS4: 16xVC-4, or 48xVC-3, or 1008xVC-12
Mapping
granularit
ies
VC-12, VC-3, VC-4, VC-12-Xv (X 64), VC-3-Xv (X 24), and

VC-4-Xv (X 8).
Encapsul
ation
formats
HDLC
Supported
LAPS
Supported
GFP-F
Supported
Supported
l N3EGS4/N4EGS4: 16xVC-4, or 48xVC-3, or 504xVC-12
MPLS
technolo
gy
Not supported
VLAN
technolo
gy

802.1q/p.
Maximu
m uplink
bandwidt
h
2.5 Gbit/s

1010

Funct
ion
and
Featu
re
12 EoS Boards
Description
VCTRU
NK
specificat
ions
64
l VC-4s numbered 1-4 and 9-12 of the N3EGS4/N4EGS4 support the
binding of VC-3 and VC-12 paths. The other VC-4s support the
binding of VC-3 paths only.
l VC-4s numbered 1-8 and VC-4s numbered 9-16 of the N3EGS4/
N4EGS4 belong to two areas. VC-4 binding must not span the two
areas. A maximum of 8 VC-4s can be bound to one VCTRUNK.
l VC-4s numbered 1-4 and VC-4s numbered 9-12 of the N3EGS4/
N4EGS4 belong to two areas. VC-12 binding must not span the two
areas.
Protec
tion
schem
es
TPS
Not supported
BPS
Supported
PPS
Supported
DLAG
Supported
LAG

LCAS

LPT
Supports the P2P LPT and the P2MP LPT in compliance with ITU-T
G.7042.
STP/
RSTP
Supports the RSTP, which complies with IEEE 802.1w.
MSTP
Does not support the MSTP.
Data DNI Not supported

Protectio
n
Clock
synchr
onizati
on
Issue 03 (2013-02-20)
Synchron
ous
Ethernet
Not supported

1011

Funct
ion
and
Featu
re
12 EoS Boards
Description
IEEE
1588v2
Not supported
l N1EGS4/N3EGS4 boards support CC and LB tests in compliance
with IEEE 802.1ag.
Maint
enanc
e
featur
es
l N4EGS4 boards support CC, LB tests, and LT tests in compliance

with IEEE 802.1ag, LM and DM in compliance with ITU-T Y.1731,
and OAM ping in compliance with Huawei proprietary protocol.
protocol (N1EGS4/N3EGS4 boards can only initiate remote
loopbacks).
Issue 03 (2013-02-20)
Test
Frame
Response
to ping
Not supported
Port
mirroring
The N4EGS4 supports ingress mirroring.
Loopbac
k
capabilit
y
Inloops
Not supported
VC-4 level
Not supported
VC-3 level
Not supported
VC-12 level
Not supported
RMON

VCTRUNKs.
Warm
resets
Supported
Cold
resets
Supported
Alarms
and
performa
nce
events


1012

12 EoS Boards
Funct
ion
and
Featu
re
Description
QoS
l Supports the CAR. The granularity is 64 kbit/s. The N1EGS4 supports 512 rate
modes, and the N3EGS4 and N4EGS4 support 60 rate modes.
l Supports the flow classification based on PORT, PORT+VLAN, or PORT
+SVLAN.
IGMP
snoopi
ng
Traffi
c
contro
l
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Not supported
Discardin
g of
unknown
broadcast
packets
Not supported
Static
broadcast
entry
Not supported

The EGS4 consists of the Ethernet access module, network processor module, mapping module,
Figure 12-55 shows the functional block diagram of the EGS4 by describing how to process
1xGE signals.
Issue 03 (2013-02-20)

1013

12 EoS Boards
Figure 12-55 Functional block diagram of the EGS4

Backplane
Cross-connect unit
Interface
converting
module
VCP
Laser
shutdown
DENCP
ENCP

processor
fabric
Data
GE Ethernet
access
module
Cross-connect unit
Mapping module
LOS
Communication
Logic and
control module
+3.3 V
Clock module
50
77
MHz MHz
Power
module
Power
module
Fuse
SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V
125 155
MHz MHz


l
Issue 03 (2013-02-20)

1014

WFQ
Three CoSs
12 EoS Boards
Mapping Module
HDLC format. The concatenation is processed. The LCAS function is supported. Then, the


l
The control module also contains basic logic units. This module has the following functions:
l
Clock Module
Power Module
require.
Issue 03 (2013-02-20)

1015

12 EoS Boards
12.10.5 Front Panel

The front panel of the EGS4 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-56 shows the appearance of the front panel of the N1EGS4/N3EGS4/N4EGS4 that
has the optical interface.
Figure 12-56 Front panel of the N1EGS4/N3EGS4/N4EGS4 that has the optical interface
EGS4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4
EGS4
The N1EGS4/N4EGS4 can also has the GE electrical interface. Figure 12-57 shows the
appearance of the front panel of the N1EGS4/N4EGS4 that has the GE electrical interface.
Issue 03 (2013-02-20)

1016

12 EoS Boards
Figure 12-57 front panel of the N1EGS4/N4EGS4 that has the GE electrical interface
EGS4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
LINK ACT
1
2
3
4
EGS4
Indicators
l
Issue 03 (2013-02-20)

1017

12 EoS Boards
Interfaces
The front panel of the N1EGS4/N3EGS4/N4EGS4 has four GE optical interfaces. Table
12-190 describes the types and usage of the optical interfaces of the N1EGS4/N3EGS4/N4EGS4.
Table 12-190 Optical interfaces of the N1EGS4/N3EGS4/N4EGS4
Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)

signals.
OUT2/IN2
LC (swappable)

signals.
OUT3/IN3
LC (swappable)

signals.
OUT4/IN4
LC (swappable)

signals.
The four GE electrical interfaces of the N1EGS4/N4EGS4 are of the same type and have the
same usage. Table 12-191 describes the types and usage of the electrical interfaces of the
N1EGS4/N4EGS4.
Table 12-191 Electrical interfaces of the N1EGS4/N4EGS4
Interface
Type of
Interface
Usage
GE
RJ-45
(swappable)
Table 12-192 provides the pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4.
Table 12-192 Pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4
Issue 03 (2013-02-20)
Pin
Description
BI_DA+
BI_DA
BI_DB+
BI_DC+
BI_DC
BI_DB
1018

Pin
Description
BI_DD+
BI_DD
12 EoS Boards

The EGS4 does not have any jumpers or DIP switches that are used for board settings.
12.10.7 Valid Slots

The EGS4 must be installed in a valid slot in the subrack. Otherwise, the EGS4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EGS4 can be installed in slots 18 and 1116 in the subrack. The relationship between the
slots valid for the EGS4 and the bandwidth is as follows:
l
When the cross-connect capacity is 200 Gbit/s, the EGS4 can be installed in slots 18 and
1116. When the EGS4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EGS4 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.

The feature code of the EGS4 indicates the type of interface.
Table 12-193 provides the relationship between the feature code of the EGS4 and the type of
interface.
Table 12-193 Relationship between the feature code of the EGS4 and the type of interface
Issue 03 (2013-02-20)
Board
Feature Code
Type of Interface
SSN1EGS410,
SSN3EGS410, and
SSN4EGS10
10
SSN1EGS411,
SSN3EGS411, and
SSN4EGS411
11
1000BASE-LX (10 km)
SSN1EGS412,
SSN3EGS412, and
SSN4EGS412
12
1000BASE-VX (40 km)

1019

12 EoS Boards
Board
Feature Code
Type of Interface
SSN1EGS413,
SSN3EGS413, and
SSN4EGS413
13
1000BASE-ZX (80 km)
SSN1EGS414 and
SSN4EGS414
14
1000BASE-T (100 m)

The EGS4 supports the BPS, PPS, and DLAG protection.
When the BPS protection is provided for the EGS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EGS4 may be connected to many sets of
communication equipment. Normally, the active board is working and services are transmitted
in two directions of the active link. On the standby link, the EGS4 disables the transmission of
all ports. In this case, the ports of the opposite board are in the link-down state. In addition, the
opposite board enables the transmission but does not transmit services. In this manner, the
receive ports of the standby EGS4 are not in the link-down state. The solid lines in Figure
12-58 show how the EGS4 normally works.
Figure 12-58 Normal working of the EGS4
No.1
Active
EGS4
Active
communication
equipment
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EGS4
No.3
Active
communication
equipment
Standby
communication
equipment
Issue 03 (2013-02-20)

1020

12 EoS Boards
BPS Protection
When the BPS protection is provided, if the active board detects the link-down state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
12-59 show how the BPS protection functions. The services numbered 1, 2 and 3 are all switched
to the standby EGS4 and the corresponding communication equipment.
Figure 12-59 Principle of the BPS protection for the EGS4
No.1
Active
EGS4
Active
communication
equipment
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EGS4
No.3
Active
communication
equipment
Standby
communication
equipment
PPS Protection
When the PPS protection is provided, if the active board detects the link-down state of any link,
the cross-connect board switches all the services to the standby board. In this manner, services
are protected. The solid lines in Figure 12-60 show how the PPS protection functions. Only the
service numbered 1 is switched to the standby EGS4 and the standby communication equipment.
Issue 03 (2013-02-20)

1021

12 EoS Boards
Figure 12-60 Principle of the PPS protection for the EGS4
No.1
Active
communication
equipment
Active
EGS4
Standby
communication
equipment
No.2
No.3
Active
communication
equipment
XCS
B
Standby
communication
equipment
No.1
No.2
Standby
EGS4
No.3
Active
communication
equipment
Standby
communication
equipment
NOTE
In the case of the PPS, when a link failure occurs on a port, only the link services on the port are switched
generally. If the services of two ports are associated, for example, the services of port IP1 and port IP2 are
converged into the same VCTRUNK, port IP1 and port IP2 are defined as associated ports. When one port
of the associated ports is faulty, the services of the entire associated port group are switched.
DLAG Protection
The DLAG is a group where the two mapping ports on two identical boards are aggregated to
from a protection group, providing 1+1 protection for the ports. By default, the port on the active
board is working, and the port on the standby board is protecting the working port.
When the DLAG is configured, the cross-connect board switches all services from the active
board to the standby board if the active board detects a link failure on a port, a board offline
event, or a board hardware failure. As shown in Figure 12-61, the services carried on port 1 are
switched to port 1 of the standby EGS4 and the associated equipment.
Issue 03 (2013-02-20)

1022

12 EoS Boards
Figure 12-61 Principle of the DLAG protection for the EGS4

PORT1
Active
PORT2
EGS4
PORT3
1#
A
2#
Active
communication
equipment
Standby
communication
equipment
VCG
3#
XCS
1#
VCG
2#
Active
communication
equipment
Standby
communication
equipment
PORT1
Standby
EGS4
PORT2
PORT3
3#
Active
communication
equipment
Standby
communication
equipment
WARNING
When the board-level protection is performed, the GE optical ports support the auto-negotiation
and 1000M full-duplex mode.
Board Configuration
Two EGS4 boards should be configured on an NE to provide the board-level protection. One
EGS4 is the active board and the other is the standby board. When you configure the EGS4 board
protection, ensure that the access capacity of the slot that houses the standby board must not be
less than the access capacity of the slot that houses the active board.


Issue 03 (2013-02-20)

1023

12 EoS Boards
matches the board.
is correct.
----End

NOTE
a LAG.
----End
Issue 03 (2013-02-20)

1024

12 EoS Boards

----End

Boards.
the Current Alarms.
----End

The EGS4 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
You can configure the following Ethernet functions for the EGS4 by using the U2000:
l
LCAS
LPT
LAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping

You can set parameters for the EGS4 by using the U2000.
You can set the following main parameters for the EGS4 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Issue 03 (2013-02-20)

1025

12 EoS Boards
Troubleshooting
Table 12-194 lists the faults that occur on the EGS4 frequently and the troubleshooting methods.
Table 12-194 Methods used to troubleshoot the faults that occur on the EGS4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EGS4, see Replacing an EOS Board.

Issue 03 (2013-02-20)

1026

12 EoS Boards
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
ETHOAM_RMT_SD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_SD_VC4
B3_EXC_VC4
B3_SD_VC3
BIP_SD
BD_STATUS
BIP_EXC
ETH_LOS
BOOTROM_BAD
COMMUN_FAIL
FLOW_OVER
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
HP_CROSSTR
FPGA_ABN
HARD_BAD
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LCAS_PLCT
LASER_MOD_ERR
LCAS_PLCR
LINK_ERR
LCAS_TLCR
LCAS_TLCT
LP_RDI
LOOP_ALM
LP_CROSSTR
LP_REI_VC3
LP_RDI_VC3
LP_REI
LP_TIM
LP_SLM
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ
LSR_WILL_DIE
LPT_RFI
LSR_NO_FITED
OUT_PWR_HIGH
LTEMP_OVER
NO_BD_SOFT
IN_PWR_LOW
OUT_PWR_LOW
IN_PWR_HIGH
TD
ETHOAM_DISCOVER_FAIL
ETHOAM_RMT_CRIT_FA
ULT
TU_AIS
TEMP_OVER
TF
TU_LOP_VC3
TU_AIS_VC3
TU_LOP
VCAT_LOM_VC12
VC3_CROSSTR
VCAT_LOA
VCAT_SQM_VC12
VCAT_LOM_VC3
VCAT_LOM_VC4
VCAT_SQM_VC3
VCAT_SQM_VC4
ETHOAM_RMT_LOOP
W_R_FAIL
ETH_NO_FLOW
VCTRUNK_NO_FLOW
TR_LOC
T_LOSEX
LAG_PORT_FAIL
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_LOO
P
DLAG_PROTECT_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST

1027

12 EoS Boards
MOD_TYPE_MISMATCH
PORT_MODULE_OFFLINE
SWDL_PKG_NOBDSOFT
ETH_CFM_MISMERGE
ETH_CFM_UNEXPERI
ETH_CFM_LOC
ETH_CFM_RDI
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
ETHOAM_RMT_SD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_SD_VC4
B3_EXC_VC4
B3_SD_VC3
BIP_SD
BD_STATUS
BIP_EXC
ETH_LOS
BOOTROM_BAD
COMMUN_FAIL
FLOW_OVER
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNFL
CT
HP_CROSSTR
FPGA_ABN
HARD_BAD
HP_REI
HP_LOM
HP_RDI
HP_UNEQ
HP_SLM
HP_TIM
LCAS_PLCT
LASER_MOD_ERR
LCAS_PLCR
LINK_ERR
LCAS_TLCR
LCAS_TLCT
LP_RDI
LOOP_ALM
LP_CROSSTR
LP_REI_VC3
LP_RDI_VC3
LP_REI
LP_TIM
LP_SLM
LP_SLM_VC3
LP_UNEQ_VC3
LP_TIM_VC3
LP_UNEQ
LSR_WILL_DIE
LPT_RFI
LSR_NO_FITED
OUT_PWR_HIGH
LTEMP_OVER
NO_BD_SOFT
IN_PWR_LOW
OUT_PWR_LOW
IN_PWR_HIGH
TD
ETHOAM_DISCOVER_F
AIL
ETHOAM_RMT_CRIT_FAU
LT
TU_AIS
TEMP_OVER
TF
TU_LOP_VC3
TU_AIS_VC3
TU_LOP
VCAT_LOM_VC12
VC3_CROSSTR
VCAT_LOA
VCAT_SQM_VC12
VCAT_LOM_VC3
VCAT_LOM_VC4
VCAT_SQM_VC3
VCAT_SQM_VC4
ETHOAM_RMT_LOOP

1028

12 EoS Boards
W_R_FAIL
DLAG_PROTECT_FAIL
VCTRUNK_NO_FLOW
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
ETH_NO_FLOW
LAG_PORT_FAIL
T_LOSEX
TR_LOC
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
Issue 03 (2013-02-20)
ALM_GFP_dCSF
ALM_GFP_dLFD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC3
B3_SD_VC4
BD_STATUS
BIP_EXC
BIP_SD
BOOTROM_BAD
COMMUN_FAIL
DLAG_PROTECT_FAIL
ETH_CFM_LOC
ETH_CFM_MISMERGE
ETH_CFM_RDI
ETH_CFM_UNEXPERI
ETH_LOS
ETH_NO_FLOW
ETHOAM_DISCOVER_FA
IL
ETHOAM_RMT_CRIT_FA
ULT
ETHOAM_RMT_LOOP
ETHOAM_RMT_SD
ETHOAM_SELF_LOOP
ETHOAM_VCG_SELF_L
OOP
EX_ETHOAM_CC_LOS
EX_ETHOAM_MPID_CNF
LCT
FCS_ERR
FLOW_OVER
FPGA_ABN
HARD_BAD
HP_CROSSTR
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_HIGH
IN_PWR_LOW
LAG_PORT_FAIL
LASER_MOD_ERR
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LINK_ERR
LOOP_ALM
LP_CROSSTR
LP_RDI
LP_RDI_VC3
LP_REI
LP_REI_VC3
LP_SLM
LP_SLM_VC3
LP_TIM
LP_TIM_VC3
LP_UNEQ
LP_UNEQ_VC3
LPT_RFI

1029

12 EoS Boards
LSR_NO_FITED
LSR_WILL_DIE
LTEMP_OVER
MOD_TYPE_MISMATCH
NO_BD_SOFT
OUT_PWR_HIGH
OUT_PWR_LOW
PORT_MODULE_OFFLINE
T_LOSEX
TD
TEMP_OVER
TF
TR_LOC
TU_AIS
TU_AIS_VC3
TU_LOP
TU_LOP_VC3
VC3_CROSSTR
VCAT_LOA
VCAT_LOM_VC12
VCAT_LOM_VC3
VCAT_LOM_VC4
VCAT_SQM_VC12
VCAT_SQM_VC3
VCAT_SQM_VC4
VCTRUNK_NO_FLOW
W_R_FAIL
WRG_BD_TYPE


Table 12-195 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
RPLMAX
RPLMIN
RPLCUR
TPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES

1030

12 EoS Boards
VC3FEUAS
VC3SES
VC3UAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

UndersizePkts
OversizePkts
LateCollisions
FCSErrors

Broadcast Packets
Received(packets)

(packets)

(packets)

(packets)

(packets)
Unicast Packets

(frames)
Multicast Packets

(packets)

(Byte)

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)
Issue 03 (2013-02-20)
Packets Transmitted
(packets)

(packets)

(packets)
Full Frame Speed

Received(Byte/s)
Full Frame Speed

Transmitted(Byte/s)

1031

12 EoS Boards

Table 12-200 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
TLBMAX
TLBMIN
TLBCUR
TPLMAX
TPLMIN
RPLMAX
RPLMIN
RPLCUR
TPLCUR
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES
VC3FEUAS
VC3SES
VC3UAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

UndersizePkts
OversizePkts
LateCollisions
FCSErrors

Broadcast Packets
Received(packets)

(packets)

(packets)

(packets)
Issue 03 (2013-02-20)

1032

12 EoS Boards

(packets)
Unicast Packets

(frames)
Multicast Packets

(packets)

(Byte)

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Packets Transmitted
(packets)

(packets)

(packets)
Full Frame Speed

Received(Byte/s)
Full Frame Speed

Transmitted(Byte/s)

Table 12-205 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPFEUAS
LPSES
LPUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES
VC3FEES
VC3FESES

1033

12 EoS Boards
VC3FEUAS
VC3SES
VC3UAS
XCSTMPCUR
XCSTMPMAX
XCSTMPMIN

OversizePkts
UndersizePkts
FCSErrors

Broadcast Packets
Received(packets)

(packets)

(packets)

(packets)

(packets)
Unicast Packets

(frames)
Multicast Packets

(packets)

(Byte)

(Byte)
FCS Errors(frames)

Received(Byte/s)

Transmitted(Byte/s)

Packets Transmitted
(packets)

(packets)

(packets)
Full Frame Speed

Received(Byte/s)
Full Frame Speed

Transmitted(Byte/s)

The technical specifications of the EGS4 include the parameters specified for optical interfaces,
consumption.
Issue 03 (2013-02-20)

1034

12 EoS Boards

Table 12-210 lists the parameters specified for the optical interfaces of the EGS4.
Table 12-210 Parameters specified for the optical interfaces of the EGS4
Parameter
Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASEVX (40 km)
1000BASELX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength range
(nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3
Receiver
sensitivity (dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
30

Table 12-211 lists the parameters specified for the electrical interfaces of the EGS4.
Table 12-211 Parameters specified for the electrical interfaces of the EGS4
Issue 03 (2013-02-20)
Type of Electrical Interface
Code Pattern
1000BASE-T, RJ-45
4D-PAM5

1035

12 EoS Boards
WARNING
Only the EGS4 boards of the N1 and N4 versions support the GE electrical interfaces.
Laser Safety Class


NOTE
N1EGS4.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Issue 03 (2013-02-20)

1036

12 EoS Boards
NOTE
are used.
configured 24 VC-3s are bound on the GE port.
l
Number of pairs: 1

Frame Size
(Byte)
Passed Rate (%)
(01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
64
100.00
1488095
1488095
128
100.00
844595
844595
256
100.00
452899
452899
512
100.00
234962
234962
1024
100.00
119732
119732
1280
100.00
96154
96154
1518
100.00
81274
81274
Issue 03 (2013-02-20)

1037

12 EoS Boards
Number of pairs: 1
Frame Size
(Byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
(%)
Average (%)
64
100.00
0.000
0.000
128
100.00
0.000
0.000
256
100.00
0.000
0.000
512
100.00
0.000
0.000
1024
100.00
0.000
0.000
1280
100.00
0.000
0.000
1518
100.00
0.000
0.000
l
Issue 03 (2013-02-20)

1038

Number of pairs: 1
12 EoS Boards

Frame
Size
(Byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
80.9
80.9
80.4
80.4
128
100.00
83.0
83.0
82.0
82.0
256
100.00
86.9
86.9
84.9
84.9
512
100.00
94.9
94.9
90.9
90.9
1024
100.00
108.8
108.8
100.7
100.7
1280
100.00
115.2
115.2
105.0
105.0
1518
100.00
120.7
120.7
108.6
108.6
l
Number of pairs: 1
Issue 03 (2013-02-20)

1039

12 EoS Boards

Frame Size
(Byte)
Rate Tested (%)
(01,03,01) to (01,03,02)
Frames)
Total (Number of
Frames)
64
100.00
2976190
2976190
128
100.00
1689190
1689190
256
100.00
905798
905798
512
100.00
469924
469924
1024
100.00
239464
239464
1280
100.00
192308
192308
1518
100.00
162548
162548
NOTE
N4EGS4.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Issue 03 (2013-02-20)

1040

12 EoS Boards
NOTE
are used.
configured and one VC-4 are bound on the GE port.
l
Number of pairs: 1

Frame Size
(byte)
Passed Rate (%)
(01,01,02) to (01,01,01)
(pks/sec)
Total (pks/sec)
64
16.54
246063
492126
128
15.81
133547
267094
256
15.40
69754
139508
512
15.20
35714
71428
1024
15.10
18074
36148
1280
15.07
14488
28976
1518
15.06
12238
24476
Issue 03 (2013-02-20)

1041

12 EoS Boards
Number of pairs: 1
Frame Size
(byte)
Rate Tested (%)
(01,01,02) to (01,01,01)
(%)
Average (%)
64
16.54
0.000
0.000
128
15.81
0.000
0.000
256
15.40
0.000
0.000
512
15.20
0.000
0.000
1024
15.10
0.000
0.000
1280
15.07
0.000
0.000
1518
15.06
0.000
0.000
l
Issue 03 (2013-02-20)

1042

Number of pairs: 1
12 EoS Boards

Frame
Size
(byte)
Rate
Tested
(%)
(01,01,02) to
(01,01,01) (us)CT (us)
Average
(CT) (us)
(01,01,02) to
(01,01,01)
(us)-S&F (us)
Average
(S&F) (us)
64
16.54
103.3
103.3
102.8
102.8
128
15.81
115.2
115.2
114.2
114.2
256
15.40
126.7
126.7
124.7
124.7
512
15.20
154.4
154.4
150.4
150.4
1024
15.10
3721.4
3721.4
3713.3
3713.3
1280
15.07
223.9
223.9
213.7
213.7
1518
15.06
3447.5
3447.5
3435.4
3435.4
l
Number of pairs: 1
Issue 03 (2013-02-20)

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12 EoS Boards

Frame Size
(byte)
Rate Tested (%)
(01,01,02) to (01,01,01)
Burst Size (frames)
Total (frames)
64
16.54
7381890
14763780
128
15.81
4006410
8012820
256
15.40
2092620
4185240
512
15.20
1071420
2142840
1024
15.10
542220
1084440
1280
15.07
434640
869280
1518
15.06
367140
734280
The mechanical specifications of the EGS4 are as follows:
l
Weight of the N1EGS4 or N3EGS4 (kg): 1.1
Power Consumption
The maximum power consumption of the N1EGS4 and N3EGS4 at room temperature (25C) is
70 W.
12.11 EAS2
technical specifications of the EAS2 (2-port 10xGE switching and processing board). This topic
also describes how to configure and commission the EAS2.

The EAS2 is available in the following functional version: N1.
12.11.2 Application
The EAS2 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
Issue 03 (2013-02-20)

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12 EoS Boards
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EAS2 supports the transmission of 10 GE Ethernet services, LCAS, and test frame functions.
Table 12-220 provides the functions and features of the EAS2.
Table 12-220 Functions and features of the EAS2
Issue 03 (2013-02-20)
Funct
ion
and
Featu
re
Description
Basic
functi
ons
Receives/Transmits 2x10 GE Ethernet services.

1045

12 EoS Boards
Funct
ion
and
Featu
re
Description
Interfa
ce
types
The optical interfaces are 10GBASE-LR and 10GBASE-LW Ethernet optical

interfaces, which comply with IEEE 802.3ae.
Functi
ons
when
being
used
with
an
interfa
ce
board
Interfa
ce
charac
teristic
s
Working
modes
10GE full-duplex in both WAN mode and LAN mode
Traffic
control at
ports
Not supported
Supported
Query/
Supported
Setting of
port
status
Query of
interface
types
Supported

optical
power
threshold
s
Servic
e
catego
ries
Issue 03 (2013-02-20)
Pluggabl
e optical
module
Supports XFP optical modules.
EPL
service

1046

Funct
ion
and
Featu
re
12 EoS Boards
Description
EVPL
service

EPLAN
service
l Supports a maximum of one virtual bridge (VB). The maximum

MAC address table that can contain 512 records.
l Supports the query of the aging time of an MAC address.
l Supports the query of learned MAC addresses by VB+VLAN or VB
+LP.
l Supports EPLAN services that are based on IEEE 802.1d MAC
bridges.
EVPLA
N service
l Supports EVPLAN services that use the stack VLAN encapsulation.

Servic
e
specifi
cation
s
Issue 03 (2013-02-20)
Formats
of
Ethernet
data
frames
IEEE 802.3
Supported
Ethernet II
Supported
IEEE 802.1q TAG
Supported
Frame
length
range
Bound
bandwidt
h
64xVC-4 or 192xVC-3
Mapping
granularit
ies
Supports the following adjacent concatenation granularities: VC-4-Xv

(X 8), VC-3-Xv (X 24), and VC-4-4c.

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Funct
ion
and
Featu
re
12 EoS Boards
Description
Encapsul
ation
formats
HDLC
Not supported
LAPS
Not supported
GFP-F
Supported
MPLS
technolo
gy
Not supported
VLAN
technolo
gy

802.1q/p.
Maximu
m uplink
bandwidt
h
10 Gbit/s
VCTRU
NK
specificat
ions
The maximum number of VCTRUNKs supported by the N1EAS2 is

24.
The EAS2 can adapt to the bandwidth of the slot.

l A VCTRUNK can be bound with a maximum of eight VC-4s or a
l A VCTRUNK can be bound with the VC-4 path or VC-3 path at one
time. A VCTRUNK should not be bound with VC-4 and VC-3 paths
at the same time. Different VCTRUNKs can be bound with paths at
different levels.
l Supports VC-4-4c adjacent concatenation and VC-3/VC-4 virtual
concatenation.
l Only VCTRUNKs numbered 14 support the Jumbo frame with a
length of 9600 bytes. The other VCG ports do not support the Jumbo
frame.
Protec
tion
schem
es
TPS
Not supported
BPS
Not supported
PPS
Not supported
DLAG
Supported
LAG

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Funct
ion
and
Featu
re
Clock
synchr
onizati
on
12 EoS Boards
Description
LCAS

LPT
Supports the P2P LPT and P2MP LPT.
STP/
RSTP
Supports the broadcast packet suppression and RSTP, which comply

with IEEE 802.1w.
MSTP
Does not support the MSTP
ERPS
Does not support the ERPS.
Synchron
ous
Ethernet
Not supported
IEEE
1588v2
Not supported
Maint
enanc
e
featur
es

protocol.
Test
Frame
Supports test frames in ETH and GFP bearer modes.
Response
to ping
Not supported
Port
mirroring
Supported
Loopbac
k
capabilit
y
Inloops
Inloops
VC-4 level
Not supported
VC-3 level
Not supported
VC-12 level
Not supported
RMON
l Supports the Ethernet performance monitoring at the port level.

l Supports the query of the rate of a port.
Warm
resets
Issue 03 (2013-02-20)
Supported

1049

Funct
ion
and
Featu
re
QoS
12 EoS Boards
Description
Cold
resets
Supported
Alarms
and
performa
nce
events
Provides various alarm and performance events, which facilitates the

l Supports traffic classification based on PORT, PORT+VLAN ID, PORT

+VLAN ID+VLAN PRI, MPLS labels, or MPLS label+EXP value.
l Each port supports eight priority queues.
l Supports shaping based on ports or queues.
IGMP
snoopi
ng
Traffi
c
contro
l
Protocol
enabling
Supported
Port
aging
time
Supported
Fast
leave
Not supported
Discardin
g of
unknown
broadcast
packets
Not supported
Static
broadcast
entry
Supported

The EAS2 consists of the interface processing module, mapping module, interface converting
Figure 12-65 shows the functional block diagram of the EAS2 by describing how to process
1x10 GE signals.
Issue 03 (2013-02-20)

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12 EoS Boards
Figure 12-65 Functional block diagram of the EAS2

Backplane
10GE
Interface
processing
module
Laser
shutdown
Service
processing
module
Interface
converting
module
Encapsulation
module
Digital encapsulation module
Mapping module
Virtual
concatenation
processing
module
Cross-connect unit
Cross-connect unit
LOS
Logic and
control module
Communication
Clock reference and frame delimitation
+3.3 V
Clock module
Power
module
Power
module
Fuse
SCC unit
SCC unit
-48 V/-60 V
-48 V/-60 V

The encapsulation or conversion module demaps and decapsulates the signals received from the
cross-connect unit. Then, the interface converting module performs the interface converting
operations and transmits the signals to the service processing module. The service processing
module implements the functions of the Layer 2 switching and private line service. After the
interface processing module converts parallel signals to serial signals and encodes the serial
signals, the Ethernet interface module transmits the serial signals.

The XFP optical module performs O/E conversion on the 10 GE Ethernet signals, and then
transmits the signals to the Ethernet interface module. The Ethernet interface module transmits
the parallel signals to the service processing module to realize the functions of the Layer 2
switching and private line service. The encapsulation module encapsulates and maps the Ethernet
GFP-F frames, and then transmits the signals to the cross-connect unit.

The logic and control module provides the communication, control, and service configuration
functions of the board.
Clock Module
The clock module traces the system reference clock, and generates the required clock signals
when the board is working.
Power Module
require.
Issue 03 (2013-02-20)

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12.11.5 Front Panel

The front panel of the EAS2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-66 shows the appearance of the front panel of the EAS2.
Figure 12-66 Front panel of the EAS2
EAS2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
EAS2
Indicators
l
Issue 03 (2013-02-20)

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12 EoS Boards
Interfaces
The front panel of the EAS2 has two 10 GE interfaces. Table 12-221 describes the types and
usage of the interfaces of the EAS2.
Table 12-221 Interfaces of the EAS2
Interface
Type of Interface
Usage
IN1IN2
LC
Receives 10 GE signals.
OUT1OUT2
LC
Transmits 10 GE signals.

The EAS2 does not have any jumpers or DIP switches that are used for board settings.
12.11.7 Valid Slots

The slots valid for the EAS2 vary with the cross-connect capacity of the subrack.
NOTE
l Slot bandwidth
l Board version
The slots valid for the EAS2 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the EAS2 can be installed in slots 58 and
1114 in the subrack and the bandwidth is 10 Gbit/s.

The EAS2 does not have the feature code.

Issue 03 (2013-02-20)

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12 EoS Boards

matches the board.
is correct.
----End

Step 3 Required: Configure the Ethernet interface.
Generally, use the default value. The default value of the J1 byte to be sent is Huawei
SBS and the default value of the J1 byte is Disabled.
l Set the parameters of the Ethernet interface as follows:
required to work in the same mode. If the working modes on two sides do not match,
packets may be lost or the bit rate may decrease. In the case of large volume of traffic,
NOTE
Step 4 Optional: Configure the Layer 2 switching management service. Perform the following tasks:
Issue 03 (2013-02-20)

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12 EoS Boards
LAG.
Step 7 Optional: Configure test frames. For details, see Configuring Test Frames.
----End

----End

Boards.
the Current Alarms.
----End

The EAS2 supports multiple Ethernet functions and features such as Layer 2 switching, LCAS,
and LAG. Configure the functions according to actual requirements.
You can configure the following Ethernet functions for the EAS2 by using the U2000:
l
LCAS
LPT
LAG
DLAG
ETH OAM
Test Frame
STP/RSTP
IGMP Snooping
QoS

You can set parameters for the EAS2 by using the U2000.
You can set the following main parameters for the EAS2 by using the U2000:
l
Working mode
LCAS
Issue 03 (2013-02-20)

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Mapping protocol
12 EoS Boards
Settings.

Troubleshooting
Table 12-222 lists the faults that occur on the EAS2 frequently and the troubleshooting methods.
Table 12-222 Methods used to troubleshoot the faults that occur on the EAS2 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.

Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
Issue 03 (2013-02-20)

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12 EoS Boards
For information on how to replace the EAS2, see Replacing an EOS Board.

12.11.13.1 Alarms of N1EAS2

ALM_GFP_dCSF
ALM_GFP_dLFD
AU_AIS
AU_LOP
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC3
B3_SD_VC4
BD_STATUS
BDID_ERROR
BOOTROM_BAD
CHIP_ABN
COMMUN_FAIL
DLAG_PROTECT_FAIL
EX_ETHOAM_MPID_C
NFLCT
ETH_LOS
EX_ETHOAM_CC_LOS
HP_RDI
FCS_ERR
HARD_BAD
IN_PWR_ABN
HP_SLM
HP_UNEQ
LASER_MOD_ERR
LAG_PORT_FAIL
LAG_VC_PORT_FAIL
LCAS_PLCR
LCAS_FOPR
LCAS_FOPT
LCAS_TLCT
LCAS_PLCT
LCAS_TLCR
LP_RDI_VC3
LINK_ERR
LOOP_ALM
LPT_RFI
LP_SLM_VC3
LP_UNEQ_VC3
LSR_WILL_DIE
LSR_BCM_ALM
LSR_NO_FITED
SLAVE_WORKING
NO_BD_SOFT
OUT_PWR_ABN
TEM_HA
SO_SK_MISMATCH
T_LOSEX
TEST_STATUS
TEM_LA
TEMP_OVER
TU_AIS_VC3
TF
TR_LOC
VCAT_LOM_VC3
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC4
VCTRUNK_NO_FLOW
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

Issue 03 (2013-02-20)

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12 EoS Boards
12.11.14.1 Performance Events of N1EAS2

Table 12-223 SDH
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES
HPFESES
HPFEUAS
HPFECSES
VC3BBE
VC3ES
VC3SES
VC3UAS
VC3CSES
VC3FEBBE
VC3FEES
VC3FESES
VC3FECSES
VC3FEUAS
OSPITMPMAX
OSPITMPMIN
OSPITMPCUR
TPLMAX
TPLMIN
TPLCUR
TLBMAX
TLBMIN
TLBCUR
RPLMAX
RPLMIN
RPLCUR
XCSTMPMAX
XCSTMPMIN
XCSTMPCUR

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
FCSErrors
Issue 03 (2013-02-20)

in Length)(packets)
Packets Received
Length)(packets)

(packets)

(packets)
Drop Events(times)

(packets)

(packets)
Fragments(packets)
Jabbers(packets)

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12 EoS Boards

Octets in Length)
(packets)
Packets Transmitted
(packets)
Packets Transmitted
(256~511 Octets in
Length)(packets)
Packets Transmitted
(packets)

(packets)

(packets)
Multicast Packets
Broadcast Packets

(frames)

(frames)
FCS Errors(frames)

Length)(packets)

in Length)(packets)

Transmitted(128~255
Octets in Length)
(packets)

Transmitted(256~511 Octets in Transmitted(512~1023
Length)(packets)

Octets in Length)
(packets)

Received(Byte/s)

Transmitted(Byte/s)

Received(Byte)

Transmitted(Byte)
Control Frames Received

(frames)
Control Frames
Transmitted(frames)
Packets Transmitted(packets)

Packets Transmitted
(packets)

(packets)

(packets)
Full Frame Speed Received

(Byte/s)
Full Frame Speed

Transmitted(Byte/s)

The technical specifications of the EAS2 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
Issue 03 (2013-02-20)

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12 EoS Boards

Table 12-228 lists the parameters specified for the optical interfaces of the EAS2.
Table 12-228 Parameters specified for the optical interfaces of the EAS2
Parameter
Value
Transmission rate
LAN: 10.3125Gbit/s
WAN: 9.953Gbit/s
Processing capability
2x10GE signals
10GBASE-LR(LAN)
10GBASE-LW(WAN)
Type of fiber
Single-mode LC
range (nm)
1290 to 1330
10
Maximum mean launched

power (dBm)
-1
Minimum mean launched

power (dBm)
-6
-11

(dB)
Connector type
LC

width (nm)
Minimum side mode

30
Laser Safety Class


NOTE
specifications, and back-to-back specifications of the EAS2 board of the N1 version.
in the case of overloading, latency specifications, and back-to-back specifications of the EAS2.
Issue 03 (2013-02-20)

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12 EoS Boards
of overloading and latency specifications
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 12-229 lists the throughput specifications of the EAS2. Table 12-230 lists the packet loss
ratio in the case of overloading of the EAS2. Table 12-231 lists the latency specifications of the
EAS2.
NOTE
are used.
configured and 64 VC-4s are bound on the 10xGE port.
Table 12-229 Throughput specifications of the EAS2
Issue 03 (2013-02-20)
Frame Size
(Byte)
Passed Rate
(%)
Number of Tx
Frames (pks/sec)
Number of Rx
Frames (pks/sec)
Total (%)
64
100.00000
148809440
148613326
99.29688
128
100.00000
84459360
84457314
99.29688
256
99.29687
44974080
44719807
98.59375
512
97.89062
23001600
22892340
97.1875
1024
96.48437
11552000
11552000
96.48438
1280
96.48437
9277280
9277280
96.48438
1518
96.48437
7841440
7831693
95.78125

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12 EoS Boards
Table 12-230 Packet loss ratio in the case of overloading of the EAS2
Frame Size
(Byte)
Rate Tested
(%)
Number of Tx
Frames (pks/sec)
Number of Rx
Frames (pks/sec)
Total (%)
64
100.00000
148809440
148614523
0.13
128
100.00000
84459360
84457396
0.00
256
100.00000
45289760
44709723
1.28
512
100.00000
23496160
22868728
2.67
1024
100.00000
11973120
11566750
3.39
1280
100.00000
9615360
9274900
3.54
1518
100.00000
8127360
7832064
3.63
Table 12-231 Latency specifications of the EAS2

Frame
Size
(Byte)
Rate
Tested
(%)
Number
of Tx
Frames
(pks/sec)
Number of
Rx Frames
(pks/sec)
Minimum
Latency
(us)
Average
Latency
(us)
Maximu
m
Latency
(us)
64
100.0000
0
14880950
14880950
59.7
90.798
98.2
128
100.0000
0
8445940
8445940
55.9
92.201
99.5
256
100.0000
0
4528980
4528980
61
96.178
103.7
512
100.0000
0
2349620
2349620
72.7
102.403
109.9
1024
100.0000
0
1197310
1197310
81.8
116.101
123.7
1280
100.0000
0
961530
961530
88.2
122.479
130.2
1518
100.0000
0
812740
812740
99.1
128.928
136.3
The mechanical specifications of the EAS2 board are as follows:
l
Weight (kg): 1.2
Issue 03 (2013-02-20)

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12 EoS Boards
Power Consumption
The maximum power consumption of the EAS2 is 70 W at room temperature (25C).
12.12 EFF8
technical specifications of the EFF8 (8x100M Ethernet optical interface board).

The EFF8 is available in one functional version, namely, N1.
12.12.2 Application
The EFF8 is an Ethernet optical interface board. The EFF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.

The EFF8 receives and transmits 8x100M Ethernet optical signals. The EFF8 must work with
the Ethernet processing board.

The EFF8 consists of the interface module and power module.
Figure 12-68 shows the functional block diagram of the EFF8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 12-68 Functional block diagram of the EFF8
Backplane
100 Mbit/s
Ethernet signal
EFT8/EFS0/EMS4/EMR0
Interface
module
100 Mbit/s
Ethernet signal
+3.3 V
Issue 03 (2013-02-20)
EFT8/EFS0/EMS4/EMR0
Power
module
Fuse
+3.3 V backup power

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12 EoS Boards
Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
Power Module
The power module provides all the modules of the EFF8 with the required DC voltages.
12.12.5 Front Panel

The front panel of the EFF8 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-69 shows the appearance of the front panel of the EFF8.
Figure 12-69 Front panel of the EFF8
EFF8
1
2
3
4
5
6
7
8
LINK ACT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT
EFF8
Issue 03 (2013-02-20)

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12 EoS Boards
Indicators
l
Eight connection status indicators (LINK) one color (green)
Eight data receiving and transmission indicators (ACT) one color (orange)
Interfaces
The front panel of the EFF8 has eight optical interfaces.
Table 12-232 describes the types and usage of the interfaces of the EFF8.
Table 12-232 Interfaces of the EFF8
Interface
Type of
Interface
Usage
IN1IN8
LC
Receives the 1st to the 8th channels of Ethernet

optical signals.
OUT1OUT8
LC
Transmits the 1st to the 8th channels of Ethernet

optical signals.
12.12.6 Valid Slots

The EFF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFT8, EFS0 or EMR0. The EFF8 can be installed in slots 1926
and 2936 in the subrack and works as the interface board of the EMS4, EMS2 or EFS0A.
Table 12-233 lists the slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the
EFF8.
Table 12-233 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the EFF8
Issue 03 (2013-02-20)
Slot Valid for the EFT8/EFS0/EMR0
Corresponding Slot for the EFF8
Slot 2
Slots 19
Slot 3
Slots 21
Slot 4
Slots 23
Slot 5
Slots 25
Slot 13
Slots 29
Slot 14
Slots 31
Slot 15
Slots 33
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12 EoS Boards
Slot 16
Slots 35
Table 12-234 lists the slots valid for the EMS4/EMS2/EFS0A and the corresponding slots for
the EFF8.
Table 12-234 Slots valid for the EMS4/EMS2/EFS0A and the corresponding slots for the EFF8
Slot Valid for the EMS4/EMS2/EFS0A
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the EFF8 include the parameters specified for optical interfaces,

Table 12-235 lists the parameters specified for the optical interfaces of the EFF8.
Table 12-235 Parameters specified for the optical interfaces of the EFF8
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
Line code pattern
Manchester encoding signal (10M) or NRZI encoding signal

(100M)
100BASE-LX
100BASE-FX
range (nm)
1261 to 1360
1270 to 1380
Type of fiber
Single-mode LC (15 km)
Multi-mode LC (2 km)

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12 EoS Boards
Parameter
Value

power (dBm)
-15 to -8
-19 to -14
(dBm)
-28
-30
Minimum overload
(dBm)
-8
-14

(dB)
8.2
10
Laser Safety Class

The mechanical specifications of the EFF8 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EFF8 at room temperature (25C) is 6 W.
12.13 EFF8A
technical specifications of the EFF8A (8x100M Ethernet optical interface board).

The EFF8A is available in one functional version, namely, N1.
12.13.2 Application
The EFF8A is an Ethernet optical interface board. The EFF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.

The EFF8A receives and transmits 8x100M Ethernet optical signals. The EFF8A must work
with the N5EFS0.
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The EFF8A consists of the interface module and power module.
Figure 12-70 shows the functional block diagram of the EFF8A by describing how to process
Figure 12-70 Functional block diagram of the EFF8A
Backplane
100 Mbit/s
Ethernet signal
N5EFS0
Interface
module
100 Mbit/s
Ethernet signal
N5EFS0
+3.3 V
Power
module
Fuse
+3.3 V backup power
Interface Module
and transmits the signals to the N5EFS0.
Power Module
The power module provides all the modules of the EFF8A with the required DC voltages.
12.13.5 Front Panel

The front panel of the EFF8A has indicators, interfaces, a bar code, and a laser safety class label.

Figure 12-71 shows the appearance of the front panel of the EFF8A.
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Figure 12-71 Front panel of the EFF8A
EFF8
1
2
3
4
5
6
7
8
LINK ACT
OUT1 IN1
OUT2 IN2
OUT3 IN3
OUT4 IN4
OUT5 IN5
OUT6 IN6
OUT7 IN7
OUT8 IN8
CLASS 1
LASER
PRODUCT
EFF8
Indicators
l
Eight connection status indicators (LINK) one color (green)
Eight data receiving and transmission indicators (ACT) one color (orange)
Interfaces
The front panel of the EFF8A has eight optical interfaces.
Table 12-236 describes the types and usage of the interfaces of the EFF8A.
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Table 12-236 Interfaces of the EFF8A

Interface
Type of Interface
Usage
IN1IN8
LC

optical signals.
OUT1OUT8
LC
Transmits the 1st to the 8th channels of Ethernet

optical signals.
12.13.6 Valid Slots

The EFF8A can be installed in slots 19, 21, 23, 25, 29, 31, 33, 35 in the subrack and works as
the interface board of the N5EFS0.
Table 12-237 lists the slots valid for the N5EFS0 and the corresponding slots for the EFF8A.
Table 12-237 Slots valid for the N5EFS0 and the corresponding slots for the EFF8A
Slot Valid for the N5EFS0
Corresponding Slot for the EFF8A
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the EFF8A include the parameters specified for optical interfaces,

Table 12-238 lists the parameters specified for the optical interfaces of the EFF8A.
Table 12-238 Parameters specified for the optical interfaces of the EFF8A
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate

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12 EoS Boards
Parameter
Value
Line code pattern
Manchester encoding signal (10M) or NRZI encoding signal

(100M)
100BASE-LX
100BASE-FX
range (nm)
1261 to 1360
1270 to 1380
Type of fiber
Single-mode LC (15 km)
Multi-mode LC (2 km)

power (dBm)
-15 to -8
-19 to -14
(dBm)
-28
-30
Minimum overload
(dBm)
-8
-14

(dB)
8.2
10
The mechanical specifications of the EFF8A are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EFF8A at room temperature (25C) is 15 W.
12.14 ETF8
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).

The ETF8 is available in one functional version, namely, N1.
12.14.2 Application
The ETF8 is an Ethernet electrical interface board. The ETF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.
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The ETF8 receives and transmits 8x100M Ethernet electrical signals. The ETF8 must work with
the Ethernet processing board.

The ETF8 consists of the interface module and power module.
Figure 12-72 shows the functional block diagram of the ETF8 by describing how to process
Figure 12-72 Functional block diagram of the ETF8
Backplane
100 Mbit/s
Ethernet signal
EFT8/EFS0/EMS4/EMR0
Interface
module
100 Mbit/s
Ethernet signal
+3.3 V
EFT8/EFS0/EMS4/EMR0
Power
module
Fuse
+3.3 V backup power
Interface Module
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
Power Module
The power module provides all the modules of the ETF8 with the required DC voltages.
12.14.5 Front Panel

The front panel of the ETF8 has interfaces and a bar code.

Figure 12-73 shows the appearance of the front panel of the ETF8.
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Figure 12-73 Front panel of the ETF8
ETF8
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
ETF8
Interfaces
The front panel of the ETF8 has eight electrical interfaces.
Table 12-239 describes the types and usage of the interfaces of the ETF8. For information about
the cables connected to the interfaces, see 23.4.6 Straight-Through Cable and 23.4.7
Crossover Cable.
Table 12-239 Interfaces of the ETF8
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
FE1FE8
RJ-45

electrical signals.

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Table 12-240 provides the pin assignments of the RJ45 connector of the ETF8.
Table 12-240 Pin assignments of the RJ45 connector of the ETF8
Front View
8 7
6 5
3 2
Pin
Description
Transmitting (+)
Transmitting ()
Receiving (+)
Grounding
Grounding
Receiving ()
Grounding
Grounding
12.14.6 Valid Slots

The ETF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFT8, EFS0 or EMR0. The ETF8 can be installed in slots 1926
and 2936 in the subrack and works as the interface board of the EMS4, EMS2 or EFS0A.
Table 12-241 lists the slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the
ETF8.
Table 12-241 Slots valid for the EFT8/EFS0/EMR0 and the corresponding slots for the ETF8
Corresponding Slot for the ETF8
Slot 2
Slots 19
Slot 3
Slots 21
Slot 4
Slots 23
Slot 5
Slots 25
Slot 13
Slots 29
Slot 14
Slots 31
Slot 15
Slots 33
Slot 16
Slots 35
Table 12-242 lists the slots valid for the EMS4/EMS2/EFS0A and the corresponding slots for
the ETF8.
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Table 12-242 Slots valid for the EMS4/EMS2/EFS0A and the corresponding slots for the ETF8
Slot Valid for the EMS4/EMS2/EFS0A
Corresponding Slot for the ETF8
Slot 2
Slots 19 and 20
Slot 3
Slots 21 and 22
Slot 4
Slots 23 and 24
Slot 5
Slots 25 and 26
Slot 13
Slots 29 and 30
Slot 14
Slots 31 and 32
Slot 15
Slots 33 and 34
Slot 16
Slots 35 and 36

The technical specifications of the ETF8 include the parameters specified for electrical

Table 12-243 lists the parameters specified for the electrical interfaces of the ETF8.
Table 12-243 Parameters specified for the optical interfaces of the ETF8
Parameter
Value
Nominal bit rate
Line code pattern

(100M)
interface
The mechanical specifications of the ETF8 are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the ETF8 at room temperature (25C) is 2 W.
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12.15 ETF8A
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).

The ETF8A is available in one functional version, namely, N1.
12.15.2 Application
The ETF8A is an Ethernet electrical interface board. The ETF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.

The ETF8A receives and transmits 8x100M Ethernet electrical signals. The ETF8A must work
with the N5EFS0.

The ETF8A consists of the interface module and power module.
Figure 12-74 shows the functional block diagram of the ETF8A by describing how to process
Figure 12-74 Functional block diagram of the ETF8A
Backplane
100 Mbit/s
Ethernet signal
N5EFS0
Interface
module
100 Mbit/s
Ethernet signal
+3.3 V
N5EFS0
Power
module
Fuse
+3.3 V backup power
Interface Module
and transmits the signals to the N5EFS0.
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Power Module
The power module provides all the modules of the ETF8A with the required DC voltages.
12.15.5 Front Panel

The front panel of the ETF8A has interfaces and a bar code.

Figure 12-75 shows the appearance of the front panel of the ETF8A.
Figure 12-75 Front panel of the ETF8A
ETF8A
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
ETF8A
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Interfaces
The front panel of the ETF8A has eight electrical interfaces.
Table 12-244 describes the types and usage of the interfaces of the ETF8A. For information
about the cables connected to the interfaces, see 23.4.6 Straight-Through Cable and 23.4.7
Crossover Cable.
Table 12-244 Interfaces of the ETF8A
Interface
Type of
Interface
Usage
FE1FE8
RJ-45

electrical signals.
Table 12-245 provides the pin assignments of the RJ45 connector of the ETF8A.
Table 12-245 Pin assignments of the RJ45 connector of the ETF8A
Front View
8 7
6 5
3 2
Pin
Description
Transmitting (+)
Transmitting ()
Receiving (+)
Grounding
Grounding
Receiving ()
Grounding
Grounding
12.15.6 Valid Slots

The ETF8A can be installed in slots 19, 21, 23, 25, 29, 31, 33, 35 in the subrack and works as
the interface board of the N5EFS0.
Table 12-246 lists the slots valid for the N5EFS0 and the corresponding slots for the ETF8A.
Table 12-246 Slots valid for the N5EFS0 and the corresponding slots for the ETF8A
Issue 03 (2013-02-20)
Corresponding Slot for the ETF8A
Slot 2
Slot 19
Slot 3
Slot 21
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12 EoS Boards
Corresponding Slot for the ETF8A
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35

The technical specifications of the ETF8A include the parameters specified for electrical

Table 12-247 lists the parameters specified for the electrical interfaces of the ETF8A.
Table 12-247 Parameters specified for the optical interfaces of the ETF8A
Parameter
Value
Nominal bit rate
Line code pattern

(100M)
interface
The mechanical specifications of the ETF8A are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the ETF8A at room temperature (25C) is 11 W.
12.16 ETS8
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
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The ETS8 is available in one functional version, namely, N1.
12.16.2 Application
The ETS8 is an Ethernet electrical interface protection switching board. The ETS8 can be used
on the OptiX OSN equipment series to realize the TPS protection on the data board.

The ETS8 is used to provide the TPS protection for 8xFE signals at the electrical interface. The
ETS8 must work with the EFS0 or EFS0A.

The ETS8 consists of the interface module, switch matrix module, and power module.
Figure 12-76 shows the functional block diagram of the ETS8 by describing how to process
Figure 12-76 Functional block diagram of the ETS8
Backplane
Cross-connect board
100 Mbit/s
Ethernet signal
Interface
module
100 Mbit/s
Ethernet signal
+3.3 V
Switch
matrix
module
Power
module
Fuse
EFS0
TSB8
TSB8
EFS0
+3.3 V backup power
Interface Module
The interface module receives and transmits the Ethernet optical signals.

module transmits the signal to the EFS0. When the TPS is performed, the switch matrix module
transmits the signal to the TSB8 for bridging.
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Power Module
The power module provides all the modules of the ETS8 with the required DC voltages.
12.16.5 Front Panel

The front panel of the ETS8 has interfaces and a bar code.

Figure 12-77 shows the appearance of the front panel of the ETS8.
Figure 12-77 Front panel of the ETS8
ETS8
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8
ETS8
Interfaces
The front panel of the ETS8 has eight electrical interfaces.
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Table 12-248 describes the types and usage of the interfaces of the ETS8. For information about
the cables connected to the interfaces, see 23.4.6 Straight-Through Cable and 23.4.7
Crossover Cable.
Table 12-248 Interfaces of the ETS8
Interface
Type of
Interface
Usage
FE1FE8
RJ-45

electrical signals.
Table 12-249 provides the pin assignments of the RJ45 connector of the ETS8.
Table 12-249 Pin assignments of the RJ45 connector of the ETS8
Front View
8 7
6 5
3 2
Pin
Description
Transmitting (+)
Transmitting ()
Receiving (+)
Grounding
Grounding
Receiving ()
Grounding
Grounding
12.16.6 Valid Slots

The ETS8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFS0. The ETS8 can be installed in slots 19, 21, 22, 23, 25, 29, 31,
33, 34, and 35 in the subrack and works as the interface board of the EFS0A.
Table 12-250 lists the slots valid for the EFS0 and the corresponding slots for the ETS8.
Table 12-250 Slots valid for the EFS0 and the corresponding slots for the ETS8
Issue 03 (2013-02-20)
Corresponding Slot for the ETS8
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
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12 EoS Boards
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35
Table 12-251 lists the slots valid for the EFS0A and the corresponding slots for the ETS8.
Table 12-251 Slots valid for the EFS0A and the corresponding slots for the ETS8
Slot 2
Slot 19
Slot 3
Slot 21 and 22
Slot 4
Slot 23
Slot 5
Slot 25
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33 and 34
Slot 16
Slot 35

The technical specifications of the ETS8 include the parameters specified for electrical

Table 12-252 lists the parameters specified for the electrical interfaces of the ETS8.
Table 12-252 Parameters specified for the optical interfaces of the ETS8
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
Line code pattern

(100M)

1083

Parameter
Value
interface
12 EoS Boards
The mechanical specifications of the ETS8 are as follows:
l
Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the ETS8 is 0 W.
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13
ATM Boards
About This Chapter

The ATM boards include STM-1 and STM-4 ATM service processing boards.
13.1 ADL4
technical specifications of the ADL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the ADL4.
13.2 ADQ1
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the ADQ1.
13.3 IDL4
technical specifications of the IDL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the IDL4.
13.4 IDQ1
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the IDQ1.
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13.1 ADL4
technical specifications of the ADL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the ADL4.

The ADL4 is available in one functional version, namely, N1.
13.1.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
The ADL4 provides one standard STM-4 optical interface and can be interconnected with the
switch or DSLAM to transmit the ATM services. In addition, the ADL4 can switch cell headers
to converge and multiplex bandwidths so that the bandwidths are not wasted. The ADL4 supports
the following types of application of the ATM services:
l
Application of the ATM services that occupy bandwidths exclusively
Application of the ATM services that share bandwidths
Application of the ATM Services That Occupy Bandwidths Exclusively

When the ATM services do not share bandwidths, only the ATM service processing boards on
the source NE and sink NE perform ATM layer processing for the ATM services. The
intermediate NEs that the ATM services traverse do not perform ATM layer processing and only
pass through the ATM services on the SDH timeslots. In this case, each ATM service occupies
the VC-3 or VC-4 channel exclusively. The ATM services can be converged at the central node
and then transmitted on the STM-4 optical interface. Figure 13-1 shows the networking and
application of the ATM services that occupy bandwidths exclusively.
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Figure 13-1 Networking and application of the ATM services that occupy bandwidths
exclusively
DSLAM
34 Mbit/s
ATM traffic
Service
convergence
NE1
155 Mbit/s
ATM traffic
622 Mbit/s
ATM traffic
2.5 Gbit/s
SDH ring
NE4
NE2
DSLAM
Router
NE3
34 Mbit/s
ATM traffic
DSLAM
Application of the ATM Services That Share Bandwidths

The VP-ring and VC-ring realize bandwidth sharing and statistical multiplexing for the ATM
services. The ATM services on each NE share one VC (VC-3, VC-4, or VC-4-Xv) channel. In
this case, each NE performs ATM layer processing for the ATM services. Figure 13-2 shows
the networking and application of the ATM services that share bandwidths.
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13 ATM Boards
Figure 13-2 Networking and application of the ATM services that share bandwidths
The ATM services on NE1 are
dropped on NE2, then converged DSLAM
with the other ATM services, and
finally sent to the VP/VC-ring.
NE1
34 Mbit/s
ATM traffic
155 Mbit/s
ATM traffic
NE4
VC4-Xv
VP/VC-ring
DSLAM
Router
622 Mbit/s
ATM traffic
NE2
NE3
34 Mbit/s
ATM traffic
DSLAM

The ADL4 supports the ATM switching and ATM protection.
Table 13-1 provides the functions and features of the ADL4.
Table 13-1 Functions and features of the ADL4
Issue 03 (2013-02-20)
Function and
Feature
ADL4
Basic functions
Transmits/Receives and processes 1xSTM-4 ATM services.
Type of optical
interface
Supports the following types of optical interfaces: S-4.1, L-4.1,

L-4.2 and Ve-4.2.
Connector type
LC
Type of optical module
SFP
E3 ATM interface
Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.
IMA function
Does not support the IMA function.

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Function and
Feature
ADL4
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s

and 4xVC-4s.
NOTE
Only VC-4s numbered 5-8 support the binding of VC-3 paths.
A VC-4 cannot be bound with VC-3 and VC-4 paths at the same time.
VCTRUNK1VCTRUNK4 can be bound with VC-4s numbered 14 only.
VCTRUNK5VCTRUNK16 can be bound with VC-4s numbered 58 and
VC-3s numbered 112.
ATM switching
capability
Unidirectional: 1.2 Gbit/s; bidirectional: 600 Mbit/s
Mapping granularities
Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.
Service types
Supports the CBR, rt-VBR, nrt-VBR, and UBR.
Number of supported
ATM connections
2048
Statistical multiplexing
Supports the statistical multiplexing.
Flow types and QoS
Complies with IETF RFC2514 and ATM forum TM4.0.
ATM multicast
connection
Supports the spatial multicast and logical multicast.
ATM protection (ITUT I.630)
Supports the unidirectional/bidirectional 1+1, unidirectional/

bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.
OAM functions (ITU-T

I.610)
Supports the AIS, RDI, LB, and CC.
Supports inloops at the ATM layer and on optical interfaces.

Supports outloops at the ATM layer.
These features can be used to locate faults quickly.
Alarms and
performance events
Reports various alarms and performance events, which can be used

to locate faults and maintain the equipment.

The ADL4 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
Figure 13-3 shows the functional block diagram of the ADL4 by describing how to process
1xSTM-4 signals.
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Figure 13-3 Functional block diagram of the ADL4

Backplane
622
Mbit/s
622
Mbit/s
E/O
622
Mbit/s
High-speed
bus
Physical
layer
622 module
Mbit/s
O/E
Cross-connect unit
Mapping
module
ATM
module
E3
module
High-speed
bus
Cross-connect unit
O/E converting
module
LOS
Laser shutdown
Logic and
control module
Communication
Cross-connect unit
SCC unit
50 MHz
77 MHz
100 MHz
Clock
module
+3.3 V
Power
module
Fuse
Fuse
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power

In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.
Physical Layer Module

The physical layer module mainly performs the following functions:
l
Maps ATM cells into SDH frames.
Demaps SDH frames to ATM cells.
Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of header error control (HEC) sequence.
ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l
Flow control
Extraction and generation of cell headers
ATM switching
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E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l
Maps the ATM cells into E3 containers.
Demaps E3 containers to ATM cells.
Implements functions at the ATM physical layer for ATM services at the E3 rate.
Mapping Module
The mapping module performs the following functions:
l
Maps ATM cells into SDH frame payloads.
Demaps SDH frame payloads to ATM cells.
Implements functions at the ATM physical layer.
Implements the VC4-Xv (X4) virtual concatenation.

The logic and control module performs the following functions:
l
Controls writing and reading of each chip.
Communicates with the NE.
Issues configured services.
Reports alarms of each functional module.
Detects R_LOS alarms of optical modules.
Controls the shutting down of the laser.
Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.
Power Module
require.
13.1.5 Front Panel

The front panel of the ADL4 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 13-4 shows the appearance of the front panel of the ADL4.
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Figure 13-4 Front panel of the ADL4
ADL4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1 IN1
ADL4
Indicators
l
Interfaces
The front panel of the ADL4 has one optical interface. Table 13-2 describes the type and usage
of the optical interface of the ADL4.
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Table 13-2 Optical interface of the ADL4

Interface
Type of
Interface
Usage
OUT1/IN1
LC
(swappable)
Transmits and receives STM-4 optical signals.

The ADL4 does not have any jumpers or DIP switches that are used for board settings.
13.1.7 Valid Slots

The ADL4 must be installed in a valid slot in the subrack. Otherwise, the ADL4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the ADL4 vary with the cross-connect capacity of the subrack. The slots valid
for the ADL4 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the ADL4 can be installed in slots 18 and
13.1.8 Feature Code

The feature code of the ADL4 indicates the type of optical interface.
Table 13-3 provides the relationship between the feature code of the ADL4 and the type of
optical interface.
Table 13-3 Relationship between the feature code of the ADL4 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1ADL410
10
S-4.1
SSN1ADL411
11
L-4.1
SSN1ADL412
12
L-4.2
SSN1ADL413
13
Ve-4.2

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13 ATM Boards


matches the board.
is correct.
----End

Step 2 Required: Configure services. For details, see Configuring ATM and IMA Services.
Step 3 Required: Set the interface.
C2 byte: Check whether the ATM parameter is set on both ends. The setting of the C2
byte on the interconnected equipment must be consistent.
----End

Step 1 Connect the ATM instrument to the external optical interface of the board.
Step 2 Perform an outloop at the ATM port on the cross-connect side of the board. For the settings, see
28.7 Checking Board Parameters.
Step 3 Configure the basic ATM services on the instrument.
Step 4 Send the ATM services on the instrument.
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Step 5 Check whether the services received on the instrument are normal and check whether certain
cells are discarded.
----End

Boards.
the Current Alarms.
----End

You can set parameters for the ADL4 by using the U2000.
You can set the following main parameters for the ADL4 by using the U2000:
l
Port type
Flow type
Service type
Peak cell rate (PCR)
Sustainable cell rate (SCR)
Maximum cell burst size
Cell delay variation tolerance (CDVT)
Settings.

Troubleshooting
Table 13-4 lists the faults that occur on the ADL4 frequently and the troubleshooting methods.
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Table 13-4 Methods used to troubleshoot the faults that occur on the ADL4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.
l The services on an ATM port

are interrupted.
l The services on all the ATM
Packet loss
Bit errors occur on the line side.

Packet Loss.
Interconnection
fault

occurs on a single ATM port.


occurs on the VCTRUNK port.
Replacing the Board

NOTE
replace the board.
For information on how to replace the ADL4, see Replacing an ATM Board.

13.1.12.1 Alarms of N1ADL4
Issue 03 (2013-02-20)
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
CC_LOC
CHCS
COMMUN_FAIL
FPGA_ABN
HARD_BAD
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
J0_MM
LASER_MOD_ERR
LASER_SHUT
LCD
LOOP_ALM
LP_RDI_VC3
LP_REI_VC3

1096

13 ATM Boards
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
LSR_NO_FITED
LSR_WILL_DIE
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OCD
OUT_PWR_ABN
POWER_ABNORMAL
R_LOF
R_LOS
R_LOSYNC
R_OOF
SLAVE_WORKING
TEM_HA
TEM_LA
TF
TU_AIS_VC3
TU_LOP_VC3
UHCS
VC_AIS
VC_RDI
VCAT_LOA
VCAT_LOM_VC4
VCAT_SQM_VC4
VP_AIS
VP_RDI
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

13.1.13.1 Performance Events of N1ADL4

Table 13-5 SDH
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSSES
RSUAS
TUPJCHIGH
TUPJCLOW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES

1097

VC3FEES
13 ATM Boards
VC3FESES
VC3SES
VC3UAS
Table 13-6 ATM

ATM_INGCELL
ATM_EGCELL
ATM_CORRECTED_HC
SERR
ATM_UNCORRECTED_HC
SERR
ATM_RECV_CELL
ATM_RECV_IDLECELL
ATM_TRAN_CELL

The technical specifications of the ADL4 include the parameters specified for optical interfaces,

Table 13-7 lists the parameters specified for the optical interfaces of the ADL4.
Table 13-7 Parameters specified for the optical interfaces of the ADL4
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
S-4.1
L-4.1
L-4.2
Ve-4.2
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength range
(nm)
1274 to 1356
1280 to 1335
1480 to 1580
1480 to 1580
Launched optical
power range
(dBm)
-15 to -8
-3 to +2
-3 to +2
-3 to +2
Minimum
overload (dBm)
-8
-8
-8
-13
Receiver
sensitivity (dBm)
-28
-28
-28
-34
Minimum
extinction ratio
(dB)
8.2
10
10
10.5

1098

13 ATM Boards
Parameter
Value
Maximum -20 dB
spectral width
(nm)
Minimum side
mode suppression
ratio (dB)
30
30
30
Laser Safety Class

The mechanical specifications of the ADL4 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the ADL4 at room temperature (25C) is 41 W.
13.2 ADQ1
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the ADQ1.

The ADQ1 is available in one functional version, namely, N1.
13.2.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
The ADQ1 provides four standard STM-1 optical interfaces and can be interconnected with the
switch or DSLAM to transmit the ATM services. In addition, the ADQ1 can switch cell headers
to converge and multiplex bandwidths so that the bandwidths are not wasted. The ADQ1 supports
the following types of application of the ATM services:
l
Issue 03 (2013-02-20)

1099

13 ATM Boards

When the ATM services do not share bandwidths, only the ATM service processing boards on
the source NE and sink NE perform ATM layer processing for the ATM services. The
intermediate NEs that the ATM services traverse do not perform ATM layer processing and only
pass through the ATM services on the SDH timeslots. In this case, each ATM service occupies
the VC-3 or VC-4 channel exclusively. The ATM services can be converged at the central node
and then transmitted on the STM-4 optical interface. Figure 13-5 shows the networking and
application of the ATM services that occupy bandwidths exclusively.
Figure 13-5 Networking and application of the ATM services that occupy bandwidths
exclusively
DSLAM
34 Mbit/s
ATM traffic
Service
convergence
NE1
155 Mbit/s
ATM traffic
622 Mbit/s
ATM traffic
2.5 Gbit/s
SDH ring
NE4
NE2
DSLAM
Router
NE3
34 Mbit/s
ATM traffic
DSLAM

The VP-ring and VC-ring realize bandwidth sharing and statistical multiplexing for the ATM
services. The ATM services on each NE share one VC (VC-3, VC-4, or VC-4-Xv) channel. In
this case, each NE performs ATM layer processing for the ATM services. Figure 13-6 shows
the networking and application of the ATM services that share bandwidths.
Issue 03 (2013-02-20)

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13 ATM Boards
Figure 13-6 Networking and application of the ATM services that share bandwidths
The ATM services on NE1 are
dropped on NE2, then converged DSLAM
with the other ATM services, and
finally sent to the VP/VC-ring.
NE1
34 Mbit/s
ATM traffic
155 Mbit/s
ATM traffic
NE4
VC4-Xv
VP/VC-ring
DSLAM
Router
622 Mbit/s
ATM traffic
NE2
NE3
34 Mbit/s
ATM traffic
DSLAM

The ADQ1 supports the ATM switching and ATM protection.
Table 13-8 provides the functions and features of the ADQ1.
Table 13-8 Functions and features of the ADQ1
Issue 03 (2013-02-20)
Function and
Feature
ADQ1
Basic functions
Type of optical
interface

Ie-1, S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the
optical interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply
with ITU-T G.957. The characteristics of the optical interfaces of
the Ie-1 and Ve-1.2 types comply with the standards defined by
Huawei.
Connector type
LC
Optical module type
SFP
E3 ATM interface
Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.
IMA function
Does not support the IMA function.

1101

13 ATM Boards
Function and
Feature
ADQ1
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s and

4xVC-4s.
NOTE
Only VC-4s numbered 5-8 support the binding of VC-3 paths.
VCTRUNK1VCTRUNK4 can be bound with VC-4s numbered 14 only.
VCTRUNK5VCTRUNK16 can be bound with VC-4s numbered 58 and
VC-3s numbered 112.
ATM switching
capability
Mapping granularities
Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.
Service types
Supports the CBR, rt-VBR, nrt-VBR and UBR.
Number of supported
ATM connections
2048
Statistical
multiplexing
Flow types and QoS
ATM multicast
connection
ATM protection (ITUT I.630)

OAM functions (ITUT I.610)

Alarms and
performance events


The ADQ1 consists of the O/E converting module, physical layer module, ATM module, E3
Figure 13-7 shows the functional block diagram of the ADQ1.
Issue 03 (2013-02-20)

1102

13 ATM Boards
Figure 13-7 Functional block diagram of the ADQ1

Backplane
4x155
Mbit/s
4x155
Mbit/s
E/O
4x155
Mbit/s
O/E
Physical
layer
4x155 module
Mbit/s
ATM
module
High-speed
bus
Cross-connect unit
High-speed
bus
Cross-connect unit
Mapping
module
E3
module
O/E converting
module
LOS
Laser shutdown
Logic and
control module
Communication
Cross-connect unit
SCC unit
50 MHz
77 MHz
100 MHz
Clock
module
+3.3 V
Power
module
Fuse
Fuse
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power


l
ATM Module
ATM protocols:
l
Flow control
ATM switching
Issue 03 (2013-02-20)

1103

13 ATM Boards
E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l
Maps the ATM cells into E3 containers.
Demaps E3 containers to ATM cells.
Implements functions at the ATM physical layer for ATM services at the E3 rate.
Mapping Module
l

l
Clock Module
Power Module
require.
13.2.5 Front Panel

The front panel of the ADQ1 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 13-8 shows the appearance of the front panel of the ADQ1.
Issue 03 (2013-02-20)

1104

13 ATM Boards
Figure 13-8 Front panel of the ADQ1
ADQ1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
ADQ1
Indicators
l
Interfaces
The front panel of the ADQ1 has four optical interfaces. Table 13-9 describes the types and
usage of the optical interfaces of the ADQ1.
Issue 03 (2013-02-20)

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13 ATM Boards
Table 13-9 Optical interfaces of the ADQ1

Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)
OUT2/IN2
LC (swappable)
OUT3/IN3
LC (swappable)
OUT4/IN4
LC (swappable)

The ADQ1 does not have any jumpers or DIP switches that are used for board settings.
13.2.7 Valid Slots

The ADQ1 must be installed in a valid slot in the subrack. Otherwise, the ADQ1 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the ADQ1 vary with the cross-connect capacity of the subrack. The slots valid
for the ADQ1 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the ADQ1 can be installed in slots 18 and
13.2.8 Feature Code

The feature code of the ADQ1 indicates the type of optical interface.
Table 13-10 provides the relationship between the feature code of the ADQ1 and the type of
optical interface.
Table 13-10 Relationship between the feature code of the ADQ1 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN1ADQ110
10
S-1.1
SSN1ADQ111
11
L-1.1
SSN1ADQ112
12
L-1.2
SSN1ADQ113
13
Ve-1.2

1106

13 ATM Boards
Board
Feature Code
SSN1ADQ114
14
Ie-1


matches the board.
is correct.
----End

----End
Issue 03 (2013-02-20)

1107

13 ATM Boards

Step 1 Connect the ATM instrument to the external optical interface of the board.
Step 2 Perform an outloop at the ATM port on the cross-connect side of the board. For the settings, see
28.7 Checking Board Parameters.
Step 3 Configure the basic ATM services on the instrument.
Step 4 Send the ATM services on the instrument.
Step 5 Check whether the services received on the instrument are normal and check whether certain
cells are discarded.
----End

Boards.
the Current Alarms.
----End

You can set parameters for the ADQ1 by using the U2000.
You can set the following main parameters for the ADQ1 by using the U2000:
l
Port type
Flow type
Service type
PCR
SCR
CDVT
Settings.

Troubleshooting
Table 13-11 lists the faults that occur on the ADQ1 frequently and the troubleshooting methods.
Issue 03 (2013-02-20)

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13 ATM Boards
Table 13-11 Methods used to troubleshoot the faults that occur on the ADQ1 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

are interrupted.
Packet loss

Packet Loss.
Interconnection
fault



Replacing the Board

NOTE
replace the board.
For information on how to replace the ADQ1, see Replacing an ATM Board.

13.2.12.1 Alarms of N1ADQ1
Issue 03 (2013-02-20)
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_EXC_VC3
B3_SD
B3_SD_VC3
BD_STATUS
CC_LOC
CHCS
COMMUN_FAIL
FPGA_ABN
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
J0_MM
LASER_MOD_ERR
LASER_SHUT
LCD
LOOP_ALM
LP_RDI_VC3
LP_REI_VC3
LP_SLM_VC3

1109

13 ATM Boards
LP_TIM_VC3
LP_UNEQ_VC3
LSR_NO_FITED
LSR_WILL_DIE
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OCD
OUT_PWR_ABN
POWER_ABNORMAL
R_LOF
R_LOS
R_LOSYNC
R_OOF
SLAVE_WORKING
TEM_HA
TEM_LA
TF
TU_AIS_VC3
TU_LOP_VC3
UHCS
VC_AIS
VC_RDI
VCAT_LOA
VCAT_LOM_VC4
VCAT_SQM_VC4
VP_AIS
VP_RDI
W_R_FAIL
PATCHFILE_NOTEXIST
PATCH_ERR
PATCH_NOT_CONFIRM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

13.2.13.1 Performance Events of N1ADQ1

Table 13-12 SDH
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSSES
RSUAS
TUPJCHIGH
TUPJCLOW
VC3BBE
VC3CSES
VC3ES
VC3FEBBE
VC3FECSES

1110

VC3FEES
13 ATM Boards
VC3FESES
VC3SES
VC3UAS
Table 13-13 ATM

ATM_INGCELL
ATM_EGCELL
ATM_CORRECTED_HC
SERR
ATM_UNCORRECTED_HC
SERR
ATM_RECV_CELL
ATM_RECV_IDLECELL
ATM_TRAN_CELL

The technical specifications of the ADQ1 include the parameters specified for optical interfaces,

Table 13-14 lists the parameters specified for the optical interfaces of the ADQ1.
Table 13-14 Parameters specified for the optical interfaces of the ADQ1
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
Ie-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Type of fiber
Multimode LC
Single-mode
LC
Single-mode
LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1270 to
1380
1261 to 1360
1263 to 1360
1480 to
1580
1480 to 1580
Transmission
distance (km)
0 to 0.5
2 to 15
15 to 40
40 to 80
80 to 100
Launched
optical power
range (dBm)
-19 to -14
-15 to -8
-5 to 0
-5 to 0
-3 to 0
Receive optical
power (dBm)
-30
-28
-34
-34
-34
Minimum
overload (dBm)
-14
-8
-10
-10
-10

1111

13 ATM Boards
Parameter
Value
Minimum
extinction ratio
(dB)
10
8.2
10
10
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression
ratio (dB)
30
30
Laser Safety Class

The mechanical specifications of the ADQ1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the ADQ1 at room temperature (25C) is 41 W.
13.3 IDL4
technical specifications of the IDL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the IDL4.

The IDL4 is available in one functional version, namely, N1.
13.3.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and lowspeed links.
The IMA board is applicable to the transmission of the ATM cells on the E1 interface or
interfaces at the other rates. The IMA board only provides a channel and does not process the
Issue 03 (2013-02-20)

1112

13 ATM Boards
service type or ATM cells. That is, the IMA board transparently transmits the ATM layer signals
and higher-layer signals. Figure 13-9 shows the networking and application of the IMA services.
Figure 13-9 Networking and application of the IMA services
RNC
NE1
NMS
25 km
NodeB 1
40 km
NE2
NE4
Two-fiber bidirectional
MSP ring
NodeB 4
35 km
30 km
NE3
NodeB 2
NodeB 3

The IDL4 supports the ATM switching, IMA, and ATM protection.
Table 13-15 provides the functions and features of the IDL4.
Table 13-15 Functions and features of the IDL4
Issue 03 (2013-02-20)
Function and
Feature
IDL4
Basic functions
Type of optical
interface
Supports the following types of optical interfaces: S-4.1, L-4.1, L-4.2

and Ve-4.2.
Connector type
LC
Optical module type
SFP
E3 ATM interface
Does not support the E3 ATM interface.

1113

13 ATM Boards
Function and
Feature
IDL4
IMA functions
(ATM Forum IMA
1.1)
l Transmits/Receives and processes IMA services when the IDL4

is used with the E1 service processing board N1PQ1 or N1PQM.
l Supports a maximum of 63 E1 IMA services.
l Supports the mapping between ATM ports and a maximum of 16
IMA groups. Each IMA group supports 132 E1 signals.
E1 links that belong to non-IMA groups.
l Supports the maximum IMA multichannel delay of 226 ms.
Maximum uplink
bandwidth

7xVC-4s.
NOTE
Only the first VC-4 supports the binding of VC-12 paths.
VCTRUNK 1VCTRUNK 66 can be bound with VC-4s numbered 14 or
VC-12s numbered 163 only. VCTRUNK 67VCTRUNK 70 can be bound
with VC-4s numbered 58.
ATM switching
capability
Mapping
granularities
Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 1

32) granularities.
Service types
Supports the CBR, rt-VBR, nrt-VBR and UBR.
Number of supported
ATM connections
2048
Statistical
multiplexing
Flow types and QoS
ATM multicast
connection
ATM protection
(ITU-T I.630)

Board-level 1+1
protection
Supports the board-level 1+1 protection.
OAM functions
(ITU-T I.610)
Maintenance
features

Issue 03 (2013-02-20)

1114

13 ATM Boards
Function and
Feature
IDL4
Alarms and
performance events

Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

The IDL4 consists of the O/E converting module, physical layer module, ATM module, IMA
Figure 13-10 shows the functional block diagram of the IDL4 by describing how to process
1xSTM-4 signals.
Figure 13-10 Functional block diagram of the IDL4
Backplane
622
Mbit/s
622
Mbit/s
622
Mbit/s
E/O
622
Mbit/s
O/E
Physical
layer
module
ATM
module
High-speed
bus
High-speed
bus
Mapping
module
IMA
module
O/E converting
module
LOS
Laser shutdown
Logic and
control module
Communication
Cross-connect unit
SCC unit
50 MHz
77 MHz
100 MHz
Clock
module
+3.3 V
Power
module
Fuse
Fuse
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power

Issue 03 (2013-02-20)

1115

13 ATM Boards

l
ATM Module
ATM protocols:
l
Flow control
ATM switching
IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l
Separation and re-creation of ATM cells
Frame synchronization
Insertion and extraction of IMA control protocol (ICP) cells
Management of IMA groups
Mapping Module
l

l
Clock Module
Issue 03 (2013-02-20)

1116

13 ATM Boards
Power Module
require.
13.3.5 Front Panel

The front panel of the IDL4 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 13-11 shows the appearance of the front panel of the IDL4.
Figure 13-11 Front panel of the IDL4
IDL4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
IDL4
Indicators
Issue 03 (2013-02-20)

1117

13 ATM Boards
Interfaces
The front panel of the IDL4 has one optical interface. Table 13-16 describes the type and usage
of the optical interface of the IDL4.
Table 13-16 Optical interface of the IDL4
Interface
Type of
Interface
Usage
OUT1/IN1
LC
(swappable)

The IDL4 does not have any jumpers or DIP switches that are used for board settings.
13.3.7 Valid Slots

The IDL4 must be installed in a valid slot in the subrack. Otherwise, the IDL4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the IDL4 vary with the cross-connect capacity of the subrack. The slots valid
for the IDL4 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the IDL4 can be installed in slots 18 and
13.3.8 Feature Code

Table 13-17 provides the relationship between the feature code of the IDL4 and the type of
optical interface.
Issue 03 (2013-02-20)

1118

13 ATM Boards
Table 13-17 Relationship between the feature code of the IDL4 and the type of optical interface
Board
Feature Code
SSN1IDL410
10
S-4.1
SSN1IDL411
11
L-4.1
SSN1IDL412
12
L-4.2
SSN1IDL413
13
Ve-4.2

The IDL4 supports the 1+1 board-level protection. The working IDL4 and protection IDL4
should be installed in paired slots.
The paired slots valid for the IDL4 vary with the cross-connect capacity.
l
When the cross-connect capacity is 200 Gbit/s: (slot 8, slot 11), (slot 7, slot 12), (slot 6,
slot 13), (slot 5, slot 14), (slot 4, slot 15), (slot 3, slot 16), and (slot 2, slot 17)


matches the board.
is correct.
----End

Issue 03 (2013-02-20)

1119

13 ATM Boards

----End

Step 1 Use the ATM instrument (for example, AX4000) to test the ATM services.
1.
Connect the ATM instrument to the external optical interface of the board.
2.
Perform an outloop at the ATM port on the cross-connect side of the board. For the settings,
see 28.7 Checking Board Parameters.
3.
Configure the basic ATM services on the instrument.
4.
Send the ATM services on the instrument.
5.
Check whether the services received on the instrument are normal and check whether
certain cells are discarded.
Step 2 Use the IMA instrument (for example, AX4000) to test the IMA services.
1.
Connect the IMA instrument to the cross-connect side of the board. The connection can be
realized by using the E1 tributary board.
2.
Perform an outloop on the optical interface side of the board by using optical fiber pairs.
3.
Configure the basic IMA services on the instrument.
4.
Send the IMA services on the instrument.
5.
----End

Boards.
the Current Alarms.
----End

You can set parameters for the IDL4 by using the U2000.
Issue 03 (2013-02-20)

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13 ATM Boards
You can set the following main parameters for the IDL4 by using the U2000:
l
Port type
Flow type
Service type
PCR
SCR
CDVT
Settings.

Troubleshooting
Table 13-18 lists the faults that occur on the IDL4 frequently and the troubleshooting methods.
Table 13-18 Methods used to troubleshoot the faults that occur on the IDL4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

are interrupted.
Transient service
interruption



are transiently interrupted.
abnormal.
Packet loss

Packet Loss.
Interconnection
fault



l The IMA interconnection fault
occurs.
Issue 03 (2013-02-20)

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13 ATM Boards
Replacing the Board

NOTE
replace the board.
For information on how to replace the IDL4, see Replacing an ATM Board.

13.3.13.1 Alarms of N1IDL4
Issue 03 (2013-02-20)
ALM_E1AIS
ALM_IMA_LIF
ALM_IMA_LINK_LCD
ALM_IMA_LODS
ALM_IMA_RFI
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_SD
BD_STATUS
BIP_EXC
BIP_SD
CC_LOC
CHCS
COMMUN_FAIL
FPGA_ABN
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
J0_MM
LASER_MOD_ER
R
LASER_SHUT
LCD
LFA
LMFA
LOOP_ALM
LP_RDI
LP_REI
LP_SLM
LP_TIM
LP_UNEQ
LSR_NO_FITED
LSR_WILL_DIE
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OCD
OUT_PWR_ABN
POWER_ABNORMAL
R_LOF
R_LOS
R_LOSYNC
R_OOF
SLAVE_WORKIN
G
TEM_HA
TEM_LA
TF
TU_AIS
TU_LOP

1122

13 ATM Boards
UHCS
VC_AIS
VC_RDI
VCAT_LOA
VCAT_LOM_VC4
VCAT_SQM_VC4
VCG_MM
VP_AIS
VP_RDI
VPG_MM
W_R_FAIL
WRG_BD_TYPE
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
SWDL_PKG_NOB
DSOFT

13.3.14.1 Performance Events of N1IDL4

Table 13-19 SDH
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPSES
LPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSSES
MSUAS
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN

1123

13 ATM Boards
Table 13-20 ATM

ATM_INGCELL
ATM_EGCELL
ATM_CORRECTED_HC
SERR
ATM_UNCORRECTED_HC
SERR
ATM_RECV_CELL
ATM_RECV_IDLECELL
ATM_TRAN_CELL

The technical specifications of the IDL4 include the parameters specified for optical interfaces,

Table 13-21 lists the parameters specified for the optical interfaces of the IDL4.
Table 13-21 Parameters specified for the optical interfaces of the IDL4
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
S-4.1
L-4.1
L-4.2
Ve-4.2
Type of fiber
Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength range
(nm)
1274 to 1356
1280 to 1335
1480 to 1580
1480 to 1580
Launched optical
power range (dBm)
-15 to -8
-3 to +2
-3 to +2
-3 to +2
(dBm)
-28
-28
-28
-34
Minimum overload
(dBm)
-8
-8
-8
-13
Minimum extinction
ratio (dB)
8.2
10
10
10.5
Maximum -20 dB
spectral width (nm)
Minimum side mode

suppression ratio
(dB)
30
30
30

1124

13 ATM Boards
Laser Safety Class

The mechanical specifications of the IDL4 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the IDL4 at room temperature (25C) is 41 W.
13.4 IDQ1
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the IDQ1.

The IDQ1 is available in one functional version, namely, N1.
13.4.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and lowspeed links.
The IMA board is applicable to the transmission of the ATM cells on the E1 interface or
interfaces at the other rates. The IMA board only provides a channel and does not process the
service type or ATM cells. That is, the IMA board transparently transmits the ATM layer signals
and higher-layer signals. Figure 13-12 shows the networking and application of the IMA
services.
Issue 03 (2013-02-20)

1125

13 ATM Boards
Figure 13-12 Networking and application of the IMA services

RNC
NE1
NMS
25 km
NodeB 1
40 km
NE2
NE4
Two-fiber bidirectional
MSP ring
NodeB 4
35 km
30 km
NE3
NodeB 2
NodeB 3

The IDQ1 supports the ATM switching, IMA, and ATM protection.
Table 13-22 provides the functions and features of the IDQ1.
Table 13-22 Functions and features of the IDQ1
Issue 03 (2013-02-20)
Function and
Feature
IDQ1
Basic functions
Type of optical
interface
Supports different types of standard optical interfaces, namely, the Ie-1,

interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T
G.957. The characteristics of the optical interfaces of the Ie-1 and Ve-1.2
types comply with the standards defined by Huawei.
Connector type
LC
Optical module
type
SFP
E3 ATM interface
Does not support the E3 ATM interface.

1126

13 ATM Boards
Function and
Feature
IDQ1
IMA functions
(ATM Forum IMA
1.1)
l Transmits/Receives and processes IMA services when the IDQ1 is

used with the E1 service processing board N1PQ1 or N1PQM.
l Supports a maximum of 63 E1 IMA services.
IMA groups. Each IMA group supports 132 E1 signals.
l Supports the mapping between ATM ports and a maximum of 16 E1
links that belong to non-IMA groups.
l Supports the maximum IMA multichannel delay of 226 ms.
Maximum uplink
bandwidth

7xVC-4s. The IDQ1 can adapt to the bandwidth of the slot.
NOTE
Only the first VC-4 supports the binding of VC-12 paths.
VCTRUNK 1VCTRUNK 66 can be bound with VC-4s numbered 14 or
VC-12s numbered 163 only. VCTRUNK 67VCTRUNK 70 can be bound with
VC-4s numbered 58.
ATM switching
capability
Mapping
granularities
Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 132)

granularities.
Service types
Supports the CBR, rt-VBR, nrt-VBR, and UBR.
Number of
supported ATM
connections
2048
Statistical
multiplexing
Flow types and

QoS
ATM multicast
connection
ATM protection
(ITU-T I.630)
Supports unidirectional/bidirectional 1+1, unidirectional/bidirectional

1:1, VP-Ring, and VC-Ring protection schemes.
Board-level 1+1
protection
Supports the board-level 1+1 protection.
OAM functions
(ITU-T I.610)
Maintenance
features

Issue 03 (2013-02-20)

1127

13 ATM Boards
Function and
Feature
IDQ1
Alarm and
performance event
Reports various alarms and performance events, which can be used to

locate faults and maintain the equipment.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

The IDQ1 consists of the O/E converting module, physical layer module, ATM module, IMA
Figure 13-13 shows the functional block diagram of the IDQ1.
Figure 13-13 Functional block diagram of the IDQ1
Backplane
4x155
Mbit/s
4x155
Mbit/s
E/O
4x155
Mbit/s
O/E
Physical
layer
4x155 module
Mbit/s
ATM
module
High-speed
bus
High-speed
bus
Mapping
module
IMA
module
O/E converting
module
LOS
Laser shutdown
Logic and
control module
Communication
Cross-connect unit
SCC unit
50 MHz
77 MHz
100 MHz
Clock
module
+3.3 V
Power
module
Fuse
Fuse
Power
module
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power

Issue 03 (2013-02-20)

1128

13 ATM Boards

l
ATM Module
ATM protocols:
l
Flow control
ATM switching
IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l
Separation and re-creation of ATM cells
Frame synchronization
Insertion and extraction of IMA control protocol (ICP) cells
Management of IMA groups
Mapping Module
l

l
Clock Module
Issue 03 (2013-02-20)

1129

13 ATM Boards
Power Module
require.
13.4.5 Front Panel

The front panel of the IDQ1 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 13-14 shows the appearance of the front panel of the IDQ1.
Figure 13-14 Front panel of the IDQ1
IDQ1
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
IDQ1
Indicators
Issue 03 (2013-02-20)

1130

13 ATM Boards
Interfaces
The front panel of the IDQ1 has four optical interfaces. Table 13-23 describes the types and
usage of the optical interfaces of the IDQ1.
Table 13-23 Optical interfaces of the IDQ1
Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)
OUT2/IN2
LC (swappable)
OUT3/IN3
LC (swappable)
OUT4/IN4
LC (swappable)

The IDQ1 does not have any jumpers or DIP switches that are used for board settings.
13.4.7 Valid Slots

The IDQ1 must be installed in a valid slot in the subrack. Otherwise, the IDQ1 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the IDQ1 vary with the cross-connect capacity of the subrack. The slots valid
for the IDQ1 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the IDQ1 can be installed in slots 18 and
13.4.8 Feature Code

The feature code of the IDQ1 indicates the type of optical interface.
Issue 03 (2013-02-20)

1131

13 ATM Boards
Table 13-24 provides the relationship between the feature code of the IDQ1 and the type of
optical interface.
Table 13-24 Relationship between the feature code of the IDQ1 and the type of optical interface
Board
Feature Code
SSN1IDQ110
10
S-1.1
SSN1IDQ111
11
L-1.1
SSN1IDQ112
12
L-1.2
SSN1IDQ113
13
Ve-1.2
SSN1IDQ114
14
Ie-1

The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be
housed in paired slots.
The valid paired slots for the IDQ1 vary with the cross-connect capacity.
l
When the cross-connect capacity is 200 Gbit/s: (slot 8, slot 11), (slot 7, slot 12), (slot 6,
slot 13), (slot 5, slot 14), (slot 4, slot 15), (slot 3, slot 16), (slot 2, slot 17)


matches the board.
is correct.
----End
Issue 03 (2013-02-20)

1132

13 ATM Boards

----End

Step 1 Use the ATM instrument (for example, AX4000) to test the ATM services.
1.
Connect the ATM instrument to the external optical interface of the board.
2.
Perform an outloop at the ATM port on the cross-connect side of the board. For the settings,
see 28.7 Checking Board Parameters.
3.
Configure the basic ATM services on the instrument.
4.
Send the ATM services on the instrument.
5.
Step 2 Use the IMA instrument (for example, AX4000) to test the IMA services.
1.
Connect the IMA instrument to the cross-connect side of the board. The connection can be
realized by using the E1 tributary board.
2.
Perform an outloop on the optical interface side of the board by using optical fiber pairs.
3.
Configure the basic IMA services on the instrument.
4.
Send the IMA services on the instrument.
5.
----End

Boards.
Issue 03 (2013-02-20)

1133

13 ATM Boards
the Current Alarms.
----End

You can set parameters for the IDQ1 by using the U2000.
You can set the following main parameters for the IDQ1 by using the U2000:
l
Port type
Flow type
Service type
PCR
SCR
CDVT
Settings.

Troubleshooting
Table 13-25 lists the faults that occur on the IDQ1 frequently and the troubleshooting methods.
Table 13-25 Methods used to troubleshoot the faults that occur on the IDQ1 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

are interrupted.
Transient service
interruption



are transiently interrupted.
abnormal.
Packet loss
Issue 03 (2013-02-20)


Packet Loss.
1134

13 ATM Boards
Fault Symptom
Common Fault Cause
Interconnection
fault



l The IMA interconnection fault
occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the IDQ1, see Replacing an ATM Board.

13.4.13.1 Alarms of N1IDQ1
Issue 03 (2013-02-20)
ALM_E1AIS
ALM_IMA_LIF
ALM_IMA_LINK_LCD
ALM_IMA_LODS
ALM_IMA_RFI
AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_SD
BD_STATUS
BIP_EXC
BIP_SD
CC_LOC
CHCS
COMMUN_FAIL
FPGA_ABN
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
J0_MM
LASER_MOD_ER
R
LASER_SHUT
LCD
LFA
LMFA
LOOP_ALM
LP_RDI
LP_REI
LP_SLM
LP_TIM
LP_UNEQ
LSR_NO_FITED

1135

13 ATM Boards
LSR_WILL_DIE
MS_AIS
MS_RDI
MS_REI
NO_BD_SOFT
OCD
OUT_PWR_ABN
POWER_ABNORMAL
R_LOF
R_LOS
R_LOSYNC
R_OOF
SLAVE_WORKIN
G
TEM_HA
TEM_LA
TF
TU_AIS
TU_LOP
UHCS
VC_AIS
VC_RDI
VCAT_LOA
VCAT_LOM_VC4
VCAT_SQM_VC4
VCG_MM
VP_AIS
VP_RDI
VPG_MM
W_R_FAIL
WRG_BD_TYPE
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
SWDL_PKG_NOB
DSOFT

13.4.14.1 Performance Events of N1IDQ1

Table 13-26 SDH
Issue 03 (2013-02-20)
AUPJCHIGH
AUPJCLOW
AUPJCNEW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
LPBBE
LPCSES
LPES
LPFEBBE
LPFECSES
LPFEES
LPFESES
LPSES
LPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSSES
MSUAS

1136

13 ATM Boards
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
RSBBE
RSCSES
RSES
RSSES
RSUAS
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Table 13-27 ATM

ATM_INGCELL
ATM_EGCELL
ATM_CORRECTED_HC
SERR
ATM_UNCORRECTED_HC
SERR
ATM_RECV_CELL
ATM_RECV_IDLECELL
ATM_TRAN_CELL

The technical specifications of the IDQ1 include the parameters specified for optical interfaces,

Table 13-28 lists the parameters specified for the optical interfaces of the IDQ1.
Table 13-28 Parameters specified for the optical interfaces of the IDQ1
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
Ie-1
S-1.1
L-1.1
L-1.2
Ve-1.2
Type of fiber
Multimode LC
Singlemode LC
Single-mode
LC
Singlemode LC
Single-mode
LC
Operating
wavelength
range (nm)
1270 to
1380
1261 to
1360
1263 to 1360
1480 to
1580
1480 to 1580
Transmission
distance (km)
0 to 0.5
2 to 15
15 to 40
40 to 80
80 to 100
Launched optical
power range
(dBm)
-19 to -14
-15 to -8
-5 to 0
-5 to 0
-3 to 0

1137

13 ATM Boards
Parameter
Value
Receiver
sensitivity
(dBm)
-30
-28
-34
-34
-34
Minimum
overload (dBm)
-14
-8
-10
-10
-10
Minimum
extinction ratio
(dB)
10
8.2
10
10
10
Maximum -20
dB spectral
width (nm)
Minimum side
mode
suppression ratio
(dB)
30
30
Laser Safety Class

The mechanical specifications of the IDQ1 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the IDQ1 at room temperature (25C) is 41 W.
Issue 03 (2013-02-20)

1138

14 RPR Boards
14
RPR Boards
About This Chapter

The RPR boards include FE/GE Ethernet ring processing boards.
14.1 EGR2
technical specifications of the EGR2 (2xGE ring processing board). This topic also describes
how to configure and commission the EGR2.
14.2 EMR0
technical specifications of the EMR0 (12xFE and 1xGE ring processing board). This topic also
describes how to configure and commission the EMR0.
Issue 03 (2013-02-20)

1139

14 RPR Boards
14.1 EGR2
technical specifications of the EGR2 (2xGE ring processing board). This topic also describes
how to configure and commission the EGR2.

The EGR2 is available in one functional version, namely, N2.
14.1.2 Application
The EGR2 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
Figure 14-1 shows the typical networking and application of the RPR board. The RPR board
accesses and converges Ethernet services, and provides the Ethernet data with the following data
features: Layer 2 switching, port isolation, flow classification, traffic control, VLAN
management, and priority configuration. In addition, the RPR board performs encapsulation/
decapsulation, virtual concatenation, and SDH mapping/demapping for data. The RPR board
can be interconnected with the bandwidth access equipment and the data communication
equipment at the same time, thus to provide a network-level solution.
NOTE
variable, and the binding granularity is at the VC-3 or VC-4 level.
Issue 03 (2013-02-20)

1140

14 RPR Boards
Figure 14-1 Networking and application of the RPR board
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EGR2 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 14-1 provides the functions and features of the EGR2.
Table 14-1 Functions and features of the EGR2
Function and
Feature
EGR2
Basic functions
Transmits/Receives and processes 2xGE services.

Supports the RPR feature.
Functions when
being used with the
interface board
Issue 03 (2013-02-20)
Transmits/Receives 2xGE signals by providing interfaces on the front

panel.

1141

14 RPR Boards
Function and
Feature
EGR2
optical interface
l The optical interfaces are 1000BASE-SX/LX/ZX/VX Ethernet

optical interfaces.
l The optical interfaces support the auto-negotiation function in
compliance with IEEE 802.3z.
l The optical interfaces use the SFP optical module and support hot
swapping.
When the multi-mode optical fiber is used, the maximum
transmission distance is 550 m.
When the single-mode optical fiber is used, the maximum
transmission distance is 10 km.
The optical modules that can meet different requirements for
the transmission distance such as 40 km and 80 km can also be
used.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Supports the setting of the frame length to a value ranging from
1518 bytes to 9600 bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
The EGR2 can adapt to the bandwidth of the slot.
Mapping
granularities
Supports VC-3, VC3-Xv (X2), VC-4 and VC4-Xv (X8)

granularities.
NOTE
VC-3 virtual concatenation on the SDH side supports only one or two VC-3s.
In addition, only the first two VC-3 timeslots of the first VC-4 in the first
STM-4 frame of each VCTRUNK can be used.
Encapsulation
format
Supports the GFP-F and LAPS protocols.
EPL services
EVPL services
l Supports EVPL services. The frame format can be Ethernet II,

IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.
l Supports the MPLS encapsulation and forwarding based on PORT
or PORT+VLAN.
l Supports five types of LSPs, including ingress LSP, egress LSP,
transit LSP, RPR ingress LSP, and RPR transit LSP.
l Supports a maximum of 512 LSPs.
Issue 03 (2013-02-20)

1142

14 RPR Boards
Function and
Feature
EGR2
EVPLAN services
l Supports EVPLAN services that use the stack VLAN

encapsulation.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table in the N2 functional version is
64K. The aging time of the MAC address can be set and queried.
l Supports the blacklist that can contain 4K records and also the
static MAC address table that can contain 4K records. The sum of
the number of records in the blacklist and the number of addresses
in the static MAC address table must not exceed 4K.
l Supports the configuration of the static MAC routes. A maximum
of 4K static MAC routes can be configured.
l Supports the creation, deletion, and query of the VB. The
maximum number of supported VBs is 16. The maximum number
of logical ports for each VB is 32.
virtual bridge.
MPLS
Supports MartinioE.
Stack VLAN
Supports the stack VLAN.
VLAN
l Supports 4096 VLAN tags, and the addition, deletion, and

exchanging of VLAN tags in compliance with IEEE 802.1q/p.
l Supports the replacement of VLAN tags in Ethernet signal frames.
Link aggregation
function
Supports the aggregation of the links of two GE ports.
RPR
l Supports the RPR feature that complies with IEEE 802.17.

l Supports a maximum of 255 nodes on the ring network, and
supports stripping at the destination node and weighted fairness
algorithm.
l Supports five priority levels, including A0, A1, B_EIR, B_CIR,
and C, and supports automatic discovery of topologies, which can
display the network status in real time.
l Supports three protection modes, including Steering, Wrapping,
and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.
l Supports the manual configuration of routes for the services on the
RPR ring network.
l Supports the self-learning of routes on the ring, that is, supports
the learning of mapping between MAC addresses and node
numbers.
RSTP
Issue 03 (2013-02-20)

with IEEE 802.1w.

1143

Function and
Feature
EGR2
IGMP snooping
Supports the IGMP snooping function.
QoS
14 RPR Boards
l Supports the flow classification based on PORT, PORT+VLAN

ID, or PORT+VLAN ID+VLAN PRI.
LCAS function

LPT function
Supports the P2MP LPT.
Flow control
function
Supports the port-based flow control function that complies with

IEEE 802.3x.
IEEE 1588v2
Not supported.
Echo test frames
Supports the echo function specified in the RPR OAM function, which
is used to test the connectivity of the link.
Port mirroring
Does not support port mirroring.
Loopback function
Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes
Supports the following protection schemes at the Ethernet network

level:
l STP/RSTP
l LCAS
l LPT
l LAG
Issue 03 (2013-02-20)
Ethernet
performance
monitoring
Alarms and
performance events

Warm resets
EGR2 boards support warm resets. If a warm reset is performed on

an EGR2 board, traffic on the board is interrupted.
Cold resets
Supported
Weighted fairness
algorithm
Supports the weighted fairness algorithm.
Automatic discovery
of topologies
Supports the automatic discovery of topologies.
Maximum number of
supported nodes
255
Service priority
levels
Supports A0, A1, B_CIR, B_EIR, and C.

1144

14 RPR Boards

The EGR2 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 14-2 shows the functional block diagram of the EGR2 by describing how to process
1xGE/FE signals.
Figure 14-2 Functional block diagram of the EGR2
Backplane
RPR protocol
processing module
Logic and
control module
Cross-connect unit
Cross-connect unit
Mapping module
Laser shutdown
LOS
Interface
converting
module
VCP
RPR
MAC
(west)
DENCP
RPR
MAC
(east)
ENCP
Control
Network signal Switch
processor
fabric
Data
GE/FE Ethernet
access
module
Communication
SCC unit
50 MHz
77 MHz
125 MHz Clock module
100 MHz
+3.3 V
Power
module
Power
module
Fuse
Fuse
Cross-connect unit
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
RPR: resilient package ring


Issue 03 (2013-02-20)

1145

14 RPR Boards
l
MPLS
L2 MPLS VPN
Ethernet/VLAN
l
WFQ
Four CoSs
RPR Protocol Processing Module

The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.
Mapping Module
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
The decapsulated data is finally transmitted to the RPR protocol processing module in packets.

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14 RPR Boards

l
functions:
l
Clock Module
Power Module
require.
14.1.5 Front Panel

The front panel of the EGR2 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 14-3 shows the appearance of the front panel of the EGR2.
Issue 03 (2013-02-20)

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14 RPR Boards
Figure 14-3 Front panel of the EGR2
EGR2
STAT
ACT
PROG
SRV
LINK1
ACT1
LINK2
ACT2
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
EGR2
Indicators
l
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Interfaces
The front panel of the EGR2 has two optical interfaces. Table 14-2 describes the types and usage
of the optical interfaces of the EGR2.
Table 14-2 Optical interfaces of the EGR2
Interface
Type of Interface
Usage
OUT1/IN1
LC (swappable)

VX signals.
OUT2/IN2
LC (swappable)

VX signals.

The EGR2 does not have any jumpers or DIP switches that are used for board settings.
14.1.7 Valid Slots

The EGR2 must be installed in a valid slot in the subrack. Otherwise, the EGR2 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EGR2 can be installed in slots 18 and 1116 in the subrack. The relationship between the
slots valid for the EGR2 and the bandwidth is as follows:
l
When the cross-connect capacity is 200 Gbit/s, the EGR2 can be installed in slots 18 and
1116. When the EGR2 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EGR2 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
14.1.8 Feature Code

The feature code of the EGR2 indicates the type of optical interface.
Table 14-3 provides the relationship between the feature code of the EGR2 and the type of
optical interface.
Table 14-3 Relationship between the feature code of the EGR2 and the type of optical interface
Issue 03 (2013-02-20)
Board
Feature Code
SSN2EGR210
10
SSN2EGR211
11
1000BASE-LX (10 km)

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14 RPR Boards
Board
Feature Code
SSN2EGR212
12
1000BASE-VX (40 km)
SSN2EGR213
13
1000BASE-ZX (80 km)


matches the board.
is correct.
----End

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14 RPR Boards

NOTE
LAG.
----End

----End

Boards.
the Current Alarms.
----End

The EGR2 supports multiple Ethernet functions and features such as Layer 2 switching and
LCAS. Configure the functions according to actual requirements.
You can configure the following Ethernet functions for the EGR2 by using the U2000:
l
STP/RSTP
LCAS
LPT
LAG
Test Frame
IGMP Snooping

You can set parameters for the EGR2 by using the U2000.
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14 RPR Boards
You can set the following main parameters for the EGR2 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

Troubleshooting
Table 14-4 lists the faults that occur on the EGR2 frequently and the troubleshooting methods.
Table 14-4 Methods used to troubleshoot the faults that occur on the EGR2 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.
Interconnection
fault



fault occurs.
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14 RPR Boards
Replacing the Board

NOTE
replace the board.
For information on how to replace the EGR2, see Replacing an EOS Board.

14.1.13.1 Alarms of N2EGR2
Issue 03 (2013-02-20)
AU_AIS
AU_LOP
B3_EXC_VC3
B3_EXC_VC4
B3_SD_VC3
B3_SD_VC4
BD_STATUS
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
LAG_FAIL
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC3
LP_REI_VC3
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
LSR_NO_FITED
NO_BD_SOFT
RPR_DUPLICATE_MAC
RPR_ECHO_DLOC
RPR_ECHO_LOC
RPR_MISCONFIG
RPR_NB_INCONSIS
RPR_PM_INCONSIS
RPR_PS_CHANGE
RPR_STATIONS_EXCEED
RPR_SUM_A0_EXCEED
SLAVE_WORKING
T_LOS
TU_AIS_VC3
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC3
VCAT_LOM_VC4
LASER_MOD_ERR
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
LINK_ERR
LPT_RFI
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

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14 RPR Boards

14.1.14.1 Performance Events of N2EGR2

Table 14-5 SDH
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors
rprSpanErrorUnavailableSeconds
rprSpanErrorTtlExpFrames
rprSpanErrorTooLongFrames
rprSpanErrorTooShortFrames
rprSpanErrorBadHecFrames
rprSpanErrorBadFcsFrames
rprSpanErrorSelfSrcUcastFrames
rprSpanErrorPmdAbortFrames
rprSpanErrorBadAddrFrames
rprSpanErrorBadParityFrames
rprSpanErrorContainedFrames
rprSpanErrorBadDataFcsFrames
rprSpanErrorBadCtrlFcsFrames
rprSpanErrorScffErrors
rprSpanErrorErroredSeconds
rprSpanErrorSeverelyErroredSeconds
Issue 03 (2013-02-20)

Packets Received
Length)(packets/s)

(packets/s)

(packets/s)

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14 RPR Boards

(packets/s)

(packets/s)
Jabbers(packets/s)
Collisions(times/s)
Packets Received(packets/
s)

Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)

(packets/s)

(packets/s)
Multicast Packets
Broadcast Packets

(Byte/s)
Table 14-9 Statistics of RMON VCG performance (receive frame count at Span side)
rprSpanRxUcastClassAFrames(frames/s)
rprSpanRxUcastClassABytes(Byte/s)
rprSpanRxUcastClassBCirFrames(frames/s)
rprSpanRxUcastClassBCirBytes(Byte/s)
rprSpanRxUcastClassBEirFrames(frames/s)
rprSpanRxUcastClassBEirBytes(Byte/s)
rprSpanRxUcastClassCFrames(frames/s)
rprSpanRxUcastClassCBytes(Byte/s)
rprSpanRxMcastClassAFrames(frames/s)
rprSpanRxMcastClassABytes(Byte/s)
rprSpanRxMcastClassBCirFrames(frames/s)
rprSpanRxMcastClassBCirBytes(Byte/s)
rprSpanRxMcastClassBEirFrames(frames/s)
rprSpanRxMcastClassBEirBytes(Byte/s)
rprSpanRxMcastClassCFrames(frames/s)
rprSpanRxMcastClassCBytes(Byte/s)
Table 14-10 Statistics of RMON VCG performance (transmit frame count at Span side)
rprSpanTxUcastClassAFrames(frames/s)
Issue 03 (2013-02-20)
rprSpanTxUcastClassABytes(Byte/s)

rprSpanTxUcastClassBCirFrames(frames/s)
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14 RPR Boards
rprSpanTxUcastClassBCirBytes(Byte/s)
rprSpanTxUcastClassBEirFrames(frames/s)
rprSpanTxUcastClassBEirBytes(Byte/s)
rprSpanTxUcastClassCFrames(frames/s)
rprSpanTxUcastClassCBytes(Byte/s)
rprSpanTxMcastClassAFrames(frames/s)
rprSpanTxMcastClassABytes(Byte/s)
rprSpanTxMcastClassBCirFrames(frames/s)
rprSpanTxMcastClassBCirBytes(Byte/s)
rprSpanTxMcastClassBEirFrames(frames/s)
rprSpanTxMcastClassBEirBytes(Byte/s)
rprSpanTxMcastClassCFrames(frames/s)
rprSpanTxMcastClassCBytes(Byte/s)
Table 14-11 Statistics of RMON VCG performance (count of control layer frames)
rprSpanTxCtrlFrames
(frames/s)
rprSpanTxOamEchoFrames
(frames/s)
rprSpanTxOamFlushFrames
(frames/s)
rprSpanTxOamOrgFrames
(frames/s)
rprSpanTxTopoAtdFrames
(frames/s)
rprSpanTxTopoChkSumFrames(frames/s)
rprSpanTxTopoTpFrames
(frames/s)
rprSpanRxCtrlFrames
(frames/s)
rprSpanRxOamEchoFrames
(frames/s)
rprSpanRxOamFlushFrames
(frames/s)
rprSpanRxOamOrgFrames
(frames/s)
rprSpanRxTopoAtdFrames
(frames/s)
rprSpanRxTopoChkSumFrames(frames/s)
rprSpanRxTopoTpFrames
(frames/s)
Table 14-12 Statistics of RMON VCG performance (frames received by Client)
Issue 03 (2013-02-20)
rprClientTxUcastClassAFrames(frames/s)
rprClientTxUcastClassABytes(Byte/s)
rprClientTxUcastClassBCirFrames(frames/s)
rprClientTxUcastClassBCirBytes(Byte/s)
rprClientTxUcastClassBEirFrames(frames/s)
rprClientTxUcastClassBEirBytes(Byte/s)
rprClientTxUcastClassCFrames(frames/s)
rprClientTxUcastClassCBytes(Byte/s)
rprClientTxMcastClassAFrames(frames/s)
rprClientTxMcastClassABytes(Byte/s)
rprClientTxMcastClassBCirFrames(frames/s)
rprClientTxMcastClassBCirBytes(Byte/s)
rprClientTxMcastClassBEirFrames(frames/s)
rprClientTxMcastClassBEirBytes(Byte/s)
rprClientTxMcastClassCFrames(frames/s)
rprClientTxMcastClassCBytes(Byte/s)
rprClientTxBcastFrames
(frames/s)

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14 RPR Boards
Table 14-13 Statistics of RMON VCG performance (frames transmitted by client)

rprClientRxUcastClassAFrames(frames/s)
rprClientRxUcastClassABytes(Byte/s)
rprClientRxUcastClassBCirFrames(frames/s)
rprClientRxUcastClassBCirBytes(Byte/s)
rprClientRxUcastClassBEirFrames(frames/s)
rprClientRxUcastClassBEirBytes(Byte/s)
rprClientRxUcastClassCFrames(frames/s)
rprClientRxUcastClassCBytes(Byte/s)
rprClientRxMcastClassAFrames(frames/s)
rprClientRxMcastClassABytes(Byte/s)
rprClientRxMcastClassBCirFrames(frames/s)
rprClientRxMcastClassBCirBytes(Byte/s)
rprClientRxMcastClassBEirFrames(frames/s)
rprClientRxMcastClassBEirBytes(Byte/s)
rprClientRxMcastClassCFrames(frames/s)
rprClientRxMcastClassCBytes(Byte/s)
rprClientRxBcastFrames
(frames/s)
Table 14-14 Statistics of RMON VCG performance (count of error frames)

(frames/s)
rprSpanErrorTooLongFrames(frames/s)
rprSpanErrorTooShortFrames(frames/s)
(frames/s)
(frames/s)
rprSpanErrorSelfSrcUcastFrames(frames/s)
rprSpanErrorPmdAbortFrames(frames/s)
rprSpanErrorBadAddrFrames(frames/s)
rprSpanErrorBadParityFrames(frames/s)
rprSpanErrorContainedFrames(frames/s)
rprSpanErrorBadDataFcsFrames(frames/s)
rprSpanErrorBadCtrlFcsFrames(frames/s)
(frames/s)
rprSpanErrorErroredSeconds(seconds/s)
rprSpanErrorSeverelyErroredSeconds(seconds/s)
rprSpanErrorUnavailableSeconds(seconds/s)

The technical specifications of the EGR2 include the parameters specified for optical interfaces,
consumption.

Table 14-15 lists the parameters specified for the optical interfaces of the EGR2.
Issue 03 (2013-02-20)

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14 RPR Boards
Table 14-15 Parameters specified for the optical interfaces of the EGR2
Parameter
Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASEVX (40 km)
1000BASELX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber
Single-mode LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5
-5 to 0
-9 to -3
-9.5 to -2.5
Operating
wavelength range
(nm)
1500 to 1580
1275 to 1350
1270 to 1355
770 to 860
Minimum
overload (dBm)
-3
-3
-3
Receiver
sensitivity (dBm)
-23
-23
-20
-17
Minimum
extinction ratio
(dB)
Maximum -20 dB
spectral width
(nm)
30
Minimum side
30
mode suppression
ratio (dB)
Laser Safety Class


NOTE
specifications, and back-to-back specifications of the EGR2 board of the N2 version.
the case of overloading, latency specifications, and back-to-back specifications of the EGR2.
Issue 03 (2013-02-20)

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14 RPR Boards
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 14-16 lists the throughput specifications of the EGR2. Table 14-17 lists the packet loss
ratio in the case of overloading of the EGR2. Table 14-18 lists the latency specifications of the
EGR2. Table 14-19 lists the back-to-back specifications of the EGR2.
NOTE
are used.
The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.
Table 14-16 lists the throughput specifications of the EGR2. The values are obtained when the
l
Number of pairs: 1
Mode: bidirectional
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14 RPR Boards
Table 14-16 Throughput specifications of the EGR2

Frame Size
(Byte)
Passed Rate
(%)
(01,08,01) to
(01,08,02) (pks/
sec)
(01,08,02) to
(01,08,01) (pks/
sec)
Total (pks/
sec)
64
80.77
1201923
1201923
2403846
128
94.87
801282
801282
1602564
256
100.00
452899
452899
905798
512
100.00
234962
234962
469924
1024
100.00
119732
119732
239464
1280
100.00
196154
96154
192308
1518
100.00
81274
81274
162548
Table 14-17 lists the packet loss ratio in the case of overloading of the EGR2. The values are
l
Number of pairs: 1
Mode: bidirectional
Table 14-17 Packet loss ratio in the case of overloading of the EGR2
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,08,01) to
(01,08,02) (%)
(01,08,02) to
(01,08,01) (%)
Average (%)
64
100.00
16.719
16.720
16.719
128
100.00
4.315
4.328
4.321
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000

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14 RPR Boards
Table 14-18 lists the latency specifications of the EGR2. The values are obtained when the
l
when the first bit of the transmitted frame reaches the output port of the equipment and the
time when the first bit of the transmitted frame reaches the input port of the equipment. In
store forward mode, the analyzer calculates the difference between the time when the first
bit of the transmitted frame reaches the output port of the equipment and the time when the
last bit of the transmitted frame reaches the input port of the equipment. In the table, the
CT values are obtained in cut through mode and the S&F values are obtained in store
forward mode.
Number of pairs: 1
Mode: bidirectional
Table 14-18 Latency specifications of the EGR2

Frame
Size
(Byte)
Rate
Tested
(%)
(01,08,01) to
(01,08,02) (us)CT (us)
Average
(CT) (us)
(01,08,01) to
(01,08,02)
(us)-S&F (us)
Average
(S&F) (us)
64
80.77
117.8
117.8
117.3
117.3
128
94.87
121.2
121.2
120.2
120.2
256
100.00
126.6
126.6
124.6
124.6
512
100.00
137.7
137.7
133.7
133.7
1024
100.00
159.9
159.9
151.8
151.8
1280
100.00
170.2
170.2
160.0
160.0
1518
100.00
182.9
182.9
170.8
170.8
Table 14-19 lists the back-to-back specifications of the EGR2. The values are obtained when
l
Issue 03 (2013-02-20)

1161

Number of pairs: 1
Mode: bidirectional
14 RPR Boards
Table 14-19 Back-to-back specifications of the EGR2

Frame Size
(Byte)
Rate Tested
(%)
(01,08,01) to
(01,08,02) Burst
Size (Number of
Frames)
(01,08,02) to
(01,08,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
298
300
598
128
100.00
650
650
1300
256
100.00
905798
905798
1811596
512
100.00
469924
469924
939848
1024
100.00
239464
239464
478928
1280
100.00
192308
192308
384616
1518
100.00
162548
162548
325096
The mechanical specifications of the EGR2 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the EGR2 at room temperature (25C) is 40 W.
14.2 EMR0
technical specifications of the EMR0 (12xFE and 1xGE ring processing board). This topic also
describes how to configure and commission the EMR0.

The EMR0 is available in one functional version, namely, N2.
Issue 03 (2013-02-20)

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14 RPR Boards
14.2.2 Application
The EMR0 is used to transmit/receive Ethernet services, manage bandwidths, and realize Layer
Figure 14-5 shows the typical networking and application of the RPR board. The RPR board
accesses and converges Ethernet services, and provides the Ethernet data with the following data
features: Layer 2 switching, port isolation, flow classification, traffic control, VLAN
management, and priority configuration. In addition, the RPR board performs encapsulation/
decapsulation, virtual concatenation, and SDH mapping/demapping for data. The RPR board
can be interconnected with the bandwidth access equipment and the data communication
equipment at the same time, thus to provide a network-level solution.
NOTE
variable, and the binding granularity is at the VC-3 or VC-4 level.
Figure 14-5 Networking and application of the RPR board
NMS
NE1
User A2
PORT 1
VLAN 100
NE2
MSP ring
NE4
NE3
PORT 2
VLAN 100
PORT 2
User B2
VLAN 100
Service flow
PORT 1 VLAN 100
User B1
Line board
Data board
Cross-connect and
timing board
User A1

The EMR0 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 14-20 provides the functions and features of the EMR0.
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14 RPR Boards
Table 14-20 Functions and features of the EMR0

Function and
Feature
EMR0
Basic functions
Transmits/Receives and processes 12xFE services and 1xGE

services.
Supports the RPR feature.
Functions when
being used with the
interface board
l Supports four FE ports and one GE port.

l Transmits/Receives 12xFE signals through the electrical interface
when the EMR0 is used with the ETF8.
l Transmits/Receives 8xFE signals through the optical interface
when the EMR0 is used with the EFF8.
optical interface
l Supports 10BASE-T/100BASE-TX signals when the EMR0 is

used with the ETF8. The maximum transmission distance is 100
m.
l Supports 100BASE-FX signals in compliance with IEEE 802.3u
when the EMR0 is used with the EFF8.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
The EMR0 can adapt to the bandwidth of the slot.
Mapping
granularities
Supports VC-3, VC3-Xv (X2), VC-4 and VC4-Xv (X8)

granularities.
NOTE
VC-3 virtual concatenation on the SDH side supports only one or two VC-3s.
In addition, only the first two VC-3 timeslots of the first VC-4 in the first
STM-4 frame of each VCTRUNK can be used.
Encapsulation format
Supports the GFP-F and LAPS protocols.
EPL services
EVPL services
l Supports EVPL services. The frame format can be Ethernet II,

IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.
l Supports the MPLS encapsulation and forwarding based on PORT
or PORT+VLAN.
l Supports five types of LSPs, including ingress LSP, egress LSP,
transit LSP, RPR ingress LSP, and RPR transit LSP.
l Supports a maximum of 512 LSPs.
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14 RPR Boards
Function and
Feature
EMR0
EVPLAN services
l Supports EVPLAN services that use the stack VLAN

encapsulation.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table in the N2 functional version is
64K. The capacity of the MAC address table in the N1 functional
version is 16K. The aging time of the MAC address can be set and
queried.
l Supports the blacklist that can contain 4K records and also the
static MAC address table that can contain 4K records. The sum of
the number of records in the blacklist and the number of addresses
in the static MAC address table must not exceed 4K.
l Supports the configuration of the static MAC routes. A maximum
of 4K static MAC routes can be configured.
l Supports the creation, deletion, and query of the VB. The
maximum number of VBs supported by the N2EMR0 is 16. The
maximum number of logical ports for each VB is 32.
virtual bridge.
MPLS
Supports MartinioE.
Stack VLAN
Supports the stack VLAN.
VLAN
l Supports 4096 VLAN tags, and the addition, deletion, and

exchanging of VLAN tags in compliance with IEEE 802.1q/p.
l Supports the replacement of VLAN tags in Ethernet signal frames.
Link aggregation
function
Supports the aggregation of the links of a maximum of eight FE ports.
RPR
l Supports the RPR feature that complies with IEEE 802.17.

l Supports a maximum of 255 nodes on the ring network, and
supports stripping at the destination node and weighted fairness
algorithm.
l Supports five priority levels, including A0, A1, B_EIR, B_CIR,
and C, and supports automatic discovery of topologies, which can
display the network status in real time.
l Supports three protection modes, including Steering, Wrapping,
and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.
l Supports the self-learning of routes on the ring, that is, supports
the learning of mapping between MAC addresses and node
numbers.
l The N2EMR0 supports the manual configuration of routes for the
services on the RPR ring network.
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14 RPR Boards
Function and
Feature
EMR0
RSTP

with IEEE 802.1w.
IGMP snooping
Supports the IGMP snooping function.
QoS function

l The N2EMR0 supports the flow classification based on PORT,
PORT+VLAN ID, or PORT+VLAN ID+VLAN PRI.
LCAS function

Flow control function
Supports the port-based flow control function that complies with

IEEE 802.3x.
Echo test frames
Supports the echo function specified in the RPR OAM function,

which is used to test the connectivity of the link.
Loopback function
Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes
Supports the following protection schemes at the Ethernet network

level:
l STP/RSTP
l LCAS
l LAG
Ethernet
performance
monitoring
Alarms and
performance events

Warm resets
EMR0 boards support warm resets. If a warm reset is performed on

an EMR0 board, traffic on the board is interrupted.
Cold resets
Supported
Weighted fairness
algorithm
Supports the weighted fairness algorithm.
Automatic discovery
of topologies
Supports the automatic discovery of topologies.
Maximum number of 255

supported nodes
Service priority
levels
Issue 03 (2013-02-20)
Supports A0, A1, B_CIR, B_EIR, and C.

1166

14 RPR Boards

The EMR0 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 14-6 shows the functional block diagram of the EMR0 by describing how to process
1xGE/FE signals.
Figure 14-6 Functional block diagram of the EMR0
Backplane
RPR protocol
processing module
Logic and
control module
Cross-connect unit
Cross-connect unit
Mapping module
Laser shutdown
LOS
Interface
converting
module
VCP
RPR
MAC
(west)
DENCP
RPR
MAC
(east)
ENCP
Control
Network signal Switch
processor
fabric
Data
GE/FE Ethernet
access
module
Communication
SCC unit
50 MHz
77 MHz
125 MHz Clock module
100 MHz
+3.3 V
Power
module
Power
module
Fuse
Fuse
Cross-connect unit
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
RPR: resilient package ring


Issue 03 (2013-02-20)

1167

MPLS
L2 MPLS VPN
Ethernet/VLAN
14 RPR Boards
l
WFQ
Four CoSs
RPR Protocol Processing Module

The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.
Mapping Module
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
The decapsulated data is finally transmitted to the RPR protocol processing module in packets.

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14 RPR Boards

l
functions:
l
Clock Module
Power Module
require.
14.2.5 Front Panel

The front panel of the EMR0 has indicators, interfaces, a bar code, and a laser safety class label.

Figure 14-7 shows the appearance of the front panel of the EMR0.
Issue 03 (2013-02-20)

1169

14 RPR Boards
Figure 14-7 Front panel of the EMR0
EMR0
STAT
ACT
PROG
SRV
LINK
ACT
CLASS 1
LASER
PRODUCT
OUT1
IN1
FE1
FE2
FE3
FE4
EMR0
Indicators
l
Issue 03 (2013-02-20)

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14 RPR Boards
Interfaces
The front panel of the EMR0 has five interfaces. Table 14-21 describes the types and usage of
the interfaces of EMR0.
Table 14-21 Interfaces of the EMR0
Interface
Type of
Interface
Usage
OUT1/IN1
LC (swappable)
Transmits and receives 1000BASE-SX/LX/ZX

signals.
FE1
RJ-45

signals.
FE2
RJ-45

signals.
FE3
RJ-45

signals.
FE4
RJ-45

signals.

The EMR0 does not have any jumpers or DIP switches that are used for board settings.
14.2.7 Valid Slots

The EMR0 must be installed in a valid slot in the subrack. Otherwise, the EMR0 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The EMR0 can be used with the ETF8 and EFF8.

The slots valid for the EMR0 are as follows:
l
When the cross-connect capacity is 200 Gbit/s, the EMR0 can be installed in slots 16 and
1316. When the EMR0 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EMR0 is installed in slots 5, 6, 13, and 14, the bandwidth is 2.5 Gbit/s.
Table 14-22 lists the slots valid for the EMR0 and the corresponding slots for the ETF8 and
EFF8.
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14 RPR Boards
Table 14-22 Slots valid for the EMR0 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMR0
Slot 1
Slot 2
Slot 19
Slot 3
Slot 21
Slot 4
Slot 23
Slot 5
Slot 25
Slot 6
Slot 13
Slot 29
Slot 14
Slot 31
Slot 15
Slot 33
Slot 16
Slot 35
14.2.8 Feature Code

The feature code of the EMR0 indicates the type of optical interface.
Table 14-23 provides the relationship between the feature code of the EMR0 and the type of
optical interface.
Table 14-23 Relationship between the feature code of the EMR0 and the type of optical interface
Board
Feature Code
SSN2EMR010
10
SSN2EMR011
11
1000BASE-LX (10 km)
SSN2EMR012
12
1000BASE-VX (40 km)
SSN2EMR013
13
1000BASE-ZX (80 km)


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14 RPR Boards
matches the board.
is correct.
----End

NOTE
LAG.
----End
Issue 03 (2013-02-20)

1173

14 RPR Boards

----End

Boards.
the Current Alarms.
----End

The EMR0 supports multiple Ethernet functions and features such as Layer 2 switching and
LCAS. Configure the functions according to actual requirements.
You can configure the following Ethernet functions for the EMR0 by using the U2000:
l
STP/RSTP
LCAS
LAG
Test Frame
IGMP Snooping

You can set parameters for the EMR0 by using the U2000.
You can set the following main parameters for the EMR0 by using the U2000:
l
Working mode
LCAS
Mapping protocol
Settings.

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14 RPR Boards
Troubleshooting
Table 14-24 lists the faults that occur on the EMR0 frequently and the troubleshooting methods.
Table 14-24 Methods used to troubleshoot the faults that occur on the EMR0 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



interrupted.
abnormal.
Packet loss

Packet Loss.
Interconnection
fault



fault occurs.
Replacing the Board

NOTE
replace the board.
For information on how to replace the EMR0, see Replacing an EOS Board.

14.2.13.1 Alarms of N2EMR0

AU_AIS
Issue 03 (2013-02-20)
AU_LOP
B3_EXC_VC3
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14 RPR Boards
B3_EXC_VC4
B3_SD_VC3
B3_SD_VC4
BD_STATUS
COMMUN_FAIL
ETH_LOS
FCS_ERR
FPGA_ABN
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
LAG_FAIL
LCAS_BAND_DECREASED
LCAS_FOPR
LCAS_FOPT
LCAS_PLCR
LCAS_PLCT
LCAS_TLCR
LCAS_TLCT
LOOP_ALM
LP_RDI_VC3
LP_REI_VC3
LP_SLM_VC3
LP_TIM_VC3
LP_UNEQ_VC3
LSR_NO_FITED
NO_BD_SOFT
RPR_DUPLICATE_MAC
RPR_ECHO_DLOC
RPR_ECHO_LOC
RPR_MISCONFIG
RPR_NB_INCONSIS
RPR_PM_INCONSIS
RPR_PS_CHANGE
RPR_STATIONS_EXCEED
RPR_SUM_A0_EXCEED
SLAVE_WORKING
SUBCARD_ABN
T_LOS
TU_AIS_VC3
TU_LOP_VC3
VCAT_LOA
VCAT_LOM_VC3
VCAT_LOM_VC4
LASER_MOD_ERR
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
ETH_NO_FLOW
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

14.2.14.1 Performance Events of N2EMR0

Table 14-25 SDH
Issue 03 (2013-02-20)
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS

1176

14 RPR Boards

DropEvent
UndersizePkts
OversizePkts
Fragments
Jabbers
Collisions
AlignmentErrors
FCSErrors
rprSpanErrorUnavailableSeconds
rprSpanErrorTooLongFrames
rprSpanErrorTooShortFrames
rprSpanErrorSelfSrcUcastFrames
rprSpanErrorPmdAbortFrames
rprSpanErrorBadAddrFrames
rprSpanErrorBadParityFrames
rprSpanErrorContainedFrames
rprSpanErrorBadDataFcsFrames
rprSpanErrorBadCtrlFcsFrames
rprSpanErrorErroredSeconds
rprSpanErrorSeverelyErroredSeconds

Packets Received
Length)(packets/s)

(packets/s)

(packets/s)

(packets/s)

(packets/s)
Jabbers(packets/s)
Collisions(times/s)
Packets Received(packets/
s)
Issue 03 (2013-02-20)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)
Packets Transmitted
(packets/s)

1177

14 RPR Boards

(packets/s)

(packets/s)
Multicast Packets
Broadcast Packets

(Byte/s)
Table 14-29 Statistics of RMON VCG performance (receive frame count at Span side)
rprSpanRxUcastClassAFrames(frames/s)
rprSpanRxUcastClassABytes(Byte/s)
rprSpanRxUcastClassBCirFrames(frames/s)
rprSpanRxUcastClassBCirBytes(Byte/s)
rprSpanRxUcastClassBEirFrames(frames/s)
rprSpanRxUcastClassBEirBytes(Byte/s)
rprSpanRxUcastClassCFrames(frames/s)
rprSpanRxUcastClassCBytes(Byte/s)
rprSpanRxMcastClassAFrames(frames/s)
rprSpanRxMcastClassABytes(Byte/s)
rprSpanRxMcastClassBCirFrames(frames/s)
rprSpanRxMcastClassBCirBytes(Byte/s)
rprSpanRxMcastClassBEirFrames(frames/s)
rprSpanRxMcastClassBEirBytes(Byte/s)
rprSpanRxMcastClassCFrames(frames/s)
rprSpanRxMcastClassCBytes(Byte/s)
Table 14-30 Statistics of RMON VCG performance (transmit frame count at Span side)
rprSpanTxUcastClassAFrames(frames/s)
rprSpanTxUcastClassABytes(Byte/s)
rprSpanTxUcastClassBCirFrames(frames/s)
rprSpanTxUcastClassBCirBytes(Byte/s)
rprSpanTxUcastClassBEirFrames(frames/s)
rprSpanTxUcastClassBEirBytes(Byte/s)
rprSpanTxUcastClassCFrames(frames/s)
rprSpanTxUcastClassCBytes(Byte/s)
rprSpanTxMcastClassAFrames(frames/s)
rprSpanTxMcastClassABytes(Byte/s)
rprSpanTxMcastClassBCirFrames(frames/s)
rprSpanTxMcastClassBCirBytes(Byte/s)
rprSpanTxMcastClassBEirFrames(frames/s)
rprSpanTxMcastClassBEirBytes(Byte/s)
rprSpanTxMcastClassCFrames(frames/s)
rprSpanTxMcastClassCBytes(Byte/s)
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14 RPR Boards
Table 14-31 Statistics of RMON VCG performance (count of control layer frames)
rprSpanTxCtrlFrames
(frames/s)
rprSpanTxOamEchoFrames
(frames/s)
rprSpanTxOamFlushFrames
(frames/s)
rprSpanTxOamOrgFrames
(frames/s)
rprSpanTxTopoAtdFrames
(frames/s)
rprSpanTxTopoChkSumFrames(frames/s)
rprSpanTxTopoTpFrames
(frames/s)
rprSpanRxCtrlFrames
(frames/s)
rprSpanRxOamEchoFrames
(frames/s)
rprSpanRxOamFlushFrames
(frames/s)
rprSpanRxOamOrgFrames
(frames/s)
rprSpanRxTopoAtdFrames
(frames/s)
rprSpanRxTopoChkSumFrames(frames/s)
rprSpanRxTopoTpFrames
(frames/s)
Table 14-32 Statistics of RMON VCG performance (frames received by Client)

rprClientTxUcastClassAFrames(frames/s)
rprClientTxUcastClassABytes(Byte/s)
rprClientTxUcastClassBCirFrames(frames/s)
rprClientTxUcastClassBCirBytes(Byte/s)
rprClientTxUcastClassBEirFrames(frames/s)
rprClientTxUcastClassBEirBytes(Byte/s)
rprClientTxUcastClassCFrames(frames/s)
rprClientTxUcastClassCBytes(Byte/s)
rprClientTxMcastClassAFrames(frames/s)
rprClientTxMcastClassABytes(Byte/s)
rprClientTxMcastClassBCirFrames(frames/s)
rprClientTxMcastClassBCirBytes(Byte/s)
rprClientTxMcastClassBEirFrames(frames/s)
rprClientTxMcastClassBEirBytes(Byte/s)
rprClientTxMcastClassCFrames(frames/s)
rprClientTxMcastClassCBytes(Byte/s)
rprClientTxBcastFrames
(frames/s)
Table 14-33 Statistics of RMON VCG performance (frames transmitted by client)
Issue 03 (2013-02-20)
rprClientRxUcastClassAFrames(frames/s)
rprClientRxUcastClassABytes(Byte/s)
rprClientRxUcastClassBCirFrames(frames/s)
rprClientRxUcastClassBCirBytes(Byte/s)
rprClientRxUcastClassBEirFrames(frames/s)
rprClientRxUcastClassBEirBytes(Byte/s)
rprClientRxUcastClassCFrames(frames/s)
rprClientRxUcastClassCBytes(Byte/s)
rprClientRxMcastClassAFrames(frames/s)
rprClientRxMcastClassABytes(Byte/s)
rprClientRxMcastClassBCirFrames(frames/s)
rprClientRxMcastClassBCirBytes(Byte/s)
rprClientRxMcastClassBEirFrames(frames/s)
rprClientRxMcastClassBEirBytes(Byte/s)
rprClientRxMcastClassCFrames(frames/s)

1179

rprClientRxMcastClassCBytes(Byte/s)
14 RPR Boards
rprClientRxBcastFrames
(frames/s)
Table 14-34 Statistics of RMON VCG performance (count of error frames)

(frames/s)
rprSpanErrorTooLongFrames(frames/s)
rprSpanErrorTooShortFrames(frames/s)
(frames/s)
(frames/s)
rprSpanErrorSelfSrcUcastFrames(frames/s)
rprSpanErrorPmdAbortFrames(frames/s)
rprSpanErrorBadAddrFrames(frames/s)
rprSpanErrorBadParityFrames(frames/s)
rprSpanErrorContainedFrames(frames/s)
rprSpanErrorBadDataFcsFrames(frames/s)
rprSpanErrorBadCtrlFcsFrames(frames/s)
(frames/s)
rprSpanErrorErroredSeconds(seconds/s)
rprSpanErrorSeverelyErroredSeconds(seconds/s)
rprSpanErrorUnavailableSeconds(seconds/s)

The technical specifications of the EMR0 include the parameters specified for optical interfaces,
consumption.

Table 14-35 lists the parameters specified for the optical interfaces of the EMR0.
Table 14-35 Parameters specified for the optical interfaces of the EMR0
Issue 03 (2013-02-20)
Parameter
Value
Type of optical
interface
1000BASE-ZX (80
km)
1000BASE-LX
(10 km)
1000BASE-SX (0.5
km)
Type of fiber
Single-mode LC
Single-mode LC
Multi-mode LC
Launched optical
power range (dBm)
-2 to 5
-9 to -3
-9.5 to -2.5
range (nm)
1500 to 1580
1270 to 1355
770 to 860
Minimum overload
(dBm)
-3
-3

1180

14 RPR Boards
Parameter
Value
(dBm)
-23
-20
-17
Minimum extinction
ratio (dB)
Maximum -20 dB
spectral width (nm)
Minimum side mode

30
Laser Safety Class


NOTE
specifications, and back-to-back specifications of the EMR0 board of the N2 version.
the case of overloading, latency specifications, and back-to-back specifications of the EMR0.
Tested
equipment 1
Tested
equipment 2
Port 1
Port 2
Data network
performance
analyzer
Table 14-36 and Table 14-37 list the throughput specifications of the EMR0. Table 14-38 and
Table 14-39 list the packet loss ratio in the case of overloading of the EMR0. Table 14-40 and
Table 14-41 list the latency specifications of the EMR0. Table 14-42 and Table 14-43 list the
back-to-back specifications of the EMR0.
Issue 03 (2013-02-20)

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14 RPR Boards
NOTE
are used.
The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the FE port, or EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.
Table 14-36 lists the throughput specifications of the EMR0 (eight VC-4s are bound on the FE
l
Number of pairs: 1
Mode: bidirectional
Table 14-36 Throughput specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame Size
(Byte)
Passed Rate
(%)
(01,06,05) to
(01,06,06) (pks/
sec)
(01,06,06) to
(01,06,05) (pks/
sec)
Total (pks/
sec)
64
100.00
148810
148810
297620
128
100.00
84459
84459
168918
256
100.00
45290
45290
90580
512
100.00
23496
23496
46992
1024
100.00
11973
11973
23946
1280
100.00
9615
9615
19230
1518
100.00
8127
8127
16254
Table 14-37 lists the throughput specifications of the EMR0 (eight VC-4s are bound on the GE
Issue 03 (2013-02-20)

1182

Number of pairs: 1
Mode: bidirectional
14 RPR Boards
Table 14-37 Throughput specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,04,01) (pks/
sec)
(01,04,01) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64
72.41
1077586
1077586
2155172
128
94.87
801282
801282
1602564
256
100.00
452899
452899
905798
512
100.00
234962
234962
469924
1024
100.00
119732
119732
239464
1280
100.00
96154
96154
192308
1518
100.00
81274
81274
162548
Table 14-38 lists the packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are
l
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Issue 03 (2013-02-20)

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14 RPR Boards
Table 14-38 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the FE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,06,05) to
(01,06,06) (%)
(01,06,06) to
(01,06,05) (%)
Average (%)
64
100.00
0.000
0.000
0.000
128
100.00
0.000
0.000
0.000
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000
Table 14-39 lists the packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are
l
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Table 14-39 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the GE port)
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,04,01) (%)
(01,04,01) to
(01,01,01) (%)
Average (%)
64
100.00
29.833
29.827
29.830
128
100.00
4.306
4.309
4.307
256
100.00
0.000
0.000
0.000
512
100.00
0.000
0.000
0.000
1024
100.00
0.000
0.000
0.000
1280
100.00
0.000
0.000
0.000
1518
100.00
0.000
0.000
0.000

1184

14 RPR Boards
Table 14-40 lists the latency specifications of the EMR0 (eight VC-4s are bound on the FE port).
l
forward mode.
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Table 14-40 Latency specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,06,05) to
(01,06,06) (us)CT (us)
Average
(CT) (us)
(01,06,05) to
(01,06,06)
(us)-S&F (us)
Average
(S&F) (us)
64
100.00
126.1
126.1
121.0
121.0
128
100.00
131.0
131.0
120.8
120.8
256
100.00
149.2
149.2
128.8
128.8
512
100.00
176.9
176.9
136.0
136.0
1024
100.00
237.0
237.0
155.1
155.1
1280
100.00
266.7
266.7
164.3
164.3
1518
100.00
289.3
289.3
167.9
167.9
Table 14-41 lists the latency specifications of the EMR0 (eight VC-4s are bound on the GE
l
Issue 03 (2013-02-20)
1185

14 RPR Boards
forward mode.
l
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Table 14-41 Latency specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,04,01) (us)CT (us)
Average
(CT) (us)
(01,01,01) to
(01,04,01)
(us)-S&F (us)
Average
(S&F) (us)
64
72.41
130.1
130.1
129.6
129.6
128
94.87
143.1
143.1
142.1
142.1
256
100.00
123.4
123.4
121.4
121.4
512
100.00
130.7
130.7
126.7
126.7
1024
100.00
154.4
154.4
146.3
146.3
1280
100.00
164.6
164.6
154.4
154.4
1518
100.00
174.4
174.4
162.3
162.3
Table 14-42 lists the back-to-back specifications of the EMR0 (eight VC-4s are bound on the
FE port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Issue 03 (2013-02-20)

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14 RPR Boards
Table 14-42 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,06,05) to
(01,06,06) Burst
Size (Number of
Frames)
(01,06,06) to
(01,06,05)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
297620
297620
595240
128
100.00
168918
168918
337836
256
100.00
90580
90580
181160
512
100.00
46992
46992
93984
1024
100.00
23946
23946
47892
1280
100.00
19230
19230
38460
1518
100.00
16254
16254
32508
Table 14-43 lists the back-to-back specifications of the EMR0 (eight VC-4s are bound on the
GE port). The values are obtained when the SmartApplication is set as follows:
l
Number of pairs: 1
Step rate: 10.00
Mode: bidirectional
Table 14-43 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the GE port)
Issue 03 (2013-02-20)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,04,01) Burst
Size (Number of
Frames)
(01,04,01) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64
100.00
3410
3410
6820
128
100.00
29054
29054
58108
256
100.00
905798
905798
1811596
512
100.00
469924
469924
939848
1024
100.00
239464
239464
478928
1280
100.00
192308
192308
384616

1187

14 RPR Boards
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,04,01) Burst
Size (Number of
Frames)
(01,04,01) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
1518
100.00
162548
162548
325096
The mechanical specifications of the EMR0 are as follows:
l
Weight (kg): 1.2
Power Consumption
The maximum power consumption of the EMR0 at room temperature (25C) is 50 W.
Issue 03 (2013-02-20)

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15
15 SAN/Video Boards
SAN/Video Boards
About This Chapter

The SAN boards are multi-service transparent transmission processing boards.
15.1 MST4
technical specifications of the MST4 (4-port multi-service transparent transmission board). This
topic also describes how to configure and commission the MST4.
15.2 VST4
technical specifications of the VST4 (4-port video-service transparent transmission board). This
topic also describes how to configure and commission the VST4.
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15.1 MST4
technical specifications of the MST4 (4-port multi-service transparent transmission board). This
topic also describes how to configure and commission the MST4.

The MST4 is available in one functional version, namely, N1.
15.1.2 Application
The MST4 is a multi-service transparent transmission board. The MST4 is used in remote
disaster recovery, remote backup and data centralization, and integration of storage resources.
The MST4 is used in the fields of the SAN services and video services. The MST4 can transmit/
receive the FC100/FICON, FC200, ESCON, and DVB-ASI services, and provides the FC100
and FC200 services with the distance extension function. Hence, the MST4 is applicable to the
long-distance transmission of the FC services on the SDH network. In addition, the MST4 meets
the transmission requirements of the storage network and extends the types of services supported
by the equipment. Figure 15-1 shows the networking and application of the SAN services.
Figure 15-1 Networking and application of the SAN services
NE1
MST4
NE2
MST4
FC Switch
FC Switch

The MST4 supports the access of multiple services, alarms, and other maintenance functions.
Table 15-1 provides the functions and features of the MST4.
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Table 15-1 Functions and features of the MST4

Function and
Feature
MST4
Basic functions
Provides four independent ports to transmit/receive multiple services.

Supports the transparent transmission of the SAN and Video services.
Connector type
LC
Optical module
type
SFP
Service types
l Supports FC100/FICON, FC200, ESCON, and DVB-ASI services.

Table 15-2 describes types and rates of the services.
l Transmits/Receives four-channel FC services (FC100/FICON and
FC200) at the same time, and the total bandwidth is less than 2.5 Gbit/
s.
l Supports the full-rate transmission of FC services (one-channel FC200
services or two-channel FC100 services).
l Transmits/Receives four-channel ESCON or DVB-ASI services, and
the total bandwidth is less than 2.5 Gbit/s.
Distance
extension
The first and second ports support the distance extension function on the
SDH side.
l FC100 services: 3000 km
l FC200 services: 1500 km
Maximum
uplink
bandwidth
2.5 Gbit/s
The backplane provides four 622 Mbit/s buses that are directly connected
to the cross-connect unit.
The MST4 can adapt to the bandwidth of the slot.
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Mapping
granularity
Supports the VC-4-Xc (X = 4, 8, or 16) granularity.
ESCON
services
Transmits/Receives four-channel ESCON services, and the total

bandwidth is less than 2.5 Gbit/s.
DVB-ASI
services
Transmits/Receives four-channel DVB-ASI services, and the total

bandwidth is less than 2.5 Gbit/s.
Encapsulation
format
Supports the GFP-T protocol, which complies with ITU-T G.7041.
Maintenance
features
Supports inloops and outloops on ports on the customer side, which can
be used to locate faults quickly.
Supports port-based RMON performance management.
Alarms and
performance
events


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Table 15-2 Service types and service rates supported by the MST4
Service Type
Rate
Remarks
FC100/FICON
1062.5 Mbit/s
SAN service
FC200
2125 Mbit/s
SAN service
ESCON
200 Mbit/s
SAN service
DVB-ASI
270 Mbit/s
Video service

The MST4 consists of the client-side access module, FC protocol processing module,
encapsulation and mapping module, logic and control module, clock module, and power module.
Figure 15-2 shows the functional block diagram of the MST4 by describing how to process
1xFC100 signals, 1xFC200 signals, 1xFICON signals, 1xDVB-ASI signals, or 1xESCON
signals.
Figure 15-2 Functional block diagram of the MST4
Backplane
FC100
FC200
FICON
DVB-ASI
ESCON
Clientside
access
module
FC1_
RCV
FC1_
SND
FC2
FC1_
SND
FC2
FC1_
RCV
FC protocol
processing module

100 MHz
125 MHz
135 MHz
212.5 MHz
622 MHz
Clock
module
Encapsulation
Decapsulation
Encapsulation and
mapping module
Communication
+3.3 V
Power
module
Interface
converting
module
Mapping
Power
module
Fuse
Fuse
Cross-connect unit A/B

SCC unit
Cross-connect unit
-48 V/-60 V
-48 V/-60 V
+3.3 V backup power
Client-Side Access Module

The client-side access module transmits/receives FC100, FC200, FICON, DVB-ASI, and
ESCON services. The client-side interface unit performs O/E conversion for services and
monitors the optical signals on the client side.
In the upstream direction, the client-side data interface (CDI) receives serial data signals accessed
through the SFP optical module. The serial data signals are then transmitted to the PCS functional
module for physical layer and 8B/10B line performance monitoring.
In the downstream direction, 8B/ 10B conversion is performed for the signals from FC. The
signals are then adapted into client reference clocks by inserting or discarding idle packets. After
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being converted from parallel signals into serial signals, the signals are transmitted through the
CDI interface to the optical module on the client side.
FC Protocol Processing Module

The FC protocol processing unit mainly extends the distance of FC service transmission. This
module supports the maximum transmission distance of 3000 km for 2xFC100 services or the
maximum transmission distance of 1500 km for 1xFC200 services.
The FC protocol processing unit performs FC1 layer and FC2 layer functions. The FC1 layer
functions include the following:
l
8B/10B conversion
Synchronous processing
Extraction of primitive signal and primitive sequence
The FC2 layer functions include the following:

l
Check and counting of all special frames
Modification of values of certain special frames (FLOG1, PLOG1, and ELP)
CRC check
Encapsulation and Mapping Module

The encapsulation and mapping module mainly performs the following functions:
l
Encapsulates and maps data.
Decapsulates and demaps data.
According to the direction of the signal flow, the functional modules inside the chip can be
classified into modules in the ingress direction and modules in the egress direction. In the ingress
direction, signals from the client side to the line side are processed. In the egress direction, signals
from the line side to the client side are processed.
Ingress direction
Through GFP encapsulation, 64B/65B conversion is performed for data bytes after decoding.
The data bytes are then mapped in compliance with the GFP protocol.
Egress direction
SDH data frames are received from the line-side interface module. After overheads are
processed, GFP data frames are extracted from SDH concatenated channels and are then
transmitted to the decapsulation module for decapsulation.

controller. This module is connected to external circuits through buses. The logic and control
module manages and configures other modules of the board. This module contains basic logic
units and performs the following functions:
l
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Clock Module
This module provides required reference clocks for boards. The clock frequency can be 100
MHz or 125 MHz.
Power Module
require.
15.1.5 Front Panel

The front panel of the MST4 has indicators, interfaces, and a bar code.

Figure 15-3 shows the appearance of the front panel of the MST4.
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Figure 15-3 Front panel of the MST4
MST4
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
MST4
Indicators
l
Interfaces
The front panel of the MST4 has four pair of optical interfaces. Table 15-3 describes the types
and usage of the optical interfaces of the MST4.
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Table 15-3 Optical interfaces of the MST4

Interface
Type of
Interface
Usage
IN1IN4
LC
Receives multi-service optical signals.
OUT1OUT4
LC
Transmits multi-service optical signals.

The MST4 does not have any jumpers or DIP switches that are used for board settings.
15.1.7 Valid Slots

The MST4 must be installed in a valid slot in the subrack. Otherwise, the MST4 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The MST4 can be installed in slots 18 and 1116 in the subrack.

l
When the cross-connect capacity is 200 Gbit/s, the MST4 can be installed in slots 18 and
1116. When the MST4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the MST4 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
15.1.8 Feature Code

The feature code of the MST4 indicates the type of supported services, type of optical interface,
and transmission distance.
Table 15-4 provides the relationship between the feature code of the MST4, the type of supported
services, type of optical interface, and transmission distance.
Table 15-4 Relationship between the feature code of the MST4, the type of supported services,
type of optical interface, and transmission distance
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Board
Feature
Code
Type of Supported Services

(Type of Optical Interface)
Transmission
Distance
SSN1MST410
10
2xFC (SM)
2 km
SSN1MST411
11
2xFC (SM)
15 km
SSN1MST412
12
2xFC (MM)
0.5 km
SSN1MST413
13
4xESCON/DVB-ASI (SM)
15 km

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Board
Feature
Code
Type of Supported Services

(Type of Optical Interface)
Transmission
Distance
SSN1MST414
14
4xESCON/DVB-ASI (MM)
2 km
SSN1MST415
15
1xFC2 (MM)
ESCON/DVB-ASI (MM)
SSN1MST416
16
1xFC2 (MM)
ESCON/DVB-ASI (SM)
SSN1MST417
SSN1MST418
17
18
1xFC (SM)
2 km
2xESCON/DVB-ASI (SM)
1xFC (SM)
2 km
2xESCON/DVB-ASI (MM)


matches the board.
is correct.
----End

Step 2 Required: Configure services. For details, see Configuring the SAN Service.
----End
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15 SAN/Video Boards

Step 1 Required: Test the SAN service channel. For details, see 28.8 Testing the SAN Service
Channel.
----End

Boards.
Step 2 Required: Query the alarms of the board. Modify the connections or configurations of the board
according to the alarms until the alarms are cleared. For the method for querying the alarms of
a board, see Viewing the Current Alarms.
----End

You can set parameters for the MST4 by using the U2000.
You can set the following parameters for the MST4 by using the U2000:
l
J1 byte
C2 byte

Troubleshooting
Table 15-5 lists the faults that occur on the MST4 frequently and the troubleshooting methods.
Table 15-5 Methods used to troubleshoot the faults that occur on the MST4 frequently
Fault Symptom
Common Fault Cause
Service
interruption


Interruptions.

Transient service
interruption



abnormal.
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Fault Symptom
Common Fault Cause
Packet loss

Packet Loss.
Interconnection
fault

occurs on a single service port.


Replacing the Board

NOTE
replace the board.
For information on how to replace the MST4, see Replacing an SAN/Video Board.

15.1.12.1 Alarms of N1MST4

AU_AIS
AU_CMM
AU_LOP
B3_EXC
B3_SD
BD_STATUS
BDID_ERROR
COMMUN_FAIL
HARD_BAD
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IN_PWR_ABN
LASER_MOD_ERR
LOOP_ALM
LSR_COOL_ALM
LSR_NO_FITED
LSR_WILL_DIE
NO_BD_SOFT
NO_LSR_PARA_FILE
PLL_FAIL
POWER_ABNORMAL
R_LOC
R_LOS
TEM_LA
T_LOSEX
TEM_HA
PATCHFILE_NOTEXIST
TF
TR_LOC
PATCH_NOT_CONFIRM
PATCH_ERR
SPARE_PATH_ALM
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE
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15.1.13.1 Performance Events of N1MST4

Table 15-6 SDH
AUPJCHIGH
AUPJCLOW
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPSES
HPUAS
OSPICCVCUR
OSPICCVMAX
OSPICCVMIN
OSPITMPCUR
OSPITMPMAX
OSPITMPMIN
RPLCUR
RPLMAX
RPLMIN
TLBCUR
TLBMAX
TLBMIN
TPLCUR
TPLMAX
TPLMIN
Table 15-7 FC
WSys_los_cnt
Client_Invld_Words
Client_Crc_Err
LinkRst_Cnt
Client_RxFrmCnt_C1
Client_RxFrmCnt_C2
Client_RxFrmCnt_C3
Client_RxFrmCnt_C4
Client_RxFrmCnt_Cf
Client_RxFrmCnt_Sum
Client_TxFrmCnt_C1
Client_TxFrmCnt_C2
Client_TxFrmCnt_C3
Client_TxFrmCnt_C4
Client_TxFrmCnt_Cf
Client_TxFrmCnt_Sum
Client_RxByteCnt_sum
Client_TxByteCnt_sum
Client_unsupos_cnt

The specifications of the MST4 include the parameters specified for optical interfaces, laser
safety class, dimensions, weight, and power consumption.

The optical interfaces of the MST4 can use several types of optical modules. Table 15-8 lists
the parameters specified for the optical interfaces of the MST4.
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Table 15-8 Parameters specified for the optical interfaces of the MST4
Parameter
Value
Service type
ESCON/DVB-ASI
FC200/FC100/FICON
Service rate
l ESCON: 200 Mbit/s
l FC200: 2125 Mbit/s
l DVB-ASI: 270
Mbit/s
l FC100/FICON: 1062.5 Mbit/s
Optical interface type
X3.296/(DVB-ASI)
EN50083-9
200-M5-SN-I
200-SM-LC-I
Part number of optical

module
34060277
34060287
34060325
34060288
34060278
Fiber type
Singlemode LC
Multimode LC
Multimode LC
Singlemode LC
Singlemode LC
range (nm)
1310
850
1310
(km)
15
0.5
15
Maximum launched
optical power (dBm)
-8
-14
-2.5
-3
Minimum launched
optical power (dBm)
-15
-19
-9.5
-10
-5
(dBm)
-31
-30
-17
-21
Minimum overload
(dBm)
-8
-14
-3
Laser Safety Class

The mechanical specifications of the MST4 are as follows:
l
Weight (kg): 0.9
Power Consumption
The maximum power consumption of the MST4 at room temperature (25C) is 26 W.
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15.2 VST4
technical specifications of the VST4 (4-port video-service transparent transmission board). This
topic also describes how to configure and commission the VST4.

The VST4 is available in one functional version, namely, N1.
15.2.2 Application
The VST4 is a transparent transmission board used for receiving/transmitting various types of
video services.
The VST4 can transmit/receive DVB-ASI, SD-SDI, and HD-SDI services. Figure 15-4 shows
the networking and application of the VST4.
Figure 15-4 Networking and application of the VST4
NE1
NE2
VST4
VST4
SDI/DVB-ASI
Switch
SDI/DVB-ASI
Switch

The VST4 receives/transmits video services, alarms, and other maintenance functions.
Table 15-9 provides the functions and features of the VST4.
Table 15-9 Functions and features of the VST4
Issue 03 (2013-02-20)
Function and
Feature
VST4
Basic functions
Provides four independent ports to transmit/receive services; supports the

transparent transmission of four-channel video services.
Interface type
SMB (SMB interfaces can be converted into BNC interfaces by means of

transit cables.)
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Function and
Feature
VST4
Service types
Supports DVB-ASI, SD-SDI, and HD-SDI services. Table 15-10

describes types and rates of the services.
Maximum
upstream
bandwidth
l When a VST4 is installed in any slot of slots 1-4 and 15-16, the
maximum upstream bandwidth is 5 Gbit/s. The VST4 can adapt to the
bandwidth of the slot.
l When a VST4 is installed in any slot of slots 5-8 and 11-14, the
maximum upstream bandwidth is 10 Gbit/s. The VST4 can adapt to the
Mapping
granularity
Supports the VC-4-Xc (X = 4 or 16) granularity.
DVB-ASI
Transmits/Receives four-channel DVB-ASI services.
SD-SDI
Transmits/Receives four-channel SD-SDI services.
HD-SDI
l When a VST4 is installed in any slot of slots 1-4 and 15-16, it transmits/
receives two-channel HD-SDI services. The VST4 can adapt to the
l When a VST4 is installed in any slot of slots 5-8 and 11-14, it transmits/
receives four-channel HD-SDI services. The VST4 can adapt to the
Encapsulation
format
Supports the GFP protocol, which complies with ITU-T G.7041.
Maintenance
features
Supports inloops and outloops on electrical ports for locating faults

quickly.
Supports port-based RMON performance management.
Alarms and
performance
events

Table 15-10 Service types and service rates supported by the VST4
Service Type
Rate
Remarks
DVB-ASI
270 Mbit/s
Video service
SD-SDI
270 Mbit/s
Video service
HD-SDI
1.485 Gbit/s
Video service

The VST4 consists of the client-side access module, encapsulation and mapping module, logic
and control module, clock module, and power module.
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Figure 15-5 shows the functional block diagram of the VST4 with the processing of 1xSD-SDI
signal, 1xHD-SDI signal, or 1xDVB-ASI signal.
Figure 15-5 Functional block diagram of the VST4
Backplane
Encaps
ulation
SD- SDI
HD- SDI
DVB- ASI
Clientside
access
module
Bus
converting
module
Mapping
Decaps
ulation

Encapsulation and
mapping module
Communication
66 MHz
100 MHz
155 MHz
SCC unit
Clock
module
+3.3V
Power
module
Power
module
Fuse
- 48 V/- 60 V
- 48V/- 60V
Fuse
+3.3 V backup power
Client-Side Access Module

The client-side access module transmits/receives SD-SDI, HD-SDI, and DVB-ASI services. The
client-side interface unit processes input/output electrical signals.
In the upstream direction, the client-side access module receives serial data signals received
through the SMB interface. The serial data signals are then transmitted to the encapsulation and
mapping module and finally to the backplane through the bus conversion module.
In the downstream direction, bus conversion is performed for the signals from the backplane.
The signals are then transmitted to the encapsulation and mapping module. After being
decapsulated and demapped, the signals are transmitted to the client-side access module.
Encapsulation and Mapping Module

The encapsulation and mapping module mainly performs the following functions: encapsulating/
mapping data, decapsulating/demapping data, processing LCAS and SDH/SONET overheads,
converging services, and encapsulating services.

controller. This module is connected to external circuits through buses. The logic and control
module manages and configures other modules of the board. This module contains basic logic
units and performs the following functions:
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Writes into and reads from the register.
Clock Module
This module provides required reference clocks for the board.
Power Module
This module converts the -48 V/-60 V power supply into the DC voltages that the modules of
the board require.
15.2.5 Front Panel

The front panel of the VST4 has indicators, interfaces, and a bar code.

Figure 15-6 shows the appearance of the front panel of the VST4.
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Figure 15-6 Front panel of the VST4

VST4
STAT
ACT
PROG
SRV
OUT1
IN1
OUT2
IN2
OUT3
IN3
OUT4
IN4
VST4
Indicators
l
Board hardware status indicator (STAT) - two colors (red and green)
Service activation status indicator (ACT) - one color (green)
Board software status indicator (PROG) - two colors (red and green)
Service alarm indicator (SRV) - three colors (red, green, and yellow)
For the meanings of indicator states, see 24 Indicators.
Interfaces
The front panel of the VST4 has four electrical interfaces. Table 15-11 describes the types and
usage of the electrical interfaces of the VST4.
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Table 15-11 Electrical interfaces of the VST4

Interface
Type of Interface
Usage
IN1-IN4
SMB (BNC
interfaces can also
be provided after
conversion cables
are connected to the
SMB interfaces.)
75-ohm interfaces that are used to receive electrical

signals.
OUT1-OUT4
SMB (BNC
interfaces can also
be provided after
conversion cables
are connected to the
SMB interfaces.)
75-ohm interfaces that are used to transmits

electrical signals.

The VST4 does not have any jumpers or DIP switches that are used for board settings.
15.2.7 Valid Slots

The VST4 must be installed in a valid slot in the subrack. Otherwise, the VST4 cannot work
properly.
The VST4 can be installed in slots 1-8 and 11-16. When the VST4 is installed in slots 1-4, 15,
and 16, the bandwidth is 5 Gbit/s. When the VST4 is installed in slots 5-8 and 11-14, the
bandwidth is 10 Gbit/s.
15.2.8 Feature Code

VST4 boards do not have feature codes.
15.2.9 Configuring and Commissioning a Board

tasks need to be performed: checking the board hardware, configuring the board, commissioning
the board, and checking the operation of the board.

matches the board.
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15 SAN/Video Boards
is correct.
----End

Step 1 Required: Add a logical board. For details, see Adding Boards.
Step 2 Required: Configure services. For details, see Configuring Video Services.
----End

Step 1 Required: Test SDI service channels. For details, see 28.9 Testing the SDI Service Channel.
----End

Step 1 Required: Check the status of the indicators on the front panel of the board to check whether
the board starts working properly. If all the indicators are on and green, the board operates
properly. For the meanings of the status of the indicators, see 24.2 Alarm Indicators on the
Boards.
Step 2 Required: Query the board alarms. Modify the connections or configurations of the board
according to the alarms until the alarms are cleared. For the method of querying the alarms of a
board, see Viewing the Current Alarms.
----End

You can set parameters for the VST4 by using the U2000.
You can set the following parameters for the VST4 by using the U2000:
l
J1 byte
C2 byte

Troubleshooting
Table 15-12 lists the faults that occur on the VST4 frequently and the troubleshooting methods.
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Table 15-12 Methods used to troubleshoot the faults that occur on the VST4 frequently
Fault Symptom
Common Fault Cause
Service
interruption
The services on a VCTRUNK port

are interrupted.

Interruptions.
Transient service
interruption



abnormal.
Packet loss

Packet Loss.
Interconnection
fault
The interconnection fault occurs on

a single service port.

Replacing the Board

NOTE
replace the board.
For information on how to replace the VST4, see Replacing an SAN/Video Board.

15.2.12.1 Alarms of N1VST4
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BD_STATUS
COMMUN_FAIL
R_LOS
R_LOC
AU_AIS
AU_LOP
HP_TIM
HP_SLM
HP_UNEQ
HP_RDI
HP_REI
B3_EXC
B3_SD
AU_CMM
LOOP_ALM
NO_BD_SOFT
TR_LOC
T_LOSEX
SPARE_PATH_ALM
BDID_ERROR
PLL_FAIL
HARD_BAD
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
WRG_BD_TYPE
POWER_ABNORMAL
TEMP_OVER
TEST_STATUS

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15.2.13.1 Performance Events of N1VST4

AUPJCHIGH
AUPJCLOW
HPBBE
HPES
HPSES
HPUAS
HPCSES
HPFEBBE
HPFEES
HPFESES
HPFECSES
XCSTMPMAX
XCSTMPMIN
XCSTMPCUR

The technical specifications of the VST4 include the parameters specified for electrical

Table 15-13 lists the parameters specified for the electrical interfaces of the VST4.
Table 15-13 Parameters specified for the electrical interfaces of the VST4
Parameter
Value
Rate
270 Mbit/s
1.485 Gbit/s
270 Mbit/s
Code type
NRZI
NRZI
MPEG-2
Interface type
SD-SDI
HD-SDI
DVB-ASI
Connector
SMB (A BNC connector is available by connecting a

conversion cable to the SMB connector.)
Transmission distance (m)
100
100
100
Interface standard compliance
SMPTE
259M
SMPTE 292M
EN 50083-9
The mechanical specifications of the VST4 are:
l
Dimensions (H x W x D): 254.1 mm x 25.4 mm x 220 mm
Weight: 0.8 kg
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Power Consumption
The maximum power consumption of the VST4 at room temperature (25C) is 37 W.
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16
16 Microwave Boards
Microwave Boards
About This Chapter

The microwave boards include the microwave intermediate frequency (IF) board IFSD1 and
microwave power board RPWR.
16.1 IFSD1
technical specifications of the IFSD1 (dual-port IF board). This topic also describes how to
configure and commission the IFSD1.
16.2 RPWR
technical specifications of the RPWR (6-channel ODU power board). This topic also describes
how to configure and commission the RPWR.
16.3 ODU
When the microwave board is used, it needs to work with the microwave outdoor unit (ODU).
The ODU types supported by the equipment are standard power (SP) and high power (HP).
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16.1 IFSD1
technical specifications of the IFSD1 (dual-port IF board). This topic also describes how to
configure and commission the IFSD1.

The IFSD1 is available in one functional version, namely, N1.
16.1.2 Application
Working as the microwave module on the OptiX OSN equipment, the IFSD1 can receive and
transmit two IF signals and work with the OptiX RTN 600 to transmit microwave signals.
The OptiX OSN equipment can be configured with multiple IFSD1 boards according to the
service configuration so that the microwave services in multiple directions can be connected.
Figure 16-1 shows the position of the OptiX OSN equipment that is configured with the IFSD1
in the network.
Figure 16-1 Position of the OptiX OSN equipment that is configured with the IFSD1 in the
network
SDH/PDH
IFSD1: 11-13
STM-64/STM-16/STM-4 ring
SDH/PDH
SDH/PDH
OptiX OSN
equipment
OptiX optical
transmission product
OptiX RTN 600

The IFSD1 transmits and receives two IF signals, provides the management channel to the ODU,
and supplies the 48 V power to the ODU.
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Table 16-1 provides the functions and features of the IFSD1.

Table 16-1 Functions and features of the IFSD1
Function and
Feature
IFSD1
Basic functions
Supports 2xSTM-1 SDH or PDH IF signals and management control

signals between the IDU and ODU, and supplies power to the ODU.
IF processing
l Maps PDH signals and SDH signals into IF signals.

l Codes and decodes IF signals.
l Modulates and demodulates IF signals.
l Modulates and demodulates ODU control signals.
l Combines and splits service signals, ODU control signals, and
48 V power supplies.
Microwave features
l Supports the software programmable radio (SPR) function. That

is, you can set the microwave capacity and modulation scheme by
using the software.
l Supports the microwave frame that is based on the tributary and
STM-1, and hence supports the interconnection with the OptiX
OSN products or the OptiX RTN 600 products that support this
type of microwave frame through the air interface.
l Supports the automatic transmit power control (ATPC) function.
Service processing
Supports the configuration of VC-12, VC-3, and VC-4 services.
Overhead processing
l Processes the section overheads of the STM-1 IF signals.

overheads of the STM-1 IF signals.
l Supports the setting and query of the J1 and C2 bytes.
Pointer processing
l Processes AU pointers of SDH IF signals.

l Processes TU pointers of PDH IF signals.
Alarms and
performance events

Protection schemes
Supports the following protection schemes:

l 1+1 HSB
l 1+1 FD
l 1+1 SD
l N+1 Protection
l Microwave lower order SNCP
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Function and
Feature
IFSD1
Maintenance
features
l Supports loopbacks on VC-4 paths.

l Supports loopbacks on IF ports.
l Supports the detection of the board temperature.
affect the services.
l Supports the query of the version information of the board.
l Supports the detection of the hardware fault.
l Supports the PRBS function.

The IFSD1 consists of the combiner interface module, IF processing module, MODEM module,
FPGA module, rate converting module, and communication and control module.
This topic considers the processing of one IF signal that is sent from the ODU as an example to
describe the working principle and signal flow of the IFSD1.
Figure 16-2 shows the functional block diagram of the IFSD1.
Figure 16-2 Functional block diagram of the IFSD1
Backplane
ODU
IF Combiner
interface
module
IF
processing
module
MODEM
module
SMOD
EM
M
U
X/
D
E
M
U
X
Rate
converting
FPGA module
Overhead
processing
Overhead
s related
to HSM
Cross-connect
unit
Board in the paired slot

SCC
-48 V
Clock
module
Power
module
Service bus
Overhead bus
Communication and
control module
IF signal
Control bus
SCC
SCC
ODU control signal

Communication bus
-48 V power supply
Signal Processing Flow in the Transmit Direction

After the service signals are processed by the rate converting module, the signals from the crossconnect unit are sent to the MUX/DEMUX module of the FPGA module where the signals are
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scrambled and the overhead byte and pointer are set. Then, the signals are sent to the MODEM
module for FEC coding and digital modulation and to the IF processing module for D/A
converting and analog modulation. The ODU control signals sent from the logic and control
module are sent to the combiner interface module after being modulated by the SMODEM
module. Finally, the IF signals, ODU control signals, and 48 V power supplies are combined
at the combiner interface module and then sent to the ODU over IF cables.
Signal Processing Flow in the Receive Direction

The combiner interface module divides the ODU control signals and IF signals from the received
IF signals. The ODU control signals are sent to the SMODEM module for demodulation and
then to the logic and control module. The IF signals are sent to the IF processing module for
filtering and A/D converting and then to the FPGA module for demultiplexing and overhead
processing. Then, the signals are sent to the rate converting module. Finally, the signals are sent
to the cross-connect unit.
Auxiliary Modules
The auxiliary modules include the logic and control module, clock module, and power module.
The functions of these modules are as follows:
l
This module realizes the alarm display, performance monitoring, and communication with the
system control and communication board and the other boards through the Ethernet interface.
In addition, this module provides two pairs of RS485 data buses and can provide quick response
in real time. This module supports the in-service loading of programs.
l
Clock module
Extracts the clock from the received signal and sends the 8 KHz clock to the clock unit.
Supports the 38 MHz system clock in the transmit direction.
Power module
Provides two 48 V power input interfaces and supports the DC power supply whose
input voltage ranges from 38.4 V to 72 V.
Provides DC power supplies for all the modules on the IFSD1.
Monitors all the power supplies for the IFSD1 and reports alarms in the case of a board
voltage abnormality.
Provides one 48 V DC power supply for the ODU.
16.1.5 Front Panel

The front panel of the IFSD1 has indicators, interfaces, power switches, and labels.

Figure 16-3 shows the appearance of the front panel of the IFSD1.
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Figure 16-3 Front panel of the IFSD1

IFSD1
STAT
PROG
SRV
LINK1
ODU1
ACT1
LINK2
ODU2
ACT2
!
WARNING
-48V OUTPUT
TURNOFFPOWERBEFORE
DISCONNECTING IF CABLE
IF1
ODU-PWR1
I
O
PWR1
PWR2
ODU-PWR2
I
O
IF2
IFSD1
Indicators
l
Active/Standby state indicator (ACT1) one color (green)
Active/Standby state indicator (ACT2) one color (green)
Connection status indicator 1 (LINK1) two colors (red and green)
Connection status indicator 2 (LINK2) two colors (red and green)
Working indicator of ODU 1 (ODU1) two colors (red and green)
Working indicator of ODU 2 (ODU2) two colors (red and green)
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Interfaces
Table 16-2 Interfaces of the IFSD1
Interface
Description
Usage
IF1
IF port 1
IF port 1 refers to the IF interface between the

IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single type-N IF
cable is used for connection.
IF2
IF port 2
IF port 2 refers to the IF interface between the

IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single N-Type IF
cable is used for connection.
PWR1
Power interface 1
The power supply provided by the RPWR is

transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum throughcurrent of 1.76 A for the ODU. The PWR1
interface must be connected to the dedicated
power cable that is delivered with the
equipment.
PWR2
Power interface 2
The power supply provided by the RPWR is

transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum throughcurrent of 1.76 A for the ODU. The PWR2
interface must be connected to the dedicated
power cable that is delivered with the
equipment.
ODU-PWR1a
ODU power switch 1
Turns on or turns off the 48 V DC power

supply for the ODU.
ODU-PWR2a
ODU power switch 2
Turns on or turns off the 48 V DC power

supply for the ODU.
CAUTION
a: The ODU-PWR1 and ODU-PWR2 switches are equipped with lockup devices. To move the
switch, you need to pull the switch lever partially. When the switch is set to "O", it indicates that
the circuit is open. When the switch is set to "I", it indicates that the circuit is closed.
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Labels
The front label has a high temperature warning label and an operation warning label.
The high temperature warning label indicates that the board surface temperature may exceed
70C when the ambient temperature is higher than 55C. In this case, you need to wear protective
gloves before touching the board.
The operation warning label indicates that the ODU power switch must be turned off before the
IF cable is removed.

The IFSD1 does not have any jumpers or DIP switches that are used for board settings.
16.1.7 Valid Slots

The IFSD1 must be installed in a valid slot in the subrack. Otherwise, the IFSD1 cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the IFSD1 are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the IFSD1 can be installed in slots 18 and
1117.
16.1.8 Feature Code

The IFSD1 does not have the feature code.

The IFSD1 supports the 1+1 HSB/FD/SD protection and N+1 protection.


Step 1 Required: Check the appearance of the board. Ensure that the board is not damaged.
l The front panel and the steel plate in the rear must not be deformed.
l There must be no unexpected sound when you shake the board gently.
l The screws on the daughter board must be tightened.
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l The power switch of the ODU must be intact and be in the OFF position.
is correct.
Step 5 Required: Check whether the cable between the IF board and the power board (N1RPWR) and
the cable between the IF board and the ODU are properly connected. In addition, check whether
the accessories such as antennas are installed.
Step 6 Required: Switch on the ODU and check whether the ODU starts to work.
----End

Step 1 Required: Add a logical board for the IF board and ODU. For details, see Adding Boards.
Step 2 Required: Set the interface parameters of the ODU. For details, see Configuring Parameters of
ODU Interfaces.
Step 3 Required: Configure the IF/ODU information. For details, see Configuring the IF/ODU
Information of a Radio Link.
Step 4 Required: Set the parameters of the IF interface. For details, see Setting the Parameters of the
IF Interface.
Step 5 Required: Configure the SDH or PDH services. For details, see Configuring the SDH/PDH
Services (on a Per-NE Basis).
Step 6 Required: Create the IF protection. For details, see Creating IF 1+1 Protection or Creating an
N+1 Protection Group (perform this operation according to actual requirements).
----End

Step 1 Required: Query the current alarms of the IF board and ODU. For details, see Querying Current
Alarms for the IF Board and ODU.
Step 2 Required: Align the antennas. For details, see Aligning the Antennas.
Step 3 Required: Log in to the NE on the opposite end. For details, see Logging In to the Opposite
NE.
Step 4 Required: Query the receive power of the ODU. For details, see Aligning the Single-Polarized
Antennas.
Step 5 Optional: Test the 24hour BER. For details, see Testing the Point-to-Point BER.
Step 6 Optional: Test the IF protection switching. For details, see Testing the protection switch.
----End
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Boards.
the Current Alarms.
----End

You can set parameters for the IFSD1 by using the U2000 LCT and U2000.
You can set the following parameters for the IFSD1 by using the network management system:
l
Radio work mode
Radio link ID
ATPC attributes
J1 byte
The J1 byte is applicable to SDH microwave only. The other parameters are applicable to both
PDH and SDH microwaves.
Radio Work Mode

Table 16-3 Radio work modes
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Service Capacity
Modulation Scheme
Channel Spacing (MHz)
4xE1
QPSK
4xE1
16QAM
3.5
8xE1
QPSK
14 (13.75)
8xE1
16QAM
16xE1
QPSK
28 (27.5)
16xE1
16QAM
14 (13.75)
22xE1
32QAM
14 (13.75)
26xE1
64QAM
14 (13.75)
35xE1
16QAM
28 (27.5)
44xE1
32QAM
28 (27.5)
53xE1
64QAM
28 (27.5)
STM-1
128QAM
28 (27.5)

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NOTE
l The channel spacings 13.75 MHz and 27.5 MHz are applied to the 18 GHz frequency band.
l The channel spacings provided in the table are the minimum channel spacings supported by the OptiX OSN
equipment series. The channel spacings equal to or larger than the values are also supported.
Radio Link ID
The radio link ID is an identification of the radio link. The transmit end sends the radio link ID
byte continuously so that the receive end can learn that the transmit end is in a constant
connection state. If the receive end detects a mismatch of the radio link ID, the receive end inserts
the all "1"s signal and the corresponding IF port reports the MW_LIM alarm.
ATPC Attributes
The ATPC is a technology that automatically adjusts the transmit power of the transmitter
according to the attenuation of the received signal level (RSL) at the receive end. The ATPC
attributes include the following parameters:
l
ATPC enable status

This parameter specifies whether the NE enables the ATPC function to control the transmit
power of the transmitter. By default, the ATPC function is disabled.
ATPC upper threshold

When the RSL at the receive end is higher than the set value of this parameter, the receive
end notifies the transmit end to reduce the transmit power by using the ATPC overhead in
the microwave frame. The decrement depends on the value of the ATPC adjustment
parameter.
ATPC lower threshold

When the RSL at the receive end is lower than the set value of this parameter, the receive
end notifies the transmit end to increase the transmit power by using the ATPC overhead
in the microwave frame. The increment depends on the value of the ATPC adjustment
parameter.
ATPC adjustment
This parameter specifies the decrement/increment of an ATPC adjustment.
NOTE
The ATPC adjustment cannot exceed the range of the ODU transmit power.
J1 Byte
The IFSD1 board supports four byte modes, which are as follows:
l
Single-byte mode
16-byte mode with CRC
16-byte mode without CRC
64-byte mode
By default, the IFSD1 board does not monitor the received J1 byte. That is, the J1 byte to be
received is set to the disabled mode. The J1 byte to be sent is a 16-byte string with CRC. The
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first byte is created automatically and the following 15 bytes are the ASCII codes "HuaWei SBS
". The last five characters of the string are blank spaces.

Troubleshooting
For the faults that occur on the IFSD1 frequently, the common fault causes, and the
troubleshooting methods, see Troubleshooting Microwave Links.
Replacing the Board

NOTE
replace the board.
For information on how to replace the IFSD1, see Replacing the IF Board.

16.1.13.1 Alarms of N1IFSD1
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AU_AIS
AU_LOP
B1_EXC
B1_SD
B2_EXC
B2_SD
B3_EXC
B3_SD
BDID_ERROR
BD_STATUS
CHIP_ABN
COMMUN_FAIL
FSELECT_STG
HARD_BAD
HP_CROSSTR
HP_LOM
HP_RDI
HP_REI
HP_SLM
HP_TIM
HP_UNEQ
IF_CABLE_OPEN
LOOP_ALM
MS_AIS
MS_CROSSTR
MS_RDI
MS_REI
MSAD_CROSSTR
MW_BER_EXC
MW_BER_SD
MW_FEC_UNCOR
MW_LIM
MW_LOF
MW_RDI
NO_BD_SOFT
PLL_FAIL
PATCH_ERR
PATCH_NOT_CONFIRM
PATCHFILE_NOTEXIST
R_LOC
R_LOF
R_LOS

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RS_CROSSTR
SLAVE_WORKING
TEMP_ALARM
TR_LOC
VOLT_LOS
POWER_ABNORMAL
SWDL_PKG_NOBDSOFT
WRG_BD_TYPE

16.1.14.1 Performance Events of N1IFSD1

AUPJCHIGH
AUPJCLOW
AUPJCNEW
FEC_BEF_COR_ER
FEC_COR_BYTE_CNT
HPBBE
HPCSES
HPES
HPFEBBE
HPFECSES
HPFEES
HPFESES
HPFEUAS
HPSES
HPUAS
MSBBE
MSCSES
MSES
MSFEBBE
MSFECSES
MSFEES
MSFESES
MSFEUAS
MSSES
MSUAS
RSBBE
RSCSES
RSES
RSOFS
RSOOF
RSSES
RSUAS
XCSTMPMAX
XCSTMPMIN
XCSTMPCUR

The technical specifications of the IFSD1 include the IF performance, baseband signal
processing performance, board mechanical specifications, and power consumption.
Microwave Capacity
One IFSD1 board can access microwave signals in both directions. The capacity of microwave
signals in each direction depends on the radio work mode of these microwave signals. For details
about the radio work modes, see 16.1.11 Parameter Settings.
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IF Performance
Table 16-4 IF performance
Item
Performance
IF signal
Transmit frequency of the IF
board (MHz)
350
Receive frequency of the IF

board (MHz)
140
Impedance (ohm)
50
ODU O&M signal

Modulation scheme
ASK
Transmit frequency of the IF

board (MHz)
5.5
Receive frequency of the IF

board (MHz)
10
Baseband Signal Processing Performance of the Modem

Table 16-5 Baseband signal processing performance of the modem
Item
Performance
Coding mode
l Uses Reed-Solomon (RS) coding for PDH signals.

l Uses Trellis-Coded Modulation (TCM) and RS two-level coding
for SDH signals.
Adaptive timedomain equalizer for

baseband signals
Consists of the feed forward equalizer filter and decision feedback

equalizer.
Mechanical Specification
The mechanical specifications of the IFSD1 are as follows:
l
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the IFSD1 at room temperature (25C) is 24 W.
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16.2 RPWR
technical specifications of the RPWR (6-channel ODU power board). This topic also describes
how to configure and commission the RPWR.

The RPWR is available in one functional version, namely, N1.
16.2.2 Application
The RPWR is a power access board and is not related to the service features. The RPWR,
however, must be configured if the product needs to provide the IF feature. The RPWR receives
two 38.4 V to 72 V DC power supplies, provides the IFSD1 with six independent 48 V power
supplies, and finally feeds power to the ODU after the IFSD1 processes the six 48 V power
supplies.
Figure 16-4 shows the position of the OptiX OSN equipment that is configured with the RPWR
in the network.
Figure 16-4 Position of the OptiX OSN equipment that is configured with the RPWR in the
network
SDH/PDH
RPWR: 11-13
STM-64/STM-16/STM-4 ring
SDH/PDH
SDH/PDH
OptiX OSN
equipment
OptiX optical
transmission product
OptiX RTN 600

The RPWR receives two 48 V/60 V DC power supplies and supplies the 48 V power to six
ODUs.
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Table 16-6 provides the functions and features of the RPWR.

Table 16-6 Functions and features of the RPWR
Function and
Feature
RPWR
Input power
l Provides the 48 V power supply after converting the 48 V DC

power supply, which is realized through the internal power module.
l Receives the 48 V/60 V DC power system. The voltage of the two
input DC power supplies ranges from 38.4 V to 72 V.
Combiner function
Combines the power supplies.
Protection against
lightning, surge,
and short-circuit
Provides protection against lightning, surge, and short-circuit.
Protection function
In the case of the DC power interface, the differential-mode voltage

must be more than 2 kV and the common-mode voltage must be more
than 4 kV.
Filtering function
Provides the filtering for the power interface and has the structural
shielding that improves the electromagnetic compatibility.
Power output
Provides six 48 V power supplies for the ODU. The maximum power
consumption of each power supply is 60 W.
Alarm and
indication
Provides one board operation indicator.

l When the indicator turns red, it indicates that one or more power
modules are faulty.
l When the indicator is on and green, it indicates that the board works
normally and no alarms are reported.
Power supply
backup
The input of the power board supports the 1+1 hot backup. The output
of the power module has no backup.

The RPWR consists of the combiner module, protection module, filtering module, DC/DC power
module (that is, power module), and status detection module.
Figure 16-5 shows the functional block diagram of the RPWR.
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Figure 16-5 Functional block diagram of the RPWR
Fuse 1
Power
module 1
IF port 1
Fuse 2
Power
module 2
IF port 2
Fuse 3
Power
module 3
IF port 3
Fuse 4
Power
module 4
IF port 4
Fuse 5
Power
module 5
IF port 5
Fuse 6
Power
module 6
IF port 6
-48V_1
-48V_2
Combiner
module
Protection
module
Filtering
module
Soft start
module
Board operation
indicator
Status
detection
module
Optical
coupling
isolation
Six channels
Signal Flow
The two 48 V power supplies pass through the combiner, protection, filtering, soft start, and
power modules after they are accessed to the power board. The voltage converting operation is
performed on the two 48 V power supplies at the power module (using the DC_I and DC_C
grounding mode). Then, six isolated ODU power supplies are sent to the IF board for processing
and finally are used to supply power to ODUs.
Status Detection Module

The status detection module checks whether the output power supply exists and reports the real
condition so that the STAT indicator indicates the condition. When the STAT indicator turns
red, it indicates that one ore more power modules are faulty. When the STAT indicator is on and
green, it indicates that the power supply works normally.
Power Module
The two 48 V power supplies enter the DC/DC power converting module after they traverse
the protection, filtering, and soft start modules. The power supplies are isolated by the internal
transformer of the power module so that six independent stable power supplies can be sent to
the status detection module and finally to the IF board.
16.2.5 Front Panel

The front panel of the RPWR has indicators, power input interfaces, and power output interfaces.

Figure 16-6 shows the appearance of the front panel of the RPWR.
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Figure 16-6 Front panel of the RPWR
RPWR
STAT
NEG(-)
RTN(+)
NEG(-)
RTN(+)
POWER1
POWER2
POWER3
POWER4
POWER4
POWER4
RPWR
Indicators
The front panel of the board has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see 24 Indicators.
Interfaces
The front panel of the RPWR has two power input interfaces and six power output interfaces.
Table 16-7 describes the types and usage of the interfaces of the RPWR.
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Table 16-7 Interfaces of the RPWR

Interface
Type of Interface
Usage
PWR1
48 V power input interface
Receives the 48 V power supply.
PWR2
48 V power input interface
POWER1
POWER6
48 V power output interface
Supplies the 48 V power to the IF

board for processing. Then, the IF
board supplies the power to the ODU.
16.2.6 Valid Slots

The RPWR must be installed in a valid slot in the subrack. Otherwise, the RPWR cannot work
normally.
NOTE
l Slot bandwidth
l Board version
The slots valid for the RPWR are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the RPWR can be installed in slots 18 and
1117.
16.2.7 Feature Code

The RPWR does not have the feature code.


Step 1 Required: Check the appearance of the board. Ensure that the board is not damaged. The front
panel and the steel plate in the rear must not be deformed.
Step 3 Required: Check the connection of the hardware.
l The subrack power cable must be correctly connected to the RPWR in the corresponding
subrack. The connector of the subrack power cable must be tightened. If the connector is not
tightened, use a screwdriver to tighten the screws on the connector.
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l The power cable between the RPWR and the IF board must be correctly connected and
tightened.
For the connection between the RPWR and the subrack power cable and the connection of the
cable between the RPWR and the IFSD1, see "Installing and Routing IF Cables Connection
of IF Cables" in Quick Installation Guide.
Step 4 Required: Check the status of the indicator of the board. The indicator should be on and green,
which indicates that the board works normally.
----End

Step 1 The RPWR does not need to be configured on the U2000.
----End

Step 1 Required: Use a multimeter to test the resistance between the 48 V interface and the BGND
interface of the DB3 cable connector. In normal cases, the resistance is not zero and is less than
100 Kohms. In this case, you can power on the RPWR.
Step 2 Check the color of the indicator of the RPWR. If the indicator is green, the RPWR works
normally. If the indicator is red, the RPWR is faulty.
----End

Step 1 Check whether the system works normally after the system is powered on.
----End

Troubleshooting
The power module output fault occurs on the RPWR frequently. When the power module output
fault occurs, the indicator is on and red, indicating an alarm. To rectify the fault, replace the
RPWR.
NOTE
The RPWR does not report the fault alarm signal and only turns on the alarm indicator.
Replacing the Board

NOTE
replace the board.
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For information on how to replace the RPWR, see Replacing the Power Supply Board of the
ODU.

The RPWR is not loaded with the software. Hence, the RPWR does not report an alarm.

The RPWR is not loaded with the software. Hence, the RPWR does not report a performance
event.

The technical specifications of the RPWR include the mechanical specifications, power
consumption, input voltage, and specifications of the fuse.
The mechanical specifications of the RPWR are as follows:
l
Weight (kg): 1.4
Power Consumption
The maximum power consumption of the RPWR at room temperature (25C) is 45 W.
Input Voltage
The input voltage range of the RPWR is as follows:
l
If the standard voltage of the accessed power supply is -48 V, the voltage of the power
supply ranges from -38.4 V to -57.6 V.
If the standard voltage of the accessed power supply is -60 V, the voltage of the power
supply ranges from -48 V to -72 V.
Specifications of the Fuses

Two types of fuses are available for the main circuit and power modules of the RPWR.
l
Specifications of the fuse for the main circuit are as follows: fast blow fuse, 250 V, 20 A,
UL certificated, 0.00355 ohms, 631 A x A x second, UL/CSA/METI
Specifications of the fuse for the power modules of the RPWR are as follows: slow blow
fuse, surface-mounted fuse, 125 V, 4 A, UL certificated, 0.023 ohms, 23 A x A x second,
UL.
16.3 ODU
When the microwave board is used, it needs to work with the microwave outdoor unit (ODU).
The ODU types supported by the equipment are standard power (SP) and high power (HP).
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16 Microwave Boards
For more information on the ODU, see the ODU Hardware Description.
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17 WDM Boards
17
WDM Boards
About This Chapter

The WDM boards include the CMR2, CMR4, MR2, MR2A, MR2C, MR4, LWX, and FIB.
17.1 CMR2
technical specifications of the TN11CMR2 (2-channel optical add/drop multiplexing board).
17.2 CMR4
17.3 CMD2
technical specifications of the CMD2 (2-channel bidirectional CWDM optical add/drop
multiplexing board).
17.4 MR2
technical specifications of the TN11MR2 (2-channel optical add/drop multiplexing board).
17.5 MR2A
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).
17.6 MR2C
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).
17.7 MR4
17.8 LWX
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).
17.9 FIB
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17 WDM Boards
technical specifications of the FIB (filter isolating board).
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17 WDM Boards
17.1 CMR2

The CMR2 is available in one functional version, namely, TN11.
17.1.2 Application
The CMR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
Figure 17-1 shows the application of the CMR2 in the CWDM system.
Figure 17-1 Application of the CMR2 in the CWDM system
Optical transmission
network
CMR2
CMR2
Line
board
Line
board
Line
board
Remarks: The line board in this figure supports CWDM wavelength signals.

The CMR2 is applied to the coarse wavelength division multiplexing (CWDM) system. The
channel spacing is 20 nm. The CMR2 supports the add/drop multiplexing function and channel
expansion function.
Table 17-1 provides the functions and features of the CMR2.
Table 17-1 Functions and features of the CMR2
Issue 03 (2013-02-20)
Function and
Feature
CMR2
Basic functions
Adds/Drops and multiplexes two signals to/from the multiplexed

signals.

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17 WDM Boards
Function and
Feature
CMR2
Channel expansion
Provides the interface to cascade another optical add/drop

multiplexing board to realize the expansion of the add/drop channel.

The CMR2 consists of the OADM module, communication and control module, and power
module.
Figure 17-2 shows the functional block diagram of the CMR2.
Figure 17-2 Functional block diagram of the CMR2
D1
IN
D2
MO
MI
Drop optical
module
A1
A2
Add optical
module
OUT
OADM optical
module
Control
Memory
CPU
Communication
Control and communication module

Power supply
module
Fuse
Required
voltage
DC power supply
from a backplane
Backplane
(controlled by SCC)
SCC
The CMR2 contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the CMR2 provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The CMR2 is a passive board and does
not have an interface with the backplane.
OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
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17 WDM Boards
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.

l
Controls the operations of the entire board.
Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.
Communicates data with the SCC.
DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
17.1.5 Front Panel

The front panel of the CMR2 has indicators, interfaces, and a laser safety class label.

Figure 17-3 shows the appearance of the front panel of the CMR2.
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17 WDM Boards
Figure 17-3 Front panel of the CMR2

CMR2
STAT
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
CMR2
Indicator
The front panel of the CMR2 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
Interfaces
The front panel of the CMR2 has eight optical interfaces. Table 17-2 describes the types and
usage of the optical interfaces of the CMR2.
Table 17-2 Optical interfaces of the CMR2
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
A1A2
LC
Receives the signals sent from the optical wavelength

converting board or centralized client-side equipment.

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Interface
Type of
Interface
Usage
D1D2
LC
Transmits signals to the optical wavelength converting board

or centralized client-side equipment.
IN
LC
Receives the multiplexed signals.
OUT
LC
Transmits the multiplexed signals.
MO
LC
Works as a cascading output optical interface and is connected

to the input optical interface of an OADM board.
MI
LC
Works as a cascading input optical interface and is connected

to the output optical interface of an OADM board.
17.1.6 Valid Slots

The CMR2 can be installed in slots 18 and 1117 in the main subrack.
17.1.7 Feature Code

The feature code of the CMR2 contains eight characters, which indicate the wavelengths of the
two channels of optical signals processed by the CMR2.
Table 17-3 describes the feature code of the CMR2.
Table 17-3 Feature code of the CMR2
Feature Code
Indication
Description
First four characters
Wavelength of optical
signals
Indicates the wavelength of

the first channel of optical
signals processed by the
CMR2.
Last four characters
signals
Indicates the wavelength of

the second channel of optical
signals processed by the
CMR2.
Consider the TN11CMR2 whose feature code is "14711571" as an example. The meaning of
the feature code of the TN11CMR2 is as follows:
l
"1471" indicates that the wavelength of the first channel of optical signals is 1471 nm.
"1571" indicates that the wavelength of the second channel of optical signals is 1571 nm.

The technical specifications of the CMR2 include the parameters specified for optical interfaces,
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Table 17-4 lists the parameters specified for the optical interfaces of the CMR2.
Table 17-4 Parameters specified for the optical interfaces of the CMR2
Optical
Interface
Parameter
Value

(nm)
1271 to 1611
Channel spacing (nm)
20
IN-D1
IN-D2
0.5 dB passband bandwidth

(nm)
6.5
Insertion loss (dB) on the

drop channel
1.5
Adjacent channel isolation

(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35

(nm)
6.5
Insertion loss (dB) on the add

channel
1.5
IN-MO
MI-OUT
Insertion loss (dB)
1.0
Isolation (dB)
> 13
Return loss (dB)
> 40
A1-OUT
A2-OUT
Laser Safety Class

The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
The mechanical specifications of the CMR2 are as follows:
l
Weight (kg): 0.8
Power Consumption
The power consumption of the CMR2 at room temperature (25C) is 0 W.
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17 WDM Boards
17.2 CMR4

The CMR4 is available in one functional version, namely, TN11.
17.2.2 Application
The CMR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/
Figure 17-4 shows the application of the CMR4 in the CWDM system.
Figure 17-4 Application of the CMR4 in the CWDM system
network
CMR4
Line
board
Line
board
CMR4
Line
board
Line
board

The CMR4 is applied to the CWDM system. The channel spacing is 20 nm. The CMR4 supports
the add/drop multiplexing function and channel expansion function.
Table 17-5 provides the functions and features of the CMR4.
Table 17-5 Functions and features of the CMR4
Issue 03 (2013-02-20)
Function and
Feature
CMR4
Basic functions
Adds/Drops and multiplexes four signals to/from the multiplexed

signals.
Channel expansion


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17 WDM Boards

The CMR4 consists of the OADM module, communication and control module, and power
module.
Figure 17-5 shows the functional block diagram of the CMR4.
Figure 17-5 Functional block diagram of the CMR4
D01 D02 D03 D04
MO
MI
A01 A02 A03 A04
Drop
IN
Add
OUT
OADM module
Communication and control module
Pow er module
DC/DC
converter
Delayed
startup
Fuse
SCC
Backplane
-48 V/-60 V
-48 V/-60 V
SCC
OADM Module
interface. Then, the drop optical module drops four wavelengths from the signal through optical
interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This
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17 WDM Boards

l
DC/DC Converter
17.2.5 Front Panel

The front panel of the CMR4 has indicators, interfaces, and a laser safety class label.

Figure 17-6 shows the appearance of the front panel of the CMR4.
Figure 17-6 Front panel of the CMR4
CMR4
STAT
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
D3
A3
D4
A4
CMR4
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17 WDM Boards
Indicators
The front panel of the CMR4 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
Interfaces
The front panel of the CMR4 has 12 optical interfaces. Table 17-6 describes the types and usage
of the optical interfaces of the CMR4.
Table 17-6 Optical interfaces of the CMR4
Interface
Type of
Interface
Usage
A1A4
LC

D1D4
LC
Transmits signals to the optical wavelength converting

board or centralized client-side equipment.
IN
LC
OUT
LC
MO
LC
Works as a cascading output optical interface and is

connected to the input optical interface of an OADM
board.
MI
LC
Works as a cascading input optical interface and is

connected to the output optical interface of an OADM
board.
17.2.6 Valid Slots

The CMR4 can be installed in slots 18 and 1117 in the main subrack.
17.2.7 Feature Code

The feature code of the CMR4 contains eight characters, which indicate the wavelengths of the
four channels of optical signals processed by the CMR4.
Table 17-7 describes the feature code of the CMR4.
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17 WDM Boards
Table 17-7 Feature code of the CMR4

Feature Code
Indication
Description
1st and 2nd characters
signals
The two characters are the

two middle characters of the
figure that indicates the
wavelength of the first
channel of optical signals
processed by the CMR4.
3rd and 4th characters
signals

wavelength of the second
5th and 6th characters
signals

wavelength of the third
7th and 8th characters
signals

wavelength of the fourth
Consider the TN11CMR4 whose feature code is "47495961" as an example. The meaning of
the feature code of the TN11CMR4 is as follows:
l
"47" indicates that the wavelength of the first channel of optical signals is 1471 nm.
"49" indicates that the wavelength of the second channel of optical signals is 1491 nm.
"59" indicates that the wavelength of the third channel of optical signals is 1591 nm.
"61" indicates that the wavelength of the fourth channel of optical signals is 1611 nm.

The technical specifications of the CMR4 include the parameters specified for optical interfaces,

Table 17-8 lists the parameters specified for the optical interfaces of the CMR4.
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17 WDM Boards
Table 17-8 Parameters specified for the optical interfaces of the CMR4
Optical
Interface
Parameter
Value

(nm)
1291 to 1611 (1371 nm excluded)
20
IN-D1
IN-D2
IN-D3
IN-D4

(nm)
6.5

drop channel

(dB)
> 25
isolation (dB)
> 35
A1-OUT
A2-OUT
A3-OUT
A4-OUT

(nm)
6.5

channel
IN-MO
MI-OUT
Insertion loss (dB)
1.5
Isolation (dB)
> 13
Return loss (dB)
> 40
Laser Safety Class

The mechanical specifications of the CMR4 are as follows:
l
Weight (kg): 0.9
Power Consumption
The power consumption of the CMR4 at room temperature (25C) is 0 W.
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17 WDM Boards
17.3 CMD2
technical specifications of the CMD2 (2-channel bidirectional CWDM optical add/drop
multiplexing board).

The CMD2 is available in one functional version, namely, SSN1.
17.3.2 Application
The CMD2 adds/drops two channels of signals to/from the multiplexed channel in two
directions. The CMD2 complies with CWDM technical specifications.
The CMD2 supports two-fiber bidirectional transmission. Figure 17-7 shows the application of
the CMD2 in a CWDM system.
Figure 17-7 Application of the CMD2 in a CWDM system
network
CMD2
Line board
Line board
CMD2
Line board
Line board

The CMD2 is used to add/drop two channels of signals in a CWDM system.
Table 17-9 provides the functions and features of the CMD2.
Table 17-9 Functions and features of the CMD2
Function and
Feature
Basic functions
Issue 03 (2013-02-20)
CMD2
Adds/Drops two channels of signals to/from the multiplexed channel
in two directions.

1248

Function and
Feature
17 WDM Boards
CMD2
CWDM
specifications
Complies with CWDM technical specifications.

The CMD2 consists of an OADM module and a communication module.
Figure 17-8 shows the functional block diagram of the CMD2.
Figure 17-8 Functional block diagram of the CMD2
D11 D12
IN1
A11
Drop
A12
Add
A21 A22
D21 D22
Add
OADM
module
Drop
IN2
OADM
module
OUT1
OUT2
Signal Flow
Optical port IN1 receives a multiplexed channel of signals from an upstream station and sends
the signals to the OADM module. The OADM module then demultiplexes two channels of
signals from the multiplexed channel, and sends one channel of signals to optical port D11 and
the other channel of signals to optical port D12.
Optical ports A11 and A12 each receive one channel of signals from the local station and send
the received signals to the OADM module. The OADM module then multiplexes the two
channels of signals and sends the multiplexed channel of signals to optical port OUT1.
Optical ports IN2 and OUT2 process signals in the same way as optical ports IN1 and OUT1
do, but in different directions.
Functions of the Board Modules

l
OADM module
Adds/Drops two CWDM channels of signals to/from the multiplexed channel.
17.3.5 Front Panel

The front panel of the CMD2 has optical interfaces.
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Figure 17-9 shows the appearance of the front panel of the CMD2.
Figure 17-9 Front panel of the CMD2
CMD2
CAUTION
HAZARDLEVEL 1M INVISIBLE
LASER RADIATION
DO NOT VIEW DIRECTLY WITH
NON-ATTENUATING OPTICAL
INSTRUMENTS
IN1 OUT1 A11 D11 A12 D12 IN2 OUT2 A21 D21 A22 D22
CMD2
NOTE
The number in the silkscreen under an optical interface on the front panel indicates one of the wavelengths
that are supported by the optical interface.
Indicators
The front panel of the CMD2 does not have any indicators.
Interfaces
The front panel of the CMD2 has 12 optical interfaces. Table 17-10 describes the types and
usage of the optical interfaces of the CMD2.
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17 WDM Boards
Table 17-10 Optical interfaces of the CMD2

Interface
Type of
Interface
Usage
IN1
LC
Receives the first multiplexed channel of signals.
OUT1
LC
Transmits the first multiplexed channel of signals.
A11/A12
LC
Receives the first channel of signals transmitted from an optical

transponder board or the integrated client equipment.
D11/D12
LC
Transmits the first channel of signals to an optical transponder

board or the integrated client equipment.
IN2
LC
Receives the second multiplexed channel of signals.
OUT2
LC
Transmits the second multiplexed channel of signals.
A21/A22
LC
Receives the second channel of signals transmitted from an

optical transponder board or the integrated client equipment.
D21/D22
LC
Transmits the second channel of signals to an optical

transponder board or the integrated client equipment.
17.3.6 Valid Slots

The CMD2 occupies one slot.
The CMD2 can be installed in slots 19-26 and 29-36 in a main subrack. If an extended subrack
is connected to the main subrack, the CMD2 can also be installed in slots 69-76 and 79-86 in
the extended subrack.
17.3.7 Feature Code

No feature code is defined for the CMD2.


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17 WDM Boards
Step 3 Required: Check whether the wavelength specified on the label, attached to the front panel of
the board, is the same as the actually used wavelength.
----End

Step 1 Required: The CMD2 is a passive board, and therefore a logical board needs to be added for it
on the NMS. For information on how to add a logical board for the CMD2 on the NMS, see
Adding Boards.
----End

Step 1 Required: Test the insertion loss of the board. For details, see 17.3.10 Maintaining the
Board.
----End

Step 1 Required: Verify that the input/output directions of fibers connected to the board are correct.
Step 2 Required: Verify that the optical wavelength used by each optical port on the board is the same
as the information specified on the label.
----End

The CMD2 does not have any parameters to be set.

Testing Insertion Loss

Insertion loss is a key specification of an optical add/drop multiplexing board. If the insertion
loss of a board is normal, the board is not faulty; otherwise, the board is faulty or optical ports
on the board need to be cleaned. The methods of testing the insertion loss of an optical multiplexer
and demultiplexer board are as follows.
Figure 17-10 shows the diagram for testing the insertion loss of the CMD2.
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17 WDM Boards
Figure 17-10 Diagram for testing the insertion loss of the CMD2
D11 D12
D21 D22
IN1
IN2
CMD2
OUT1
OUT2
A11 A12
A21 A22
Step 1 Required: Measure the input optical power Pi at the A11 port and the output optical power Po
at the OUT1 port on the CMD2. The optical power is expressed in dBm.
The value obtained by subtracting Po from Pi represents the insertion loss from the A11 port to
the OUT1 port.
In the case of the CMD2, use the preceding method to measure the insertion loss of IN1-D11,
A11-OUT1, IN1-D12, A12-OUT1, IN2-D21, A21-OUT2, IN2-D22, and A22-OUT2.
For the normal insertion loss value of the board, see 17.3.13 Technical Specifications.
----End
Troubleshooting
When all services on an NE are interrupted or a service on a WDM-side channel of the CMD2
is interrupted, the CMD2 may be faulty.
Step 1 Required: Check whether the insertion loss of the CMD2 is normal. For details, see the insertion
loss specification of the CMD2. If the insertion loss is excessively high, go to the next step.
Step 2 Required: Use a fiber cleaning tool to clean the internal and external fibers and optical ports
on the CMD2. Then, test the insertion loss again. If the insertion loss returns to normal, the fault
is rectified; if the insertion loss is still excessively high, go to the next step.
Step 3 Optional: The CMD2 is faulty. In this case, replace the CMD2.
----End

No alarm is defined for the CMD2.

No performance event is defined for the CMD2.

The technical specifications of the CMD2 include the parameters specified for optical interfaces,
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17 WDM Boards

Table 17-11 lists the parameters specified for the optical interfaces of the CMD2.
Table 17-11 Parameters specified for the optical interfaces of the CMD2
Optical
Interface
Parameter
Value

(nm)
1471 to 1611
20
IN1-D11
IN1-D12
IN2-D21
IN2-D22

(nm)
13.0

drop channel
< 1.5

(dB)
> 30
isolation (dB)
> 40
A11-OUT1
A12-OUT1
A21-OUT2
A22-OUT2

(nm)
13.0

channel
< 1.5
Reflectance (dB)
< -40
Laser Safety Class

The mechanical specifications of the CMD2 are as follows:
l
Weight (kg): 0.6
Power Consumption
The power consumption of the CMD2 at room temperature (25C) is 0 W.
17.4 MR2
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17 WDM Boards

The MR2 is available in one functional version, namely, TN11.
17.4.2 Application
The MR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/from
the multiplexed signals.
Figure 17-11 shows the application of the MR2 in the DWDM system.
Figure 17-11 Application of the MR2 in the DWDM system
network
MR2
Line
board
Line
board
MR2
Line
board
Line
board
Remarks: The line board in this figure supports DWDM wavelength signals.

The MR2 is applied to the dense wavelength division multiplexing (DWDM) system. The
channel spacing is 0.8 nm. The MR2 supports the add/drop multiplexing function and channel
expansion function.
Table 17-12 provides the functions and features of the MR2.
Table 17-12 Functions and features of the MR2
Issue 03 (2013-02-20)
Function and
Feature
MR2
Basic functions
Adds/Drops and multiplexes any two signals to/from the multiplexed

signals.
Channel expansion


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17 WDM Boards

The MR2 consists of the OADM module, communication and control module, and power
module.
Figure 17-12 shows the functional block diagram of the MR2.
Figure 17-12 Functional block diagram of the MR2
D1
IN
D2
MO
MI
Drop optical
module
A1
A2
Add optical
module
OUT
OADM optical
module
Control
Memory
CPU
Communication
Control and communication module

Power supply
module
Fuse
Required
voltage
DC power supply
from a backplane
Backplane
(controlled by SCC)
SCC
OADM Module
interface.

l
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17 WDM Boards
DC/DC Converter
17.4.5 Front Panel

The front panel of the MR2 has indicators, interfaces, and a laser safety class label.

Figure 17-13 shows the appearance of the front panel of the MR2.
Figure 17-13 Front panel of the MR2
MR2
STAT
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2
A2
MR2
Indicators
The front panel of the MR2 has one indicator as follows: board hardware status indicator (STAT)
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17 WDM Boards
Interfaces
The front panel of the MR2 has eight optical interfaces. Table 17-13 describes the types and
usage of the optical interfaces of the MR2.
Table 17-13 Optical interfaces of the MR2
Interface
Type of
Interface
Usage
A1A2
LC

D1D2
LC

IN
LC
OUT
LC
MO
LC

board.
MI
LC

board.
17.4.6 Valid Slots

The MR2 can be installed in slots 18 and 1117 in the main subrack.
17.4.7 Feature Code

The feature code of the MR2 contains eight characters, which indicate the frequencies of the
two channels of optical signals processed by the MR2.
Table 17-14 describes the feature code of the MR2.
Table 17-14 Feature code of the MR2
Issue 03 (2013-02-20)
Feature Code
Indication
Description
First four (14) characters
Frequency of optical signals
The four characters are the

last four characters of the
frequency of the first channel
of optical signals processed
by the MR2.

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17 WDM Boards
Feature Code
Indication
Description
Last four (58) characters

frequency of the second
processed by the MR2.
Consider the TN11MR2 whose feature code is "93609370" as an example. The meaning of the
feature code of the TN11MR2 is as follows:
l
"9360" indicates that the frequency of the first channel of optical signals is 193.60 THz.
"9370" indicates that the frequency of the second channel of optical signals is 193.70 THz.

The technical specifications of the MR2 include the parameters specified for optical interfaces,

Table 17-15 lists the parameters specified for the optical interfaces of the MR2.
Table 17-15 Parameters specified for the optical interfaces of the MR2
Optical
Interface
Parameter
Value

(nm)
1529 to 1561
Channel spacing (GHz)
100
IN-D1
IN-D2

(nm)
0.11

drop channel
1.5

(dB)
> 25
isolation (dB)
> 35

(nm)
0.11

channel
1.5
Insertion loss (dB)
1.0
A1-OUT
A2-OUT
IN-MO
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17 WDM Boards
Optical
Interface
Parameter
Value
MI-OUT
Isolation (dB)
> 13
Return loss (dB)
> 40
Laser Safety Class

The mechanical specifications of the MR2 are as follows:
l
Weight (kg): 0.9
Power Consumption
The power consumption of the MR2 at room temperature (25C) is 0 W.
17.5 MR2A
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).

The MR2A is available in one functional version, namely, N1. The N1MR2A is discontinued.
17.5.2 Application
The MR2A is mainly used to add/drop and multiplex two channels of wavelength signals to/
Figure 17-14 shows the application of the MR2A in the DWDM system.
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17 WDM Boards
Figure 17-14 Application of the MR2A in the DWDM system
network
MR2A
Line
board
MR2A
Line
board
Line
board
Line
board

The MR2A is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2A supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 17-16 provides the functions and features of the MR2A.
Table 17-16 Functions and features of the MR2A
Issue 03 (2013-02-20)
Function and
Feature
MR2A
Basic functions
Adds/Drops any two adjacent standard wavelengths defined in ITU-T

G.692 (DWDM). The signals are transparently transmitted and the
operating wavelength ranges from 1535.82 nm to 1560.61 nm.
OTM function
One MR2A board can work as a two-channel add/drop OTM station,

as shown in Figure 17-15. Two MR2A boards can be cascaded to work
as a four-channel add/drop OTM station, as shown in Figure 17-16.
OADM function
Works as a two-channel add/drop OADM station when working with

the LWX. For details, see Figure 17-17.
Central wavelength
Supports the standard wavelengths defined in ITU-T

Recommendations. The channel spacing is 100 GHz.

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17 WDM Boards
Figure 17-15 One MR2A board working as a two-channel add/drop OTM station
D2
D1
IN
MO
Drop
OUT
MI
Add
MR2A
A1
A2
Figure 17-16 Two MR2A boards being cascaded to work as a four-channel add/drop OTM
station
D2
D1
IN
D1
MO IN
Drop
OUT
Drop
MI OUT
Add
MR2A
D2
MO
MI
Add
MR2A
A1
A2
A1
A2
Figure 17-17 MR2A and LWX working as a two-channel add/drop OADM station
LWX
A2
D2
MO
Out
MR2A
In
D1
MI
A1
LWX

The MR2A consists of the OADM module.
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Figure 17-18 shows the functional block diagram of the MR2A.

Figure 17-18 Functional block diagram of the MR2A
D01
D02
MO
MI
Drop
IN
A01
A02
Add
OUT
OADM
module
The MR2A contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2A provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2A is a passive board and does
OADM Module
interface.
17.5.5 Front Panel

The front panel of the MR2A has interfaces and a laser safety class label.

Figure 17-19 shows the appearance of the front panel of the MR2A.
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Figure 17-19 Front panel of the MR2A
MR2A
CLASS 1
LASER
PRODUCT
OUT
IN
MO
MI
D1
A1
D2 A2
MR2A
Interfaces
The front panel of the MR2A has four LC optical interfaces. Table 17-17 describes the types
and usage of the optical interfaces of the MR2A.
Table 17-17 Optical interfaces of the MR2A
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
A01A02
LC
Adds two wavelengths of signals from the local equipment.
D01D02
LC
Drops two wavelengths of signals to the local equipment.
IN
LC
Receives the multiplexed signals of two wavelengths.
OUT
LC
Transmits the multiplexed signals of two wavelengths.

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Interface
Type of
Interface
Usage
MO/MI
LC
Works as a cascading interface and cascades several MR2A

boards.
17.5.6 Valid Slots

The slots valid for the MR2A vary with the cross-connect capacity and subrack of the equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the MR2A are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the MR2A can be installed in slots 18 and

The technical specifications of the MR2A include the parameters specified for optical interfaces,

Table 17-18 lists the parameters specified for the optical interfaces of the MR2A.
Table 17-18 Parameters specified for the optical interfaces of the MR2A
Issue 03 (2013-02-20)
Parameter
Value
range (nm)
The operating wavelength range is from 1535.82 nm to 1560.61

nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).
Line code pattern
NRZ
100
Insertion loss on the add

channel or drop channel
(dB)
<2

(dB)
> 25
isolation (dB)
> 35

1265

Parameter
Value
-0.5 dB channel bandwidth

(nm)
< 0.11
17 WDM Boards
Laser Safety Class

The mechanical specifications of the MR2A are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the MR2A at room temperature (25C) is 0 W.
17.6 MR2C
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).

The MR2C is available in one functional version, namely, N1.
17.6.2 Application
The MR2C is mainly used to add/drop and multiplex two channels of wavelength signals to/
Figure 17-20 shows the application of the MR2C in the DWDM system.
Figure 17-20 Application of the MR2C in the DWDM system
MR2C
Line
board
network
Line
board
MR2C
Line
board
Line
board
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The MR2C is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2C supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 17-19 provides the functions and features of the MR2C.
Table 17-19 Functions and features of the MR2C
Function and
Feature
MR2C
Basic functions
Adds/Drops any two adjacent standard wavelengths defined in ITUT G.692 (DWDM). The signals are transparently transmitted and the
operating wavelength ranges from 1535.82 nm to 1560.61 nm.
OTM function
One MR2C board can work as a two-channel add/drop OTM station,

as shown in Figure 17-21. Two MR2C boards can be cascaded to
work as a four-channel add/drop OTM station, as shown in Figure
17-22.
OADM function
Works as a two-channel add/drop OADM station when working with

the LWX. For details, see Figure 17-23.
Central wavelength
Supports the standard wavelengths defined in ITU-T

Recommendations. The channel spacing is 100 GHz.
Figure 17-21 One MR2C board working as a two-channel add/drop OTM station
D2
D1
IN
Drop
OUT
MO
MI
Add
MR2C
A1
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A2

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Figure 17-22 Two MR2C boards being cascaded to work as a four-channel add/drop OTM
station
D2
D1
IN
D1
MO IN
Drop
OUT
MR2C
MO
Drop
MI OUT
Add
D2
MI
Add
MR2C
A1
A2
A1
A2
Figure 17-23 MR2C and LWX working as a two-channel add/drop OADM station
LWX
A2
D2
MO
Out
MR2C
In
D1
MI
A1
LWX

The MR2C consists of the OADM module.
Figure 17-24 shows the functional block diagram of the MR2C.
Figure 17-24 Functional block diagram of the MR2C
D01
IN
D02
MO
MI
Drop
A01
A02
Add
OUT
OADM
module
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The MR2C contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2C provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2C is a passive board and does
OADM Module
interface.
17.6.5 Front Panel

The front panel of the MR2C has interfaces and a laser safety class label.

Figure 17-25 shows the appearance of the front panel of the MR2C.
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Figure 17-25 Front panel of the MR2C
MR2C
OUT AO1
AO2
MI
MO
DO2
DO1
IN
CLASS 1
LASER
PRODUCT
MR2C
Interfaces
The front panel of the MR2C has four pairs of LC optical interfaces. Table 17-20 describes the
types and usage of the optical interfaces of the MR2C.
Table 17-20 Optical interfaces of the MR2C
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
A01A02
LC
Adds two wavelengths of signals from the local equipment.
D01D02
LC
Drops two wavelengths of signals to the local equipment.
IN
LC
Receives the multiplexed signals of two wavelengths.
OUT
LC
Transmits the multiplexed signals of two wavelengths.

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Interface
Type of
Interface
Usage
MO/MI
LC
Works as a cascading interface and cascades several MR2C

boards.
17.6.6 Valid Slots

The slots valid for the MR2C vary with the cross-connect capacity and subrack of the equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the MR2C are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the MR2C can be installed in slots 1926

The technical specifications of the MR2C include the parameters specified for optical interfaces,

Table 17-21 lists the parameters specified for the optical interfaces of the MR2C.
Table 17-21 Parameters specified for the optical interfaces of the MR2C
Issue 03 (2013-02-20)
Parameter
Value
range (nm)
The operating wavelength range is from 1535.82 nm to 1560.61

nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).
Line code pattern
NRZ
100
Insertion loss on the add

channel or drop channel
(dB)
<2

(dB)
> 25
isolation (dB)
> 35

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Parameter
Value
-0.5 dB channel bandwidth

(nm)
< 0.11
Laser Safety Class

The mechanical specifications of the MR2C are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the MR2C at room temperature (25C) is 0 W.
17.7 MR4

The MR4 is available in one functional version, namely, TN11.
17.7.2 Application
The MR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/from
the multiplexed signals.
Figure 17-26 shows the application of the MR4 in the DWDM system.
Figure 17-26 Application of the MR4 in the DWDM system
network
MR4
Line
board
Line
board
MR4
Line
board
Line
board
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17 WDM Boards

The MR4 is applied to the DWDM system. The channel spacing is 0.8 nm. The MR4 supports
the add/drop multiplexing function and channel expansion function.
Table 17-22 provides the functions and features of the MR4.
Table 17-22 Functions and features of the MR4
Function and
Feature
MR4
Basic functions
Adds/Drops and multiplexes four continuous signals to/from the

multiplexed signals.
Channel expansion


The MR4 consists of the OADM module, communication and control module, and power
module.
Figure 17-27 shows the functional block diagram of the MR4.
Figure 17-27 Functional block diagram of the MR4
D01 D02 D03 D04
MO
MI
A01 A02 A03 A04
Drop
IN
Add
OUT
OADM module
Pow er module
DC/DC
converter
Delayed
startup
Fuse
SCC
Backplane
Issue 03 (2013-02-20)
-48 V/-60 V
-48 V/-60 V
SCC

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17 WDM Boards
OADM Module
interface. Then, the drop optical module drops four wavelengths from the signal through optical
interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This

l
DC/DC Converter
17.7.5 Front Panel

The front panel of the MR4 has indicators, interfaces, and a laser safety class label.

Figure 17-28 shows the appearance of the front panel of the MR4.
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Figure 17-28 Front panel of the MR4

MR4
STAT
OUT
IN
MO
IN
D1
A1
D2
A2
D3
A3
D4
A4
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
MR4
Indicators
The front panel of the MR4 has one indicator as follows: board hardware status indicator (STAT)
Interfaces
The front panel of the MR4 has 12 optical interfaces. Table 17-23 describes the types and usage
of the optical interfaces of the MR4.
Table 17-23 Optical interfaces of the MR4
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
A1A4
LC


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Interface
Type of
Interface
Usage
D1D4
LC

IN
LC
OUT
LC
MO
LC

board.
MI
LC

board.
17.7.6 Valid Slots

The MR4 can be installed in slots 18 and 1117 in the subrack.
17.7.7 Feature Code

The feature code of the MR4 contains eight characters, which indicate the frequencies of the
first channel and fourth channel of optical signals processed by the MR4.
Table 17-24 describes the feature code of the MR4.
Table 17-24 Feature code of the MR4
Feature Code
Indication
Description
First four (14) characters

frequency of the first channel
of optical signals processed
by the MR4.
Last four (58) characters

frequency of the fourth
processed by the MR4.
Consider the TN11MR4 whose feature code is "92109240" as an example. The meaning of the
feature code of the TN11MR4 is as follows:
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17 WDM Boards
"9210" indicates that the frequency of the first channel of optical signals is 192.10 THz.
"9240" indicates that the frequency of the fourth channel of optical signals is 192.40 THz.
The four channels of optical signals processed by the MR4 are successive. Hence, we can infer
the following:
l
The frequency of the second channel of optical signals is 192.20 THz.
The frequency of the third channel of optical signals is 192.30 THz.

The technical specifications of the MR4 include the parameters specified for optical interfaces,

Table 17-25 lists the parameters specified for the optical interfaces of the MR4.
Table 17-25 Parameters specified for the optical interfaces of the MR4
Optical Interface
Parameter
Value
1529 to 1561
100
IN-D1
IN-D2
IN-D3
IN-D4
0.5 dB passband bandwidth (nm)
0.11
Insertion loss on the drop channel (dB)
2.2
Adjacent channel isolation (dB)
> 25
Non-adjacent channel isolation (dB)
> 35
A1-OUT
A2-OUT
A3-OUT
A4-OUT
0.5 dB passband bandwidth (nm)
0.11
Insertion loss on the add channel (dB)
2.2
IN-MO
MI-OUT
Insertion loss (dB)
1.5
Isolation (dB)
> 13
Return loss (dB)
> 40
Laser Safety Class

The mechanical specifications of the MR4 are as follows:
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17 WDM Boards
Weight (kg): 0.9
Power Consumption
The power consumption of the MR4 at room temperature (25C) is 0 W.
17.8 LWX
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).

The LWX is available in one functional version, namely, N1. The N1LWX is discontinued.
17.8.2 Application
The LWX is a wavelength conversion board. The LWX converts a wavelength at an arbitrary
rate (10 Mbit/s to 2.7 Gbit/s) into a standard wavelength defined in ITU-T G.692, and performs
the reverse process.
Figure 17-29 shows the application of the LWX in the DWDM system.
Figure 17-29 Application of the LWX in the DWDM system
Client side
Multiplexing
10 Mbit/s-2.7 Gbit/s
LWX
Demultiplexing
G.692
WDM side
G.692
LWX
WDM side
Client side

The LWX converts a wavelength at an arbitrary rate (10 Mbit/s to 2.7 Gbit/s, NRZ code) on the
client side into a standard wavelength defined in ITU-T G.692, and performs the reverse process.
The LWX supports the optical wavelength conversion, 3R function, protection, and loopback
function.
Table 17-26 provides the functions and features of the LWX.
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17 WDM Boards
Table 17-26 Functions and features of the LWX

Function
and Feature
LWX
Basic
functions
Converts a wavelength on the client side into a standard wavelength defined

in ITU-T G.692 (DWDM), and performs the reverse process.
Transparently transmits signals.
3R function
Provides the 3R function for the signals at a rate ranging from 10 Mbit/s to
2.7 Gbit/s on the client side, restores the clock, and monitors the rate.
Protection
schemes
Single fed and single

receiving
Supports the inter-board protection and 1+1 interboard hot standby protection. The protection
switching time is less than 50 ms.
Dual fed and

selective receiving
Supports the intra-board protection. One board can

realize the optical channel protection. The protection
switching time is less than 50 ms.
ALS function
Supports the ALS function. When the LWX does not receive light, the LWX
automatically turns off the corresponding optical transmit module.
Loopback
function
Supports inloops and outloops at optical interfaces so that faults can be

located quickly.
Performance
and alarm
monitoring

maintenance of the equipment.
Central
wavelength
Supports the standard wavelengths defined in ITU-T Recommendations. The

channel spacing is 100 GHz.

The LWX consists of the O/E converting module, cross-connect module, CDR module, logic
and control module, DC/DC converter, and other modules.
Figure 17-30 shows the functional block diagram of the LWX.
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17 WDM Boards
Figure 17-30 Functional block diagram of the LWX

Loopback control
Reference clock
10 Mbit/s to 2.7
Gbit/s
Optical module on
the client side
10 Mbit/s to 2.7
Gbit/s
O/E
E/O
2x2 crossconnection
WDM side
loopback
Data
LOS
Laser
Communication
shutdown
and control
module
LOS
10 Mbit/s to 2.7
Gbit/s
Optical module 2
on the WDM side
Multi-rate
CDR
Client side
loopback
O/E
2x2 crossconnection
Multi-rate
CDR
Loopback control
Reference
clock
10 Mbit/s to 2.7
Gbit/s
Optical module 1
on the WDM side
O/E
Clock
10 Mbit/s to 2.7
Gbit/s
Optical
splitter
E/O
Data
LOS
Communication
and control
module
Communication
Laser shutdown
+3.3
V
DC/DC
converter
DC/DC
converter
Fuse
SCC unit
-48 V/ -60 V
-48 V/ -60 V
Fuse
+3.3 V backup
power

l
The optical module on the client side applies SFP encapsulation and can be configured as
different types of optical modules. This module can transmit/receive the optical signals at
a rate ranging from 10 Mbit/s to 2.7 Gbit/s.
The optical module on the WDM side can be configured as an optical transceiver module,
or both an optical transceiver module and an optical receiver module. When two modules
are configured on the WDM side, an optical splitter is used to perform dual feeding.
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In the receive direction, the module converts the received optical signals into electrical
signals.
In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
Detects the R_LOS alarm and provides the function of shutting down the laser.
Cross-Connect Module
l
Supports the data selection from the client side to the WDM side and the data selection
from the WDM side to the client side.
Supports the selection of WDM-side optical modules.
Supports the loopback of client-side signals.
Supports the loopback of WDM-side signals.
Restores the data and clock signals from the signals that are at a rate ranging from 10 Mbit/
s to 2.7 Gbit/s.
Reads the rates of the accessed services.
CDR Module

l
Supports Ethernet communication.
Supports the reference clock of the CDR module.
Selects and configures the services of the other modules.
Controls the laser.
Selects the clock signal from the active and standby cross-connect boards.
DC/DC Converter
require.
17.8.5 Front Panel

The front panel of the LWX has indicators, interfaces, and a laser safety class label.

Figure 17-31 shows the appearance of the front panel of the LWX.
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Figure 17-31 Front panel of the LWX
LWX
STAT
ACT
PROG
SRV
CLASS 1
LASER
PRODUCT
TX
RX
OUT1 IN1
OUT2 IN2
LWX
Indicators
l
Interfaces
The front panel of the LWX has six optical interfaces. Table 17-27 describes the types and usage
of the optical interfaces of the LWX.
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Table 17-27 Optical interfaces of the LWX

Interface
Type of
Interface
Usage
IN1IN2
LC
Receives the signals sent from the MR2A.
OUT1OUT2
LC
Transmits signals to the MR2A.
TX
LC
Transmits signals to the client-side equipment.
RX
LC
Receives the signals sent from the client-side

equipment.
17.8.6 Valid Slots

The slots valid for the LWX vary with the cross-connect capacity and subrack of the equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the LWX are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the LWX can be installed in slots 18 and
17.8.7 Feature Code

The feature code of the LWX indicates the scheme that the optical interfaces use to receive and
transmit signals.
Table 17-28 provides the relationship between the feature code of the LWX and the signal
receive/transmit scheme.
Table 17-28 Relationship between the feature code of the LWX and the signal receive/transmit
scheme
Board
Feature Code
Signal Receive/Transmit Scheme
SSN1LWX01
01
Single fed and single receiving
SSN1LWX02
02
Dual fed and selective receiving

You can set the parameters for the LWX by using the U2000.
You can set the following parameters for the LWX by using the U2000:
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Path use status
Optical interface loopback
Service type
Client service bearer rate (M)
Laser status
Automatic laser shutdown
Current bearer rate (M)
Actual wavelength No./wavelength (nm)/frequency (THz)
Actual band type
Configure wavelength No./wavelength (nm)/frequency (THz)
Configure band type
SD trigger condition

The technical specifications of the LWX include the parameters specified for optical interfaces,
the safety class of the laser, mechanical specifications and power consumption.

Table 17-29 and Table 17-30 list the parameters specified for the client-side and WDM-side
optical interfaces of the LWX.
Table 17-29 Parameters specified for the client-side optical interfaces of the LWX
Parameter
Value
Nominal bit rate
10 Mbit/s to 2.7 Gbit/s
Line code pattern
NRZ
Type of fiber
Single-mode LC
Single-mode LC
Single-mode LC
Transmission
distance (km)
15
40
80
Characteristics of the transmitter at point S
Issue 03 (2013-02-20)
Operating
wavelength range
(nm)
1260 to 1360
1260 to 1360
1500 to 1580
Maximum mean
launched power
(dBm)
+3
+3
Minimum mean
launched power
(dBm)
-5
-2
-2
Minimum extinction
ratio (dB)
+8.2
+8.2
+8.2

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17 WDM Boards
Parameter
Value
Minimum side mode

suppression ratio
(dB)
30
30
30
Eye pattern mask
Complies with the

mask defined in ITUT G.957.
Complies with the

Complies with the

Characteristics of the receiver at point S

Receiver type
PIN
APD
APD
Receiver wavelength
range (nm)
1200 to 1600
1200 to 1600
1200 to 1600
(dBm)
-18
-27
-28
Minimum overload
(dBm)
-9
-9
Maximum
reflectance (dB)
-27
-27
-27
Table 17-30 Parameters specified for the WDM-side optical interfaces of the LWX
Parameter
Value
Channel
spacing (GHz)
100
Line code
pattern
NRZ
Characteristics of the transmitter at point Sn
Issue 03 (2013-02-20)
Transmission
distance (km)
640
170 (2 mW)
170 (10 mW)
360
Maximum mean
launched power
(dBm)
+3
+3
+7
+3
Minimum mean
launched power
(dBm)
-2
-2
-2
Minimum
extinction ratio
(dB)
+10
+10
+10
+10

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Parameter
Value
Nominal central
frequency
(THz)
192.10 to
196.00
192.10 to
196.00
192.10 to
196.00
192.10 to
196.00
Central
frequency
deviation (GHz)
12.5
12.5
12.5
12.5
Maximum -20
dB spectral
width (nm)
0.2
0.4
0.4
0.4
Minimum side
mode
suppression
ratio (dB)
35
35
35
35
Dispersion
compensation
(ps/nm)
12800
3400
3400
7200
Eye pattern
mask
Complies with
the mask
defined in ITUT G.957.
Complies with
the mask
Complies with
the mask
Complies with
the mask
Characteristics of the receiver at point Rn

Receiver type
APD
PIN
Receiver
wavelength
range (nm)
1200 to 1600
1200 to 1600
Receiver
sensitivity
(dBm)
-28
-18
Minimum
overload (dBm)
-9
Maximum
reflectance (dB)
-27
-27
Laser Safety Class

The mechanical specifications of the LWX are as follows:
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17 WDM Boards
Weight (kg): 1.1
Power Consumption
The maximum power consumption of the LWX at room temperature (25C) is 30 W.
17.9 FIB
technical specifications of the FIB (filter isolating board).

The FIB is available in one functional version, namely, N1.
17.9.2 Application
The FIB is used in the remote optical pumping amplifier system. The FIB can realize longdistance optical regeneration transmission when it works with the single-wavelength longdistance board ROP.
Figure 17-32 shows the position of the FIB in an optical transmission system.
Figure 17-32 Position of the FIB in an optical transmission system
C (single span)
a (54 dB)
Optical
transmitter
BA17
G.652 fiber
FIB
b (18 dB)
Erbium
ROP
doped fiber G.652 fiber
->
ISO
Filter
1550.12
Optical
receiver

The FIB filters and isolates one optical signals.
Table 17-31 provides the functions and features of the FIB.
Table 17-31 Functions and features of the FIB
Issue 03 (2013-02-20)
Function and
Feature
FIB
Optical isolator
The isolator allows optical signals to pass in a single direction. The

operating wavelength ranges from 1529 nm to 1561 nm.

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Function and
Feature
FIB
Optical filter
The filter filters out the wavelengths other than the 1550.12 nm
wavelength.

The FIB consists of an isolator and a filter.
Figure 17-33 shows the functional block diagram of the FIB.
Figure 17-33 Functional block diagram of the FIB
Isolator
Filter
Optical signals are heavily attenuated and degraded after they travel for a long distance in fibers.
The degraded signals cannot be normally received by an optical receiver. Hence, an ROP needs
to be used to amplify the gain of the optical signals. To prevent other factors from affecting the
ROP because the ROP has high optical power, the FIB needs to be used to filter wavelengths.
The isolator of the FIB allows the optical signals to pass in a single direction. The filter of the
FIB filters out the wavelengths other than the 1550.12 nm wavelength. As a result, the optical
receiver receives the optical signals normally.
17.9.5 Front Panel

The front panel of the FIB has one channel of optical interface.

Figure 17-34 shows the appearance of the front panel of the FIB.
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Figure 17-34 Front panel of the FIB
FIB
CLASS 1
LASER
PRODUCT
OUT
IN
FIB
Interfaces
The front panel of the FIB has one optical interface. The optical interface is used to receive and
transmit one channel of optical signals. Table 17-32 describes the types and usage of the optical
interfaces of the FIB.
Table 17-32 Optical interfaces of the FIB
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
IN
LSH
Receives one channel of optical signals.
OUT
LC
Transmits one channel of optical signals.

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17.9.6 Valid Slots

The slots valid for the FIB vary with the cross-connect capacity and subrack of the equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the FIB are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the FIB can be installed in slots 18 and
1117 in the main subrack.

The technical specifications of the FIB include the parameters specified for optical interfaces,

Table 17-33 lists the parameters specified for the optical interfaces of the FIB.
Table 17-33 Parameters specified for the optical interfaces of the FIB
Parameter
Value
Nominal bit rate
2488320 kbit/s
Line code pattern
NRZ
Central wavelength
(nm)
1550.120.05
-0.5 dB bandwidth
(nm)
> 0.4
Laser Safety Class

The mechanical specifications of the FIB are as follows:
l
Weight (kg): 0.4
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Power Consumption
The maximum power consumption of the FIB at room temperature (25C) is 0 W.
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18 Auxiliary Boards
Auxiliary Boards
About This Chapter

This topic describes the auxiliary boards including the AUX and FAN.
18.1 AUX
technical specifications of the AUX (system auxiliary interface board).
18.2 FAN
technical specifications of the FAN (fan board).
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18.1 AUX
technical specifications of the AUX (system auxiliary interface board).

The AUX is available in one functional version, namely, N1.
18.1.2 Application
The AUX is a system auxiliary interface board. The AUX can be used on the OptiX OSN
equipment series to provide various management interfaces and auxiliary interfaces.

The AUX provides various management and auxiliary interfaces for the system, and provides
the centralized backup for the +3.3 V power supply of the boards in the subrack.
Table 18-1 provides the functions and features of the AUX.
Table 18-1 Functions and features of the AUX
Item
AUX
Management
interface
l Provides the OAM interface, which supports the X.25 protocol.

l Provides the management serial interface F&f.
l Provides the 10M/100M NM interface.
Auxiliary interface
l Provides the serial interfaces Serial 1Serial 4, which can

function as four broadcast data interfaces or two pairs of time
interfaces. The two functions of the interfaces are mutually
exclusive.
l The two pairs of time interfaces work in full-duplex mode and
support synchronous time input and output of two channels.
l Both the time interface and the broadcast data interface support
the RS-422 level and RS-232 level.
l Provides one F1 interface for the 64 kbit/s codirectional data
channel.
External time
interface
l Supports the input and output of two channels of time signals,

with the external time transmitted in 1pps+TOD mode.
l For details about the external time input and output interfaces,
see Table 18-2 and Table 18-3.
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Item
AUX
Clock interface
l Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 120 ohms).
l Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 75 ohms).
Alarm interface
l Provides 16-input and 4-output alarm interfaces.

l Provides 4-output alarm cascading interfaces.
Cabinet alarm
indicator
l Provides four cabinet alarm indicator output interfaces.
Orderwire interface
l Provides two NNI connection signaling interfaces.
l Provides four cabinet alarm indicator input cascading interfaces.
l Provides one orderwire phone interface.

l Provides two NNI voice interfaces.
Commissioning
interface
Provides one commissioning interface COM.
Internal
communication
Realizes communication between boards in the subrack.
Power supply backup

and checking
l Monitors the two independent 48 V power supplies, detects the

overvoltage (72 V) and undervoltage (38.4 V) conditions, and
reports alarms to the SCC unit in the case of overvoltage or
undervoltage occurs.
l Provides the centralized backup for the +3.3 V power supply of
the boards in the subrack, which realizes the 1:N protection for
the secondary power supply of each board.
l Detects the overvoltage (+3.8 V) and undervoltage (+3.1 V)
conditions for the +3.3 V backup power supply.
Audible alarm
Supports the audible alarm and the clearing of the audible alarm.
Ethernet port
connection status
checking
Supports the checking of the Ethernet port connection status.
Note: The COM interface is used for internal commissioning only. That is, the COM interface
cannot be used for equipment monitoring. Otherwise, the Ethernet communication between
boards may become abnormal.
Table 18-2 External time input interfaces

External Time Input
TOD-Related Interfacea
1pps-Related Interface
Channel 1
S1
S3 (using the RS422 level)
S1
ALMI4 (using the TTL level)
S2
Channel 2
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External Time Input
18 Auxiliary Boards
S2
ALMI4 (using the TTL level)
a: The TOD-related interfaces can use the RS232 level or RS422 level as required.
Table 18-3 External time input interfaces

External Time Output
Channel 1
S1
Channel 2
S2
a: The TOD-related interfaces can use the RS232 level or RS422 level as required.

The AUX consists of the communication module, interface module, and power module.
Figure 18-1 shows the functional block diagram of the AUX.
Figure 18-1 Functional block diagram of the AUX
Backplane
F&f
OAM
One orderwire phone
interface
Two NNI voice interfaces
S1~S4
F1
16-input and 4-output alarm
interfaces
2-input and 2-output clock
interfaces
SCC A
SCC B
Interface
module
Cross-connect
unit
Four channels of subrack

indicator interface
Alarm cascading interface
ETH interface
(VLAN A)
COM interface
(VLAN B)
100/10 Mbit/s
EXT interface
(VLAN B)
100/10 Mbit/s
100/10 Mbit/s
19x100/10 Mbit/s
Ethernet bus
Communication
module
100/10 Mbit/s
100/10 Mbit/s
Power supply
module
Other units (VLAN B)

SCC A (VLAN A)
SCC B (VLAN A)
-48 V/-60 V
+3.3 V backup
power supply
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Communication Module
This module provides the network management interface for the active and standby GSCC
boards, OAM interface for remote maintenance, and interface for communication between
boards.
Interface Module
This module provides various auxiliary interfaces, including the F&f interface, OAM interface,
F1 interface, and clock input\output interface.
Power Module
This module provides the working power supply for the board and centralized +3.3 V backup
power supply for the other boards.
18.1.5 Jumpers
The jumper J9 is available in the lower right corner of the side panel of the AUX. The jumper
J9 is used to specify the subrack that works as the main subrack or extended subrack.
Figure 18-2 and Figure 18-3 show the position of the jumper J9 on the AUX.
Figure 18-2 Position of the jumper J9 on the AUX(version B)
Power
Module
J9
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Figure 18-3 Position of the jumper J9 on the AUX(version C)
NOTE
The AUX is available in two versions: version B and version C. For the AUX of version C, jumper J9 is
under the daughter board. You can find it only after the daughter board is removed.
Set the jumper J9 as follows:

l
To enable the subrack to work as the main subrack, cap the jumper J9.
To enable the subrack to work as the extended subrack, do not cap the jumper J9.
18.1.6 Front Panel

The front panel of the AUX has indicators and interfaces of various types.

Figure 18-4 shows the appearance of the front panel of the AUX.
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Figure 18-4 Front panel of the AUX
AUX
STAT
CLKI2
CLKO2
CLKI1
CLKO1
CLK2
CLK1
ETH
REV
COM
F&f
EXT
F1
LAMP1
PHONE
LAMP2 ALMO1 ALMO2
V1
V2
OAM
ALMI1
S1
ALMI2
S2
ALMI3
S3
ALMI4
S4
AUX
Indicators
l
Interfaces
The front panel of the AUX has 28 interfaces. Table 18-4 describes the types and usage of the
interfaces of the AUX.
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Table 18-4 Interfaces of the AUX
Issue 03 (2013-02-20)
Interface
Type of
Interface
Usage
CLKO1
SMB
75-ohm clock output interface 1
CLKO2
SMB
75-ohm clock output interface 2
CLK1
RJ-45
120-ohm clock input/output interface 1
REV
RJ-45
Reserved
F&f
RJ-45
F&f interface
F1
RJ-45
F1 interface
PHONE
RJ-45
Orderwire phone interface
V1
RJ-45
NNI voice interface 1
V2
RJ-45
NNI voice interface 2
OAM
RJ-45
OAM interface
S1
RJ-45
Serial 1
S2
RJ-45
Serial 2
S3
RJ-45
Serial 3
S4
RJ-45
Serial 4
CLKI1
SMB
75-ohm clock input interface 1
CLKI2
SMB
75-ohm clock input interface 2
CLK2
RJ-45
120-ohm clock input/output interface 2
ETH
RJ-45
NM interface
COM
RJ-45
Commissioning interface
EXT
RJ-45
Interface for connection to the extended subrack
LAMP1
RJ-45
Cabinet alarm indicator output interface
LAMP2
RJ-45
Cabinet alarm indicator cascading input interface
ALMO1
RJ-45
Interface for the 1st to the 4th channels of alarm

outputs
ALMO2
RJ-45
Alarm signal cascading interface
ALMI1
RJ-45
Interface for the 1st to the 4th channels of alarm

inputs
ALMI2
RJ-45
Interface for the 5th to the 8th channels of alarm

inputs

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18 Auxiliary Boards
Interface
Type of
Interface
Usage
ALMI3
RJ-45

inputs
ALMI4
RJ-45

inputs
Note: S1/S3 and S2/S4 form a pair of time input and output interfaces.
Table 18-5 describes the pins of the CLK1 and CLK2 interfaces.
Table 18-5 Pins of the CLK1 and CLK2 interfaces
Front View
Pin
Usage
Receiving ()
Receiving (+)
Grounding
Transmitting ()
Transmitting (+)
Grounding
7, 8
Unspecified
Table 18-6 describes the pins of the ETH, COM, EXT, and F1 interfaces.
Table 18-6 Pins of the ETH, COM, EXT, and F1 interfaces
Front View
Pin
Usage
Transmitting (+)
Transmitting ()
Receiving (+)
Unspecified
Unspecified
Receiving ()
7, 8
Unspecified
Table 18-7 describes the pins of the F&f interface.

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18 Auxiliary Boards
Table 18-7 Pins of the F&f interface

Front View
Pin
Usage
Receive end for RS-232 data
Grounding
Transmit end for RS-232 data
1, 2, 3, 6, 7
Unspecified
Table 18-8 describes the pins of the PHONE, V1, and V2 interfaces.
Table 18-8 Pins of the PHONE, V1, and V2 interfaces
Front View
Pin
Usage
Signal 1
Signal 2
1, 2, 3, 6, 7, 8
Unspecified
Table 18-9 describes the pins of the LAMP1 and LAMP2 interfaces.
Table 18-9 Pins of the LAMP1 and LAMP2 interfaces
Front View
Issue 03 (2013-02-20)
Pin
Usage
Critical alarm signal (+)
Critical alarm signal ()
Major alarm signal (+)
Power indicator driving signal

(+)
Power indicator driving signal

()
Major alarm signal ()
Minor alarm signal (+)
Minor alarm signal ()

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18 Auxiliary Boards
Table 18-10 describes the pins of the ALM01 and ALM02 interfaces.
Table 18-10 Pins of the ALM01 and ALM02 interfaces
Front View
Pin
Usage
Critical and major alarm signal output

(+)
Critical and major alarm signal output

()
Minor and warning alarm signal output

(+)
Alarm signal output 1 (+)
Alarm signal output 1 ()
Minor and warning alarm signal output

()
Alarm signal output 1 ()
Table 18-11 describes the pins of the OAM interface.

Table 18-11 Pins of the OAM interface
Front View
Pin
Usage
Requests for transmission.
Transmits the DTE ready signal.
Transmits data.
Grounding
Grounding
Receives data.
Transmits the DCE ready signal.
Ready for receiving signals.
Table 18-12 describes the pins of the S1, S2, S3, and S4 interfaces.
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18 Auxiliary Boards
Table 18-12 Pins of the S1, S2, S3, and S4 interfaces of the AUX
Front View
Pin
Usage
RS-422 data transmitting (+)
RS-422 data transmitting ()
RS-422 data receiving (+)
Receive end for RS-232 data
Grounding
RS-422 data receiving ()
Unspecified
Transmit end for RS-232 data
Table 18-13 describes the pins of the ALMI1 interface.

Table 18-13 Pins of the ALMI1 interface
Front View
Pin
Usage
Alarm input 1
Ground for alarm input 1
Alarm input 2
Alarm input 3
Alarm input 4
Table 18-14 lists the pins of the ALMI2 interface.
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18 Auxiliary Boards

Front View
Pin
Usage
Alarm input 5
Alarm input 6
Alarm input 7
Alarm input 8

Front View
Pin
Usage
Alarm input 9
Alarm input 10
Alarm input 11
Alarm input 12
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18 Auxiliary Boards

Front View
Pin
Usage
Alarm input 13
Alarm input 14
Alarm input 15
Alarm input 16
Connections for Alarm Cascading

l
Connections for alarm signal cascading
Figure 18-5 shows the connections when one or multiple cabinets input or output alarm signals.
Connect the alarm output interface to the alarm cascading interface of a lower level. Make the
connections one by one until the alarm output is connected to the centralized alarm system.
Figure 18-5 Connections for alarm input, alarm cascading, and alarm output
Cabinet1
Cabinet2
Subrack1
Centralized
alarm system
Issue 03 (2013-02-20)
Subrack3
ALMO1
ALMO1
ALMO2
ALMO2
ALMI1
ALMI1
Subrack2
Subrack4
ALMO1
ALMO1
ALMO2
ALMO2
ALMI1
ALMI1
Connections of cabinet alarm indicators

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18 Auxiliary Boards
Figure 18-6 shows the connections of the 4-channel cabinet alarm indicators. Connect LAMP1
of subrack 2 to LAMP2 of subrack 1. Finally, connect LAMP1 of subrack 1 to the indicator
interface at the top of the cabinet.
Figure 18-6 Connections of cabinet alarm indicators
4 cabinet
alarm indicators
Cabinet indicator
subrack 1
LAMP1
LAMP2
subrack 2
LAMP1
LAMP2
18.1.7 Valid Slots

The AUX can be installed in slot 37 in the subrack.

The technical specifications of the AUX include the mechanical specifications and power
consumption.
The mechanical specifications of the AUX are as follows:
l
Weight: 1.0 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the AUX is 19 W.
18.2 FAN
technical specifications of the FAN (fan board).

The FAN is available in one functional version, namely, N1.
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18 Auxiliary Boards
The logical board of fan tray assembly XE1FAN is displayed as N1FAN on the U2000. The
XE1FAN is of the two-layer structure. The one-layer fan is no longer manufactured.
18.2.2 Application
The FAN is a system fan board. The FAN can be used on the OptiX OSN equipment series to
provide the heat dissipation function.

The FAN adjusts the fan speed, checks the fan status, reports the fault of the fan control board,
and reports the off-position alarm of the fan.
Table 18-17 provides the functions and features of the FAN.
Table 18-17 Functions and features of the FAN
Function and
Feature
FAN
Function of
intelligent speed
adjustment
Provides the following functions of intelligent speed adjustment:

l Automatically adjusts the fan speed.
When the temperature difference in the local area is more than
43C, the fans operate at low speed.
When the temperature difference in the local area is less than
43C, the fans operate at medium speed.
When the temperature difference in the local area is less than
33C, the fans operate at high speed.
l Ensures that the fan operates at full speed when the speed
adjustment signal is abnormal.
l In normal situations, all the fan tray assemblies operate normally.
When one fan tray assembly reports an alarm, the other fan tray
assemblies adjust the fan speed to operate at full speed.
Issue 03 (2013-02-20)
Hot swapping
function
Provides the hot swapping function for the fan tray assembly.
Backup function
Provides the mutual backup function for the power supplies of the fans
in the fan tray assemblies.
Status checking
Supports the checking of the fan status.
Alarm function
Reports the fan alarm and in-service information.
Fan backup
The two fans in the fan tray assembly function as a backup for each
other. The two fans operate at the same time. When one fan is faulty,
the other fan adjusts the speed to operate at full speed.

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18 Auxiliary Boards
NOTE
When one fan of the three fan tray assemblies fails, the system can work normally for 96 hours at
the ambient temperature ranging from 0C to 45C.
The fan tray assembly must be replaced when one of the following situations occurs.
l One or more fans in each fan tray assembly of the three fan tray assemblies are faulty.
l Two fans in a fan tray assembly are faulty.
When a fan tray assembly works normally, the upper fan and lower fan in the fan tray assembly
operate at the same speed.

The FAN consists of the fan control unit and fan power supply unit.
Figure 18-7 shows the functional block diagram of the XE1FAN.
Figure 18-7 Functional block diagram of the XE1FAN
Status signal
Speed adjusting signal
Status signal
Fan control
unit
Fan
Alarm signal
Power
Fan power
supply
unit

Fan Power Supply Unit

This unit provides the driving voltage for the fan to operate.
Fan Control Unit

The fan control unit controls the operation speed of the fan through the speed adjusting signal.
The fan control unit also detects its faults, faults in the fans, and faults in the fan power supply
unit. When detecting any fault, the fan control unit reports alarm information and the SCC then
issues commands to enable other fans to operate at full speed. The fan control unit also receives
commands from the SCC when the temperature is very low, and stops the fans. The fan control
unit detects the fault in the fan power supply unit, speed adjusting signal, fan state, and in-position
state of the FAN.
18.2.5 Front Panel

The front panel of the FAN has indicators.

The OptiX OSN equipment series use a modular fan platform.
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18 Auxiliary Boards
One subrack uses three fan tray assemblies, as shown in Figure 18-8.
Figure 18-8 Modular fan tray assembly
Indicators
The indicator (STATE) on the front panel of the board indicates the running state of the hardware.
This indicator is red, green, or yellow when it is on.
18.2.6 Valid Slots

The FAN can be installed in slots 3840 in the subrack.

The technical specifications of the FAN include the mechanical specifications, power
consumption, and working voltages.
The mechanical specifications of the FAN are as follows:
l
Weight of the XE1FAN: 1.5 kg
Weight of the XE3FAN:1.2 kg
Power Consumption
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE1FAN is 16 W when the input voltage is -48 V.
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18 Auxiliary Boards
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE3FAN is 16 W when the input voltage is -48 V.
Working Voltages
The working voltages of the FAN can be -48 V20% DC or -60 V20% DC.
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19
19 Optical Amplifier Boards and Dispersion Compensation

Boards
Optical Amplifier Boards and
Dispersion Compensation Boards
About This Chapter

This topic describes the optical amplifier boards and the dispersion compensation boards.
19.1 BA2
technical specifications of the BA2 (optical booster amplifier board).
19.2 BPA
technical specifications of the BPA (optical booster and pre-amplifier board).
19.3 COA
technical specifications of the COA (case-shaped optical amplifier).
19.4 RPC01
technical specifications of the RPC01 (forward Raman driving board).
19.5 RPC02
technical specifications of the RPC02 (backward Raman driving board).
19.6 OBU1
technical specifications of the TN11OBU1 (optical booster amplifier board).
19.7 DCU
technical specifications of the DCU (dispersion compensation board).
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Boards
19.1 BA2
technical specifications of the BA2 (optical booster amplifier board).

The BA2 is available in one functional version, namely, N1.
19.1.2 Application
The BA2 is a two-channel optical power amplifier board. The BA2 amplifies the power of optical
signals and is applicable to the long-distance optical fiber transmission.
Figure 19-1 shows the position of the BA in an optical transmission system.
Figure 19-1 Position of the BA in an optical transmission system
Tx
BA
Rx

During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA is required to ensure that the optical receiver can receive normal optical signals.
The BA2 amplifies the power of two-channel optical signals. Table 19-1 provides the functions
and features of the BA2.
Table 19-1 Functions and features of the BA2
Issue 03 (2013-02-20)
Function and
Feature
BA2
Basic functions
Increases the launched optical power of the line board to 1315 dBm
or 1518 dBm. As a result, when the G.652 optical fiber with a loss
of 0.275 dB/km is used, the transmission distance can be 120 km, 130
km, or above.

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Boards
Function and
Feature
BA2
Supporting the
EDFA
Supports the automatic control of the laser temperature and optical

power of the EDFA module.
Supports the automatic monitoring of the input and output optical
power of the EDFA module and query of the optical power of the
EDFA module.
Supports the protection function of the EDFA module. When no
optical signals are received, the laser is automatically turned off.
When optical signals are received, the laser is automatically turned
on.
Performance events
and alarms
monitoring
Supports the reporting of the performance parameters of the laser.

Software upgrade
Supports the software upgrade and expansion without interrupting

services.
CAUTION
The wavelength of the optical signal transmitted to the BA2 must be within the range from 1530
nm to 1565 nm. Otherwise, the input optical signal cannot be amplified correctly. Hence, make
sure that the output wavelength of the line board that is interconnected with the BA2 is within
the required range.
NOTE
The BA2 provides the intelligent power adjustment (IPA) function. When the IPA function is enabled and
no input signals are detected on the receive side of a line board, the pumping laser is turned off to prevent
high laser power from damaging the eyes.

The BA2 consists of the EDFA module, control module, communication module, and DC/DC
converter module.
Figure 19-2 shows the functional block diagram of the BA2.
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Boards
Figure 19-2 Functional block diagram of the BA2

Optical
input
Fiber
distributor
EDFA module
Doped
erbium
fiber
WDM
Input
Output
isolate
isolate
coupler
Input
power
monitor
(Pin1)
Input
power
Optical
splitter
Filter
Optical
output
Output
power
monitor
(Pin2)
Laser pump
Pump Pump Temperat

current
ure
current detect
Laser
shutdown
Manual
LOS in
control
AD/DA
Output
power
Pump
temperature
control
Control&Generation alarms
Control module
Communication
module
+3.3 V
DC/DC
converter
module
DC/DC
converter
module
Communication
SCC unit
Fuse
-48 V/ -60 V
-48 V/ -60 V
Fuse
+3.3 V
backup
power
EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.
Control Module
The control module performs the following functions:
l
Detects and drives bump electricity.
Controls the temperature of the bump laser.
Detects the input and output power.
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Boards
Reports alarms.
The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25C. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25C.
The communication module supports Ethernet communication.
DC/DC Converter Module

require.
19.1.5 Front Panel

The front panel of the BA2 has indicators and interfaces.

The BA2 is available in two types, namely, one-interface BA2 and two-interface BA2.
Figure 19-3 shows the appearance of the front panel of the one-interface BA2.
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Figure 19-3 Front panel of the one-interface BA2
BA2
STAT
ACT
PROG
SRV
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT1
IN1
BA2
Figure 19-4 shows the appearance of the front panel of the two-interface BA2.
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Figure 19-4 Front panel of the two-interface BA2
BA2
STAT
ACT
PROG
SRV
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
OUT1
IN1
OUT2 IN2
BA2
Indicators
l
Interfaces
The front panel of the one-interface BA2 has one optical interface. The optical interface transmits
and receives one channel of optical signals. The one-interface BA2 uses the swappable optical
module, which facilitates the maintenance and upgrading of the optical module.
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The front panel of the two-interface BA2 has two optical interfaces. The optical interfaces
transmit and receive two channels of optical signals. The two-interface BA2 uses the swappable
optical module, which facilitates the maintenance and upgrading of the optical module.
WARNING
If the front panel of the one-interface BA2 has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the BA2 whose front panel has two LC optical
interfaces, determine whether the BA2 is a one-interface BA2 or a two-interface BA2 according
to 19.1.7 Feature Code.
Table 19-2 describes the type and usage of the optical interface of the one-interface BA2.
Table 19-2 Optical interface of the one-interface BA2
Interface
Type of
Interface
Usage
IN
LC
OUT
LC
Table 19-3 describes the types and usage of the optical interfaces of the two-interface BA2.
Table 19-3 Optical interfaces of the two-interface BA2
Interface
Type of Interface
Usage
IN1
LC
Receives the first channel of optical signals.
OUT1
LC
Transmits the first channel of optical signals.
IN2
LC
Receives the second channel of optical signals.
OUT2
LC
Transmits the second channel of optical signals.
19.1.6 Valid Slots

The slots valid for the BA2 vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the BA2 are as follows:

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When the cross-connect capacity is 200 Gbit/s, the BA2 can be installed in slots 18 and
19.1.7 Feature Code

The feature code of the BA2 indicates the output optical power of the optical interfaces.
Table 19-4 provides the relationship between the feature code of the BA2 and the output optical
power.
Table 19-4 Relationship between the feature code of the BA2 and the output optical power
Board
Feature Code
Output Optical Power
SSN1BA201
01
Dual-channel optical power

amplification: 14 dBm
SSN1BA202
02

amplification: 17 dBm
SSN1BA203
03
Optical power amplification:

14 dBm
SSN1BA204
04
Optical power amplification:

17 dBm
SSN1BA205
05

amplification: 14 dBm and 17
dBm

The technical specifications of the BA2 include the parameters specified for optical interfaces,

Table 19-5 lists the parameters specified for the optical interfaces of the BA2.
Table 19-5 Parameters specified for the optical interfaces of the BA2
Issue 03 (2013-02-20)
Parameter
Value
Nominal bit rate
2488320 kbit/s and 9953280 kbit/s
Application code
V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2
Line code pattern
NRZ
Input wavelength (nm)
BA: 1530 to 1565
Input optical power

(dBm)
BA: -6 to +3

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Parameter
Value
Output optical power

(dBm)
BA: 13 to 15 or 15 to 17
Noise figure (dB)
BA: < 6.5
Laser Safety Class

The mechanical specifications of the BA2 are as follows:
l
Weight (kg): 1.0
Power Consumption
The maximum power consumption of the BA2 at room temperature (25C) is 20 W.
19.2 BPA
technical specifications of the BPA (optical booster and pre-amplifier board).

The BPA is available in the following functional versions: N1 and N2. The N1BPA is
discontinued.
Table 19-6 describes the versions of the BPA.
Table 19-6 Versions of the BPA
Issue 03 (2013-02-20)
Item
Description
Functional Versions
The BPA is available in two functional versions, namely, N1

and N2.
Differences
The N1BPA consists of two EDFA optical modules, whereas

the N2BPA has only one EDFA optical module.

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Item
Description
Substitution
The two versions can substitute for each other when certain
conditions are met. If the ALS function is required and the
N2BPA is used to substitute for the N1BPA, enable the ALS
function on the N2BPA. If the ALS function is required and the
N1BPA is used to substitute for the N2BPA, enable the ALS
function on the line board. If the ALS function is not required,
this restriction is not applicable.
19.2.2 Application
The BPA is an optical booster and pre-amplifier board. The BPA provides a BA and a PA, which
are respectively used at the transmit end and receive end of the OptiX OSN equipment.
Figure 19-5 shows the position of the BA and PA in an optical transmission system.
Figure 19-5 Position of the BA and PA in an optical transmission system
Optical
transmitter
BA
PA
Optical
receiver
1550.12nm

During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA and PA are required to ensure that the optical receiver can receive normal optical signals.
Table 19-7 provides the functions and features of the BPA.
Table 19-7 Functions and features of the BPA
Issue 03 (2013-02-20)
Function and
Feature
BPA
Basic functions
Increases the launched optical power of the line board to 1315

dBm or 1517 dBm. As a result, when the G.652 optical fiber with
a loss of 0.275 dB/km is used, the transmission distance can be 120
km, 130 km, or above.
Pre-amplification
function
Provides the PA module to pre-amplify the received optical signals.

Increases the power of the small-volume optical signals by 22-25
dB (N1BPA) or 22-33 dB (N2BPA) so that the sensitivity of the
receiver increases to -38 dBm.

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Function and
Feature
BPA
Supporting the EDFA
l Supports the automatic control of the laser temperature and

optical power of the EDFA module.
l Supports the automatic monitoring of the input and output
optical power of the EDFA module and query of the optical
power of the EDFA module.
l Supports the protection function of the EDFA module. When
no optical signals are received, the laser is automatically turned
off. When optical signals are received, the laser is automatically
turned on.
Performance events
and alarms monitoring
Supports the reporting of the performance parameters of the laser.

Reports various alarms and performance events, which facilitates
the management and maintenance of the equipment.
Software upgrade
Supports the software upgrade and expansion without interrupting

services.

The BPA consists of the optical part, driving and detecting part, and data processing and
communication part.
Figure 19-6 shows the functional block diagram of the N1BPA.
Figure 19-6 Functional block diagram of the N1BPA
Optical input
Optical output
Optical input
Pump current
check
Drive
module
Optical
part
EDFA optical module 2
EDFA optical module 1
Module
temperature
control
Optical output
Input/output
power
check
Pump
Drive
current
module
check
Module
temperature
control
Input
power
check
Output
power
check
Driving
and
detecting
Fixed filter
part
A/D or D/A conversion
SCC
Communication
module
Control
module
Data processing and

communication part
Figure 19-7 shows the functional block diagram of the N2BPA.
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Figure 19-7 Functional block diagram of the N2BPA

Optical input
Optical output
Optical input
Optical output
Fixed
filter
For pre-amplification
Optical part
EDFA optical module
Pump current
check
Drive
module
Module
temperature
control
Input/output
power
check
Pump
current
check
Module
Drive
temperature
module
control
Input/output
power
check
Driving and
detecting part
SCC
Communication
module
Control
module
Data processing and

communication part
Optical Part
The N1BPA consists of two EDFA optical modules. The N2BPA has only one EDFA optical
module. The EDFA optical module magnifies the optical power.
Driving and Detecting Part

The driving and detecting part provides the EDFA optical module with the driving current. It
also checks the working status of each part in the EDFA optical module. In addition, it predicts
and handles possible faults.
The driving and detecting part performs the following functions: checking the pump current,
driving the optical module, controlling the temperature of the optical module, and checking the
input and output optical power.
Data Processing and Communication Part

The data processing and communication part consists of the CPU and peripheral chips. The data
processing and communication part analyzes the test result of the tested circuit. Then, it adjusts
the driving circuit based on the analysis result so that the gain or output optical power of the
EDFA optical module remains in the range of the rated value. It also classifies the abnormal
states represented by the measured values and reports the abnormal states to the NMS.
19.2.5 Front Panel

The front panel of the BPA has indicators, interfaces, and a laser safety class label.

Figure 19-8 shows the appearance of the front panel of the BPA.
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Figure 19-8 Front panel of the BPA
BPA
STAT
ACT
PROG
SRV
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
BOUT
BIN
POUT
PIN
BPA
Indicators
l
Interfaces
The front panel of the BPA has two LC optical interfaces. Table 19-8 describes the types and
usage of the optical interfaces of the BPA.
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Table 19-8 Optical interfaces of the BPA

Interface
Type of
Interface
Usage
BIN
LC
Receives one channel of optical signals for

amplification.
BOUT
LC
Transmits one channel of amplified optical signals.
PIN
LC
Receives one channel of optical signals for preamplification.
POUT
LC
Transmits one channel of pre-amplified optical

signals.
19.2.6 Valid Slots

The slots valid for the BPA vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the BPA are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the BPA can be installed in slots 18 and
19.2.7 Feature Code

The feature code of the BPA indicates the output optical power of the optical interfaces.
Table 19-9 provides the relationship between the feature code of the BPA and the output optical
power.
Table 19-9 Relationship between the feature code of the BPA and the output optical power
Issue 03 (2013-02-20)
Board
Feature Code
Description
SSN1BPA01 and
SSN2BPA01
01
The output optical power of the BA

module is 14 dBm.
SSN1BPA02
02
The output optical power of the BA

module is 17 dBm.

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The technical specifications of the BPA include the parameters specified for optical interfaces,

Table 19-10 lists the parameters specified for the optical interfaces of the BPA.
Table 19-10 Parameters specified for the optical interfaces of the BPA
Parameter
Value
Nominal bit rate
2488320 kbit/s or 9953280 kbit/s
Application code
V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2
Line code pattern
NRZ
Input wavelength (nm)
BA: 1530 to 1565

PA: 1550.12
Input optical power

(dBm)
BA: -6 to +3
Output optical power

(dBm)
N1BPA: 13 to 15 or 15 to 17 (BA)
PA: -44 to -10
N1BPA: -16 to +15 (PA)

N2BPA: 13 to 15 (BA)
N2BPA: -16 to +23 (PA)
Noise figure (dB)
BA: < 6.5

PA: < 6
Signal gain (dB)
N1BPA: +22 to +25 (PA)

N2BPA: +22 to +33 (PA)
NOTE
When you perform a loopback on the PA module of the BPA, prevent the damage caused by high input
optical power to the optical module.
Laser Safety Class

The mechanical specifications of the BPA are as follows:
l
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1326

Weight of the N1BPA (kg): 1.0
Weight of the N2BPA (kg): 1.2

Boards
Power Consumption
The maximum power consumption of the N1BPA at room temperature (25C) is 20 W.
The maximum power consumption of the N2BPA at room temperature (25C) is 11 W.
19.3 COA
technical specifications of the COA (case-shaped optical amplifier).

The COA is available in three functional versions, namely, 61, 62, and N1.
The working principle of the 62COA is basically the same as the working principle of the 61COA
or N1COA. The difference between the 62COA and the 61COA (N1COA) is with regard to the
used optical amplifier modules. The 62COA uses the Raman optical amplifier module, whereas
the 61COA and N1COA use the EDFA optical amplifier module.
NOTE
The COA that occurs in the following text includes the 61COA, N1COA, and 62COA. The characteristics
of the COA are the common characteristics of the three types of COAs.
Table 19-11 describes the versions of the COA.

Table 19-11 Versions of the COA
Item
Description
Functional versions
The COA is available in three functional versions, namely, 61, 62, and
N1.
Differences
The 61COA can function as a BA or a PA. The BA is the EDFA optical

amplifier in the 1530 nm to 1560 nm fiber communication window;
the PA is the EDFA optical amplifier in the 1550 nm fiber
communication window.
The N1COA can function as a PA. The PA is the EDFA optical
amplifier in the 1530 nm to 1560 nm fiber communication window.
The N1COA does not have a filter and is a multi-wavelength amplifier.
The 62COA uses the Raman optical amplifier module.
Substitution
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The versions cannot be substituted with each other.

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19.3.2 Application
The COA is a case-shaped optical amplifier that is not installed in a slot of the subrack. The
COA is mainly used to amplify optical signals and is applicable to the long-distance optical fiber
transmission.
The application of the COA is the same as that of the BA and PA on the OptiX OSN equipment
series. For details, see Figure 19-5.

The COA integrates the optical amplifier module, the driving circuit, and the communication
circuit in an aluminium case.
The COA is an external and independent amplifier and does not occupy a slot in the subrack.
The COA can work independently. The equipment supports a maximum of two 61COAs, two
N1COAs, or one 62COA.
61COA and N1COA

The 61COA/N1COA is equipped with only one EDFA optical module. The 61COA/N1COA
can work as a power amplifier, a pre-amplifier, or a line amplifier. Figure 19-9 shows the
appearance of the 61COA/N1COA.
The optical characteristics of the 61COA/N1COA are the same as the optical characteristics of
the optical amplifier boards such as the BPA and BA2. The difference between the 61COA/
N1COA and the optical amplifier boards is that the 61COA/N1COA is an external optical
amplifier unit, which does not occupy a slot in the subrack. The 61COA/N1COA can be directly
installed in the ETSI cabinet but requires separate power supply.
Figure 19-9 Appearance of the 61COA/N1COA (PA)
The application of the 61COA/N1COA in the optical transmission system is the same as the
application of the BA2 and BPA in the optical transmission system. Table 19-12 provides the
functions and features of the 61COA/N1COA.
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Table 19-12 Functions and features of the 61COA/N1COA

Function and
Feature
61COA/N1COA
Power amplification
function
The 61COA increases the launched optical power of the line board.
As a result, the valid transmission distance of optical signals is
extended.
Pre-amplification
function
The 61COA/N1COA provides the pre-amplification function.
ALS function
Supports the ALS function.
Communication
through serial ports
Communicates with the GSCC through the RS-232 serial port,

reports the alarms and performance events of the COA to the NMS,
and receives the configuration commands issued by the NMS.
62COA
The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the SDH
equipment.
The 62COA transmits counter-propagated pumping optical signals to fibers for distributed
Raman amplification. The gain medium of distributed Raman amplification is the line fiber that
can realize better noise performance. This is different from the 61COA. Hence, the 62COA can
extend the transmission distance, reduce the signal-to-noise ratio, and realize ultra long hop
transmission for a single span.
Figure 19-10 shows the appearance of the 62COA.
Figure 19-10 Appearance of the 62COA
4
2
3
1. Captive screw
4. ESD jack
Issue 03 (2013-02-20)
2. Ejector lever
5. Power access board
3. COA board

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The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the optical
transmission system. The optical signals are amplified during transmission based on the
stimulated Raman scattering effect of the fiber. The 62COA needs to work with the EDFA to
realize the transmission of optical signals for more than 170 km. For details, see Figure
19-11.
Figure 19-11 Application of the 62COA
Raman amplifier
Signal light
EDFA
Pump light
Pump light
Fiber
Transmitting end
EDFA
Laser
Coupler
Receiving end
The Raman amplifier amplifies optical signals during transmission by transmitting counterpropagated pumping optical signals to fibers for distributed Raman amplification. As a result,
the phase of optical signals is significantly different from the phase of pump signals. The power
fluctuation of the Raman pumping is offset in the counter-propagation. Hence, the noise caused
by the pump can be effectively suppressed.
Table 19-13 provides the functions and features of the 62COA.
Table 19-13 Functions and features of the 62COA
Function and
Feature
62COA
Basic functions
Is configured at the receive end of the SDH system, and realizes

extra long-haul transmission (more than 170 km) when working
with an EDFA whose output power is 17 dBm at the transmit end.
Pre-amplification
function
The 62COA provides the pre-amplification function.
ALS function
Supports the ALS function.
Communication
through serial ports
Communicates with the GSCC through the RS-232 serial port,

reports the alarms and performance events of the COA to the NMS,
and receives the configuration commands issued by the NMS.

The 61COA and N1COA consist of the EDFA module, control module, communication module,
and DC/DC converter module.
The working principle of the N1COA is similar to the working principle of the 61COA. The
61COA has the filter unit, whereas the N1COA does not have the filter unit.
Figure 19-12 shows the functional block diagram of the 61COA/N1COA.
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Figure 19-12 Functional block diagram of the 61COA/N1COA

Optical output
Optical input
Fixed
filter
For pre-amplification
EDFA optical
module
Pump
power check
Drive
module
Module
temperature
control
Optical part
Input/Output
Power check
Driving and
detecting part
SCC
Communication
module
Control
module
Data processing and

communication part
EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.
Control Module
The control module performs the following functions:
l
Detects and drives bump electricity.
Controls the temperature of the bump laser.
Detects the input and output power.
Reports alarms.
The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
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controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25C. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25C.
The communication module supports Ethernet communication.
DC/DC Converter Module

require.
19.3.5 Front Panel

The front panel of the COA has indicators and interfaces.

Figure 19-13 shows the appearance of the front panel of the 61COA/N1COA.
Figure 19-13 Front panel of the 61COA/N1COA
9
10
1. ID DIP switch
2. Running indicator
4. RS-232-1
7. MONITOR-2
5. RS-232-2
6. MONITOR-1
8. IN: input optical interface
9. OUT: output optical interface 10. Power switch
11
3. Alarm indicator
11. -48 V power interface
Figure 19-14 shows the appearance of the front panel of the 62COA.
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Figure 19-14 Front panel of the 62COA
1. SC/PC optical interface (OUT)
2. LSH optical interface (IN)
3. Air filter
4. Fan board
5. RJ-45 interface
6. RS-232-1
7. RS-232-2
8. DIP switch (bits 8-5)
9. DIP switch (bits 4-1)
10. Power input interface
11. Power switch
Indicators
l
Board running status indicator (RUN) one color (green)
Fan alarm indicator (ALM) one color (red)
Interfaces
The front panel of the 61COA/N1COA has one SC/PC optical interface. The optical interface
receives and transmits one channel of optical signals. The input optical interface of the 62COA
is connected to the LSH flange and the output optical interface is connected to the SC flange.
Figure 19-15 shows the SC/PC fiber connector that the SC/PC optical interfaces of the 61COA
and N1COA use.
Figure 19-15 SC/PC fiber connector
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Figure 19-16 shows the flange and fiber connector that the input optical interface of the 62COA
uses.
Figure 19-16 LSH flange and fiber connector
NOTE
The protective cap of the LSH fiber jumper is specially designed. When you connect the LSH fiber jumper
to an LSH flange, do not remove the protective cap but insert the LSH fiber jumper into the LSH flange
directly.
The COA has two RS-232 serial ports, which function as the control and communication ports.
The serial ports communicate with the SCC unit and report alarms and performance events.
Table 19-14 provides the pin assignments of the RS-232 serial port.
Table 19-14 Pin assignments of the RS-232 serial port
Front View
Pin of RS-232-2
Definition
Used to receive
data.
Used to transmit
data.
Used for common

grounding.
Pin of RS-232-1
TIP
To realize the communication between the COA and the GSCC, use a serial port control line to connect
the RS-232-1 serial port of the COA to the F&f port of the subrack.
The RS-232-2 serial port is used in the scenario where several COAs are used at a single station.
To enable each COA to communicate with the SCC unit, use a serial port line to connect the
RS-232-2 port of COA 1 to the RS-232-1 port of COA 2, and use another serial port line to
connect the RS-232-2 port of COA 2 to the RS-232-1 port of COA 3. Connect the other COAs
similarly. In this case, each COA communicates with the SCC unit through the RS-232-1 serial
port of COA 1.
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NOTE
When you cascade COAs, set the last four digits of the DIP switch on the front panel of each COA to a
unique value. The values are used to identify the COAs. One OptiX OSN 3500 subrack supports a maximum
of two COAs. When bit 1 of the DIP switch is set downwards, the logical slot of the COA on the NMS is
slot 101. When bit 2 of the DIP switch is set downwards, the logical slot of the COA on the NMS is slot
102.
The COA has two MONITOR interfaces. When the 61COA is used alone, the MONITOR-1
interface and MONITOR-2 interface are the alarm output interfaces. In this case, the two
MONITOR interfaces have the same functions. Table 19-15 provides the pin assignments of
the MONITOR interfaces.
Table 19-15 Pin assignments of the MONITOR interfaces
Front View
Pin of
MONITOR-2
Definition
1 and 6
1 and 6
The input optical power of the

EDFA module is very low.
2 and 7
2 and 7
The working current of the pump

laser of the EDFA module
exceeds the threshold.
3 and 8
3 and 8
The cooling current of the pump

laser of the EDFA module
exceeds the threshold.
4 and 9
4 and 9
The ambient temperature of the

EDFA module exceeds the
threshold.
Digital ground
Pin of
MONITOR1
The 62COA has one RJ45 connector, through which the 62COA is connected to the computer
for software loading. Table 19-16 provides the pin assignments of the RJ45 connector of the
62COA.
Table 19-16 Pin assignments of the RJ45 connector of the 62COA
Front View
8 7 6 5 4 3 2 1
Issue 03 (2013-02-20)
Pin
Description
Transmitting (+)
Transmitting ()
Receiving (+)
Not defined
Not defined
Receiving ()

1335

Front View

Boards
Pin
Description
78
Not defined
The COA has one 48 V power interface. The 48 V power interface receives the 48 V power
provided by the PIU in the OptiX OSN 3500 subrack or the PDU at the top of the cabinet. The
working voltage under normal working conditions ranges from 38.4 V to 57.6 V (48 V20%).
The COA has one DIP switch.
l
The DIP switches of the 61COA/N1COA are in the lower left corner of the front panel.
The DIP switches are used to set the ID of the 61COA/N1COA. When a bit of the DIP
switch is set upwards, the bit is in the OFF position. When the bit is set downwards, the bit
is in the ON position. The SCC identifies a 61COA/N1COA through the ID of the 61COA/
N1COA. The SCC communicates with the 61COAs/N1COAs whose IDs are different in
the master-slave calling mode.
The DIP switch of the 62COA is used to set the ID of the 62COA and the type of fiber.
The DIP switch has eight bits. The bit on the leftmost side is numbered "8" and the bit on
the rightmost side is numbered "1". When a bit of the DIP switch is set upwards, the bit
indicates "0". When the bit is set downwards, the bit indicates "1". The first four bits (1
4) are used to set the board ID, which ranges from 20 to 35. In actual situations, the first
four bits indicate only the range from 20 to 27. The fifth bit is used to set the type of fiber.
When bit 5 indicates "0", the fiber is of the G.652 type. When bit 5 indicates "1", the fiber
is of the G.655 type.
19.3.6 Valid Slots

The COA adopts the case-shape design. Hence, the COA does not require a slot in the subrack.
In the ETSI cabinet, the 61COA or N1COA is installed on a special bracket, and the 62COA is
installed directly in the cabinet through the mounting ears. On the NMS, the logical slots of the
61COA, N1COA, and 62COA are slots 101 and 102.
Installation Position of the 61COA or N1COA

The installation of the 61COA is considered as an example. The bracket is fixed on the crossbars
on both sides of the cabinet. There are guide rails on the bracket. The 61COA is pushed onto
the bracket along the guide rails and is fixed on the bracket. One bracket can hold two 61COAs
horizontally. The front panels of the two 61COAs are on the front side of the cabinet, as shown
in Figure 19-17.
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Figure 19-17 Position of the 61COA in the ETSI cabinet
Installation Position of the 62COA

The case-shaped 62COA can be installed in the 300 mm or 600 mm ETSI cabinet through
mounting ears and screws. If the upward-wiring scheme is applied, the 62COA is installed at
the bottom of the ETSI cabinet (positions of the first and third floating nuts). If the downwardwiring scheme is applied, the 62COA is installed in any idle place of the 2.6 m high cabinet or
in the ETSI cabinet that is not fully configured.
19.3.7 Feature Code

The feature code of the 61COA indicates the output optical power of the optical interfaces.
Table 19-17 provides the relationship between the feature code of the 61COA and the output
optical power.
Table 19-17 Relationship between the feature code of the 61COA and the output optical power
Board
Feature Code
Description
SS61COA01
01
The output optical power of the

BA module is 14 dBm.
SS61COA02
02
The output optical power of the

BA module is 17 dBm.

The technical specifications of the COA include the parameters specified for optical interfaces,

Table 19-18 lists the parameters specified for the optical interfaces of the COA.
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Table 19-18 Parameters specified for the optical interfaces of the COA
Parameter
Value
61COA
Line code pattern
NRZ
Operating
wavelength range
(nm)
1550
Input optical power

range (dBm)
BA: -6 to +3
N1COA
62COA
1550.12
-10 to -37
-43 to -20
(The LOS alarm is reported
when the input optical
power reaches -45 dBm.)
15 to 17
> 23
13
PA: -28 to -10 (when

the BPA works with
the line board at the
rate of 10 Gbit/s)
PA: -38 to -10 (when
the BPA works with
rate less than 10 Gbit/
s)
Launched optical
power range (dBm)
BA14: 13 to 15
BA17: 15 to 17
PA: -2 to +16 (when
the BPA works with
rate of 10 Gbit/s)
PA: -12 to +16 (when
the BPA works with
rate less than 10 Gbit/
s)
NOTE
"BA14" indicates that
the output optical power
of a BA is always 14
dBm.
"BA17" indicates that
the output optical power
of a BA is always 17
dBm.
Issue 03 (2013-02-20)
Signal gain (dB)
PA: > 26
Pump wavelength
(nm)
1451.2
Maximum on/off
gain (dB)
> 15 (in the case of the G.

652 fiber)

1338

Parameter

Boards
Value
61COA
Noise figure (dB)
N1COA
BA14: < 7
62COA
< -1.5
BA17: < 7
PA: < 5
Laser Safety Class

The mechanical specifications of the 61COA and N1COA are as follows:
l
Dimensions (mm): 240 (W) x 190 (D) x 50 (H)
Weight (kg): 3.5
The mechanical specifications of the 62COA are as follows:

l
Dimensions (mm): 294 (W) x 436 (D) x 86 (H)
Weight (kg): 8.0
Power Consumption
The maximum power consumption of the 61COA at room temperature (25C) is 10 W.
The maximum power consumption of the 62COA at room temperature (25C) is 75 W.
The maximum power consumption of the N1COA at room temperature (25C) is 10 W.
19.4 RPC01
technical specifications of the RPC01 (forward Raman driving board).

The RPC01 is available in one functional version, namely, N1.
19.4.2 Application
The RPC01 is an external forward Raman driving board that must work with the EDFA.
Figure 19-18 shows the position of the RPC01 in an optical transmission system.
Figure 19-18 Position of the RPC01 in an optical transmission system
Transmitting
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RPC01
Receiving

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The RPC01 supports the online optical performance monitoring function and other functions.
Table 19-19 provides the functions and features of the RPC01.
Table 19-19 Functions and features of the RPC01
Function and
Feature
RPC01
Basic functions
l Generates multi-channel pump light of high power, which

provides energy for the amplification of signals in the fiber.
l Realizes the distributed online amplification of signals over long
distance with wide bandwidth and low noise.
Online optical
performance
monitoring function
Provides the online monitoring interface. A small amount of optical

signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.
Performance events
and alarms
monitoring
l Detects the pump optical power, temperature control current,

pump current, and back facet current.
l Supports the setting of the LOS value to disable the output port of
the laser.

The RPC01 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
The RPC01 is used at the transmit end of the system. The RPC01 utilizes the stimulated Raman
scattering effect of the fiber to amplify the optical signals during transmission.
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Figure 19-19 Functional block diagram of the RPC01 (forward pump)

Splitter Signal light
Signal light
LINE
Pump light
Pump source
Control the
pumping current
and temperature.
SYS
MON
Raman pump optical module
Detect the pump

light power and
current.
PIN
Detect the
temperature.
Driving and detecting module
Control
Memory
CPU
Communication

Power supply
module
Fuse
Voltages required
by the board
DC power provided
by the backplane
SCC
Backplane
(controlled by
the SCC)
Signal Flow
The signal light is received at the SYS interface and transmitted to the optical line through the
LINE interface. A few supervisory signals are transmitted to the test instrument through the
MON interface for online optical performance monitoring. The pump light that is generated by
the RPC01 is transmitted to the optical line through the LINE interface in the same direction of
the signal light, to realize the distributed amplification of the optical signal. The Ethernet
interface of the RPC01 is connected to the COM interface of an NE directly or through a hub to
realize the communication with the SCC.
Functional Modules
l

The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.
The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.
l
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Detects the optical power of the service signals in real time.

Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.
Drives the pump laser inside the pump optical module.
Reports alarms and performance events to the logic and control module.
l

Controls the operations on the board.
Controls the operations on each module of the board according to the CPU instructions.
Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.
Communicates with the SCC.
Power supply module

Converts the DC power provided by the backplane into the power required by each module
of the board.
19.4.5 Front Panel

The front panel of the RPC01 has indicators, interfaces, and a laser safety class label.

Figure 19-20 shows the appearance of the front panel of the RPC01.
Figure 19-20 Front panel of the RPC01
03793010860000002 Y SSN1 RPC 01
Board manufacturing
information
MON
SYS
Board serial
number and name
LINE
LASER
RADIATION
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
SCATTERED RADIATION
CRPC
CLASS 4 LASER
PRODUCT
ALM
RUN
WARNING: FIBERS MUST

BE CONNECTED SEFORE
POWER UP
RS232-1
RS232-2
LAN
Indicators
l

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Interfaces
The front panel of the RPC01 has six interfaces. Table 19-20 describes the types and usage of
the interfaces of the RPC01.
Table 19-20 Interfaces of the RPC01
Interface
Type of
Interface
Usage
LINE
LSH/APC
Transmits the amplified signals to the fibers.
SYS
LC
Is connected to the BA and receives the optical signals

transmitted from the BA.
NOTE
The permissible input power for the SYS interface on the
RPC01 board ranges from +5 dBm to +8 dBm. Therefore,
when the output power of a BA is +14 dBm or +17 dBm, you
need to add an optical attenuator ranging from 5 dB to 10 dB
in front of the SYS interface.
MON
LC
Monitors the optical performance.

The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.
LAN
RJ-45
Is connected to the COM interface of an NE directly or

through a hub to realize the communication with the
SCC.
RS232-1/
RS232-2
Is an RS-232 communication interface.
19.4.6 Valid Slots

The RPC01 is an external forward Raman driving board. Hence, the RPC01 is not installed in
the subrack. The RPC01 is connected to the COM interface of an NE directly or through a hub
to realize the communication with the SCC. The logical slot of the RPC01 on the NMS is slot
104.
NOTE
Only two logical slots are designed for the RPC, one for monitoring the RPC01 (using logical slot 104)
and the other for monitoring the RPC02 (using logical slot 105). Otherwise, an IP address conflict occurs.

The RPC01 has two groups of jumpers, namely, group J3 and group J4.
Figure 19-21 shows the jumpers of the RPC01.
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Figure 19-21 Jumpers of the RPC01

RPC01
10
10
J3
J4
CPU
To ensure that the board can operate normally, set the jumpers as follows:
l
Short-circuit jumpers 1 and 2 of group J4.
19.4.8 Feature Code

The feature code of the RPC01 contains three characters, which indicate the gain of the optical
signal processed by the RPC01.
Table 19-21 describes the feature code of the RPC01.
Table 19-21 Feature code of the RPC01
Feature Code
Indication
Description
The first character
Is always "G".
The second and third

characters
Gain
Indicates the gain.
Consider the N1RPC01 whose feature code is "G10" as an example. "G10" indicates that the
maximum gain of the optical signal is 10 dB.

You can set the parameters for the RPC01 by using the U2000.
You can set the following parameters for the RPC01 by using the U2000:
l
Laser status
Board work type
Fixed Pump Optical Power (dBm)
Min. Fixed Pump Optical Power (dBm)
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Max. Fixed Pump Optical Power (dBm)
For the description of each parameter, see 27.9 Optical Amplifier Boards.
Interface Display
Table 19-22 shows the serial numbers of the optical interfaces on the front panel of the RPC01
on the NMS.
Table 19-22 Serial numbers of the optical interfaces on the front panel of the RPC01 on the
NMS
Interface on the Front Panel
Serial Number of the NMS Interface
LINE
SYS
MON

The technical specifications of the RPC01 include the parameters specified for optical interfaces,

Table 19-23 lists the parameters specified for the optical interfaces of the RPC01.
Table 19-23 Parameters specified for the optical interfaces of the RPC01
Issue 03 (2013-02-20)
Parameter
Value
Pump wavelength (nm)
1400 to 1500
Operating wavelength (nm)
1529 to 1561
Maximum pump power (dBm)
29
Gain on the G.652 fiber (dB)
10
Gain on the LEAF fiber (dB)
12
Equivalent noise figure on the G.652 fiber

(dB)
Equivalent noise figure on the LEAF fiber

(dB)
-1
Polarization dependent loss (dB)
0.5
Type of output connector
LSH/APC or LC/PC

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Laser Safety Class

the optical interfaces is more than 27 dBm (500 mW).
l
Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)
Weight (kg): 4.0
Power Consumption
The maximum power consumption of the RPC01 at room temperature (25C) is 70 W.
19.5 RPC02
technical specifications of the RPC02 (backward Raman driving board).

The RPC02 is available in one functional version, namely, N1.
19.5.2 Application
The RPC02 is an external backward Raman driving board that must work with the EDFA.
Figure 19-22 shows the position of the RPC02 in an optical transmission system.
Figure 19-22 Position of the RPC02 in an optical transmission system
Transmitting
RPC02
Receiving

The RPC02 supports the online optical performance monitoring function and other functions.
Table 19-24 provides the functions and features of the RPC02.
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Boards
Table 19-24 Functions and features of the RPC02

Function and
Feature
RPC02
Basic functions
l Generates multi-channel pump light of high power, which

provides energy for the amplification of signals in the fiber.
l Realizes the distributed online amplification of signals over long
distance with wide bandwidth and low noise.
Online optical
performance
monitoring function

signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.
Performance events
and alarms
monitoring
l Detects the pump optical power, temperature control current,

pump current, and back facet current.
l Supports the setting of the LOS value to disable the output port of
the laser.

The RPC02 consists of the Raman pump optical module, driving and detecting module,
The RPC02 is used at the receive end of the system. The RPC02 utilizes the stimulated Raman
scattering effect of the fiber to amplify the optical signals during transmission. The pump light
travels in the reverse direction of the signal light. The RPC02 must work with the EDFA.
Figure 19-23 shows the functional block diagram of the RPC02.
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Figure 19-23 Functional block diagram of the RPC02 (backward pump)

Splitter Signal light
Signal light
LINE
Pump light
Pump source
Control the
pumping current
and temperature.
SYS
MON
Detect the pump

light power and
current.
PIN
Detect the
temperature.
Control
Memory
CPU
Communication

Power supply
module
Fuse
Voltages required
by the board
DC power provided
by the backplane
SCC
Backplane
(controlled by
the SCC)
Signal Flow
The pump source of the RPC02 sends the pump light to the WDM side through the LINE optical
interface. On the line, the signals that are amplified through the distributed amplification are
received through the LINE interface. Then, the splitter splits the signals into two channels. The
service optical signals are transmitted through the SYS interface. A few supervisory signals are
transmitted to the test instrument through the MON interface for online optical performance
monitoring. The Ethernet interface of the RPC02 is connected to the COM interface of an NE
directly or through a hub to realize the communication with the SCC.
Functional Modules
l

The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.
The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.

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Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.
l

Controls the operations on the board.
Controls the operations on each module of the board according to the CPU instructions.
Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.
Communicates with the SCC.
Power supply module

Converts the DC power provided by the backplane into the power required by each module
of the board.
19.5.5 Front Panel

The front panel of the RPC02 has indicators, interfaces, and a laser safety class label.

Figure 19-24 shows the appearance of the front panel of the RPC02.
Figure 19-24 Front panel of the RPC02
03793010860000002 Y SSN1 RPC02
Board manufacturing
information
MON
Board serial
number and name
SYS
LINE
LASER
RADIATION
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
SCATTERED RADIATION
CRPC
CLASS 4 LASER
PRODUCT
ALM
RUN
WARNING: FIBERS MUST

BE CONNECTED SEFORE
POWER UP
RS232-1
RS232-2
LAN
Indicators
l

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Boards
Interfaces
The front panel of the RPC02 has six interfaces. Table 19-25 describes the types and usage of
the interfaces of the RPC02.
Table 19-25 Interfaces of the RPC02
Interface
Type of
Interface
Usage
LINE
LSH/APC
Receives the optical signals transmitted from the line.
SYS
LC
Is connected to the BA and transmits the amplified

signals to the fibers.
MON
LC
Monitors the optical performance.

The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.
LAN
RJ-45
Is connected to the COM interface of an NE directly or

through a hub to realize the communication with the
SCC.
RS232-1/
RS232-2
Is an RS-232 communication interface.
19.5.6 Valid Slots

The RPC02 is an external backward Raman driving board. Hence, the RPC02 is not installed in
the subrack. The RPC02 is connected to the COM interface of an NE directly or through a hub
to realize the communication with the SCC. The logical slot of the RPC02 on the NMS is slot
105.
NOTE
Only two logical slots are designed for the RPC, one for monitoring the RPC01 (using logical slot 104)
and the other for monitoring the RPC02 (using logical slot 105). If more than two RPC boards are monitored,
an IP address conflict occurs.

The RPC02 has two groups of jumpers, namely, group J3 and group J4.
Figure 19-25 shows the jumpers of the RPC02.
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Boards
Figure 19-25 Jumpers of the RPC02

RPC02
10
10
J3
J4
CPU
To ensure that the board can operate normally, set the jumpers as follows:
l
Do not short-circuit jumpers 9 and 10 of group J3.
19.5.8 Feature Code

The feature code of the RPC02 contains three characters, which indicate the gain of the optical
signal processed by the RPC02.
Table 19-26 describes the feature code of the RPC02.
Table 19-26 Feature code of the RPC02
Feature Code
Indication
Description
The first character
Is always "G".

characters
Gain
Indicates the gain.
Consider the N1RPC02 whose feature code is "G10" as an example. "G10" indicates that the
maximum gain of the optical signal is 10 dB.

You can set the parameters for the RPC02 by using the U2000.
You can set the following parameters for the RPC02 by using the U2000:
l
Laser status
Board work type
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For the description of each parameter, see 27.9 Optical Amplifier Boards.
Interface Display
Table 19-27 shows the serial numbers of the optical interfaces on the front panel of the RPC02
on the NMS.
Table 19-27 Serial numbers of the optical interfaces on the front panel of the RPC02 on the
NMS
Interface on the Front Panel
Serial Number of the NMS Interface
LINE
SYS
MON

The technical specifications of the RPC02 include the parameters specified for optical interfaces,

Table 19-28 lists the parameters specified for the optical interfaces of the RPC02.
Table 19-28 Parameters specified for the optical interfaces of the RPC02
Issue 03 (2013-02-20)
Parameter
Value
Pump wavelength (nm)
1400 to 1500
Operating wavelength (nm)
1529 to 1561
Maximum pump power (dBm)
29.5
Gain on the G.652 fiber (dB)
> 10
Gain on the LEAF fiber (dB)
NA
Equivalent noise figure on the G.652 fiber (dB)
NA
Equivalent noise figure on the LEAF fiber (dB)
NA
0.5
Type of output connector
LSH/APC or LC/PC

1352


Boards
Laser Safety Class

the optical interfaces is more than 27 dBm (500 mW).
The mechanical specifications of the RPC02 are as follows:
l
Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)
Weight (kg): 4.2
Power Consumption
19.6 OBU1
technical specifications of the TN11OBU1 (optical booster amplifier board).

The OBU1 is available in the following functional version: TN11.
19.6.2 Application
The OBU1 is an optical booster amplifier board that amplifies optical signals.
The OBU1 is available in two types, namely, OBU101 and OBU103. The OBU101 is used at
the receive end and the OBU103 is used at the transmit end. Figure 19-26 shows the position
of the OBU1 in an optical transmission system.
Figure 19-26 Position of the OBU1 in an optical transmission system
Transmitting
Transmitting
OBU103
OBU101
Receiving
Receiving

The OBU1 supports the online optical performance monitoring function, gain lock, transient
control, and other functions.
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Table 19-29 provides the functions and features of the OBU1.

Table 19-29 Functions and features of the OBU1
Function and
Feature
OBU1
Basic functions
Amplifies a maximum of 40 channels of optical signals with the channel

spacing of 100 GHz at the same time.
Supports the system to transmit services over different fiber spans
without electrical regeneration.
Typical gain
The typical gain of the OBU101 is 20 dB and the typical gain of the
OBU103 is 23 dB.
Online optical
performance
monitoring
function

signal can be transmitted to the spectrum analyzer through the interface
so that the spectrum and optical performance of the multiplexed optical
signal can be monitored without a service interruption.
Gain lock function
The EDFA inside the board has the gain lock function. When one or
more channels are added or dropped, or optical signals of certain
channels fluctuate, the signal gain of other channels is not affected.
Transient control
function
The EDFA inside the board has the transient control function. When
channels are added or dropped, the board can suppress the fluctuation
of the optical power in the path to realize the smooth upgrading and
expansion.
Performance
events and alarms
monitoring
Checks and reports the optical power.

Controls the temperature of the pump laser.
Detects the pump driving current, back facet current, cooling current,
temperature of the pump laser, and ambient temperature of the board.
NOTE
The OBU1 is available in two types, namely, OBU101 and OBU103. The OBU101 is used at the receive
end and the OBU103 is used at the transmit end.

The OBU1 consists of the EDFA optical module, splitter, driving and detecting module,
Figure 19-27 shows the functional block diagram of the OBU1.
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Boards
Figure 19-27 Functional block diagram of the OBU1
Splitter
EDFA optical module

IN
OUT
Driving
current
MON
Detect the pump

current and
temperature.
PIN
Control
Memory
CPU
Communication

Power supply
module
Voltages required
by the board
Fuse
DC power provided
by the backplane
Backplane
(controlled
by the
SCC
SCC)
Signal Flow
The OBU1 receives the multiplexed optical signals, which are amplified by the EDFA optical
module. Then, the OBU1 sends the amplified optical signals to the splitter and transmits the
signals through the OUT interface. The OBU1 also sends a few supervisory signals to the test
instrument for online optical performance monitoring.
EDFA Optical Module

The EDFA optical module amplifies the input optical signals. The EDFA optical module adopts
the automatic gain control technology. Hence, the gain of each operating wavelength signal can
remain in the allowed range.
Splitter
The splitter splits one channel of optical signals from the EDFA optical module into two channels
of signals of different power. One channel of signals is transmitted through the OUT interface
to the main optical path. The other channel of signals is transmitted to the MON interface for
spectrum detection and supervising.
The power of the MON interface is 1/99 of the power of the OUT interface. That is, the power
of the MON interface is 20 dB less than the power of the OUT interface.
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Boards

l
Detects the driving current, back facet current, cooling current, and operating temperature
of the pump inside the pump optical module in real time.
Communication and control Module

l
The communication and control module controls and monitors the functional modules of
the board, and manages the communication.
The communication and control module collects the alarms, performance events, working
status, voltage detection information, and other information of each functional module of
the board, and reports the collected information to the SCC.
The communication and control module receives the commands issued by the SCC to
control and coordinate the operation of each functional module.
Power supply module

Converts the DC power provided by the backplane into the power required by each module of
the board.
19.6.5 Front Panel

The front panel of the OBU1 has indicators, interfaces, and a laser safety class label.

Figure 19-28 shows the appearance of the front panel of the OBU1.
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Boards
Figure 19-28 Front panel of the OBU1
OBU1
STAT
ACT
PROG
SRV
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
MON
OUT
IN
OBU1
Indicators
l
Interfaces
The front panel of the OBU1 has three optical interfaces. Table 19-30 describes the types and
usage of the optical interfaces of the OBU1.
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Table 19-30 Optical interfaces of the OBU1

Interface
Type of
Interface
Usage
IN
LC
Receives the multiplexed signals to be amplified.
OUT
LC
Transmits the amplified multiplexed signals.
MON
LC
Is connected to the test instrument to monitor the inservice performance.
19.6.6 Valid Slots

The OBU1 can be installed in slots 18 and 1117 in the main subrack.
19.6.7 Feature Code

The feature code of the OBU1 contains six characters, which indicate the gain and maximum
nominal input optical power of the optical signals processed by the OBU1.
Table 19-31 describes the feature code of the OBU1.
Table 19-31 Feature code of the OBU1
Feature Code
Indication
Description
The first character
Is always "G".

characters
Gain
Indicates the gain.
The fourth character
Is always "I".
The fifth and sixth characters
Maximum nominal input

optical power
Indicates the maximum

nominal input optical power.
Consider the TN11OBU1 whose feature code is "G23I-3" as an example. "G23I-3" indicates
that the gain is 23 dB and the maximum nominal input optical power is -3 dBm.

You can set the parameters for the OBU1 by using the U2000.
You can set the following parameters for the OBU1 by using the U2000:
l
Threshold of input power loss
Laser status
Gain
Nominal gain upper threshold
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1358

Nominal gain lower threshold
Rated optical power
Configure band
Configure working band parity
Actual band
Actual working band parity

Boards

The technical specifications of the OBU1 include the parameters specified for optical interfaces,

Table 19-32 lists the parameters specified for the optical interfaces of the OBU1.
Table 19-32 Parameters specified for the optical interfaces of the OBU1
Parameter
Value
TN11OBU101
TN11OBU103
1529 to 1561
1529 to 1561
Nominal input power range

(dBm)
-32 to -4
-32 to -3
Input power range per

channel
40
channe
ls
-32 to -20
-32 to -19
80
channe
ls
-32 to -23
-32 to -22
40
channe
ls
-20
-19
80
channe
ls
-23
-22
Input power (dBm) of a typical

single wavelength
-20
-19
Maximum nominal output optical

power (dBm) of a single
wavelength
Noise figure (dB)
5.5
6.0
Nominal gain (dB)
20
23
Nominal singlewavelength input

optical power
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Parameter

Boards
Value
TN11OBU101
TN11OBU103
Gain response time on adding/

dropping of channels (ms)
< 10
< 10
Channel gain (dB)
201.5
231.5
Gain flatness (dB)
2.0
2.0
Input reflectance (dB)
< -40
< -40
Output reflectance (dB)
< -40
< -40
Pump leakage at input (dBm)
< -30
< -30
Maximum reflectance tolerance at

input (dB)
-27
-27
Maximum reflectance tolerance at

output (dB)
-27
-27
Maximum total output optical

power (dBm)
16
20
Multi-channel gain slope (dB/dB)
2.0
2.0
0.5
0.5
Pre-incline of the gain spectral

form (dB)
00.2
1.00.2
Laser Safety Class

The mechanical specifications of the OBU1 are as follows:
l
Weight (kg):
TN11OBU1: 1.3
TN12OBU1: 1.1
Power Consumption
l
The maximum power consumption of the TN11OBU101 at room temperature (25C) is 16

W.
The maximum power consumption of the TN11OBU103 at room temperature (25C) is 13

W.
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19.7 DCU
technical specifications of the DCU (dispersion compensation board).

The DCU is available in the following functional versions: N1 and N2. The difference between
the two versions is with regard to the insertion attenuation and compensation.
Table 19-33 describes the versions of the DCU.
Table 19-33 Versions of the DCU
Item
Description
Functional versions
The DCU is available in two functional versions, namely, N1 and N2.
Commonness
The working principle of the N1DCU is the same as the working

principle of the N2DCU.
Differences
The insertion loss of the N2DCU is 3 to 5 dB less than the insertion

loss of the N1DCU.
In the case of the N1DCU, two compensation modes are available,
namely, 60 km and 80 km. In the case of the N2DCU, three
compensation modes are available, namely, 40 km, 60 km, and 80
km.
Use attenuators to prevent overloaded optical power when you use
the N2DCU to substitute for the N1DCU.
Substitution
19.7.2 Application
The DCU is a dispersion compensation board. The DCU compensates for the dispersion that is
accumulated in the fiber during the transmission of the optical signals in the 10 Gbit/s system,
and compresses optical signal pulse. In this manner, the optical signals that are transmitted can
be restored. In addition, the DCU can realize long-haul optical transmission when it works with
an optical amplifier board.
During the long-haul transmission (more than 80 km) of 10 Gbit/s signals, the pulse width of
the optical signals is expanded and the signals are severely distorted due to the impact of
dispersion. As a result, the optical signals cannot be normally received by the optical receiver.
Therefore, the DCU is required to compensate for the dispersion. Figure 19-29 shows the
position of the DCU in an optical transmission system.
Figure 19-29 Position of the DCU in an optical transmission system
Pulse broadening Pulse compression
Issue 03 (2013-02-20)
PA
DCU
Optical
receiver
Optical
transmitter
1550.12 nm
BA
1550.12 nm

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NOTE
The operating wavelength of the chirp grating of the DCU is 1550.12 nm. Therefore, the central wavelength
of the optical signals transmitted by the optical interface board on the opposite end must also be 1550.12
nm. Otherwise, the dispersion of the optical signals cannot be compensated for and the insertion loss is
high. As a result, no optical signals can be transmitted.

The DCU can compensate for the dispersion for a maximum of two channels of optical signals.
The DCU can be used with the BA and PA.
Table 19-34 provides the functions and features of the DCU.
Table 19-34 Functions and features of the DCU
Function
and Feature
N1DCU
N2DCU
Basic
functions
Compensates for the dispersion of a

maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 1020 ps/
nm (for the dispersion caused by the
60 km G.652 optical fiber), 1360 ps/
80 km G.652 optical fiber), or any
combination.
Compensates for the dispersion of a

maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 680 ps/
80 km G.652 optical fiber), or any
combination.
Dispersion
compensatio
n method
Compensates for the dispersion accumulated during the transmission by using

the chirp grating and suppresses the pulse signals to restore the optical signals.
Long haul
transmission
with optical
regeneration
Realizes long haul transmission with optical regeneration when working with
the BA and PA.

The DCU consists of the dispersion compensation module.
Figure 19-30 shows the functional block diagram of the DCU.
Figure 19-30 Functional block diagram of the DCU
IN
OUT
module
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The dispersion compensation module is used behind the PA to provide optical signals of required
compensation and path penalty.
19.7.5 Front Panel

The front panel of the DCU has interfaces, and a laser safety class label.

Figure 19-31 shows the appearance of the front panel of the one-interface DCU.
Figure 19-31 Front panel of the one-interface DCU
DCU
CLASS 1
LASER
PRODUCT
OUT
IN
DCU
Figure 19-32 shows the appearance of the front panel of the two-interface DCU.
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Figure 19-32 Front panel of the two-interface DCU
DCU
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2 IN2
DCU
Interfaces
The front panel of the one-interface DCU has one optical interface. The optical interface
transmits and receives one channel of optical signals.
The front panel of the two-interface DCU has two optical interfaces. The optical interfaces
transmit and receive two channels of optical signals.
WARNING
If the front panel of the one-interface DCU has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the DCU whose front panel has two LC optical
interfaces, determine whether the DCU is a one-interface DCU or a two-interface DCU according
to 19.7.7 Feature Code.
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Table 19-35 describes the type and usage of the optical interface of the one-interface DCU.
Table 19-35 Optical interface of the one-interface DCU
Interface
Type of
Interface
Usage
IN
LC
OUT
LC
Table 19-36 describes the types and usage of the optical interfaces of the two-interface DCU.
Table 19-36 Optical interfaces of the two-interface DCU
Interface
Type of
Interface
Usage
IN1
LC
Receives the first channel of optical signals.
OUT1
LC
Transmits the first channel of optical signals.
IN2
LC
Receives the second channel of optical signals.
OUT2
LC
Transmits the second channel of optical signals.
19.7.6 Valid Slots

The slots valid for the DCU vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
l Slot bandwidth
l Board version
The slots valid for the DCU are as follows:

l
When the cross-connect capacity is 200 Gbit/s, the DCU can be installed in slots 18 and
19.7.7 Feature Code

The feature code of the DCU indicates the compensated dispersion for the optical signals.
Table 19-37 provides the relationship between the feature code of the DCU and the compensated
dispersion.
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Table 19-37 Relationship between the feature code of the DCU and the compensated dispersion
Board
Feature Code
Compensated Dispersion
SSN1DCU01
01
Compensated dispersion for a single channel: 60

km
SSN1DCU02
02

km
SSN1DCU03
03
Compensated dispersion for dual channels: 60

km/60 km
SSN1DCU04
04

km/80 km
SSN1DCU05
05

km/80 km
SSN2DCU01
01

km
SSN2DCU02
02

km
SSN2DCU03
03

km
SSN2DCU04
04

km/40 km
SSN2DCU05
05

km/60 km
SSN2DCU06
06

km/80 km
SSN2DCU07
07

km/60 km
SSN2DCU08
08

km/80 km
SSN2DCU09
09

km/80 km

The technical specifications of the DCU include the parameters specified for optical interfaces,

Table 19-38 lists the parameters specified for the optical interfaces of the DCU.
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Table 19-38 Parameters specified for the optical interfaces of the DCU
Parameter
Value
Nominal bit rate
9953280 kbit/s
Line code pattern
NRZ
Central wavelength
(nm)
1550.120.05
-0.5 dB bandwidth
(nm)
> 0.4
Compensated
dispersion (ps/nm)
N1DCU: 1020 (60 km); 1360 (80 km)
Insertion loss (dB)
Less than 8.3 dB in the case of the N1DCU and less than 3 dB in
the case of the N2DCU
N2DCU: 680 (40 km); 1020 (60 km); 1360 (80 km)
Laser Safety Class

The mechanical specifications of the DCU are as follows:
l
Weight (kg): 0.4
Power Consumption
The maximum power consumption of the DCU at room temperature (25C) is 0 W.
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20
Power Boards
About This Chapter

This topic describes the power boards such as the UPM, PIU and PIUA.
20.1 UPM
technical specifications of the UPM (uninterruptible power module).
20.2 PIU
technical specifications of the PIU (power interface board).
20.3 PIUA
technical specifications of the PIUA (power interface board).
20.4 PIUB
The PIUB board is the power interface unit between the DC power distribution box and each
board on the subrack. This section describes the versions, functions, working principle, front
panel, configuration, and technical specifications of the PIUB board.
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20.1 UPM
technical specifications of the UPM (uninterruptible power module).

None.
20.1.2 Application
The UPM is an external uninterruptible power module. The UPM can directly convert 110 V/
220 V AC mains power into -48 V DC power required by the transmission equipment. The UPM
is suitable for the telecom carriers who cannot provide -48 V DC power supply or requires
batteries.
Figure 20-1 shows the application of the UPM on the OptiX OSN equipment series.
Figure 20-1 Application of the UPM on the OptiX OSN equipment series
OptiX OSN equipment
110 V/220 V
UPM
Backplane
-48 V
PIU
Board A
-48 V
PIU
Board B
-48 V
Table 20-1 shows different mapping policies of UPM.

Table 20-1 Mapping policies of UPM on the OptiX OSN 3500
Issue 03 (2013-02-20)
Type of Subrack
Mapping PDU
Mapping PIU
Mapping UPM
General OptiX OSN

3500 subrack
N1PDU,
DPD100-2-8 PDU
N1PIU, N1PIUA
EPS75-4815AF
Enhanced OptiX
OSN 3500 subrack
(1100 W)
N1PDU,
DPD100-2-8 PDU
N1PIUA
EPS75-4815AF

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20 Power Boards
Type of Subrack
Mapping PDU
Mapping PIU
Mapping UPM
OptiX OSN 3500

type III subrack
(2300 W)
TN51PDU,
DPD63-8-8 PDU
N1PIUB
EPS75-4815AF

The UPM is a special power supply system and is numbered EPS75-4815AF. The UPM can
directly convert 110 V/220 V AC power into 48 V DC power that the transmission equipment
requires. The UPM is suitable for the telecom carriers who cannot provide 48 V DC power for
the equipment or telecom carriers who require storage batteries.
The UPM consists of the rectifier module, monitoring module, and DC/AC power distribution
frame. The rectifier module and monitoring module are hot-swappable so that faulty modules
can be replaced without the system being shut down.
The output power of a single EPS75-4815AF power system is 1700 W. The EPS75-4815AF
power system is 3U high. Figure 20-2 shows the appearance of the EPS75-4815AF power
system.
Figure 20-2 Appearance of the EPS75-4815AF power system
The UPM power box can be installed in an ETSI cabinet.

The storage batteries of the UPM work with one EPS75-4815AF power system. When the
external AC power system supplies power normally, the batteries store power. When the 110
V/220 V AC power supply is interrupted, the batteries can supply power for 3 to 4 hours. To
supply power to the OptiX OSN equipment, only one power system is required to be connected
to the batteries.
The full configuration of an EPS75-4815AF power system includes five rectifier modules and
one monitoring module.
NOTE
The storage batteries do not belong to the EPS75-4815AF power system. They need to be configured
separately. If the batteries are required, a battery cabinet is provided generally or a dedicated space in the
equipment cabinet is reserved for the batteries.
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Table 20-2 provide the functions and features of the UPM.

Table 20-2 Functions and features of the EPS75-4815AF power system
Function and
Feature
EPS75-4815AF
Hot-swappable
function
The AC/DC rectifier module of the UPM is hot-swappable. When

you replace a faulty rectifier module, the other rectifier module can
still work normally. Therefore, the maintainability of the system is
improved.
Storage battery
protection function
The UPM provides the storage battery protection function. When the
mains supply is interrupted, the power system of the equipment
automatically switches to the storage battery, which ensures that the
equipment operates normally. The battery module provides a capacity
of 40 to 500 Ah. The default capacity is 65 Ah.
Lightning-proof
function
The rectifier module is embedded with the lightning-proof protector.

The rectifier module can bear 5 lightning-simulated surges with an
8/20 s current waveform at the amplitude of 5 kA. When the
lightning current enters the rectifier module along with the power
cable, install category-C and category-B light arresters before you
connect the AC mains supply to the power system to prevent the
overvoltage caused by the direct lightning strike from damaging the
rectifier module.

The UPM is fed by one 110 V/220 V AC mains power supply. The rectifier module converts
the input power into 48 V DC voltage to provide four DC branches and one battery branch.
The UPM consists of the rectifier module and the monitoring module. Figure 20-3 shows the
block diagram of the UPM.
Figure 20-3 Block diagram of the UPM
110 V/220 V AC
Rectifier
module
48 V DC
PIU
Monitoring
module
System control unit
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Rectifier Module
The rectifier module converts the 110 V/220 V AC mains power supply into 48 V DC voltage
required by the transmission equipment.
Monitoring Module
When the UPM works normally, the monitoring module controls the rectifier module, storage
battery loop, and load loop, which work according to the preset parameters or user settings. The
monitoring module also monitors the status and data of the rectifier module, storage battery loop,
and load loop.
In the case of a mains supply failure, the equipment is fed by the storage battery group that is
connected to the UPM. The battery group must be connected to the UPM before the mains supply
fails. When the batteries start to discharge due to a mains supply failure, the monitoring module
reports the no-mains-supply alarm. With the discharge of the batteries, the battery voltage starts
to drop. When the battery voltage is lower than 45 V, the monitoring module reports the DC
undervoltage alarm. When the battery voltage reaches 43 V, the battery group enables the poweroff protection function to interrupt the connection between the battery group and the equipment.
As a result, the batteries are automatically protected.
When the mains supply is restored, the UPM resumes normal operations.
20.1.5 Front Panel

The front panel of the UPM has indicators and ports of many types.

Figure 20-4 shows the front panel of the EPS75-4815AF power system (subject to the UPM
onsite).
Figure 20-4 Front panel of the EPS75-4815AF power system
1
10
5 6
14
11
12
13
15
1. Control circuit breaker of the AC 2. Control circuit breaker of the 3. Control circuit breaker of load 1 (10
input (30 A)
battery branch (80 A)
A)
4. Control circuit breaker of load 2 5. Control circuit breaker of load 6. Control circuit breaker of load 4 (40
(30 A)
3 (40 A)
A)
7. AC phase line terminal
Issue 03 (2013-02-20)
8. AC zero line terminal

9. Negative 48 V terminal of the battery

branch
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20 Power Boards
10. Negative 48 V terminal of the

load branch
11. Positive 48 V terminal of the 12. Positive 48 V terminal of the load

battery branch
branch
13. Connecting terminal of the

PGND cable
14. DB44 signal port
15. Communication port (COM)
Indicators of the EPS75-4815AF

The front panel of each rectifier module has the following indicators:
l
Running status indicator (RUN) one color (green)
Alarm and protection indicator (ALM) one color (yellow)
Faulty state indicator (FAULT) one color (red)
The front panel of the monitoring module has the following indicators:
l
Power supply system fault indicator (ALM) one color (red)
Power supply system status indicator (RUN) one color (green)
Ports of the EPS75-4815AF Power System

The front panel of the EPS75-4815AF has six ports. Table 20-3 describes the types and usage
of these ports.
Table 20-3 Ports of the EPS75-4815AF power system
Issue 03 (2013-02-20)
Port
Type
Usage
Power input port
Power port
"7" and "8" indicate the AC mains input

terminals, which receive 110 V/220 V AC
power.
Power output port
Power port
The power output ports are in the lower left

corner on the front panel of the UPM. The
terminals indicated by "9" and "11" form a
battery port, through which the power system is
connected to the battery input socket at the back
of the storage battery box through a battery
cable. "10" and "12" indicate the output ports of
four loads. The output ports can supply power
to the OptiX OSN equipment by using power
cables.
Connecting
terminal of the
PGND cable
Power port
The UPM is grounded through the cabinet.

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20 Power Boards
Port
Type
Usage
DB44 signal port
DB44
The backplane of the subrack can be connected

to the sensor transfer box (an optional device)
through the DB44 signal port and to the
monitoring module through the 96-pin DIN
connector. In addition, the sensor transfer box
can be connected to multiple sensors. As a
result, the monitoring function is extended.
Communication
port (COM)
RJ-45
Reserved
Switch button
Button
The switch buttons are on the left of the UPM,

as shown in Figure 20-4. "1" indicates the
control circuit breaker of the AC input (30 A),
which enables and disables the input of the AC
mains supply. "2", "3", "4", and "5" indicate the
load control switches, which enable and disable
the load output.
Table 20-4 provides the definition of DB44 signal pins.

Table 20-4 Definition of DB44 signal pins
Pin Diagram
Issue 03 (2013-02-20)
Pin
Definiti
on
Function
Pin
Definit
ion
Function
24 V
Auxiliary power
output
23
SMOK
E
Smoke sensor
12 V
Auxiliary power
output
24
WATE
R
Water damage detection
12 V
Auxiliary power
output
25
DOOR
Door status switch (DSS)

signal detection
GND
Signal ground
26
WIRE
Distribution frame
connection
GND
Signal ground
27
JK1+
Positive terminal of dry

contact 1
SIM1
Voltage
detection of the
first battery pack
28
JK1-
Negative terminal of dry

contact 1
SIM2
Voltage
detection of the
second battery
pack
29
JK2+
Positive terminal of dry

contact 2

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Pin Diagram
20 Power Boards
Pin
Definiti
on
Function
Pin
Definit
ion
Function
30
JK2-
Negative terminal of dry

contact 2
31
CONT1
O+
Positive terminal for output

control of optical coupler 1
10
GND
Signal ground
32
CONT1
O-
Negative terminal for output

11
VHUM
Ambient
humidity
measurement
33
CONT2
O+
Positive terminal for output

12
VBTEM
1
Battery
temperature
measurement 1
34
CONT2
O-
Negative terminal for output

13
VBTEM
2
Battery
temperature
measurement 2
35
FANCT
R1+
Positive terminal for fan

rotation control
14
VTEM1
Ambient
temperature
measurement 1
36
FANCT
R1-
Negative terminal for fan

rotation control
15
VTEM2
Ambient
temperature
measurement 2
37
JKM1+
Positive terminal for a surge

protector failure alarm
16
JTD1
Backup 1
38
JKM1-
Negative terminal for a surge

protector failure alarm
17
JTD2
Backup 2
39
JKM2+
Positive terminal for an AC

power-off alarm
18
JTD3
Backup 3
40
JKM2-
Negative terminal for an AC

power-off alarm
19
JTD4
Backup 4
41
JKM3+
Positive terminal for a battery

undervoltage alarm
20
JTD5
Backup 5
42
JKM3-
Negative terminal for a

battery undervoltage alarm
21
JTD6
Backup 6
43
JKM4+
Positive terminal for power

supply system failure
22
JTD7
Backup 7
44
JKM4-
Negative terminal for power

supply system failure
20.1.6 Valid Slots

The UPM is case shaped. Hence, the UPM does not occupy a slot in the subrack.
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The technical specifications of the UPM include the power parameters and mechanical
specifications.
The equipment supports the 110 V/220 V power supply through an uninterrupted power modules
(UPM). The UPM is used to convert 110 V/220 V AC into -48 V DC, and to provide power
supply for the equipment.
The type of UPM supported by the OptiX OSN equipment is 75-4815AF. If the 110 V/220 V
AC power fails, the storage battery can provide power supply for 4 hours.
Power Parameters
Table 20-5 lists the power parameters of the UPM.
Table 20-5 Power parameters of the EPS75-4815AF
Parameter
Value
Voltage range of
the AC input
90-290 V AC
AC input
One single-phase three-wire system: 45-65 Hz
Rated input current
28 A
Output nominal
voltage
53.50.5 V
Rated output
current
DC output branches
Load MCB 1: 10 A
Load MCB 2: 3 0A
Load MCB 3: 40 A
Load MCB 4: 40 A
Battery MCB: 80 A
Total output DC current
Issue 03 (2013-02-20)
37.53 A to 753 A
Regulated voltage
precision
1%
Non-balance of
load sharing
5% (50%-100% load)
Rated efficiency of
the integrated
equipment
89%
Power factor
0.99 (nominal input or output)
Peak-to-peak noise
voltage
200mV (within the range of 20 MHz)
Electrical network
adjustment rate
0.1%

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Parameter
Value
Lightning
protection
performance
When the UPM works alone, the input end can bear the simulated
lightning surge current whose waveform is 8/20s and amplitude is 5
kA for five times in both directions. The interval between two surges
must not be less than one minute. If the lightning surge current is higher
than the preceding indexes, the UPM may be damaged and cannot work
normally.
Cooling method
The fan that is embedded in the rectifier module cools the module.
The mechanical specifications of the EPS75-4815AF are as follows:
l
l
Dimensions of the UPM (mm): 133mm (W) x 255mm (D) x 436mm (H)
Weight: 15 kg
20.2 PIU
technical specifications of the PIU (power interface board).

The PIU is available in one functional version, namely, N1. The N1PIU is discontinued.
20.2.2 Application
The PIU is a power interface board that is mainly used to receive the power supply for the OptiX
OSN equipment.
Figure 20-5 shows the application of the PIU on the OptiX OSN equipment series.
Figure 20-5 Application of the PIU on the OptiX OSN equipment series
OptiX OSN equipment
-48 V
PIU
Backplane
-48 V
PIU
Board A
Board B
-48 V
Issue 03 (2013-02-20)
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The PIU is used to receive the power supply and to provide the lightning protection function
and filtering function.
Table 20-6 provides the functions and features of the PIU.
Table 20-6 Functions and features of the PIU
Function and
Feature
PIU
Lightning
protection function
Provides the lightning protection function and reports the alarm that
indicates a surge protection failure.
Filtering function
Enhances the electromagnetic compatibility of the system by filtering

the power supply interface and shielding the structure of the board.
Power supply
interface
Provides two 50 W power interfaces for external devices such as the

COA.
Power supply of the

FAN
Provides the FAN with normal working voltages.
Alarm monitoring
Reports the board in-position alarm.
Power supply
backup
Supports the 1+1 hot backup. Any one PIU can supply power to an
entire subrack.
NOTE
One PIU can supply power to an entire subrack.

The PIU consists of the power access unit, filtering unit, and unit that detects whether the
lightning-proof unit fails.
Figure 20-6 shows the functional block diagram of the PIU.
Figure 20-6 Functional block diagram of the PIU
COA power supply unit
Power
access
unit
Unit that detects

whether the
lightning-proof
unit f ails
Filtering
unit
Filtering
unit
Backplane
Alarm indicating a
lightning-proof unit f ailure
Sy stem controlunit
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Power Access Unit

This unit receives the 48 V or 60 V power supply for the system.
Unit That Detects Whether the Lightning-Proof Unit Fails

This unit protects the equipment from overcurrent and lightning and reports the alarm that
indicates its failure to the SCC unit.
Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment operates
stably.
20.2.5 Front Panel

The front panel of the PIU has power interfaces.

Figure 20-7 shows the appearance of the front panel of the PIU.
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Figure 20-7 Front panel of the PIU
PIU
PWR
PS1
PS2
PIU
Interfaces
The front panel of the PIU has two power interfaces. Table 20-7 describes the types and usage
of the interfaces of the PIU.
Table 20-7 Interfaces of the PIU
Issue 03 (2013-02-20)
Interface
Type of Interface Usage
PWR
3V3 terminal
PS1/PS2
Four-phase socket
Provides the 50 W power output and can supply

power to the COA.

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20 Power Boards
20.2.6 Valid Slots

The PIU can be installed in slots 27 and 28 in the subrack.

The technical specifications of the PIU include the mechanical specifications, power
consumption, input voltage, and fuse.
The mechanical specifications of the PIU are as follows:
l
Weight: 1.2 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the PIU is 8W.
Input Voltage
The input voltage range of the PIU is as follows:
l
If the standard voltage of the input power is -48 V, the power voltage ranges from -38.4 V
to -57.6 V.
If the standard voltage of the input power is -60 V, the power voltage ranges from -48 V
to -72 V.
Fuse
The main loop fuse F7 of the PIU is 250 V-20 A-0.00355 ohms.
20.3 PIUA
technical specifications of the PIUA (power interface board).

The PIUA is available in one functional version, namely, N1.
20.3.2 Application
The PIUA is a power interface board that is mainly used to receive the power supply for the
OptiX OSN equipment.
Figure 20-8 shows the application of the PIUA on the OptiX OSN equipment series.
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Figure 20-8 Application of the PIUA on the OptiX OSN equipment series
OptiX OSN equipment
-48 V
PIUA
Backplane
PIUA
-48 V
Board A
Board B
-48 V
-48 V

The PIUA is used to receive the power supply and to provide the lightning protection function
and filtering function.
Table 20-8 provides the functions and features of the PIUA.
Table 20-8 Functions and features of the PIUA
Function and
Feature
PIUA
Lightning
protection function
Filtering function

Power supply
interface
Provides two 50 W power interfaces for external devices such as the

COA and hub.
Alarm monitoring
Power supply
backup
Supports the 1+1 hot backup. Any one PIUA can supply power to the
entire subrack.

The PIUA consists of the power access unit, filtering unit, and unit that detects whether the
lightning-proof unit fails.
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20 Power Boards
Figure 20-9 shows the functional block diagram of the PIUA.

Figure 20-9 Functional block diagram of the PIUA
Unit that detects
whether the lightningproof unit fails
Power
access
unit
Filtering
unit
Backplane
Alarm indicating a
lightning-proofunitfailure
System control unit
Power Access Unit

This unit receives the 48 V or 60 V power supply for the system.
Unit That Detects Whether the Lightning-Proof Unit Fails

This unit protects the equipment from overcurrent and lightning and reports the alarm that
indicates a lightning-proof unit failure to the SCC unit.
Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment can operate
stably.
20.3.5 Front Panel

The front panel of the PIUA has indicators and power interfaces.

Figure 20-10 shows the appearance of the front panel of the PIUA.
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20 Power Boards
Figure 20-10 Front panel of the PIUA
PIUA
POWER
NEG(-)
PWR
RTN(+)
PS1
RTN(+)
NEG(-)
PS2
RTN(+)
NEG(-)
PIUA
Indicators
The front panel of the board has a power supply indicator (POWER). The POWER indicator is
green when it is on.
Interfaces
The front panel of the PIUA has two power interfaces. Table 20-9 describes the types and usage
of the interfaces of the PIUA.
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Table 20-9 Interfaces of the PIUA

Interface
Type of Interface
Usage
PWR
3V3 terminal
PS1/PS2
Four-phase socket
Provides the 50 W power output and can supply

power to the COA.
20.3.6 Valid Slots

The PIUA can be installed in slots 27 and 28 in the subrack.

The technical specifications of the PIUA include the mechanical specifications, power
consumption, input voltage, and the fuse.
The mechanical specifications of the PIUA are as follows:
l
Weight: 0.5 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the PIUA is 3 W.
Input Voltage
The input voltage range of the PIUA is as follows:
l
to -57.6 V.
If the standard voltage of the input power is -60 V, the power voltage ranges from -48V to
-72 V.
Fuse
The main loop fuse of the PIUA is 250 V-32 A-0.00355 ohms.
20.4 PIUB
The PIUB board is the power interface unit between the DC power distribution box and each
board on the subrack. This section describes the versions, functions, working principle, front
panel, configuration, and technical specifications of the PIUB board.
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20 Power Boards

The PIUB is available in one functional version, namely, N1. The PIUB board only can be used
on a type III subrack (2300 W).
20.4.2 Application
The PIUB board is a power interface board that provides power supply for the OptiX OSN
3500.
Figure 20-11 shows the application of the PIUB board in the OptiX OSN system.
Figure 20-11 Application of the PIUB board in the OptiX OSN system
OptiX OSN equipment
-48 V
PIU
Backplane
-48 V
PIU
Board A
Board B
-48 V
-48 V

The PIUB is a power interface board that provides power supply, lightning protection, and
filtering functions.
Table 20-10 provides the functions and features of the PIUB board.
Table 20-10 Functions and features of the PIUB board
Issue 03 (2013-02-20)
Functions and
Features
Description
Lightning
protection function
Filtering function


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20 Power Boards
Functions and
Features
Description
Power supply
interface
Provides two 50 W power interfaces for external units such as the COA.
Alarm monitoring
Power supply
backup
Supports 1+1 hot backup. Any one PIUB can supply power to an entire
subrack.

The PIUB board consists of the filtering unit, protection unit, protection circuit failure detecting
unit, and power detecting unit.
Figure 20-12 shows the functional block diagram of the PIUB.
Figure 20-12 Functional block diagram of the PIUB
COA power supply interface
COA
NEG(-)
NEG(-)
Protection
unit
Filtering
unit
RTN(+)
RTN(+)
Protection
circuit failure
detecting unit
System control unit
Power
detecting
unit
LED
indication
Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment operates
stably.
Protection Unit
This unit protects the equipment from overcurrent and lightning.
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20 Power Boards
Protection Circuit Failure Detecting Unit

This unit monitors the protection unit and reports the alarm that indicates a protection unit failure
to the SCC unit.
Power Detecting Unit

This unit checks whether the input power supply is valid, and uses the indicator to indicate the
status of the input power supply.
20.4.5 Front Panel

The front panel of the PIUB has indicators and power interfaces.

Figure 20-13 shows the appearance of the front panel of the PIUB board.
Figure 20-13 Front panel of the PIUB
PIUB
POWER
RTN(+)
NEG(-)
PS1
RTN(+)
NEG(-)
PS2
RTN(+)
NEG(-)
PIUB
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20 Power Boards
Indicators
The front panel of the board has a power supply indicator (POWER). The POWER indicator is
green when it is on.
Interfaces
The front panel of the PIUB board has two power interfaces. Table 20-11 provides the types
and usage of the power interfaces of the PIUB board.
Table 20-11 Description of the interfaces on the PIUB board
Interface
Silkscreen
Type of
Interface
Usage
PWR
RTN(+),
NEG(-)
Dual-OT
terminal
Provides -48 V power input.
PWS
PS1, PS2
Four-phase
socket
Provides two 50 W power outputs for the COA.
Table 20-12 provides the pin description of the PS1 and PS2 interfaces on the PIUB board.
Table 20-12 Pin description of the PWS interfaces on the PIUB board
Front View
Pin
Usage
48 V
48 V
Grounding
Not defined
20.4.6 Valid Slots

The PIUB board can be installed in slots 27 and 28 on the subrack.

The technical specifications of the PIUB board include the mechanical specifications, power
consumption, input voltage.
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20 Power Boards
The mechanical specifications of the PIUB are as follows:
l
Weight (kg): 0.6
Power Consumption
The maximum power consumption of the PIUB at room temperature (25C) is 6 W.
Input Voltage
The input voltage range of the PIUB is as follows:
l
to -57.6 V.
If the standard voltage of the input power is -60 V, the power voltage ranges from -48 V
to -72 V.
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21
21 Pluggable Optical Module
Pluggable Optical Module
About This Chapter

Certain boards on the OptiX OSN equipment supports the small form-factor pluggable (SFP),
enhanced small form-factor pluggable (eSFP), and 10 Gigabit small form-factor pluggable
(XFP) optical modules. When you need to adjust the type of accessed services or replace such
a faulty optical module, you just need to directly replace the pluggable optical module without
replacing its board.
21.1 Overview
The SFP/eSFP is a small form-factor pluggable optical transceiver. It is mainly used for SDH
optical communication and Ethernet data communication. The XFP is a 10-Gigabit small formfactor pluggable optical transceiver. It is mainly for SDH optical communication, GE/10GE data
communication, and DWDM communication.
21.2 SFP/eSFP
This topic describes the BOM number, name, specifications, and supported boards of the SFP/
eSFP optical modules.
21.3 XFP
This topic describes the BOM number, name, specifications, and supported boards of the XFP
optical modules.
21.4 CWDM/DWDM
This topic describes the BOM number, name, specifications, and supported boards of the
CWDM/DWDM optical modules.
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21.1 Overview
The SFP/eSFP is a small form-factor pluggable optical transceiver. It is mainly used for SDH
optical communication and Ethernet data communication. The XFP is a 10-Gigabit small formfactor pluggable optical transceiver. It is mainly for SDH optical communication, GE/10GE data
communication, and DWDM communication.
Appearance
Figure 21-1 shows the appearances of the SFP and eSFP optical modules, and Figure 21-2
shows the appearance of the XFP optical module.
Figure 21-1 SFP/eSFP optical module
The dimensions of the SFP and eSFP optical modules are 13.4 mm (W) x 56.5 mm (D) x 8.5
mm (H).
Figure 21-2 XFP optical module
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The dimensions of the XFP optical module are 18.3 mm (W) x 78 mm (D) x 8.5 mm (H).
BOM
The BOM of a pluggable optical module is used to identify different types of optical modules.
The BOM can be marked on a label that is attached to each pluggable optical module.
Figure 21-3 shows the label of a pluggable optical module.
Figure 21-3 Label of a pluggable optical module
NOTE
You can check the specifications of an optical module in this manual according to the BOM of the optical
module.
21.2 SFP/eSFP
This topic describes the BOM number, name, specifications, and supported boards of the SFP/
eSFP optical modules.
Table 21-1 lists the BOM numbers and specifications of the SFP/eSFP optical modules.
Table 21-1 Mapping table of the BOM numbers and the types of the SFP/eSFP optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
340605
88
2 Mbit/s eSFP
optical module
Optical transceiver, eSFP,

1310 nm, 2.048 Mb/s, 15
dBm, 8 dBm, 26 dBm, LC,
SM, 2 km
N1PFL1
340602
87
155 Mbit/s SFP

optical module
Optical transceiver, SFP,

1310 nm, STM1, -19 to -14
dBm, -30 dBm, LC, MM, 2
km
N1ADQ1, N1EFF8,
N1IDQ1, N1MST4,
N1SLQ1, N1SLQ1A,
N1IDQ1A, N1EFF8A,
N1PEFF8, R1PEF4F
Specifications
Compatible Board
(Name-Encapsulation
Form-Operating
Wavelength-RateMinimum Output
Optical Power-Maximum
Output Optical PowerReceiver SensitivityOptical Interface TypeOptical Fiber TypeTransmission Distance)

1393

BOM
Numb
er
Name
340602
76
155 Mbit/s eSFP

optical module
340602
81
Issue 03 (2013-02-20)
Specifications
Compatible Board
(Name-Encapsulation
Form-Operating
1310 nm, STM1, -15 to -8
dBm, -31 dBm, LC, SM, 15
km
N1OU08, N1SL1, N2SL1,

N1SLQ1, N2SLQ1,
R1SLQ1, R1SL1, N1ADQ1,
N1EFF8, N1IDQ1, N1SLT1,
Q2CXL1, N2SLO1,
Q3CXL1, N1SL1A,
N1SLQ1A, R1CXLLN,
R2CXLLN, Q5CXLLN,
Q6CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLQ41, Q6CXLQ41,
N1IDQ1A, N3SLO1,
R3SL1, R3SLQ1,
N1EFF8A, R1PCXLN,
N1PEFF8, R1PEF4F,
N1EDQ41, TNN1CO1,
TNN1AFO1

1310 nm, STM1, -5 to 0 dBm,
-37 dBm, LC, SM, 40 km
N1SL1, N2SL1, N1SLQ1,

N2SLQ1, N1ADQ1,
N1IDQ1, Q2CXL1,
Q3CXL1, N2SLO1,
N1SL1A, N1SLQ1A,
N3SLO1, R1CXLLN,
R2CXLLN, Q5CXLLN,
Q6CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLQ41, Q6CXLQ41,
R1SL1, R3SL1, R1SLQ1,
R3SLQ1, N1SLT1,
R1PCXLN, N1PEFF8,
R1PEF4F, N1EDQ41,
TNN1CO1, TNN1AFO1

1394

BOM
Numb
er
Name
Issue 03 (2013-02-20)
Compatible Board
(Name-Encapsulation
Form-Operating
340602
82
340602
77
Specifications
622 Mbit/s eSFP

optical module

1550 nm, STM1, -5 to 0 dBm,
N1SL1, N2SL1, N1SLQ1,

N2SLQ1, R1SLQ1, R1SL1,
N1ADQ1, N1IDQ1,
Q2CXL1, Q3CXL1,
N1SL1A, N1SLQ1A,
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN,
R1CXLD41, R1CXLQ41,
R2CXLQ41, Q5CXLQ41,
Q6CXLQ41, N3SLO1,
R3SL1, R3SLQ1, N1SLT1,
N1PEFF8, R1PEF4F,
N1EDQ41, TNN1CO1,
TNN1AFO1

1310 nm, STM4, -15 to -8
km
N1SL4, N2SL4, N1SL4A,

N1SLD4, N2SLD4,
N1SLD4A, N1SLQ4,
N2SLQ4, N1SLQ4A,
R1PCXLN, N1EDQ41,
Q2CXL4, Q3CXL4,
Q5CXLLN, Q6CXLLN,
Q5CXLQ41, Q6CXLQ41,
R1CXLD41, R1CXLLN,
R2CXLLN, R1CXLQ41,
R2CXLQ41, R1SL4,
R3SL4, R1SLD4, R3SLD4

1395

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Specifications
Compatible Board
(Name-Encapsulation
Form-Operating
340602
80

1310 nm, STM4, -3 to 2 dBm,
N2SLQ4, N2SL4, N1SL4,

N1SLD4, N2SLD4,
N1SLQ4, N2SLQ4, R1SL4,
R1SLD4, N1ADL4,
N1IDL4, Q2CXL4,
Q3CXL4, N1MST4,
N1SL4A, N1SLD4A,
N1SLQ4A, R1CXLLN,
R2CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLLN, Q6CXLLN,
Q5CXLQ41, Q6CXLQ41,
R3SL4, R3SLD4,
R1PCXLN, N1EDQ41
340602
84

1550 nm, STM4, -3 to 2dBm,
N1SL4, N2SL4, N1SLD4,

N2SLD4, N1SLQ4,
N2SLQ4, R1SL4, R1SLD4,
N1ADL4, N1IDL4,
Q2CXL4, Q3CXL4,
N1SL4A, N1SLD4A,
N1SLQ4A, R1CXLLN,
R2CXLLN, Q5CXLLN,
Q6CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLQ41, Q6CXLQ41,
N1SL4A, N1SLD4A,
N1SLQ4A, R3SL4,
R3SLD4, R1PCXLN,
N1EDQ41

1396

BOM
Numb
er
Name
Compatible Board
(Name-Encapsulation
Form-Operating
340602
85

1550 nm, STM4, -3 to +2
km
N1SL4, N2SL4, N1SL4A,

N1SLD4, N2SLD4,
N1SLD4A, N2SLQ4,
N1SLQ4A, Q2CXL4,
Q3CXL4, Q5CXLLN,
Q6CXLLN, Q5CXLQ41,
Q6CXLQ41, R1CXLD41,
R1CXLLN, R2CXLLN,
R1CXLQ41, R2CXLQ41,
R1SL4, R3SL4, R1SLD4,
R3SLD4

1310 nm, 1.25 Gbit/s, -9 to -3
km
N2EGS2, N1EGT2,
N2EGR2, N2EMR0,
N1EGS4, N1EMS4,
N3EGS4, N2EGT2,
N3EGS2, N4EGS4,
N1EMS2, N1PEG16,
N1PEG8, R1PEGS1,
Q1PEGS2, TNN1EG8
340602
98

1310 nm, 1.25 Gbit/s, -5 to -0
km
N2EGS2, N3EGS2,
N1EGT2, N2EGT2,
N2EGR2, N2EMR0,
N1EGS4, N3EGS4,
N4EGS4, N1EMS4,
N1EMS2, N1PEG16,
N1PEG8, R1PEGS1,
Q1PEGS2, TNN1EG8
340603
60

1550 nm, 1.25 Gbit/s, -2 to 5
km
N1EGT2, N3EGS2,
N2EGT2, N4EGS4,
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2,
TNN1EG8
340604
73
Issue 03 (2013-02-20)
Specifications
1.25 Gbit/s eSFP

optical module

1397

Issue 03 (2013-02-20)
Specifications
BOM
Numb
er
Name
Compatible Board
340602
86
2.125 Gbit/s eSFP

optical module

850 nm, 2.125 Gbit/s (multi
rate), -9.5 to -2.5 dBm,
-17dBm, LC, MM, 0.5 km
N2EGS2, N1EGT2,
N2EMR0, N1EGS4,
N1EMS4, N3EGS4,
N2EGT2, N3EGS2,
N4EGS4, N1EMS2,
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2,
TNN1EG8
340602
78
2.5 Gbit/s eSFP

optical module
Optical Transceiver, eSFP,

1310 nm, STM16, -5 to 0
km
N1SLD16, N2SLQ16
340602
88

1310 nm, STM16, -10 to -3
km
N1SLQ16, N2SLQ16,
N1SLD16
340604
84
Optical Transceiver, eSFP,

1310 nm, 155 Mbit/s to 2.67
Gbit/s, -10 to -3 dBm, -21
dBm, LC, SM, 2 km
N1SLO16, N3SL16A,
Q2CXL16, Q5CXLLN,
Q6CXLLN, R1CXLLN,
R2CXLLN
340604
85

1310 nm, 155 Mbit/s to 2.67
Gbit/s, -5 to 0 dBm, -21 dBm,
LC, SM, 15 km
Q2CXL16, Q3CXL16,
N2SL16A, N3SL16A,
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN,
N1SLO16, R1PCXLN
340602
89

1310 nm, STM16, -2 to 3
km
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN
340604
88

1550 nm, STM16, -2 to 3
km
N1SLQ16, N2SLQ16,
N2SL16A, N3SL16A,
N1SLD16, Q5CXLLN,
Q6CXLLN, R2CXLLN,
N1SLO16, R1PCXLLN
(Name-Encapsulation
Form-Operating

1398

BOM
Numb
er
Name
Specifications
Compatible Board
(Name-Encapsulation
Form-Operating
03030
GGV
OptiX HPLAT,
SSX2T1SA02, 2.5 Gbit/s
ESFP transceiver (-30 dBm
to -9 dBm, 1310 nm, 40 km,
-2 dBm to +3 dBm, LC)
N1SLD16, N1SLO16,
N1SLQ16, N2SLQ16,
N3SL16A, Q2CXL16,
Q3CXL16
NOTE
Optical module data is subject to product versions, so contact Huawei local office for latest data.
21.3 XFP
This topic describes the BOM number, name, specifications, and supported boards of the XFP
optical modules.
Table 21-2 lists the BOM numbers and specifications of the XFP optical modules.
Table 21-2 Mapping table of the BOM numbers and the types of the XFP optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
340603
13
9.95 Gbit/s to
10.71 Gbit/s XFP
optical module
Specifications
Compatible Board
(Name-Encapsulation
Form-Operating
Optical transceiver, XFP,
1310 nm, 9.95 Gbit/s to 10.71
Gbit/s, -6 dBm to -1 dBm, -11
dBm, LC, SM, 10 km

N1SLD64, N1EAS2,
N4SL64, N1PEX1,
N2PEX1, N1PEX2,
TNN1EX2
1399

Specifications
BOM
Numb
er
Name
Compatible Board
03030J
CB
9.95 Gbit/s to 11.1

Gbit/s XFP optical
module

1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, -1 dBm to 2 dBm, -17
dBm, LC, SM, 40 km
N1SLD64, N4SL64
340603
62
10.3 Gbit/s XFP

optical module

850 nm, 10.3 Gbit/s, -7.3
dBm to -1.3 dBm, -7.5 dBm,
LC, MM, 0.3 km
N1PEX1
340603
22
9.95 Gbit/s to 11.1

Gbit/s XFP optical
module

1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, -1 dBm to 2 dBm, -15
dBm, LC, SM, 40 km
N1PEX1, N2PEX1,
N1PEX2, TNN1EX2
340603
61
9.95 Gbit/s to 11.1

Gbit/s XFP optical
module

1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, 0 dBm to 4 dBm, -24
dBm, LC, SM, 80 km
N1PEX1, N2PEX1,
N1PEX2, TNN1EX2,
N4SL64
03030J
HE
10.71 Gbit/s XFP

optical module
Optical transceiver (-19 dBm

to 0 dBm, 1550 nm, 800 ps/
nm, -1 dBm to +2 dBm, 193.4
THz, LC/PC), 100 GHz
spacing wavelength, FEC,
EA
N4SL64
(Name-Encapsulation
Form-Operating
NOTE
21.4 CWDM/DWDM
This topic describes the BOM number, name, specifications, and supported boards of the
CWDM/DWDM optical modules.
Issue 03 (2013-02-20)

1400

CWDM Optical Module

Table 21-3 lists the BOM numbers and specifications of the 2.5 Gbit/s CWDM eSFP optical
modules. Table 21-4 lists the BOM numbers and specifications of the 10 Gbit/s CWDM XFP
optical modules.
Table 21-3 Mapping table of the BOM numbers and the types of the 2.5 Gbit/s CWDM eSFP
optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
(Name, Encapsulation
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Optical Power, Receiver
Sensitivity, Optical
Interface Type, Optical
Fiber Type, Transmission
Distance)
Compatible Board
340604
83
2.5 Gbit/s CWDM

eSFP optical
module
Transceiver, eSFP, 1471 nm,

100 Mbit/s to 2.67 Gbit/s, 0
dBm, 5 dBm, -28 dBm, LC,
80 km
N3SLH41, N1SL4A,
N3SLQ41, N3SL16A,
N1PEG8, N4SLO16,
N4SLQ16, TNN1EG8
340604
81

80 km
340604
79

80 km
340604
82

80 km
340604
78

80 km
340604
76

80 km
340604
77

80 km
1401

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340604
80

80 km
340604
16

single mode, 40 km
340604
17

single mode, 40 km
340604
18

single mode, 40 km
340604
19

single mode, 40 km
340604
20

single mode, 40 km
340604
21

single mode, 40 km
340604
22

single mode, 40 km

Compatible Board
N1PEG16, R1PEGS1,
Q1PEGS2, N1PEG8,
TNN1EG8
1402

BOM
Numb
er
Name
340604
23
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
Compatible Board

single mode, 40 km
Table 21-4 Mapping table of the BOM numbers and the types of the 10 Gbit/s CWDM XFP
optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
Compatible Board
340605
47
9.95 Gbit/s to 11.1

Gbit/s CWDM
XFP optical
module
Transceiver, XFP, 1471 nm,

9.95 Gbit/s to 11.1 Gbit/s, 1
70 km
TNN1EX2, N4SL64,
N4SLD64, N1PEX2,
N2PEX1
340605
48

70 km
340605
49

70 km
340605
50

70 km

1403

BOM
Numb
er
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340605
51

70 km
340605
52

70 km
340605
53

70 km
340605
54

70 km
Compatible Board
DWDM Optical Module

Table 21-5 lists the BOM numbers and specifications of the 2.5 Gbit/s DWDM eSFP optical
modules. Table 21-6 lists the BOM numbers and specifications of the 10 Gbit/s DWDM XFP
optical modules.
Issue 03 (2013-02-20)

1404

Table 21-5 Mapping table of the BOM numbers and the types of the 2.5 Gbit/s DWDM eSFP
optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
Compatible Board
340603
66
2.5 Gbit/s DWDM

eSFP optical
module

1560.61 nm, 125 Mbit/s to
2.67 Gbit/s, 1 dBm, 3 dBm,
-28 dBm, LC, 120 km
N3SLH41, N1SL4A,
N3SLQ41, N3SL16A,
N1PEG8, TNN1EG8,
N4SLO16, N4SLQ16
340603
72

1559.79 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
73

1558.98 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
74

1558.17 nm, 125 Mbit/s to
2.67 G bit/s, 1 dBm, 3 dBm,
-28 dBm, LC, 120 km
340603
75

1557.36 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
76

1556.55 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
77

1555.75 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
78

1554.94 nm, 125 Mbit/s to
-28 dBm, LC, 120 km

1405

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340603
79

1554.13 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
80

1553.33 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
81

1552.52 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
82

1551.72 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
83

1550.92 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
84

1550.12 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
85

1549.32 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
86

1548.51 nm, 125 Mbit/s to
-28 dBm, LC, 120 km

Compatible Board
1406

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340603
87

1547.72 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
88

1546.92 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
89

1546.12 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
90

1545.32 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
91

1544.53 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
92

1543.73 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
93

1542.94 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
94

1542.14 nm, 125 Mbit/s to
-28 dBm, LC, 120 km

Compatible Board
1407

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340603
95

1541.35 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
96

1540.56 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
97

1539.77 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
98

1538.98 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340603
99

1538.19 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
00

1537.40 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
01

1536.61 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
02

1535.82 nm, 125 Mbit/s to
-28 dBm, LC, 120 km

Compatible Board
1408

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power,
Maximum Output
Distance)
340604
03

1535.04 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
04

1534.25 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
05

1533.47 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
06

1532.68 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
07

1531.90 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
08

1531.12 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
09

1530.33 nm, 125 Mbit/s to
-28 dBm, LC, 120 km
340604
10

1529.55 nm, 125 Mbit/s to
-28 dBm, LC, 120 km

Compatible Board
1409

Table 21-6 Mapping table of the BOM numbers and the types of the 10 Gbit/s DWDM XFP
optical modules
Issue 03 (2013-02-20)
BOM
Numb
er
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Power, Maximum
Output Optical Power,
Receiver Sensitivity,
Optical Interface Type,
Optical Fiber Type,
Transmission Distance)
Compatible Board
03030J
GQ
9.95 Gbit/s to 11.1

Gbit/s DWDM
XFP optical
module

1560.61 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm, 2 dBm,
N1SL64, N1PEX2,
N2PEX1, N4SL64,
TNN1EX2
03030J
GR

1559.79 nm, 9.95 Gbit/s to
03030J
GS

1558.98 nm, 9.95 Gbit/s to
03030J
GT

1558.17 nm, 9.95 Gbit/s to
03030J
GU

1557.36 nm, 9.95 Gbit/s to
03030J
GV

1556.55 nm, 9.95 Gbit/s to
03030J
GW

1555.75 nm, 9.95 Gbit/s to
03030J
GX

1554.94 nm, 9.95 Gbit/s to

1410

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Fiber Type,
03030J
GY

1554.13 nm, 9.95 Gbit/s to
03030J
HA

1553.33 nm, 9.95 Gbit/s to
03030J
HB

1552.52 nm, 9.95 Gbit/s to
03030J
HC

1551.72 nm, 9.95 Gbit/s to
03030J
HD

1550.92 nm, 9.95 Gbit/s to
03030J
HE

1550.12 nm, 9.95 Gbit/s to
03030J
HF

1549.32 nm, 9.95 Gbit/s to
03030J
HG

1548.51 nm, 9.95 Gbit/s to
03030J
HH

1547.72 nm, 9.95 Gbit/s to

Compatible Board
1411

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Fiber Type,
03030J
HJ

1546.92 nm, 9.95 Gbit/s to
03030J
HK

1546.12 nm, 9.95 Gbit/s to
03030J
HL

1545.32 nm, 9.95 Gbit/s to
03030J
HM

1544.53 nm, 9.95 Gbit/s to
03030J
HN

1543.73 nm, 9.95 Gbit/s to
03030J
HP

1542.94 nm, 9.95 Gbit/s to
03030J
HQ

1542.14 nm, 9.95 Gbit/s to
03030J
HR

1541.35 nm, 9.95 Gbit/s to
03030J
HS

1540.56 nm, 9.95 Gbit/s to

Compatible Board
1412

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Fiber Type,
03030J
HT

1539.77 nm, 9.95 Gbit/s to
03030J
HU

1538.98 nm, 9.95 Gbit/s to
03030J
HV

1538.19 nm, 9.95 Gbit/s to
03030J
HW

1537.40 nm, 9.95 Gbit/s to
03030J
HX

1536.61 nm, 9.95 Gbit/s to
03030J
HY

1535.82 nm, 9.95 Gbit/s to
03030J
JA

1535.04 nm, 9.95 Gbit/s to
03030J
JB

1534.25 nm, 9.95 Gbit/s to
03030J
JC

1533.47 nm, 9.95 Gbit/s to

Compatible Board
1413

BOM
Numb
er
Issue 03 (2013-02-20)
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Fiber Type,
03030J
JD

1532.68 nm, 9.95 Gbit/s to
03030J
JE

1531.90 nm, 9.95 Gbit/s to
03030J
JF

1531.12 nm, 9.95 Gbit/s to
03030J
JG

1530.33 nm, 9.95 Gbit/s to
03030J
JH

1529.55 nm, 9.95 Gbit/s to
340605
33

1551.72 nm, 9.95 Gbit/s to
340605
01

1550.92 nm, 9.95 Gbit/s to
340605
02

1550.12 nm, 9.95 Gbit/s to
340605
14

1549.32 nm, 9.95 Gbit/s to

Compatible Board
N1PEX2, N2PEX1,
N4SLD64, N4SL64,
TNN1EX2
1414

BOM
Numb
er
Name
Form, Operating
Wavelength, Rate,
Minimum Output
Optical Fiber Type,
340605
31

1548.51 nm, 9.95 Gbit/s to
340605
34

1532.68 nm, 9.95 Gbit/s to
340605
03

1531.90 nm, 9.95 Gbit/s to
340605
04

1531.12 nm, 9.95 Gbit/s to
340605
15

1530.33 nm, 9.95 Gbit/s to
340605
32

1529.55 nm, 9.95 Gbit/s to
Compatible Board
NOTE
Issue 03 (2013-02-20)

1415

22
22 Pluggable Electrical Module
Pluggable Electrical Module
A pluggable electrical module is used at an SFP interface to transmit/receive electrical signals.
Appearance
Figure 22-1 shows the appearance of the SFP electrical module.
Figure 22-1 Appearance of the GE SFP electrical module
SFP electrical module

Table 22-1lists the BOM numbers and specifications of the pluggable electrical modules.
Table 22-1 Mapping table of the BOM numbers and the types of the electrical modules
Issue 03 (2013-02-20)
BOM Number
Name
Specifications
Compatible Board
34100052
1000BASE-T SFP
electrical module
1000BASE-T (RJ45)
SFP electrical
module, 100 m
TNN1EG8,
N1PEG8,
Q1PEGS2,
R1PEGS1, N3EGS2,
N2EGT2, N1EGS4,
N4EGS4, N1EMS4,
N1EMS2

1416

22 Pluggable Electrical Module
NOTE
Electrical module data is subject to product versions, so contact Huawei local office for latest data.
Issue 03 (2013-02-20)

1417

23 Cables
23
Cables
About This Chapter

This topic describes the cables that the equipment uses, including the fiber jumper, power cable,
alarm cable, management cable, signal cable, and clock cable.
23.1 Fiber Jumper
This topic describes the categories and connectors of the fiber jumpers.
23.2 Power Cable and Ground Cable
The power cables and ground cables include the cabinet power cable, subrack power cable, COA
power cable, and ground cable of the cabinet door.
23.3 Alarm Cable
The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
23.4 Management Cable
The management cables include the serial cable, ordinary phone line, COA cascading cable, and
network cable.
23.5 Signal Cable
The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
23.6 Clock Cable
The clock cables include the 75-ohm/120-ohm clock cable and clock transit cable.
Issue 03 (2013-02-20)

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23 Cables
23.1 Fiber Jumper

This topic describes the categories and connectors of the fiber jumpers.
23.1.1 Categories of the Fiber Jumpers

The OptiX OSN equipment uses various types of fiber jumpers.
Table 23-1 lists the categories of the fiber jumpers that the OptiX OSN equipment uses.
Table 23-1 Categories of the fiber jumpers that the OptiX OSN equipment uses
Usage
Connector
1
Connector
2
Fiber
Available Length
Used to connect
the OptiX OSN
equipment to the
ODF or to
connect an
interface board of
the OptiX OSN
equipment to
other equipment
LC/PC
FC/PC
2 mm singlemode fiber
6 m, 10 m, 20 m, 30 m,
and 50 m
2 mm multimode fiber
3 m, 5 m, 10 m, 20 m,
30 m, and 50 m
5 m, 10 m, 20 m, 30 m,
and 50 m
10 m, 20 m, 30 m, and
50 m
Used to connect
the OptiX OSN
equipment
LC/PC
SC/PC
SC/PC
SC/PC
2 m, 5 m, 10 m, 20 m,
30 m, 50 m, and 80 m
LC/PC
LC/PC
1.5 m, 3 m, 5 m, 10 m,
20 m, and 30 m
3 m, 5 m, 10 m, 20 m,
and 30 m
LC/PC
FC/PC
6 m, 10 m, 20 m, 30 m,
and 50 m
LC/PC
SC/PC
5 m, 10 m, 20 m, 30 m,
and 50 m
Select the fiber connector and fiber length according to the on-site survey.
23.1.2 Connector
The OptiX OSN equipment uses various types of fiber connectors.
The four types of fiber connectors are described as follows:
l
Issue 03 (2013-02-20)
Most of the optical interfaces on the front panels of the boards are the LC/PC optical
interfaces. See Figure 23-1.
1419

23 Cables
The N2OU08 and 61COA provide the SC/PC optical interfaces.
The "IN" interface on the case-shaped 62COA that is externally installed uses the LSH/
APC connector. See Figure 23-4.
Generally, the ODF on the client side provides the FC/PC or SC/PC optical interface.
Figure 23-3 and Figure 23-2 show the corresponding FC/PC and SC/PC fiber connectors.
Table 23-2 describes the four types of fiber connectors.

Table 23-2 Types of fiber connectors
Type of Internal
Fiber Connector
Description
LC/PC
Plug-in square fiber connector/protruding polished
LSH/APC
Connector with a dust-proof cover/protruding polished (eight

degrees)
FC/PC
Round fiber connector/protruding polished
SC/PC
Square fiber connector/protruding polished
LC/PC Fiber Connector

Figure 23-1 shows the appearance of the LC/PC fiber connector.
Figure 23-1 Appearance of the LC/PC fiber connector
The axial operation instead of rotation is required to insert or remove an LC/PC fiber connector.
To insert a fiber jumper that uses an LC/PC connector, align the head of the fiber jumper with
the optical interface and apply proper force. To remove the fiber jumper, first, press the clip,
then, slightly push the fiber connector inward, and finally, pull out the connector.
SC/PC Fiber Connector

Figure 23-2 shows the appearance of the SC/PC fiber connector.
Issue 03 (2013-02-20)

1420

23 Cables
Figure 23-2 Appearance of the SC/PC fiber connector
FC/PC Fiber Connector

Figure 23-3 shows the appearance of the FC/PC fiber connector.
Figure 23-3 Appearance of the FC/PC fiber connector
LSH/APC Fiber Connector

Figure 23-4 shows the appearance of the LSH/APC fiber connector.
Figure 23-4 Appearance of the LSH/APC fiber connector
Issue 03 (2013-02-20)

1421

23 Cables
23.2 Power Cable and Ground Cable

The power cables and ground cables include the cabinet power cable, subrack power cable, COA
power cable, and ground cable of the cabinet door.
23.2.1 Power Cable of the Cabinet

The -48 V power cable, BGND power cable, and PGND power cable are used to supply power
to the equipment in a cabinet. One end of the power cable is connected to the power distribution
cabinet and the ground bar in the equipment room, and the other end is connected to the DC
PDU at the top of the cabinet.
Structure
Figure 23-5 shows the structure of the -48 V/BGND power cable of the cabinet. Figure 23-6
and Figure 23-7 show the structure of the PGND power cable of the cabinet.
Figure 23-5 Structure of the -48 V/BGND power cable of the cabinet
1
3
1. Cord end terminal
2. Bare crimping terminal - type OT
3. Cable tie
Figure 23-6 Structure of the PGND power cable of the cabinet (JG2)
2. Cable tie
3. Bare crimping terminal (JG2)
4. Heat shrink tubing
5. Main label
6. Wire
Issue 03 (2013-02-20)

1422

23 Cables
Figure 23-7 Structure of the PGND power cable of the cabinet (OT)
2. Cable tie
3. Bare crimping terminal (OT)
5. Main label
6. Wire
Table 23-3 Technical specifications of the cabinet power cable
Item
-48 V power
cable of the
cabinet
BGND power
cable of the
cabinet
PGND power
cable of the
cabinet
Issue 03 (2013-02-20)
Description
Terminal 2
(telecommu
nications
room side)
Bare crimping terminal - type OT - M8 - tin plated - round

bare terminal - 16 mm2/25 mm2
Terminal 1
(PDU side)
Single cord end terminal - 0.024 m - insertion depth of 12

mm - 80 A - green - 16 mm2/25 mm2
Cable type
Power cable - 450 V/750 V - blue - 85 A - 16 mm2/25

mm2
Terminal 2

Terminal 1
Single cord end terminal - 0.024 m - insertion depth of 12

mm - 80 A - green - 16 mm2/25 mm2
Cable type
Power cable - 450 V/750 V - black - 16 mm2/25 mm2
Terminal 1

Terminal 3


1423

Item
23 Cables
Description
Cable type
Power cable - 450 V/750 V - yellow/green - 16 mm2/25

mm2
Fireproof class
IEC60332-3A
Length
Determined by the site survey result.
Structure
Figure 23-8 shows the structure of the -48 V/BGND power cable of the cabinet. Figure 23-9
shows the structure of the PGND power cable of the cabinet.
Figure 23-8 Structure of the -48 V/BGND power cable
Figure 23-9 Structure of the PGND power cable
Issue 03 (2013-02-20)

1424

23 Cables
Item
Description
-48 V power
cable of the
cabinet
BGND power
cable of the
cabinet
PGND power
cable of the
cabinet
Terminal 2
(telecommu
nications
room side)

bare terminal - 16 mm2/25 mm2/35 mm2
Terminal 1
(PDU side)
Bare crimping terminal - type JG2 - M6 - tin plated - round

Cable type
Power cable - 450 V/750 V - blue - 16 mm2/25 mm2/35

mm2
Terminal 2

Terminal 1
Bare crimping terminal - type JG2 - M6 - tin plated - round

Cable type
Power cable - 450 V/750 V - black - 16 mm2/25 mm2/35

mm2
Terminal 1

Terminal 3

Cable type
Power cable - 450 V/750 V - yellow/green - 16 mm2/25

mm2/35 mm2
Fireproof class
IEC60332-3A
Length
Determined by the site survey result.
Structure
Figure 23-10 shows the structure of the -48 V/BGND power cable of the cabinet. Figure
23-11 shows the structure of the PGND power cable of the cabinet.
Figure 23-10 Structure of the -48 V/BGND power cable
Bare crimping terminal (JG2)
Issue 03 (2013-02-20)
Bare crimping terminal (type OT)

1425

23 Cables
Figure 23-11 Structure of the PGND power cable
Item
Description
Terminal
Bare crimping terminal - type JG2 - 25 mm2 -M6 - 95 A - in plated

Bare crimping terminal - type OT - 25 mm2- M8 - tin plated - round
bare terminal
NOTE
Select cables with proper cross-sectional areas according to the required length of cabinet power cables:
l If the length of the cabinet power cable is required to be not more than 20 m, select the cable with a
cross-sectional area of 16 mm2.
l If the length of the cabinet power cable is required to be in the range from 21 m to 30 m, select the
cable with a cross-sectional area of 25 mm2.
l If the length of the cabinet power cable is required to be in the range from 31 m to 50 m, select the
cable with a cross-sectional area of 35 mm2.
Pin Assignments
None.
23.2.2 Ground Cable of the Cabinet Door

The ground cable of the cabinet door grounds the front door, rear door and side panels of the
cabinet. The ground cables of the cabinet door are correctly connected before delivery.
Structure
Figure 23-12 shows the structure of the ground cable of the cabinet door.
Issue 03 (2013-02-20)

1426

23 Cables
Figure 23-12 Structure of the ground cable of the cabinet door
3. Main label
Pin Assignments
None.
Item
Description
Terminal X1/X2
Bare crimping terminal - OT - 6 mm2 - M6 - tin plated - round

insulated terminal - 12 to 10 AWG
Cable
Type
Wire - 600 V - UL1015 - 10 AWG - 105-core twisted pair yellow and green, round - 50 A
Fireproof
class
UL1015
Length
0.35 m
23.2.3 Subrack Power Cable

The subrack power cable connects the DC PDU at the top of the cabinet and the PIU in the
subrack. The subrack power cable leads the -48 V power from the top of the cabinet to the
subrack. The subrack power cable is correctly connected before delivery.
NOTE
A type III subrack (2300 W) uses different power cables from those used by a general subrack or an
enhanced subrack (1100 W).
Structure
Figure 23-13 shows the structure of the power cable for the general subrack and enhanced
subrack (1100 W).
Issue 03 (2013-02-20)

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23 Cables
Figure 23-13 Structure of the power cable for the general subrack and enhanced subrack (1100
W)
1. Cable connector
2. Main label
3. Cable tie
4. Label
Figure 23-14 shows the structure of the power cable for the type III subrack (2300 W).
Figure 23-14 Structure of the power cable for the type III subrack (2300 W)
1
W1
W1
W2
W2
X1
X2
Pin Assignments
Table 23-6 provides the pin assignments of the power cable for the general subrack and enhanced
subrack (1100 W).
Issue 03 (2013-02-20)

1428

23 Cables
Table 23-6 Pin assignments of the power cable for the general subrack and enhanced subrack
(1100 W)
Cable
Connector
Bare
Crimping
Terminal
Connection
Color of the Core
X1.A1
X2
A1 is connected to X2.
Blue (-48 V power)
X1.A3
X3
A3 is connected to X3.
Black (power ground)
Table 23-7 Technical specifications of the power cable for the general subrack and enhanced
subrack (1100 W)
Item
Description
Cable connector X1
Cable connector - type D - 3-pin - female - without intermediate

male terminals
Bare crimping terminals

X2 and X3
Single cord end terminal - 4 mm2 - 20 A - insertion depth of 10

mm - gray
Cable
Type
Power cable - 600 V - 5.26 mm2 - 10 AWG - black (the core is in

blue and black) - 41 A
Number of
cores
Fireproof
class
CM
Color
The core is in blue and black.
Length
2.5 m, 3 m, and 3.5 m
Table 23-8 Technical specifications of the power cable for the type III subrack (2300 W)
Item
Description
Cable connector
Bare crimping terminal - OT2- 10 mm2 - 60 A - tin plated
Cable
l Wire - 450 V/750 V - H07Z - K UL3386 - 10 mm2 - blue
Type
l Wire - 450 V/750 V - H07Z - K UL3386 - 10 mm2 - black
23.2.4 COA Power Cable

The PIU can supply power to a maximum of two pieces of external equipment (for example, the
COA).
Issue 03 (2013-02-20)

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23 Cables
The COA power cable connects a power interface on the PIU to a power interface of the external
equipment. Both ends of the COA power cable use the 4-pin connector. One end of the COA
power cable is connected to the PIU and the other end is connected to the power interface of the
external equipment (for example, the COA).
Structure
Figure 23-15 shows the structure of the COA power cable.
Figure 23-15 Structure of the COA power cable
1
A-A
W1
3 1
4 2
X1
A 2
X3
W2
X2
W1.1
W1
W1.2
W2.1
X3
W2
W2.2
1. Common terminal - female 2. Common connector - 4-pin 3. Main label A-A. Sectional view in direction A
Pin Assignments
Table 23-9 provides the pin assignments of the COA power cable.
Table 23-9 Pin assignments of the COA power cable
Connectors X1
and X2
Cables W1 and W2
Color
Connector X3
X1.1
W1.1
Brown
X3.1
X2.1
W2.1
X1.3
W1.2
Black
X3.3
X2.3
W2.2
Issue 03 (2013-02-20)
Item
Description
Connector X3
Common connector - 4-pin - double rows/4.20 mm

1430

23 Cables
Item
Description
Connector X1/X2
Common terminal - female - 4-pin - 18/26 AWG - 13.7 mm in

length
Model of wire W1/W2
Symmetrical twisted-pair cable - 0 ohms - UL2464 - 0.64 mm 22 AWG - one pair - black
Number of cores
Fireproof class
CM
Color
Black
Length
1.8 m
23.2.5 RPC Power Cable

One end of the RPC power cable is connected to the power input interface of the case-shaped
Raman amplifier, and the other end is connected to the output interface of the DC power
distribution box at the top of the cabinet.
Structure
Figure 23-16 shows the structure of the RPC power cable.
Figure 23-16 Structure of the RPC power cable
Label 3
Main label
Label 1
Label 2
1. Bare crimping terminal 2. Common connector - 4- 3. Common terminal pin

female
A-A. Sectional view in

direction A
Pin Assignments
Table 23-10 provides the pin assignments of the RPC power cable.
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Table 23-10 Pin assignments of the RPC power cable

Connectors X1
and X2
Cables W1 and W2
Color
Connector X3
X1
W1
Blue
X3.1
X2
W1
Black
X3.3
Table 23-11 lists the technical specifications of the RPC power cable.
Table 23-11 Technical specifications of the RPC power cable
Item
Description
Connector X3
Common terminal - female - 18/26 AWG 13.7 mm in length, common connector - 4-pin
- double rows - 4.2 mm
Connector X1/X2
Bare crimping terminal - single cord end

terminal - 1 mm2 - 5 A - tin plated - insertion
depth of 6 mm - yellow
Model of wire W1/W2
Power cable - 600 V - UL1015 - 18 AWG black - OA
Number of cores
Fireproof class
VM-1
Color
Blue and black
Length
3.5 m
23.3 Alarm Cable

The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
23.3.1 Cabinet Indicator Cable

The cabinet indicator cable is used to connect the AUX in the subrack to the cabinet indicators.
The cabinet indicator cable leads the indicator signal from the AUX to the cabinet indicators.
Structure
Figure 23-17 shows the structure of the cabinet indicator cable.
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Figure 23-17 Structure of the cabinet indicator cable
X2
X3
X1
X4
X5
A-A. Sectional view in direction A
B-B. Sectional view in direction B
Pin Assignments
Table 23-12 provides the pin assignments of the cabinet indicator cable.
Table 23-12 Pin assignments of the cabinet indicator cable
Connector
X1
Direction
Connector X2/X3/X4/X5
Relations
hip
Print on the
Label
X1.4
Out
X2.2
Green
X1.5
Out
X2.1
Twisted
pair
X1.1
Out
X3.2
Red
X1.2
Out
X3.1
Twisted
pair
X1.3
Out
X4.2
Orange
X1.6
Out
X4.1
Twisted
pair
X1.7
Out
X5.2
Yellow
X1.8
Out
X5.1
Twisted
pair
Issue 03 (2013-02-20)
Item
Description
Connector X1
Network interface connector - 8-pin - 8-bit - shielded RJ45 connector
Connector X2/X3/X4/X5
Common connector - 2-pin - single row/2.5 mm
Cable type
Symmetrical twisted-pair cable - 120 ohms - SEYPVPV

- 0.5 mm - 24 AWG - 8-core - PANTONE 430U
Number of cores

1433

23 Cables
Item
Description
Fireproof class
CM
Diameter of the core
0.5 mm
Length
2.5 m, 3 m, and 3.5 m
23.3.2 Indicator Cascading Cable Between Subracks or Alarm

Cascading Cable Between the OptiX OSN Equipment
The indicator cascading cable between subracks or the alarm cascading cable between the OptiX
OSN equipment cascades the indicator signals or alarm signals between the subracks of the
Both ends of the cable use the RJ45 connector. One end of the cable is connected to the LAMP1
or ALMO2 interface of the AUX in one subrack. The other end of the cable is connected to the
LAMP2 or ALMO1 interface of the AUX in another subrack.
Structure
Figure 23-18 shows the structure of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment.
Figure 23-18 Structure of the indicator cascading cable between subracks or the alarm cascading
cable between the OptiX OSN equipment
1. RJ-45 network interface connector
2. Label 1
Pin Assignments
Table 23-13 provides the pin assignments of the indicator cascading cable between subracks or
the alarm cascading cable between the OptiX OSN equipment.
Table 23-13 Pin assignments of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment
Issue 03 (2013-02-20)
Connect
or X1
Directio
n
Connect
or X2
Relationshi
p
Alarm Output
X1.1
Out
X2.1
Twisted pair
Critical alarm output and major

alarm output (+)

1434

Connect
or X1
Directio
n
Connect
or X2
X1.2
Out
X2.2
X1.3
Out
X2.3
X1.6
Out
X2.6
X1.4
Out
X2.4
X1.5
Out
X2.5
X1.7
Out
X2.7
X1.8
Out
X2.8
23 Cables
Relationshi
p
Alarm Output
Critical alarm signal output and
major alarm signal output (-)
Twisted pair
Minor alarm signal output and

warning alarm signal output (+)
Minor alarm signal output and
warning alarm signal output (-)
Twisted pair

Alarm signal output 1 (-)
Twisted pair

Alarm signal output 2 (-)
Item
Description
Connector X1/
X2
Network interface connector - 8-pin - 8-bit - shielded - RJ45 connector
Cable type
Symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.5 mm - 24

AWG - 8-core - PANTONE 430U
Number of cores
Fireproof class
CM
Diameter of the
core
0.5 mm
Length
3 m, 5 m, 10 m, and 20 m
23.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment

and the Other Huawei Transmission Equipment
The alarm cascading cable cascades the alarm signals of the OptiX OSN equipment and the
alarm signals of the other Huawei transmission equipment such as the OptiX 2500+ and OptiX
OSN 9500.
Both ends of the cable use the RJ45 connector. One end of the cable is connected to the
ALMO1 or ALMO2 interface of the OptiX OSN subrack. The other end of the cable is connected
to the alarm output interface or the alarm cascading interface of the subrack of the other Huawei
transmission equipment.
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Structure
Figure 23-19 shows the structure of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Figure 23-19 Structure of the alarm cascading cable between the OptiX OSN equipment and
the other Huawei transmission equipment
1. RJ-45 network interface connector 2. Main label 3. Label 1 4. Cable connector - type D - 9-pin - female
L: 5 m, 10 m, and 20 m
Pin Assignments
Table 23-14 provides the pin assignments of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Table 23-14 Pin assignments of the alarm cascading cable between the OptiX OSN equipment
and the other Huawei transmission equipment
Connector
X1
Direction
Connector
X2
Relations
hip
Description
X1.1
Out
X2.7
Critical alarm signal output (+)
X1.2
Out
X2.3
Twisted
pair
X1.3
Out
X2.6
Major alarm signal output (+)
X1.6
Out
X2.1
Twisted
pair
Critical alarm signal output (-)
Major alarm signal output (-)
Issue 03 (2013-02-20)
Item
Description
Connector
X1

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23 Cables
Item
Description
Connector
X2
Cable connector - type D - 9-pin - female
Cable type
Symmetrical twisted-pair cable - 100 ohms - SEYVP - 0.48 mm - 26 AWG

- 4-core - black
Number of
cores
Fireproof
class
CM
Diameter of
the core
0.5 mm
Length
5 m, 10 m, and 20 m
23.3.4 Alarm Input/Output Cable

The alarm input cable transmits the alarm signals of the external equipment to the OptiX OSN
equipment. The alarm output cable transmits the alarm signals of the OptiX OSN equipment to
the centralized alarm monitoring equipment.
The alarm input/output cable uses an RJ45 connector at one end to connect to the alarm input/
output interface of the equipment. The other end of the alarm input/output cable is connected to
the external equipment or the centralized alarm monitoring equipment. The connector needs to
be prepared on site as required. Each alarm input/output cable transmits four channels of alarm
signals.
Structure
Figure 23-20 shows the structure of the alarm input/output cable.
Figure 23-20 Structure of the alarm input/output cable
Issue 03 (2013-02-20)
2. Main label

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23 Cables
Pin Assignments
Table 23-15 provides the pin assignments of the alarm input/output cable.
Table 23-15 Pin assignments of the alarm input/output cable
Connector X1
Color
Relationship
Usage
X1.1
Blue
Twisted pair
Critical or major alarm input/

output (+)
X1.2
White
X1.3
Orange
X1.6
White
X1.4
Green
X1.5
White
X1.7
Brown
X1.8
White
Critical or major alarm input/

output (-)
Twisted pair
Minor or warning alarm input/

output (+)
Minor or warning alarm input/
output (-)
Twisted pair
Alarm signal input/output 1 (+)

Alarm signal input/output 1 (-)
Twisted pair
Alarm signal input/output 2 (+)

Alarm signal input/output 2 (-)
NOTE
X1.1 to X1.8 can be set to alarm signal input or alarm signal output as required.
Item
Description
Connector X1
Cable type
Symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.5 mm - 24 AWG

- 8-core - PANTONE 430U
Number of
cores
Fireproof class
CM
Core diameter
0.5 mm
Length
10 m, 20 m, and 30 m
23.4 Management Cable

The management cables include the serial cable, ordinary phone line, COA cascading cable, and
network cable.
Issue 03 (2013-02-20)

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23.4.1 OAM Serial Cable

The OAM serial cable is used for the management and remote maintenance of the OptiX OSN
equipment.
The OAM serial cable uses an RJ45 connector at one end to connect to the OAM interface of
the equipment and uses a DB25 connector at the other end to connect to a laptop computer, serial
NMS, or modem.
Structure
Figure 23-21 shows the structure of the OAM serial cable (using the DB25 connector).
Figure 23-21 Structure of the OAM serial cable
1. RJ-45 network
interface connector
2. Main label 3. Cable connector DB25 male
A-A. Sectional view in B-B. Sectional view in

direction A
direction B
Pin Assignments
Table 23-16 provides the pin assignments of the OAM serial cable.
Table 23-16 Pin assignments of the OAM serial cable
Issue 03 (2013-02-20)
Connecto
r X1
Direction
Connector X2
Relationshi
p
Description
X1.2
Out
X2.20
Single
Data terminal ready (DTR)
X1.3
Out
X2.2
Single
Transmitting data (TD)
X1.6
In
X2.3
Single
Receiving data (RD)
X1.4
X2.7
Twisted pair
Signaling ground (SG)
X1.5

1439

23 Cables
Item
Description
Connector X1
Network interface connector - RJ45 connector - 8-pin - 8-bit - shielded connector
Connector X2
Cable connector - type D - 25-pin - male, or cable connector - type D - 9pin - male
Type

Number of
cores
Fireproof class
CM
Length
5000 mm
23.4.2 Serial 1 to 4/F1/F&f Serial Cable

The serial 1-4/F1/F&f serial cable uses an RJ45 connector at one end to connect to the serial 1-4
interfaces, F1 serial port, or F&f serial port, and uses a DB9 connector at the other end to connect
to the external detecting equipment or external managed equipment.
The serial 1-4/F1/F&f serial cable performs the following functions:
l
Transparently transmits the environment monitoring data signal.
Manages external devices such as the COA.
Structure
Figure 23-22 shows the structure of the serial 1-4/F1/F&f serial cable.
Figure 23-22 Structure of the serial 1-4/F1/F&f serial cable
1. RJ-45 network
interface connector
Issue 03 (2013-02-20)
2. Main label 3. Cable connector DB9 male
A-A. Sectional view in B-B. Sectional view in

direction A
direction B

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23 Cables
Pin Assignments
Table 23-17 provides the pin assignments of the serial 1-4/F1/F&f serial cable.
Table 23-17 Pin assignments of the serial 1-4/F1/F&f serial cable
Connector
X1
Direction
Connector X2
Relationshi
p
Description
X1.1
Out
X2.8
Twisted pair
RS422TX+
X1.2
Out
X2.9
X1.3
In
X2.6
X1.6
In
X2.7
X1.4
In
X2.3
X1.8
Out
X2.2
X1.5
X2.5
RS422TXTwisted pair
RS422RX+
RS422RX-
Twisted pair
RS232RX
RS232TX
Single
SG
Item
Description
Connector X1
Network interface connector - RJ45 connector - 8-pin - 8-bit - shielded connector
Connector X2
Cable connector - type D - 9-pin - male
Cable type
(1) Symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.5 mm - 24

AWG - 8-core - PANTONE 430U (2) Symmetrical twisted-pair cable - 100
ohms - SEYVP - 0.48 mm - 26 AWG - 8-core - black
Number of
cores
Fireproof class
CM
Length
15 m in the case of cable type 1 and 3 m in the case of cable type 2
23.4.3 RS-232/RS-422 Serial Cable

The RS-232/RS-422 serial cable is used to transport the management signals between subnets.
Both ends of the RS-232/RS-422 serial cable use the RJ45 connector. One end of the RS-232/
RS-422 serial cable is connected to the RS-232/RS-422 serial port of the equipment. The other
end is connected to the RS-232/RS-422 serial port of another piece of equipment that needs to
make orderwire calls to the other equipment.
Issue 03 (2013-02-20)

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23 Cables
Structure
Figure 23-23 shows the structure of the RS-232/RS4-22 serial cable.
Figure 23-23 Structure of the RS-232/RS-422 serial cable
2. Main label
Pin Assignments
Table 23-18 provides the pin assignments of the RS-232/RS-422 serial cable.
Table 23-18 Pin assignments of the RS-232/RS-422 serial cable
Connecto
r X1
Direction
Connector X2
Relationship
Description
X1.3
In
X2.1
Twisted pair
RX+
X1.6
In
X2.2
X1.1
Out
X2.3
X1.2
Out
X2.6
X1.5
Out
X2.5
X1.4
In
X2.8
X1.8
X2.4
RXTwisted pair
TX+
TX-
Twisted pair
232TX
232RX
Single
SG
Issue 03 (2013-02-20)
Item
Description
Connector X1/X2
Network interface connector - RJ45 connector - 8-pin - 8-bit - shielded

- connector

1442

23 Cables
Item
Description
Cable type

Number of cores
Fireproof class
CM
Length
15 m
23.4.4 Ordinary Telephone Line

The ordinary telephone line is used to connect the orderwire phone. Both ends of the ordinary
telephone line use the RJ45 connector. One end of the ordinary telephone line is connected to
the PHONE interface of the equipment, and the other end is connected to the interface of the
orderwire phone.
Structure
Figure 23-24 shows the structure of the ordinary telephone line.
Figure 23-24 Structure of the ordinary telephone line
1. RJ45 connector
2. Main label
Pin Assignments
Table 23-19 provides the pin assignments of the ordinary telephone line.
Table 23-19 Pin assignments of the ordinary telephone line
Issue 03 (2013-02-20)
Connector X1
Connector X2
Description
X1.1
X2.1
Not connected
X1.2
X2.2
Not connected
X1.3
X2.3
TIP
X1.4
X2.4
RING
X1.5
X2.5
Not connected

1443

23 Cables
Connector X1
Connector X2
Description
X1.6
X2.6
Not connected
Item
Description
Connector X1/X2
Network interface connector - 6-pin - 26 to 28 AWG
Cable type
Power cable - 150 V - UL20251 - 0.08 mm2 - 28 AWG - black - 1

A - 2-core telephone line
Number of cores
Fireproof class
CM
Length
15 m
23.4.5 COA Cascading Cable

When multiple COAs are installed in a cabinet, use COA cascading cables to cascade the COAs.
Both ends of the COA cascading cable use the DB9 connector. One end of the COA cascading
cable is connected to the RS232-1 serial port of one COA, and the other end is connected to the
RS232-2 serial port of another COA.
Structure
Figure 23-25 shows the structure of the COA cascading cable.
Figure 23-25 Structure of the COA cascading cable
1. Cable connector - DB9 male
2. Label
Pin Assignments
Table 23-20 provides the pin assignments of the COA cascading cable.
Issue 03 (2013-02-20)

1444

23 Cables
Table 23-20 Pin assignments of the COA cascading cable

Connector X1
Connector X2
Remarks
One pair
Grounding
Item
Description
Connector X1/X2
Cable type
Symmetrical twisted-pair cable - 100 ohms - UL2464 - 0.32 mm 28 AWG - 2P - Huawei gray
Number of cores
Two pairs
Fireproof class
CM
Length
0.6 m and 2.5 m
23.4.6 Straight-Through Cable

The straight-through cable is used to connect the OptiX OSN equipment to an NM computer.
Both ends of the straight-through cable use the RJ45 connector. One end of the straight-through
cable is connected to the ETH interface of the equipment, and the other end is connected to the
network interface of the NM computer.
NOTE
As the ETH interface of the OptiX OSN equipment supports the auto-sensing function, the ETH interface
can use a straight-through cable or a crossover cable.
Structure
Figure 23-26 shows the structure of the straight-through cable.
Issue 03 (2013-02-20)

1445

23 Cables
Figure 23-26 Structure of the straight-through cable
2. Label 1
3. Main label
4. Label 2
Pin Assignments
Table 23-21 provides the pin assignments of the straight-through cable.
Table 23-21 Pin assignments of the straight-through cable
Connector X1
Connector X2
Color
Relationship
X1.1
X2.1
White/Orange
Twisted pair
X1.2
X2.2
Orange
X1.3
X2.3
White/Green
X1.6
X2.6
Green
X1.4
X2.4
Blue
X1.5
X2.5
White/Blue
X1.7
X2.7
White/Brown
X1.8
X2.8
Brown
Twisted pair
Twisted pair
Twisted pair
Issue 03 (2013-02-20)
Item
Description
Connector X1/X2

- connector - 24 to 26 AWG - CAT 6/configured with the SFTP network
cable
Cable type
Communication cable - 10015 ohms - CAT5E SFTP 24 AWG - 8core - PANTONE 445U
Number of cores

1446

23 Cables
Item
Description
Fireproof class
CM
Length
5 m, 10 m, 20 m, and 30 m
23.4.7 Crossover Cable

The crossover cable is used to connect the OptiX OSN equipment, network management
computer, and Ethernet to achieve communication. Both ends of the crossover cable use the
RJ45 connector.
Structure
Figure 23-27 shows the structure of the crossover cable.
Figure 23-27 Structure of the crossover cable
2. Label 1
3. Main label
4. Network cable
5. Label 2
Pin Assignments
Table 23-22 provides the pin assignments of the crossover cable.
Table 23-22 Pin assignments of the crossover cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Color
Relationship
X1.6
X2.2
Orange
Twisted pair
X1.3
X2.1
White/Orange
X1.1
X2.3
White/Green
X1.2
X2.6
Green
X1.4
X2.4
Blue
X1.5
X2.5
White/Blue
X1.7
X2.7
White/Brown
X1.8
X2.8
Brown

Twisted pair
Twisted pair
Twisted pair
1447

23 Cables
Item
Description
Connector X1/X2

- connector - 24 to 26 AWG - CAT 6/configured with the SFTP
network cable
Cable type
Communication cable - 1005 ohms - CAT5E SFTP 24 AWG - 8core - PANTONE 646U
Number of cores
Fireproof class
CM
Length
5 m and 30 m
23.5 Signal Cable

The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
23.5.1 75-ohm 8xE1 Cable

The 75-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 75-ohm 8xE1 cable uses a DB44 connector at one end to connect to the D75S. The other
end of the 75-ohm 8xE1 cable is connected to the digital distribution frame (DDF). The connector
needs to be prepared on site as required. Each 75-ohm 8xE1 cable can transmit 8xE1 signals.
Structure
Figure 23-28 shows the structure of the 75-ohm 8xE1 cable.
Issue 03 (2013-02-20)

1448

23 Cables
Figure 23-28 Structure of the 75-ohm 8xE1 cable

View A
Pos.1
Pos.44
MO55
Main label
W
1. Cable connector - type D - 44-pin - male
2. Main label
Pin Assignments
Table 23-23 provides the pin assignments of the 75-ohm 8xE1 cable.
Table 23-23 Pin assignments of the 75-ohm 8xE1 cable
Issue 03 (2013-02-20)
Connect
or
Cable W
Cor
e
No.
38
Rin
g
23
Tip
37
Rin
g
22
Tip
36
Rin
g
21
Tip
35
Rin
g
20
Tip
15
Rin
g
30
Tip
Rema
rks
Direct
ion
Connect
or
Cable W
Cor
e
No.
R1
In
34
Rin
g
In
19
Tip
In
33
Rin
g
In
18
Tip
In
32
Rin
g
In
17
Tip
In
31
Rin
g
In
16
Tip
Out
11
Rin
g
Out
26
Tip
R2
R3
R4
T1

Rema
rks
Direct
ion
R5
In
In
11
R6
In
In
13
R7
In
In
15
R8
In
In
10
T5
Out
Out
1449

Connect
or
Cable W
23 Cables
Rema
rks
Direct
ion
Connect
or
Cable W
Cor
e
No.
T2
Out
10
Rin
g
12
Out
25
Tip
Out
Rin
g
Out
24
Tip
Out
Rin
g
Rema
rks
Direct
ion
T6
Out
Cor
e
No.
14
Rin
g
29
Tip
13
Rin
g
28
Tip
12
Rin
g
27
Tip
Out
Tip
Out
Shell
External braid shield

layer/Without the
external braid shield
layer
Shell
External braid shield

layer/Without the
external braid shield
layer
T3
T4
Out
14
T7
Out
Out
16
T8
Out
The external layer of the 75-ohm E1 cable may be of the shielded type or unshielded type. The
specifications of the 75-ohm E1 cable with the shielded layer are different from the specifications
of the 75-ohm E1 cable with the unshielded layer. Table 23-24 lists the specifications of the 75ohm E1 cable with the external braid shield layer. Table 23-25 lists the specifications of the 75ohm E1 cable without the external braid shield layer.
Table 23-24 Specifications of the 75-ohm E1 cable with the external braid shield layer
Issue 03 (2013-02-20)
Item
Description
Connector X
Connector accessories- type D - 44-pin - male - cable welding type

- 3-row pins
Cable type
Coaxial cable - SYFVZP-LC 75-1-1x16 - 75 ohms - 13.10 mm - 1.2

mm - 0.254 mm - Pantone Warm Gray 1U
Fireproof class
Complies with IEC60332-3C.
Number of cores
16 cores, 8xE1
Diameter of the shield

layer - diameter of the
internal insulation
internal conductor
13.10 mm - 1.2 mm - 0.254 mm
Length
3 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

1450

23 Cables
Table 23-25 Specifications of the 75-ohm E1 cable without the external braid shield layer
Item
Description
Connector X
Connector accessories- type D - 44-pin - male - cable welding type

- 3-row pins
Cable type
Coaxial cable - SYFVZP-LC 75-1-1x16 - 75 ohms - 12.40 mm - 1.2

mm - 0.254 mm - Pantone Warm Gray 1U
Fireproof class
Complies with IEC60332-3C.
Number of cores
16 cores, 8xE1
Diameter of the shield

internal insulation
internal conductor
12.40 mm - 1.2 mm - 0.254 mm
Length
5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m
CAUTION
The pin assignment table is delivered with the 75-ohm 8xE1 cable in a packing bag. You must
keep the table carefully.
23.5.2 120-ohm 8xE1 Cable

The 120-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 120-ohm 8xE1 cable uses a DB44 connector at one end to connect to the 120-ohm E1
electrical interface board. The other end of the 120-ohm 8xE1 cable is connected to the DDF.
The connector needs to be prepared on site as required. Each 120-ohm 8xE1 cable can transmit
8xE1 signals.
Structure
Figure 23-29 shows the structure of the 120-ohm 8xE1 cable.
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Figure 23-29 Structure of the 120-ohm 8xE1 cable
1. Cable connector - type D - 44-pin - male
2. Label 1, marked with "W1 (TX1-8)"
3. Label 3, marked with "W2 (RX1-8)"
4. Main label
Pin Assignments
Table 23-26 provides the pin assignments of the 120-ohm 8xE1 cable.
Table 23-26 Pin assignments of the 120-ohm 8xE1 cable
Issue 03 (2013-02-20)
Connec
tor
Cable W1
Cor
e
No.
15
Blue
30
Whi
te
14
Ora
nge
29
Whi
te
13
Gree
n
28
Whi
te
12
Bro
wn
27
Whi
te
Rema
rks
Direc
tion
Connec
tor
Cable W2
Cor
e
No.
Twist
ed
pair
TX1
Out
38
Blue
Out
23
Whit
e
Twist
ed
pair
TX2
Out
37
Oran
ge
Out
22
Whit
e
Twist
ed
pair
TX3
Out
36
Gree
n
Out
21
Whit
e
Twist
ed
pair
TX4
Out
35
Bro
wn
Out
20
Whit
e

Rema
rks
Direc
tion
Twisted
pair
RX1
In
Twisted
pair
RX2
In
In
In
Twisted
pair
RX3
In
In
Twisted
pair
RX4
In
In
1452

Connec
tor
Cable W1
23 Cables
Rema
rks
Direc
tion
Connec
tor
Cable W2
Cor
e
No.
Out
34
Gray
Twisted
pair
Out
19
Whit
e
Out
33
Blue
Out
18
Red
Out
32
Oran
ge
Out
17
Red
Out
31
Gree
n
Out
16
Red
In
Shell
External braided shield
Cor
e
No.
11
Gra
y
TX5
26
Whi
te
Twist
ed
pair
10
Blue
TX6
25
Red
Twist
ed
pair
Ora
nge
TX7
24
Red
Twist
ed
pair
Gree
n
TX8
Red
Twist
ed
pair
Shell
External braided shield
Rema
rks
Direc
tion
RX5
In
In
Twisted
pair
RX6
Twisted
pair
RX7
In
In
In
In
Twisted
pair
RX8
In
Item
Description
Connector X
Cable type
Communication cable - 120 ohms - SEYPVPV - 0.5 mm - 24 AWG 16-core - PANTONE 430U
Number of cores
16
Diameter of the
internal conductor
0.5 mm
Fireproof class
CM
Length
10 m, 15 m, 20 m, 30 m, and 40 m
23.5.3 E3/T3/STM-1 Cable

The E3/T3/STM-1 cable is used to receive and transmit E3/T3/STM-1 electrical signals. The
E3/T3/STM-1 cable uses an SMB connector at one end to connect to the E3/T3/STM-1 electrical
access board. The other end of the E3/T3/STM-1 cable is connected to the DDF. The connector
needs to be chosen on site as required.
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Structure
Figure 23-30 shows the structure of the E3/T3/STM-1 cable.
Figure 23-30 Structure of the E3/T3/STM-1 cable
1. Coaxial connector - SMB
2. Main label
3. Coaxial cable
Pin Assignments
None.
Item
Description
Connector
Coaxial connector - SMB connector - 75 ohms - straight - female
Cable I
Coaxial cable - 75 ohms - 3.9 mm - 2.1 mm - 0.34 mm - shielded

Diameter of the shield layer - diameter of the internal insulation layer diameter of the internal conductor: 3.9 mm - 2.1 mm - 0.34 mm
Length: 10 m, 15 m, 20 m, and 30 m
Cable II
Coaxial cable - 75 ohms - 4.4 mm - 2.4 mm - 0.4 mm - shielded - gray

Length: 15 m, 20 m, 25 m, 30 m, and 40 m
Cable III
Coaxial cable - 75 ohms - 6.7 mm - 3.8 mm - 0.61 mm - shielded - gray

Length: 15 m, 20 m, 25 m, 30 m, and 130 m
Cable IV
Coaxial cable - 75 ohms - 5.80 mm - 3.71 mm - 0.643 mm - black

Length: 30 cm
Cable V
Issue 03 (2013-02-20)
Coaxial cable - 75 ohms - 3.9 mm - 2.1 mm - 0.34 mm - shielded

1454

Item
23 Cables
Description
Length: 10 m
Fireproof class
CM
23.5.4 Framed E1 Cable

The framed E1 cable is connected to the DB44 connector of the DM12 to transmit/receive eight
channels of framed E1 signals.
The framed E1 cables are available in two types, namely, 75-ohm framed E1 cable and 120-ohm
framed E1 cable.
l
For the structure, pin assignments, and technical specifications of the 75-ohm framed E1
cable, see the topic that describes the 75-ohm 8xE1 cable.
For the structure, pin assignments, and technical specifications of the 120-ohm framed E1
cable, see the topic that describes the 120-ohm 8xE1 cable.
23.5.5 Nx64 kbit/s Cable

The Nx64 kbit/s cable is connected to the DB28 connector of the DM12 to transmit/receive one
channel of Nx64 kbit/s signals.
Table 23-27 provides the pin assignments of the DB28 connector.
Table 23-27 Pin assignments of the DB28 connector of the DM12
Issue 03 (2013-02-20)
Pin
Signal
Direction
Description
TXD+
--->
Transmits data.
TXD-
--->
Transmits data.
TXC+
<-->
Transmits the clock signal provided by the

DCE to the DTE.
TXC-
<-->
Transmits the clock signal provided by the

DCE to the DTE.
NC
GND
-----
Circuit_GND
MODE0
<---
Receives the signal that identifies the type of

cable.
MODE1
<---

cable.

1455

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Pin
Signal
Direction
Description
MODE2
<---

cable.
10
MODE_DC
E
<---

DCE/DTE cable.
11
DCD+
<-->
Detects the carrier.
12
DCD-
<-->
Detects the carrier.
13
RTS+
--->
14
RTS-
--->
15
TXCE+
--->
Transmits the data clock in the case of the

DCE and loops back the clock in the case of
the DTE.
16
TXCE-
--->
Transmits the data clock in the case of the

DCE and loops back the clock in the case of
the DTE.
17
RXC+
<---
Receives clock signals.
18
RXC-
<---
Receives clock signals.
19
RXD+
<---
Receives data.
20
RXD-
<---
Receives data.
21
GND
-----
Shield_GND
22
LL
<-->
Receives the loopback control signal.
23
CTS+
<---
Permits the transmission.
24
CTS-
<---
Permits the transmission.
25
DSR+
<---
Receives the DCE ready signal.
26
DSR-
<---
Receives the DCE ready signal.
27
DTR+
--->
28
DTR-
--->
The Nx64 kbit/s cables are classified into the following categories according to the protocol,
which the Nx64 kbit/s signals comply with:
l
V.35 DCE cable
V.35 DTE cable
V.24 DCE cable
V.24 DTE cable
Issue 03 (2013-02-20)

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X.21 DCE cable
X.21 DTE cable
RS-449 DCE cable
RS-449 DTE cable
RS-530 DCE cable
RS-530 DTE cable
23 Cables
V.35 DCE Cable

Figure 23-31 shows the structure of the V.35 DCE cable.
Figure 23-31 Structure of the V.35 DCE cable
A-A
B-B
Pos.28
W
Pos.1
C
H
X1
X2
M
S
W
AA
EE
KK
A
E
K
P
U
Y
CC
HH
MM
1. Cable connector - D28 - male
2. Main label
3. Cable connector - D34 - female + D34 plastic shell
D
J
N
T
X
BB
FF
LL
B
F
L
R
V
Z
DD
JJ
NN
Table 23-28 provides the pin assignments of the V.35 DCE cable.
Table 23-28 Pin assignments of the V.35 DCE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
19
Twisted pair
20
15
16
AA
17
U
Twisted pair
Twisted pair
Twisted pair
Twisted pair
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23 Cables
Connector X1
Connector X2
Relationship
18
11
22
23
13
25
27
21
6+7+8
Pins 6, 7, and 8 are shortcircuited.
The technical specifications of the V.35 DCE cable are as follows.

Item
Description
Connector X1
Cable connector - type-D dual-edge subassembly - 28-pin - straight male - cable welding type - spacing 0.80 mm - matching with 28 to 30
AWG, exclusively used by the OEM
Connector X2
Cable connector - V35 plug - 34-pin - molding shell - kit, exclusively

used by the OEM
Cable connector - V35 DCE plug - 34-pin - female - cable crimping
type - housing core, exclusively used by the OEM
Cable type
Symmetrical twisted-pair cable - 100 ohms - 0.38 mm - 28 AWG - 5

pairs - 8 cores - PANTONE 296U - exclusively used by the OEM
Number of cores
Five pairs and eight cores
Diameter of the
core
0.32 mm
Length
3m
V.35 DTE Cable

Figure 23-32 shows the structure of the V.35 DTE cable.
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Figure 23-32 Structure of the V.35 DTE cable

A-A
B-B
Pos.28
Pos.1
X1
X2
1. Cable connector - D28 - male 2. Main label

4. Ordinary terminal
A
B
C
D
E
F
H
J
L N K M
R T P S
V X U W
Z BB Y AA
DD FF CC EE
JJ LL HH KK
NN MM
3. Cable connector - D34 - plastic shell
Table 23-29 provides the pin assignments of the V.35 DTE cable.
Table 23-29 Pin assignments of the V.35 DTE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
Twisted pair
19
20
17
18
AA
15
16
11
22
13
23
27
25
21

Twisted pair
Twisted pair
Twisted pair
Twisted pair
1459

23 Cables
Connector X1
Connector X2
Relationship
6 + 10 + 7 + 8
Pins 6, 7, 8, and 10 are shortcircuited.
The technical specifications of the V.35 DTE cable are as follows.

Item
Description
Connector X1
Cable connector - type-D dual-edge subassembly - 28-pin - straight - male

- cable welding type - spacing 0.80 mm - matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2
Cable connector - V35 plug - 34-pin - molding shell - kit, exclusively used
by the OEM
Cable connector - V35 DTE plug - 34-pin - female - cable crimping type housing core, exclusively used by the OEM
Cable type
Symmetrical twisted-pair cable - 100 ohms - 0.38 mm - 28 AWG - 5 pairs

- 8 cores - PANTONE 296U - exclusively used by the OEM
Number of
cores
Diameter of
the core
0.32 mm
Length
3m
V.24 DCE Cable

Figure 23-33 shows the structure of the V.24 DCE cable.
Figure 23-33 Structure of the V.24 DCE cable
A-A
B-B
Pos.25
Pos.1
Pos.28
Pos.1
X1
X2
1. Cable connector - D25 - female
2. Main label
Table 23-30 provides the pin assignments of the V.24 DCE cable.
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Table 23-30 Pin assignments of the V.24 DCE cable

Connector X1
Connector X2
Relationship
19
Twisted pair
23
13
25
20
27
11
22
18
15
17
24
15
17
21
Single
6+7
Pins 6 and 7 are shortcircuited.
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the V.24 DCE cable are as follows.

Table 23-31 Technical specifications of the V.24 DCE cable
Issue 03 (2013-02-20)
Item
Description
Connector X1

Connector X2
Cable connector - type D - 25-pin - female - cable welding type
Cable type

Number of
cores
Diameter of the
core
0.32 mm
Length
3m

1461

23 Cables
V.24 DTE Cable

Figure 23-34 shows the structure of the V.24 DTE cable.
Figure 23-34 Structure of the V.24 DTE cable
A-A
B-B
1
Pos.1
Pos.1
Pos.28
Pos.25
X1
X2
2. Main label
Table 23-32 provides the pin assignments of the V.24 DTE cable.
Table 23-32 Pin assignments of the V.24 DTE cable
Connector X1
Connector X2
Relationship
Twisted pair
19
13
23
27
20
25
11
22
18
15
15
24
17
17
21
Single
6 + 10 + 7
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the V.24 DTE cable are as follows.

Issue 03 (2013-02-20)

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Table 23-33 Technical specifications of the V.24 DTE cable

Item
Description
Connector X1

Connector X2
Cable connector - type D - 25-pin - male - cable welding type
Cable type

Number of
cores
Diameter of the
core
0.32 mm
Length
3m
X.21 DCE Cable

Figure 23-35 shows the structure of the X.21 DCE cable.
Figure 23-35 Structure of the X.21 DCE cable
A-A
B-B
2
Pos.15
Pos.1
Pos.28
Pos.1
X1
X2
2. Main label
Table 23-34 provides the pin assignments of the X.21 DCE cable.
Table 23-34 Pin assignments of the X.21 DCE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
13
Twisted pair
14
12
23
24
10
Twisted pair
1463

23 Cables
Connector X1
Connector X2
Relationship
19
Twisted pair
20
11
15
16
13
21
6+9
Twisted pair
Twisted pair
The technical specifications of the X.21 DCE cable are as follows.

Table 23-35 Technical specifications of the X.21 DCE cable
Item
Description
Connector X1

Connector X2
Cable type

Number of
cores
Diameter of
the core
0.32 mm
Length
3m
X.21 DTE Cable

Figure 23-36 shows the structure of the X.21 DTE cable.
Issue 03 (2013-02-20)

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Figure 23-36 Structure of the X.21 DTE cable

A-A
B-B
2
Pos.1
Pos.1
Pos.28
Pos.15
X2
X1
2. Main label
Table 23-36 provides the pin assignments of the X.21 DTE cable.
Table 23-36 Pin assignments of the X.21 DTE cable
Connector X1
Connector X2
Relationship
13
Twisted pair
14
10
23
24
12
19
20
11
15
16
13
17
18
13
21
6 + 10 + 9
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the X.21 DTE cable are as follows.
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Table 23-37 Technical specifications of the X.12 DTE cable

Item
Description
Connector X1

Connector X2
Cable type

Number of
cores
Diameter of the
core
0.32 mm
Length
3m
RS-449 DCE Cable

Figure 23-37 shows the structure of the RS-449 DCE cable.
Figure 23-37 Structure of the RS-449 DCE cable
A-A
B-B
2
Pos.1
Pos.1
Pos.28
Pos.15
X2
X1
2. Main label
3. Cable connector - D37 - female - I
Table 23-38 provides the pin assignments of the RS-449 DCE cable.
Table 23-38 Pin assignments of the RS-449 DCE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
27
11
Twisted pair
28
29
25
12
26
30
Twisted pair
1466

23 Cables
Connector X1
Connector X2
Relationship
13
Twisted pair
14
27
23
24
25
11
13
12
31
19
20
22
24
15
16
26
17
17
18
35
23
22
10
21
6+8
19
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the RS-449 DCE cable are as follows.

Table 23-39 Technical specifications of the RS-449 DCE cable
Issue 03 (2013-02-20)
Item
Description
Connector X1
Cable connector - type-D dual-edge subassembly - 28-pin - straight male - cable welding type - spacing 0.80 mm - matching with 28 to 30
AWG, exclusively used by the OEM
Connector X2
Cable connector - type D - 37-pin - female - cable welding type,

Cable type
Symmetrical twisted-pair cable - 100 ohms - communication cable 0.32 mm - 28 AWG - 26-core - PANTONE 296U - exclusively used
by the OEM
1467

Item
Description
Number of cores
26
Diameter of the
core
0.32 mm
Length
3m
23 Cables
RS-449 DTE Cable

Figure 23-38 shows the structure of the RS-449 DTE cable.
Figure 23-38 Structure of the RS-449 DTE cable
A-A
B-B
1
3
Pos.37
Pos.28
Pos.1
X1
X2
2. Main label
Pos.1
3. Cable connector - D37 - male - I
Table 23-40 provides the pin assignments of the RS-449 DTE cable.
Table 23-40 Pin assignments of the RS-449 DTE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
27
12
Twisted pair
28
30
25
11
26
29
13
14
25
23
24
27
11
13
12
31
Twisted pair
Twisted pair
Twisted pair
Twisted pair
1468

23 Cables
Connector X1
Connector X2
Relationship
19
Twisted pair
20
24
22
15
17
16
35
17
18
26
23
22
10
21
6 + 8 + 10
19
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the RS-449 DTE cable are as follows.

Table 23-41 Technical specifications of the RS-449 DTE cable
Item
Description
Connector X1

Connector X2
Cable connector - type D - SUB plug - 37-pin - straight - male - cable welding
type - two rows, standard installation holes, exclusively used by the OEM
Cable type
Symmetrical twisted-pair cable - 100 ohms - communication cable - 0.32

mm - 28 AWG - 26-core - PANTONE 296U - exclusively used by the OEM
Number of
cores
26
Diameter of
the core
0.32 mm
RS-530 DCE Cable

Figure 23-39 shows the structure of the RS-530 DCE cable.
Issue 03 (2013-02-20)

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23 Cables
Figure 23-39 Structure of the RS-530 DCE cable

A-A
Pos.25
B-B
3
Pos.1
X1
Pos.1
Pos.28
X2
2. Main label
Table 23-42 provides the pin assignments of the RS-530 DCE cable.
Table 23-42 Pin assignments of the RS-530 DCE cable
Issue 03 (2013-02-20)
Connector X1
Connector X2
Relationship
28
22
Twisted pair
27
26
23
25
20
24
19
23
22
18
Single
21
Single
20
14
Twisted pair
19
18
11
17
24
16
15
17
14
13
13
12
10
11
12
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
1470

23 Cables
Connector X1
Connector X2
15
16
6+7+9
Relationship
Twisted pair
The technical specifications of the RS-530 DCE cable are as follows.

Table 23-43 Technical specifications of the RS-530 DCE cable
Item
Description
Connector X1

Connector X2
Cable type

mm - 28 AWG - 26-core - PANTONE 296U - exclusively used by the
OEM
Number of
cores
26
Diameter of the
core
0.32 mm
Length
3m
RS-530 DTE Cable

Figure 23-40 shows the structure of the RS-530 DTE cable.
Figure 23-40 Structure of the RS-530 DTE cable
B-B
A-A
1
Pos.1
Pos.1
X1
Pos.25
X2
Issue 03 (2013-02-20)
Pos.28
2. Main label

1471

23 Cables
Table 23-44 provides the pin assignments of the RS-530 DTE cable.
Table 23-44 Pin assignments of the RS-530 DTE cable
Connector X1
Connector X2
Relationship
27
20
Twisted pair
28
23
25
26
22
13
14
19
23
24
13
11
12
10
19
20
16
14
15
24
16
11
17
17
18
15
12
22
18
21
6 + 7 + 9 + 10
Pins 6, 7, 9, and 10 are shortcircuited.
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
Twisted pair
The technical specifications of the RS-530 DTE cable are as follows.
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Table 23-45 Technical specifications of the RS-530 DTE cable

Item
Description
Connector X1

Connector X2
Cable type

mm - 28 AWG - 26-core - PANTONE 296U - exclusively used by the OEM
Number of
cores
26
Diameter of the
core
0.32 mm
Length
3m
23.6 Clock Cable

The clock cables include the 75-ohm/120-ohm clock cable and clock transit cable.
23.6.1 75-ohm/120-ohm Clock Cable

The clock cables are available in two types, namely, 75-ohm clock cable and 120-ohm clock
cable. The clock cable is used to receive and transmit external clock signals. In the case of the
75-ohm clock cable, the cable uses an SMB connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required. In the case of the 120ohm clock cable, the cable uses an RJ45 connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required.
Structure
Figure 23-41 shows the structure of the 75-ohm clock cable. Figure 23-42 shows the structure
of the 120-ohm clock cable.
Figure 23-41 Structure of the 75-ohm clock cable
1. Coaxial connector - SMB
Issue 03 (2013-02-20)

2. Label
1473

23 Cables
Figure 23-42 Structure of the 120-ohm clock cable
1. Label 1 (R) and label 2 (T) 2. Communication cable 3. Main label 4. Network interface connector - RJ-45
Pin Assignments
Table 23-46 provides the pin assignments of the 120-ohm clock cable.
Table 23-46 Pin assignments of the 120-ohm clock cable
X1
Remarks
X1.1
Blue
W1
X1.2
White
X1.4
Orange
X1.5
White
W2
Table 23-47 Pin assignments of the 120-ohm clock cable

X1
Relationship
Description
External Clock Mode
External Time Mode

(1 PPS + Time
Information)
X1.1
Twisted pair
X1.2
X1.3
Twisted pair
X1.6
X1.4
Twisted pair
X1.5
X1.7
X1.8
Issue 03 (2013-02-20)
Twisted pair
CLK receive end (-)
Not defined
CLK receive end (+)
Not defined
Not defined
1 PPS signal (-)
Not defined
1 PPS signal (+)
CLK transmit end (-)
Grounding end
CLK transmit end (+)
Grounding end
Not defined
Time information (-)
Not defined
Time information (+)

1474

23 Cables
Item
Description
75-ohm
clock cable
Connector: coaxial connector - SMB - 75 ohms - straight - female

Cable type: coaxial cable - 75 ohms - 3.9 mm - 2.1 mm - 0.34 mm - shielded
Diameter of the shield layer - diameter of the internal insulation layer - diameter
of the internal conductor: 3.9 mm - 2.1 mm - 0.34 mm
Length: 10 m, 15 m, 20 m, and 30 m
120-ohm
clock cable
Connector X: network interface connector - 8-pin - 8-bit - shielded - crystal

model connector
Cable type: symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.4 mm
- 26 AWG - 2 pairs - PANTONE 430U
Diameter of the internal conductor: 0.4 mm/26 AWG
Length: 5 m, 10 m, 20 m, 30 m, 40 m, 50 m, 70 m, and 100 m
23.6.2 One-Channel Clock Transit Cable and Two-Channel Clock

Transit Cable
The clock transit cables are available in two types, namely, one-channel 75-ohm-to-120-ohm
clock transit cable and two-channel 75-ohm-to-120-ohm clock transit cable.
Structure
Figure 23-43 shows the structure of the one-channel 75-ohm-to-120-ohm clock transit cable.
Figure 23-44 shows the structure of the two-channel 75-ohm-to-120-ohm clock transit cable.
Figure 23-43 Structure of the one-channel 75-ohm-to-120-ohm clock transit cable
1. Coaxial connector - SMB - 75 ohms - straight/plug female
Issue 03 (2013-02-20)
2. Main label 3. 75-ohm-to-120-ohm transit PCB

1475

23 Cables
Figure 23-44 Structure of the two-channel 75-ohm-to-120-ohm clock transit cable
1. Coaxial connector - SMB - 75 ohms - straight/plug - female 2. Label 1: "1#" 3. Label 2: "2#" 4. Main label
5. 75-ohm-to-120-ohm transit PCB
6. Label 3: "1#" 7. Label 4: "2#"
Pin Assignments
Table 23-48 provides the pin assignments of the two-channel 75-ohm-to-120-ohm clock transit
cable.
Table 23-48 Pin assignments of the two-channel 75-ohm-to-120-ohm clock transit cable
Connector
75-ohm Cable
Color
120-ohm Cable
X1
Core
Blue
W3
Shield layer
White
Core
Blue
Shield layer
White
X2
W4
Item
Description
One
channel
Connector: coaxial connector - SMB - 75 ohms - straight - female

75-ohm cable: coaxial cable - 75 ohms - 3.9 mm - 2.1 mm - 0.34 mm - shielded
75-ohm cable: diameter of the shield layer (3.9 mm) - diameter of the internal
insulation layer (2.1 mm) - diameter of the internal conductor (0.34 mm)
120-ohm cable: symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.4
mm - 26 AWG - 2 pairs - PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m
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1476

23 Cables
Item
Description
Two
channels
Connector X1/X2: coaxial connector - SMB - 75 ohms - straight - female

75-ohm cable: coaxial cable - 75 ohms - 3.9 mm - 2.1 mm - 0.34 mm - shielded
75-ohm cable: diameter of the shield layer (3.9 mm) - diameter of the internal
insulation layer (2.1 mm) - diameter of the internal conductor (0.34 mm)
120-ohm cable: symmetrical twisted-pair cable - 120 ohms - SEYPVPV - 0.4
mm - 26 AWG - 2 pairs - PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m
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24 Indicators
24
Indicators
About This Chapter

This topic describes the indicators on the OptiX OSN equipment and the indicators on the boards
of the OptiX OSN equipment.
24.1 Indicators on the Cabinet
This topic describes the indicators on the cabinet of the OptiX OSN equipment.
24.2 Alarm Indicators on the Boards
This topic describes the alarm indicators on the boards.
Issue 03 (2013-02-20)

1478

24 Indicators
24.1 Indicators on the Cabinet

This topic describes the indicators on the cabinet of the OptiX OSN equipment.
Indicator
Description
Power indicator Power (green)
On: Power is supplied to the equipment.

Off: Power is not supplied to the equipment.
Critical alarm indicator Critical (red)
On: A critical alarm occurs on the equipment.

Off: No critical alarm occurs on the equipment.
Major alarm indicator Major (orange)
On: A major alarm occurs on the equipment.

Off: No major alarm occurs on the equipment.
Minor alarm indicator Minor

(yellow)
On: A minor alarm occurs on the equipment.

Off: No minor alarm occurs on the equipment.
24.2 Alarm Indicators on the Boards

This topic describes the alarm indicators on the boards.
Board Hardware Status Indicator (STAT)

Status
Meaning
On (green)
The board operates properly.
On (red)
The hardware of the board is faulty or does not match

the equipment.
Off
The board is not powered on or does not start to work.
NOTE
STAT indicators are designed for non-service alarms such as alarms related to power, temperature,
abnormal communication, or absent optical modules.
Service Activation Status Indicator/Board Status (Active/Standby) Indicator (ACT)
Issue 03 (2013-02-20)
Status
Meaning of the Service

Activation Status Indicator
Meaning of the Board Status

(Active/Standby) Indicator
On (green)
The services are activated. The

board is in the working state.
The board works as the working

board.

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24 Indicators
Status
Meaning of the Service

Activation Status Indicator
Meaning of the Board Status

(Active/Standby) Indicator
Off
The services are not activated.
The board works as the

protection board.
Board Software Status Indicator (PROG)

Status
Meaning
On (green)
The board software or FPGA in the flash is

successfully loaded and stored, or the board software
is successfully initiated.
On for 100 ms and off for 100 ms

repeatedly (green)
The board software is being loaded to the flash or the

FPGA software is being loaded to the FPGA.
On for 300 ms and off for 300 ms

repeatedly (green)
l The board software is being initialized and is in

the BIOS boot state.
l The board is in the BIOS state because the board
is reset for three times in five minutes.
l The board software or FPGA in the flash is lost.
On (red)
l The board software fails to be loaded.

l The board software fails to be initialized.
l No power is accessed.
Off
l The high-power-consumption board enters the

low-power-consumption mode.
Service Alarm Indicator (SRV)

Type of Board
Status
Meaning
Service board
On (green)
The services are normal and no

service alarm is generated.
On (red)
A critical or major alarm occurs in

the services.
On (yellow)
A minor or remote alarm occurs in

the services.
Off
The services are not configured and

no alarm is generated, or no power is
supplied to the board.
On (green)

Cross-connect and timing

board
Issue 03 (2013-02-20)

1480

Type of Board
System control board
24 Indicators
Status
Meaning
On (red)
A critical alarm occurs.
On (yellow)
A minor alarm occurs.
Off

On (green)

On (red)
A critical or major alarm occurs in

the subrack.
On (yellow)
A minor or remote alarm occurs in

the subrack.
Off

Synchronization Clock Status Indicator (SYNC)

Status
Meaning
On (green)
l The clock works in free-run mode and the system

clock priority list is not set. By default, the system
clock priority list contains only internal sources.
l The clock works in locked mode and is tracing a
clock source other than the internal sources in the
priority list.
The system clock priority list is set. All the clock
sources, however, are lost except for the internal
clock sources. The clock works in holdover mode or
free-run mode.
On (red)
Alarm Mute Indicator (ALMC)
Issue 03 (2013-02-20)
Status
Meaning
On (yellow)
The board is in the alarm mute state.
Off
When an alarm is generated, the equipment emits an alarm

sound.

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24 Indicators
Power Monitoring Indicators

Indicator
Status
Meaning
48 V power supply indicator of

channel A (PWRA)
On (green)
The 48 V power supply of channel

A is normal.
On (red)
The 48 V power supply of channel

A is faulty (lost or failed).
On (green)
The 48 V power supply of channel B

is normal.
On (red)
The 48 V power supply of channel B

is faulty (lost or failed).
On (green)
The +3.3 V backup power supply of

the system is normal.
On (red)
The +3.3 V backup power supply of

the system is lost.
48 V power supply indicator of

channel B (PWRB)
+3.3 V backup power supply

indicator of the system (PWRC)
Ethernet Indicators
Indicator
Status
Meaning
Connection status indicator

LINK (green)
On
The fiber cable is successfully

connected to the equipment.
Off
The fiber cable is not connected to the

equipment.
Flashing
The Ethernet interface is receiving or

transmitting data.
Off
The Ethernet interface is not receiving

or transmitting data.
Data receiving and

transmission indicator ACT
(orange)
FAN Running Status Indicator (STATE)
Issue 03 (2013-02-20)
Status
Meaning
On (green)
The fan operates properly.
On (red)
The fan, fan power supply board, or fan control board

is abnormal.
On (yellow)
The fan stops when the temperature is very low.

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24 Indicators
Indicators on the Front Panel of the COA

Indicator
Status
Meaning
Running indicator
RUN (green)
Flashing once every two

seconds (green)
The COA operates properly.
Flashing once every four

seconds (green)
The COA is in database protection mode.

The communication between the COA
and the SCC is interrupted.
Flashing five times every

second (green)
The program is being started or loaded.
On (red)
Errors occur during the memory selfcheck.
Flashing thrice every other

second (red)
A critical alarm occurs.
Flashing twice every other

second (red)
A major alarm occurs.
Flashing once every other

second (red)
A minor alarm occurs.
Alarm indicator
ALM
Power Indicator (POWER)

Status
Meaning
On (green)
The input of the power supply is normal.
Off
No power is supplied or the power supply fails.
Indicators on the UPM

Module
Indicator
Status
Meaning
Rectifier
module
RUN (green)
On
The rectifier module operates properly.
Off
The rectifier module is faulty or is disabled.
Off
The rectifier module operates properly.
On
An alarm and revertive protection occur on

the module.
Flashing
The communication is interrupted.
On
The rectifier module is faulty.
ALM
(yellow)
FAULT
(red)
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24 Indicators
Module
Indicator
Status
Meaning
Monitoring
module
RUN
Flashing
(green)
Flashing slowly (on for 1s and off for 1s

repeatedly): The entire power system is
normal.
Flashing quickly (on for 125 ms and off for
125 ms repeatedly): The power system is not
registered or the communication is
interrupted.
ALM
On (red)
The entire power system is faulty. In normal

situations, the indicator is off.
Indicators on the Microwave Boards

Indicator
Status
Meaning
Connection status indicator 1

(LINK1) two colors (red and
green)
On (green)
The link at the microwave layer is

normal.
On (red)

faulty.
Connection status indicator 2

(LINK2) two colors (red and
green)
On (green)

normal.
On (red)

faulty.
Active/Standby state
indicator (ACT1) one color
(green)
On (green)
The board is in the active state when

the board is in the 1+1 protection
system.
The board is activated when the board
is not protected.
Off
The board is in the standby state when

system.
The board is not activated when the
board is not protected.
On (green)
The board is in the active state when

system.
The board is activated when the board
is not protected.
Off
The board is in the standby state when

system.
The board is not activated when the
board is not protected.
Active/Standby state
indicator (ACT2) one color
(green)
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1484

Issue 03 (2013-02-20)
24 Indicators
Indicator
Status
Meaning
Working indicator of ODU 1

(ODU1) two colors (red and
green)
On (green)
ODU 1 operates properly.
On (red)
ODU 1 is faulty.
Working indicator of ODU 2

(ODU2) two colors (red and
green)
On (green)
ODU 2 operates properly.
On (red)
ODU 2 is faulty.

1485

25 Labels
25
Labels
About This Chapter

This topic describes the safety labels and engineering labels on the OptiX OSN equipment.
25.1 Safety Labels
Various safety labels are attached to the equipment. This topic provides the indications and
positions of the safety labels.
25.2 Engineering Labels
The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.
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1486

25 Labels
25.1 Safety Labels

Various safety labels are attached to the equipment. This topic provides the indications and
positions of the safety labels.
25.1.1 Label Description

Labels, such as the ESD protection label, grounding label, and fan warning label are attached to
the subrack.
Table 25-1 Labels on the equipment
Label
! ATTENTION
CLEAN PERIODICALLY
Label Name
Indication
ESD protection
label
The equipment is
sensitive to static
electricity.
Laser safety class

label
The power class of the

laser source
Grounding label
The grounding
position
Periodic cleaning
label
The air filter should be

cleaned periodically.
Fan warning label
The fan blades should

not be touched when
the fan is rotating.
APD warning label
The overload point of

the indicator is 9
dBm.
RoHS label
The equipment may

contain some of the
poisonous substances
specified by the
regulations in China,
but can be safely used
within a period of 50
years. The equipment
should be recycled or
reused after 50 years.
DON'T TOUCH THE

FANLEAVESBEFORE
THEYSLOW DOWN !
APD
Receiver
MAX:-9dBm
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1487

Label
25 Labels
Label Name
Indication
Product nameplate
label
The product name and

certification
Certificate of
qualification label
The equipment is
qualified.
In the case of the enhanced subrack:
25.1.2 Label Position

The ESD protection label and grounding label are attached to the subrack. The laser safety class
label and APD warning label are attached to the front panel of the board.
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25 Labels
Figure 25-1 Positions of the labels attached to the OptiX OSN 3500 subrack (1)
50
DON'T
TOUCH THE
FAN LEAVES BEFORE

THEY SLOW DOWN !
ATTENTION
CLEAN PERIODICALLY
Figure 25-2 Positions of the labels attached to the OptiX OSN 3500 subrack (2)
Issue 03 (2013-02-20)

1489

25 Labels
Figure 25-3 Positions of the labels attached to the board

SL16
CLASS 1
LASER
PRODUCT
APD
Receiver
MAX:-9dBm
BA2
LASER
RADIATION
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
25.2 Engineering Labels

The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.
Table 25-2 provides the engineering specifications of Huawei.
For information on how to prepare and attach labels, see the OptiX OSN 3500 Intelligent Optical
Transmission System Installation Guide.
Issue 03 (2013-02-20)

1490

25 Labels
Table 25-2 Huawei specifications for the engineering labels

Label
Engineer
ing label
for the
power
cable
Illustration
TO:
A01
B08
(1)
-48V2
Description
TO:
B03
-48V2
(2)
(1) Label on the loaded cabinet side, that is,

the position of the cable on the power
distribution cabinet side
(2) Label on the power distribution cabinet
side, that is, the position of the cable on the
loaded cabinet side
Engineer
ing label
for the
external
alarm
cable
On the loaded cabinet side, the

label marked with "A01/B08
48V2" on the cable indicates that
the cable supplies the 48 V2
power. This cable is led out from
the eighth connector in the
second row of the 48 V bus bar
in the power distribution cabinet
in row A and column 01 in the
equipment room.
On the power distribution cabinet
side, the label marked with "B03
48V2" on the cable indicates
that the cable supplies the 48 V2
power. This cable is led out from
the loaded cabinet in row B and
column 03 in the equipment
room. In the case of the PGND
cable and BGND cable, specify
only the row number and column
number of the power distribution
cabinet. It is not required to
specify the connector on the bus
bar.
The external alarm cable is
connected to the power
distribution cabinet (the first
cabinet in each row used for
power distribution). Attach labels
to the terminals of the power
distribution cabinet to indicate
the equipment that uses the
terminals. No engineering label
needs to be attached to the
equipment side, unless otherwise
specified.
"A01" indicates that the alarm
cable connects the power
distribution cabinet and the
cabinet in row A and column 01
in the equipment room.
Issue 03 (2013-02-20)

1491

Label
Illustration
Engineer
ing label
for the
network
cable
25 Labels
Description
"A01-03-06-05" indicates that
the local end of the network cable
is connected to network port 05 in
slot 06 of subrack 03 in the
"B02-03-12" indicates that the
opposite end of the network cable
is connected to network port 12 in
subrack 03 in the cabinet in row
B and column 02 in the
equipment room. It is not
required to specify the slot
number.
Issue 03 (2013-02-20)
Engineer
ing label
for the
fiber that
connects
two
pieces of
equipme
nt
"A01-01-05-05-R" indicates that

the local end of the fiber is
connected to optical receiving
port 05 in slot 05 of subrack 01 in
the cabinet in row A and column
01 in the equipment room.
Engineer
ing label
for the
fiber that
connects
the
equipme
nt and
the ODF
"ODF-G01-01-01-R" indicates
that the local end of the fiber is
connected to the optical receiving
terminal in row 01 and column 01
of the ODF in row G and column
"G01-01-01-01-T" indicates that

the opposite end of the fiber is
connected to optical transmitting
the cabinet in row G and column

the opposite end of the fiber is
connected to optical receiving
the cabinet in row A and column

1492

Label
Illustration
25 Labels
Description
Engineer
ing label
for the
trunk
cable
that
connects
the
equipme
nt and
the DDF

the local end of the trunk cable is
connected to the receiving
terminal of trunk cable 01 in slot
01 of subrack 03 in the cabinet in
row A and column 01 in the
equipment room.
Engineer
ing label
for the
subscrib
er cable
"A01-03-01-01" indicates that

the local end of the subscriber
cable is connected to cable 01 in
slot 01 of subrack 03 in the
"DDF-G01-01-01-AR" indicates
that the opposite end of the trunk
cable is connected to the
receiving terminal of direction A
(connected to the optical
transmission equipment) in row
01 and column 01 of the DDF in
row G and column 01 in the
equipment room.
TO:
"MDF-G01-01-01" indicates that

the opposite end of the subscriber
cable is connected to the terminal
in row 01 and column 01 of the
MDF in row G and column 01 in
the equipment room.
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26
26 Board Information Quick Reference
Board Information Quick Reference
About This Chapter

This topic provides information about whether a board is supported by the OptiX OSN products,
the parameters specified for the interfaces of the boards (including the parameters specified for
optical interfaces, electrical interfaces, and auxiliary interfaces), the loopback capability of each
board, the functions supported by each board, and the protection schemes supported by each
board.
26.1 Board Version Replacement
The board version replacement function is used only for some specified boards. Before using
this function, you should be familiar with the mapping between boards and their substitute
boards.
26.2 Quick Reference Table for Optical Interfaces
This topic lists the common parameters specified for the interfaces of boards.
26.3 Quick Reference of Board Functions
This topic describes the functions supported by SDH boards, PDH boards, data boards, and
packet boards.
26.4 Loopback Capability of the Boards
The SDH boards, PDH boards, and data boards of the OptiX OSN equipment support various
types of loopbacks.
26.5 Protection Schemes Supported by Each Board
The SDH boards, PDH boards, data boards, microwave boards, and packet boards of the OptiX
OSN equipment support various protection schemes.
26.6 Quick Reference of Power Consumption and Weight of Each Board
This section lists the power consumption and weight of each board of the OptiX OSN series
equipment.
Issue 03 (2013-02-20)

1494

26.1 Board Version Replacement

The board version replacement function is used only for some specified boards. Before using
this function, you should be familiar with the mapping between boards and their substitute
boards.
Table 26-1 provides the mapping between boards and their substitute boards.
Table 26-1 Mapping between boards and their substitute boards
Substitute Board
To-Be-Substituted Board
Physical Board
Logical Board
Physical Board
N1PSXCS
N1SXCSA
N1SXCSA
N1PSXCS
N1SXCSA
N1SXCSB
N1EXCSA
N1SXCSA
N1UXCSA
N1EXCSA
N1UXCSB
N1UXCSB
N1UXCSA
N1SXCSB
N2PSXCSA
N1PSXCS
N1PSXCS
N2PSXCSA
N3PSXCSA
N1SL1A
N1SXCSA
N1PSXCS
N2PSXCSA
N3PSXCSA
N1SXCSA
N1SL1
N1SL1
N1PSXCS
N2PSXCSA
N1SL1A
N1SL4A
N1SL4
N1SL4
N1SL4A
N1SL64
N1SLD4A
N1SL64
N2SL64
T2SL64
N2SL64
N1SLD4
N1SLD4
T2SL64
N1SLD4A
N1SLQ1A
N1SLQ1
N1SLQ1
N1SLQ1A
N1SLQ4A
N1SLQ4
N1SLQ4
N1SLQ4A
Issue 03 (2013-02-20)

1495

Substitute Board
Physical Board
Logical Board
Physical Board
N2SLQ16
N1SLQ16
N1SLQ16
N2SLQ16
N3SL16
N1SL16
N1SL16
N3SL16
N3SL16A
N1SL16
N1SL16A
N3SL16
N3SLQ41
N1SLQ1
N1SLQ4
N2SLQ1
N2SLQ4
N1SLQ1
N1SLQ4
N2SLQ1
N3SLQ41
N2SLQ4
N4SF64
N1SF64
N1SF64
N4SL64
N1SL64
N2SL64
T2SL64
N4SL64
N1SL64
N1SLD64
N1SLD64
N4SLD64
N2SL64
T2SL64
N4SLD64
N4SLO16
N1SLO16
N1SLO16
N4SLO16
N4SLQ16
N2PD3
N1SLQ16
N2SLQ16
N4SLQ16
N1SLQ16
N1PD3
N1PD3
N2SLQ16
N2PD3
N2PL3
N1PL3
N1PL3
N2PL3
N2PL3A
N1PL3A
N1PL3A
N2PL3A
N2PQ1
N1PQ1
N1PQ1
N2PQ1
Issue 03 (2013-02-20)
N2PQ1A
N2PQ1
N1PQ1A
N2PQ1B
N2PQ1
N1PQ1B

1496

Substitute Board
Physical Board
Logical Board
Physical Board
N2SPQ4
N1SPQ4
N1SPQ4
N2SPQ4
R2PD1
R1PD1
R1PD1
R2PD1
R2PD1A
R2PD1
R1PD1A
R2PD1B
R2PD1
R1PD1B
N2EFS0
N1EFS0
N1EFS0
N2EFS0
N2EFS4
N1EFS4
N1EFS4
N2EFS4
N2EFT8
N1EFT8
N1EFT8
N2EFT8A
N1EFT8A
N1EFT8A
N2EGS2
N1EGS2
N1EGS2
N2EGS2
N2EGT2
N1EGT2
N1EGT2
N2EGT2
N3EFS4
N3EGS2
N4EFS0
N4EGS4
N1EFS4
N2EFS4
N3EFS4
N1EFS4
N1EGS2
N2EGS2
N3EGS2
N1EGS2
N1EFS0
N2EFS0
N4EFS0
N1EFS0
N3EGS4
N3EGS4
N2EFS4
N2EGS2
N2EFS0
N4EGS4
N5EFS0
Q2SAP
N1EFS0
N2EFS0
N4EFS0
N5EFS0
N1EFS0
Q1SAP
Q1SAP
N2EFS0
N4EFS0
Q2SAP
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1497

Substitute Board
Physical Board
Logical Board
Physical Board
TN12OBU1
TN11OBU1
TN11OBU1
A substitute board may not support all the functions of its to-be-substituted board. Therefore,
when you replace a board with its substitute board, consider the differences between the two
boards. If a substitute board does not support an enabled function of its to-be-substituted board
and the enabled function may be used on the live network, the board cannot be replaced. For
restrictions on board replacement, see Table 26-2.
Table 26-2 Restrictions on board replacement
Board That Supports the
Board Version
Replacement Function
Board That Cannot Be

Substituted
Condition
N1SL16A
N2SL16A
The TCM function is enabled

for the N2SL16A/N3SL16A.
N3SL16A
N1SL64
N2SL64
T2SL64
N1SLQ16
N2SLQ16

or AU-3 services are
configured for the N2SLQ16.
N3SL16
N2SL16

configured for the N2SL16.
N3SL16A
N2SL16A
AU-3 services are configured

for the N2SL16A.
N3SLO1
N2SLO1
AU-3 services are configured

for the N2SLO1.
N4SL64
N2SL64

configured for the N2SL64/
T2SL64.
T2SL64
Issue 03 (2013-02-20)

configured for the N2SL64/
T2SL64.

1498


Board Version

Substituted
Condition
N2EFS0
N1EFS0
l The N1EFS0 is
configured with QoS
functions.
N4EFS0
l If an N4EFS0/N2EFS0 is
configured as an N1EFS0
and the simulation
package loading method
is used, the board
software of the N1EFS0 is
loaded. As a result, a cold
reset is performed on the
board and the board
version replacement
function becomes
ineffective. Therefore, an
N4EFS0/N2EFS0 must
not be configured as an
N1EFS0.
Issue 03 (2013-02-20)
N2EFS4
N1EFS4
If an N2EFS4 is configured
as an N1EFS4 and the
simulation package loading
method is used, the board
board and the board version
replacement function
becomes ineffective.
Therefore, an N2EFS4 must
N1EFS4.
N4EFS0
N2EFS0
If an N4EFS0 is configured
as an N2EFS0 and the
simulation package loading
method is used, the board
board and the board version
replacement function
becomes ineffective.
Therefore, an N4EFS0 must
N2EFS0.
N2EGS2
N1EGS2
The N1EGS2 is configured

with QoS functions.

1499


Board Version

Substituted
Condition
N1BPA
N2BPA
The ALS function is required

but not enabled on the line
board.
N2BPA
N1BPA
The ALS function is required

but not enabled on the
N2BPA.
26.2 Quick Reference Table for Optical Interfaces

This topic lists the common parameters specified for the interfaces of boards.
26.2.1 Common Parameters Specified for Optical Interfaces of SDH

Boards
This topic describes common parameters specified for optical interfaces of SDH boards.
Table 26-3 lists the common parameters specified for the optical interfaces of the SDH boards.
Table 26-3 Common parameters specified for the optical interfaces of the SDH boards
Board
Name
SL1 and
SL1A
Issue 03 (2013-02-20)
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
I-1
-15
S-1.1
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-8
-23
-8
Singlemode
LC
-15
-8
-28
-8
Singlemode
LC
L-1.1
-5
-34
-10
Singlemode
LC
L-1.2
-5
-34
-10
Singlemode
LC

1500

Board
Name
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
Ve-1.2
-3
I-1
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-34
-10
Singlemode
LC
-15
-8
-23
-8
Singlemode
LC
S-1.1
-15
-8
-28
-8
Singlemode
LC
L-1.1
-5
-34
-10
Singlemode
LC
L-1.2
-5
-34
-10
Singlemode
LC
Ve-1.2
-3
-34
-10
Singlemode
LC
Ie-1
-19
-14
-30
-14
Multimode
LC
SLT1
S-1.1
-15
-8
-28
-8
Singlemode
LC
SL4,
SL4A,
SLD4,
SLD4A,
SLQ4, and
SLQ4A
I-4
-15
-8
-23
-8
Singlemode
LC
S-4.1
-15
-8
-28
-8
Singlemode
LC
L-4.1
-3
-28
-8
Singlemode
LC
L-4.2
-3
-28
-8
Singlemode
LC
SLQ1 and
SLQ1A
Issue 03 (2013-02-20)

1501

Board
Name
SL16
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
Ve-4.2
-3
L-16.2
SLD16
Issue 03 (2013-02-20)
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-34
-13
Singlemode
LC
-2
-28
-9
Singlemode
LC
L-16.2Je
-28
-9
Singlemode
LC
V-16.2Je
(BA)
-2 (without
the BA)
3 (without
the BA)
-28
-9
13 (with the
BA)
15 (with the
BA)
Singlemode
LC
-2 (without
the BA or
PA)
3 (without
the BA or
PA)
-28
(without the
BA or PA)
Singlemode
LC
15 (with the
BA)
18 (with the
BA)
-32 (with
the PA)
-9
(without
the BA or
PA)
I-16
-10
-3
-18
-3
Singlemode
LC
S-16.1
-5
-18
Singlemode
LC
L-16.1
-2
-27
-9
Singlemode
LC
L-16.2
-2
-28
-9
Singlemode
LC
I-16
-10
-3
-18
-3
Singlemode
LC
S-16.1
-5
-18
Singlemode
LC
U-16.2Je
(BA+PA)
SL16A

-10 (with
the PA)
1502

Board
Name
SLQ16
SLO16
SL64
Issue 03 (2013-02-20)
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
L-16.1
-2
L-16.2
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-27
-9
Singlemode
LC
-2
-28
-9
Singlemode
LC
I-16
-10
-3
-18
-3
Singlemode
LC
S-16.1
-5
-18
Singlemode
LC
L-16.1
-2
-27
-9
Singlemode
LC
L-16.2
-2
-28
-9
Singlemode
LC
I-16
-10
-3
-18
-3
Singlemode
LC
S-16.1
-5
-18
Singlemode
LC
L-16.1
-2
-27
-9
Singlemode
LC
L-16.2
-2
-28
-9
Singlemode
LC
I-64.1
-6
-1
-11
-1
Singlemode
LC
I-64.2
-5
-1
-14
-1
Singlemode
LC

1503

Board
Name
SLD64
SLQ41
Issue 03 (2013-02-20)
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
S-64.2b
-1
L-64.2b
(BA)
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-14
-1
Singlemode
LC
-4 (without
the BA)
2 (without
the BA)
-14
-1
13 (with the
BA)
15 (with the
BA)
Singlemode
LC
P1L1-2D
2
-24
-7
Singlemode
LC
Le-64.2
-21
-8
Singlemode
LC
Ls-64.2
-21
-8
Singlemode
LC
V-64.2b
(BA+PA
+DCU)
-4 (without
the BA, PA,
or DCU)
-1 (without
the BA, PA,
or DCU)
-1
Singlemode
LC
13 (with the
BA)
15 (with the
BA)
-14
(without the
BA, PA, or
DCU)
I-64.1
-6
-1
-11
-1
Singlemode
LC
S-64.2b
-1
-14
-1
Singlemode
LC
I-1
-15
-8
-23
-8
Singlemode
LC
S-1.1
-15
-8
-28
-8
Singlemode
LC
L-1.1
-5
-34
-10
Singlemode
LC
-26 (with
the PA)

1504

Board
Name
SLH41
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
L-1.2
-5
Ve-1.2
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-34
-10
Singlemode
LC
-3
-34
-10
Singlemode
LC
I-4
-15
-8
-23
-8
Singlemode
LC
S-4.1
-15
-8
-28
-8
Singlemode
LC
L-4.1
-3
-28
-8
Singlemode
LC
L-4.2
-3
-28
-8
Singlemode
LC
Ve-4.2
-3
-34
-13
Singlemode
LC
S-1.1
-15
-8
-28
-8
Singlemode
LC
L-1.1
-5
-34
-10
Singlemode
LC
S-4.1
-15
-8
-28
-8
Singlemode
LC
Table 26-4 lists common parameters specified for optical interfaces of SDH boards (FEC
boards).
Issue 03 (2013-02-20)

1505

Table 26-4 Common parameters specified for optical interfaces of SDH boards (FEC boards)
Board
Name
SF16
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimu
m (dBm)
Maximu
m (dBm)
Ue-16.2c
Without
BA or PA:
-5
Without
BA or PA:
-1
With BA:
13
With BA:
15
Without
BA or PA:
-5
Without
BA or PA:
-1
With BA:
13
With BA:
15
Without
BA, RA, or
PA: -5
Without
BA, RA, or
PA: -1
Without
BA, RA, or
PA: -27.5
With BA:
15
With BA:
18
With PA:
-42
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Without BA
or PA: -27.5
-10
Singlemode
LC
-10
Singlemode
LC
-10
Singlemode
LC
Ue-64.2c
-3
-14
-1
Singlemode
LC
Ue-64.2d
-3
-14
-1
Singlemode
LC
Ue-64.2e
-3
-14
-1
Singlemode
LC
Ue-64.2c
-4
-1
-14
-1
Singlemode
LC
Ue-64.2d
-4
-1
-14
-1
Singlemode
LC
Ue-64.2e
-4
-1
-14
-1
Singlemode
LC
Ue-64.2c
-4
-1
-14
-1
Singlemode
LC
Ue-16.2d
Ue-16.2f
SF64
SF64A
SFD64
Issue 03 (2013-02-20)
Type of
Fiber
With PA:
-37
Without BA
or PA: -27.5
With PA:
-37

1506

Board
Name
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimu
m (dBm)
Maximu
m (dBm)
Ue-64.2d
-4
Ue-64.2e
-4
Type of
Fiber
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
-1
-14
-1
Singlemode
LC
-1
-14
-1
Singlemode
LC
26.2.2 Parameters Specified for the Optical Ports of PDH Boards

This topic lists parameters specified for optical ports of PDH boards.
Table 26-5 lists the common parameters specified for the optical interfaces of the PDH boards.
Table 26-5 Common parameters specified for the optical interfaces of the PDH boards
Board
Name
PFL1
Optical Module
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Minimum
(dBm)
Maximum
(dBm)
I-2M
-15
-8
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
-23
-8
Type of
Fiber
Singlemode
LC
26.2.3 Common Parameters Specified for Optical Interfaces of

Packet Boards
This topic describes common parameters specified for optical interfaces of packet boards.
Table 26-6 lists common parameters specified for optical interfaces of packet processing
boards.Table 26-7 lists common parameters specified for optical interfaces of packet interface
boards.
Issue 03 (2013-02-20)

1507

Table 26-6 Parameters specified for optical interfaces of packet processing boards
Board Name
N1PEX1
N2PEX1
PEG16
Issue 03 (2013-02-20)
Optical Module
Type
of
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
10GB
ASESR/SW
-7.3
10GB
ASELR/
LW
Type
of
Fiber
Trans
missi
on
Dista
nce
(km)
Receive
r
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-1.3
-7.5
-1
Multimode
LC
0.3
-6
-1
-11
-1
Single
-mode
LC
10
10GB
ASEER/
EW
-1
-15
-1
Single
-mode
LC
40
10GB
ASEZR/
ZW
-24
-7
Single
-mode
LC
80
10GB
ASELR
-6
-1
-11
-1
Single
-mode
LC
10
10GB
ASEER
-1
-15
-1
Single
-mode
LC
40
10GB
ASEZR
-24
-7
Single
-mode
LC
80
1000B
ASEZX
-2
-23
-3
Single
-mode
LC
80
1000B
ASEVX
-5
-23
-3
Single
-mode
LC
40
1000B
ASELX
-9
-3
-20
-3
Single
-mode
LC
10
1000B
ASESX
-9.5
-2.5
-17
Multimode
LC
0.5

1508

Board Name
Optical Module
PEX2
PEG8
Type
of
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
10GB
ASELR
-6
10GB
ASEER
Type
of
Fiber
Trans
missi
on
Dista
nce
(km)
Receive
r
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-1
-11
-1
Single
-mode
LC
10
-1
-15
-1
Single
-mode
LC
40
10GB
ASEZR
-24
-7
Single
-mode
LC
80
1000B
ASEZX
-2
-23
-3
Single
-mode
LC
80
1000B
ASEVX
-5
-23
-3
Single
-mode
LC
40
1000B
ASELX
-9
-3
-20
-3
Single
-mode
LC
10
1000B
ASESX
-9.5
-2.5
-17
Multimode
LC
0.5
Table 26-7 Parameters specified for optical interfaces of packet interface boards
Board
Name
CQ1
Issue 03 (2013-02-20)
Optical Module
Type of
Interfac
e
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
S-1.1
-15
L-1.1
-5
Type of
Fiber
Transm
ission
Distanc
e (km)
Receive
r
Sensiti
vity
(dBm)
Minim
um
Overloa
d (dBm)
-8
-28
-8
Singlemode LC
2 to 15
-34
-10
Singlemode LC
15 to 40

1509

Board
Name
PEFF8
Optical Module
Type of
Interfac
e
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
L-1.2
-5
100BAS
E-ZX
Type of
Fiber
Transm
ission
Distanc
e (km)
Receive
r
Sensiti
vity
(dBm)
Minim
um
Overloa
d (dBm)
-34
-10
Singlemode LC
40 to 80
-5
-34
-10
Singlemode LC
80
100BAS
E-VX
-5
-34
-10
Singlemode LC
40
100BAS
E-LX
-15
-8
-28
-8
Singlemode LC
15
100BAS
E-FX
-19
-14
-30
-14
Multimode LC
26.2.4 Common Parameters Specified for Optical Interfaces of

Packet Boards
This topic describes common parameters specified for optical interfaces of the EoD.
Table 26-8 lists the parameters specified for optical interfaces of the EoD.
Table 26-8 Parameters specified for optical interfaces of the EoD
Board
Name
EDQ41
Issue 03 (2013-02-20)
Optical Module
Type of
Interface
Mean Launched Optical

Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Type of
Fiber
Maximu
m (dBm)
Minimum
(dBm)
S-1.1
-8
-15
-28
-8
Singlemode
LC
L-1.1
-5
-34
-10
Singlemode
LC
L-1.2
-5
-34
-10
Singlemode
LC

1510

Board
Name
Optical Module
Type of
Interface
Mean Launched Optical

Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Type of
Fiber
Maximu
m (dBm)
Minimum
(dBm)
S-4.1
-8
-15
-28
-8
Singlemode
LC
L-4.1
-2
-3
-28
-8
Singlemode
LC
L-4.2
-2
-3
-28
-8
Singlemode
LC
Ve-4.2
-2
-3
-34
-13
Singlemode
LC
26.2.5 Common Parameters Specified for Optical Interfaces of Data

Boards
This topic describes common parameters specified for optical interfaces of data boards.
Table 26-9 lists the common parameters specified for the optical interfaces of the data boards.
Table 26-9 Common parameters specified for the optical interfaces of the data boards
Board Name
Optical Module
EGS2, EGS4, EGR2, EGT2,

EMS2, EMS4, EGS4, EGS4A
and EMR0
Issue 03 (2013-02-20)
Type
of
Supp
orted
Optic
al
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
1000B
ASEZX (80
km)
-2

Receiv
er
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-23
-3
Type
of
Fiber
Singl
emode
LC
1511

Board Name
Optical Module
Type
of
Supp
orted
Optic
al
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
1000B
ASEVX (40
km)
-5
1000B
ASELX (10
km)
Type
of
Fiber
Receiv
er
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-23
-3
Singl
emode
LC
-9
-3
-20
-3
Singl
emode
LC
1000B
ASESX
(0.5
km)
-9.5
-2.5
-17
Multi
mode
LC
EAS2
10GB
ASELR/
LW
-6
-1
-11
-1
Singl
emode
LC
EFF8, EFF8A
100BA
SE-LX
(15
km)
-15
-8
-28
-8
Singl
emode
LC
100BA
SE-FX
(2 km)
-19
-14
-30
-14
Multi
mode
LC
S-4.1
-15
-8
-28
-8
Singl
emode
LC
L-4.1
-3
-28
-8
Singl
emode
LC
ADL4, IDL4
Issue 03 (2013-02-20)

1512

Board Name
ADQ1, IDQ1
MST4
Issue 03 (2013-02-20)
Optical Module
Type
of
Supp
orted
Optic
al
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
L-4.2
-3
Ve-4.2
Type
of
Fiber
Receiv
er
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-28
-8
Singl
emode
LC
-3
-34
-13
Singl
emode
LC
Ie-1
-19
-14
-30
-14
Multi
mode
LC
S-1.1
-15
-8
-28
-8
Singl
emode
LC
L-1.1
-5
-34
-10
Singl
emode
LC
L-1.2
-5
-34
-10
Singl
emode
LC
Ve-1.2
-3
-34
-10
Singl
emode
LC
X3.29
6/
(DVBASI)
EN500
83-9
200M5SN-I
-15
-8
-31
-8
Singl
emode
LC
-19
-14
-30
-14
Singl
emode
LC

1513

Board Name
Optical Module
Type
of
Supp
orted
Optic
al
Interf
ace
Mean Launched
Optical Power
Minim
um
(dBm)
Maxim
um
(dBm)
200SMLC-I
-9.5
Type
of
Fiber
Receiv
er
Sensiti
vity
(dBm)
Mini
mum
Overl
oad
(dBm)
-2.5
-17
Singl
emode
LC
-10
-3
-21
-3
Multi
mode
LC
-5
-21
Singl
emode
LC
26.3 Quick Reference of Board Functions

This topic describes the functions supported by SDH boards, PDH boards, data boards, and
packet boards.
26.3.1 Information Quick Reference of SDH Boards

This topic describes the functions supported by different types of SDH boards.
Table 26-10 provides the functions supported by SDH boards.
Table 26-10 Basic functions of SDH boards
Issue 03 (2013-02-20)
Func
tion
ALS
REG
Speci
ficati
ons
PRBS
AU-3
TCM
FEC
Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N1SL
64
N2SL
64

1514

Issue 03 (2013-02-20)
Func
tion
ALS
REG
Speci
ficati
ons
PRBS
AU-3
TCM
FEC
Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N4SL
64
T2SL
64
T2SL
64A
N1SF
64
N1SF
64A
N1SL
D64
N4SL
D64
N1SL
16
N2SL
16
N3SL
16
N1SL
16A
N2SL
16A
N3SL
16A
N1SL
D16
N1SL
Q16
N2SL
Q16
N4SL
Q16

1515

Issue 03 (2013-02-20)
Func
tion
ALS
REG
Speci
ficati
ons
PRBS
AU-3
TCM
FEC
Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N1SL
O16
N4SL
O16
N1SF
16
N3SL
Q41
N3SL
H41
N1SL
4
N2SL
4
R1SL
4
N1SL
4A
N1SL
Q4
N2SL
Q4
N1SL
Q4A
N1SL
D4
N2SL
D4
R1SL
D4
R3SL
D4
N1SL
D4A

1516

Func
tion
ALS
REG
Speci
ficati
ons
PRBS
AU-3
TCM
FEC
Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N1SL
T1
N1SL
Q1
N2SL
Q1
R1SL
Q1
N1SL
Q1A
R3SL
Q1
N1SL
1
N2SL
1
N1SL
1A
R1SL
1
R3SL
1
N1SL
H1
N1SE
P1
N2SL
O1
N3SL
O1
26.3.2 Information Quick Reference of PDH Boards

This topic describes the functions supported by different types of PDH boards.
Table 26-11 provides the functions supported by PDH boards.
Issue 03 (2013-02-20)

1517

Table 26-11 Basic functions of PDH boards

Function
PRBS
TPS
E13
M13
R1PL1
R1PD1
R2PD1
R3PD1
YNote
N1PQ1
N2PQ1
N1PQM
N1PL3
N2PL3
N1PL3A
N2PL3A
N1PD3
N2PD3
N2PQ3
N1DX1
N1DXA
N1SPQ4
N2SPQ4
N1PFL1
NOTE
The R3PD1 supports the E13 function only in server mode.
26.3.3 Information Quick Reference of Data Boards

This topic describes the functions supported by different types of data boards.
Table 26-12 provides the functions supported by Ethernet boards.
Issue 03 (2013-02-20)

1518

Table 26-12 Basic functions of Ethernet boards
Issue 03 (2013-02-20)
Fu
nct
ion
EP
L
EV
PL
EP
LA
N
EV
PL
AN
MP
LS
VC
TR
UN
K
spe
cifi
cati
ons
Qo
S
ET
H
OA
M
(80
2.1
ag)
ET
H
OA
M
(80
2.3
ah)
Tes
t
Fra
me
s
Qi
nQ
R
M
ON
IG
MP
Sn
oo
pin
g
R1
EF
T4
N1
EF
T8
16
N1
EF
T8
A
N1
EG
T2
N2
EG
T2
N1
EF
S0
12
N2
EF
S0
24
N4
EF
S0
24
N5
EF
S0
24
N1
EF
S0
A
32
N1
EF
S4
12

1519

Issue 03 (2013-02-20)
Fu
nct
ion
EP
L
EV
PL
EP
LA
N
EV
PL
AN
MP
LS
VC
TR
UN
K
spe
cifi
cati
ons
Qo
S
ET
H
OA
M
(80
2.1
ag)
ET
H
OA
M
(80
2.3
ah)
Tes
t
Fra
me
s
Qi
nQ
R
M
ON
IG
MP
Sn
oo
pin
g
N2
EF
S4
24
N3
EF
S4
24
N2
EG
S2
48
N3
EG
S2
48
N1
EM
S4
64
N1
EM
S2
48
N1
EG
S4
64
N3
EG
S4
64
N4
EG
S4
64
N2
EG
R2
N2
EM
R0
N1
EA
S2
24

1520

Fu
nct
ion
EP
L
EV
PL
EP
LA
N
EV
PL
AN
MP
LS
VC
TR
UN
K
spe
cifi
cati
ons
Qo
S
ET
H
OA
M
(80
2.1
ag)
ET
H
OA
M
(80
2.3
ah)
Tes
t
Fra
me
s
Qi
nQ
R
M
ON
IG
MP
Sn
oo
pin
g
NOTE
For the ETH OAM functions supported by data boards, see "Availability" in the Feature Description.
Table 26-13 provides basic functions supported by SAN/Video boards.

Table 26-13 Basic functions supported by SAN/Video boards
Functio
n
FC100
FC200
FICON
ESCON
DVBASI
SD-SDI
HDSDI
N1MST
4
N1VST4
26.3.4 Information Quick Reference of Packet Boards

This topic describes the functions supported by different types of packet boards.
Table 26-14 provides the functions supported by packet Ethernet boards.
Issue 03 (2013-02-20)

1521

Table 26-14 Basic functions of packet Ethernet boards
Issue 03 (2013-02-20)
F
u
n
ct
io
n
E
L
i
n
e
E
L
A
N
E
A
G
G
R
H
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
el
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
M
C
L
A
G
M L
S P
T T
P
M
SP
W
E
T
H
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
pi
n
g
1
5
8
8
V
2
I
n
b
a
n
d
D
C
N
R
M
O
N
T
N
N
1
E
G
8
T
N
N
1
E
X
2
N
1
P
E
G
1
6
N
1
P
E
G
8
N
1
P
E
X
1

1522

Issue 03 (2013-02-20)
F
u
n
ct
io
n
E
L
i
n
e
E
L
A
N
E
A
G
G
R
H
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
el
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
M
C
L
A
G
M L
S P
T T
P
M
SP
W
E
T
H
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
pi
n
g
1
5
8
8
V
2
I
n
b
a
n
d
D
C
N
R
M
O
N
N
2
P
E
X
1
N
1
P
E
X
2
N
1
P
E
T
F
8
N
1
P
E
F
F
8
N
1
E
D
Q
4
1

1523

Issue 03 (2013-02-20)
F
u
n
ct
io
n
E
L
i
n
e
E
L
A
N
E
A
G
G
R
H
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
el
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
M
C
L
A
G
M L
S P
T T
P
M
SP
W
E
T
H
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
pi
n
g
1
5
8
8
V
2
I
n
b
a
n
d
D
C
N
R
M
O
N
Q
1
P
E
G
S
2
R
1
P
E
G
S
1
R
1
P
E
F
4
F
R
1
P
E
F
S
8
T
N
N
1
E
T
M
C

1524

F
u
n
ct
io
n
E
L
i
n
e
E
L
A
N
E
A
G
G
R
H
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
el
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
M
C
L
A
G
M L
S P
T T
P
M
SP
W
E
T
H
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
pi
n
g
1
5
8
8
V
2
I
n
b
a
n
d
D
C
N
R
M
O
N
T
N
N
1
E
F
F
8
26.4 Loopback Capability of the Boards

The SDH boards, PDH boards, and data boards of the OptiX OSN equipment support various
types of loopbacks.
Table 26-15 provides the loopback capability of the SDH boards of the OptiX OSN equipment.
Table 26-15 Loopback capability of the SDH boards
Issue 03 (2013-02-20)
Board
Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N1SL1
Supported
Supported
Supported
Not
supported
Not
supported
R1SL1
Supported
Supported
Supported
Not
supported
Not
supported
N1SL4
Supported
Supported
Supported
Not
supported
Not
supported
R1SL4
Supported
Supported
Supported
Not
supported
Not
supported
N1SL16
Supported
Supported
Supported
Not
supported
Not
supported
N3SL16
Supported
Supported
Supported
Supported
Not
supported

1525

Issue 03 (2013-02-20)
Board
Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N1SL64
Supported
Supported
Supported
Supported
Not
supported
N2SL64
Supported
Supported
Not
supported
Not
supported
Not
supported
N4SL64
Supported
Supported
Supported
Supported
Not
supported
N1SF64
Supported
Supported
Supported
Supported
Not
supported
N1SF64A
Supported
Supported
Supported
Supported
Not
supported
N1SLD64
Supported
Supported
Supported
Supported
Not
supported
N4SLD64
Supported
Supported
Supported
Supported
Not
supported
N1SL16
Supported
Supported
Supported
Not
supported
Not
supported
N2SL16
Supported
Supported
Not
supported
Not
supported
Not
supported
N3SL16
Supported
Supported
Supported
Supported
Not
supported
N1SL16A
Supported
Supported
Supported
Not
supported
Not
supported
N2SL16A
Supported
Supported
Not
supported
Not
supported
Not
supported
N3SL16A
Supported
Supported
Supported
Supported
Not
supported
N1SLD16
Supported
Supported
Supported
Supported
Not
supported
N1SLQ16
Supported
Supported
Supported
Supported
Not
supported
N2SLQ16
Supported
Supported
Not
supported
Not
supported
Not
supported
N4SLQ16
Supported
Supported
Supported
Supported
Not
supported
N1SLO16
Supported
Supported
Supported
Supported
Not
supported

1526

Issue 03 (2013-02-20)
Board
Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N4SLO16
Supported
Supported
Supported
Supported
Not
supported
N1SF16
Supported
Supported
Supported
Not
supported
Not
supported
N3SLQ41
Supported
Supported
Supported
Supported
Not
supported
N3SLH41
Supported
Supported
Supported
Supported
Not
supported
N1SL4
Supported
Supported
Supported
Not
supported
Not
supported
N1SL4A
Supported
Supported
Supported
Supported
Not
supported
N2SL4
Supported
Supported
Not
supported
Not
supported
Not
supported
R1SL4
Supported
Supported
Supported
Not
supported
Not
supported
N1SLQ4
Supported
Supported
Supported
Not
supported
Not
supported
N1SLQ4A
Supported
Supported
Supported
Supported
Not
supported
N2SLQ4
Supported
Supported
Not
supported
Not
supported
Not
supported
N1SLD4
Supported
Supported
Supported
Not
supported
Not
supported
N1SL4DA
Supported
Supported
Supported
Supported
Not
supported
N2SLD4
Supported
Supported
Not
supported
Not
supported
Not
supported
R1SLD4
Supported
Supported
Supported
Not
supported
Not
supported
N1SLT1
Supported
Supported
Supported
Supported
Not
supported
N1SLQ1
Supported
Supported
Supported
Not
supported
Not
supported
N1SLQ1A
Supported
Supported
Supported
Supported
Not
supported

1527

Board
Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N2SLQ1
Supported
Supported
Not
supported
Not
supported
Not
supported
R1SLQ1
Supported
Supported
Supported
Not
supported
Not
supported
N1SL1
Supported
Supported
Supported
Not
supported
Not
supported
N1SL1A
Supported
Supported
Supported
Supported
Not
supported
N2SL1
Supported
Supported
Not
supported
Not
supported
Not
supported
R1SL1
Supported
Supported
Supported
Not
supported
Not
supported
N1SLH1
Supported
Supported
Supported
Supported
Not
supported
N1SEP1
Supported
Supported
Supported
Not
supported
Not
supported
N2SLO1
Supported
Supported
Not
supported
Not
supported
Not
supported
N3SLO1
Supported
Supported
Supported
Supported
Not
supported
Table 26-16 provides information on whether each SDH board of the OptiX OSN equipment
supports the insertion of the AU_AIS when the board is looped back.
Table 26-16 Information on whether each SDH board of the OptiX OSN equipment supports
the insertion of the AU_AIS when the board is looped back
Issue 03 (2013-02-20)
Board
Insertion of
the AU_AIS to
the Port Side
(Inloop at an
Interface)
Insertion of the
AU_AIS to the
Cross-Connect
Side (Outloop
at an Interface)
Insertion of
the AU_AIS to
the CrossConnect Side
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on a
VC-4 Path)
N1SL64
Supported
Supported
Supported
Supported
N4SL64
Supported
Supported
Supported
Supported
N2SL64
Not supported
Supported
Not supported
Not supported
N1SF64
Supported
Supported
Supported
Supported

1528

Issue 03 (2013-02-20)
Board
Insertion of
the AU_AIS to
the Port Side
(Inloop at an
Interface)
Insertion of the
AU_AIS to the
Cross-Connect
Side (Outloop
at an Interface)
Insertion of
the AU_AIS to
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on a
VC-4 Path)
N1SF64A
Supported
Supported
Supported
Supported
N1SLD64
Supported
Supported
Supported
Supported
N1SL16
Not supported
Supported
Not supported
Not supported
N2SL16
Not supported
Supported
Not supported
Not supported
N3SL16
Supported
Supported
Supported
Supported
N1SL16A
Not supported
Supported
Not supported
Not supported
N2SL16A
Not supported
Supported
Not supported
Not supported
N3SL16A
Supported
Supported
Supported
Supported
N1SLD16
Supported
Supported
Supported
Supported
N1SLQ16
Supported
Supported
Supported
Supported
N2SLQ16
Not supported
Supported
Not supported
Not supported
N1SLO16
Supported
Supported
Supported
Supported
N1SF16
Not supported
Supported
Not supported
Not supported
N3SLQ41
Supported
Supported
Supported
Supported
N3SLH41
Supported
Supported
Supported
Supported
N1SL4
Not supported
Supported
Not supported
Not supported
N1SL4A
Supported
Supported
Supported
Supported
N2SL4
Not supported
Supported
Not supported
Not supported
R1SL4
Not supported
Supported
Not supported
Not supported
N1SLQ4
Not supported
Supported
Not supported
Not supported
N1SLQ4A
Supported
Supported
Supported
Supported
N2SLQ4
Not supported
Supported
Not supported
Not supported
N1SLD4
Not supported
Supported
Not supported
Not supported
N1SLD4A
Supported
Supported
Supported
Supported
N2SLD4
Not supported
Supported
Not supported
Not supported
R1SLD4
Not supported
Supported
Not supported
Not supported
N1SLT1
Supported
Supported
Supported
Supported

1529

Board
Insertion of
the AU_AIS to
the Port Side
(Inloop at an
Interface)
Insertion of the
AU_AIS to the
Cross-Connect
Side (Outloop
at an Interface)
Insertion of
the AU_AIS to
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on a
VC-4 Path)
N1SLQ1
Not supported
Supported
Not supported
Not supported
N1SLQ1A
Supported
Supported
Supported
Supported
N2SLQ1
Not supported
Supported
Not supported
Not supported
R1SLQ1
Not supported
Supported
Not supported
Not supported
N1SL1
Not supported
Supported
Not supported
Not supported
N1SL1A
Supported
Supported
Supported
Supported
N2SL1
Not supported
Supported
Not supported
Not supported
R1SL1
Not supported
Supported
Not supported
Not supported
N1SLH1
Supported
Supported
Supported
Supported
N1SEP1
Not supported
Supported
Not supported
Not supported
N2SLO1
Not supported
Supported
Not supported
Not supported
N3SLO1
Supported
Supported
Supported
Supported
Table 26-17 provides the loopback capability of the PDH boards of the OptiX OSN equipment.
Table 26-17 Loopback capability of the PDH boards
Issue 03 (2013-02-20)
Board
Inloop at an Interface
Outloop at an Interface
R1PL1
Supported
Supported
R1PD1
Supported
Supported
N1PQ1
Supported
Supported
N1PQM
Supported
Supported
N1PD3
Supported
Supported
N1PL3
Supported
Supported
N2PQ3
Supported
Supported
N2SPQ4
Supported
Supported
N1PFL1
Supported
Supported

1530

Table 26-18 provides the loopback capability of the data boards of the OptiX OSN equipment.
Table 26-18 Loopback capability of the data boards of the OptiX OSN equipment
Issue 03 (2013-02-20)
Board
Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1EFS4
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N2EFS4
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N3EFS4
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1EFS0
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N2EFS0
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N4EFS0
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N5EFS0
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1EFS0A
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1EGT2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N2EGT2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1EFT8
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N1EFT8A
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
R1EFT4
Not
supported
Supported
Not
supported
Supported
Not
supported
Supported
N1EMS4
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
N1EMS2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported

1531

Board
Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1EGS4
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
N3EGS4
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
N2EGS4
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
N4EGS4
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
N2EGS2
Not
supported
Not
supported
Not
supported
Supported
Not
supported
Supported
N3EGS2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N2EGR2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1EAS2
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N2EMR0
Not
supported
Supported
Not
supported
Supported
Not
supported
Not
supported
Table 26-19 provides the loopback capability of the ATM/IMA boards of the OptiX OSN
equipment.
Table 26-19 Loopback capability of the ATM/IMA boards of the OptiX OSN equipment
Issue 03 (2013-02-20)
Board
Outloop at an
External
Interface
Inloop at an
External
Interface
Outloop at an
Internal
Interface
Inloop at an
Internal
Interface
N1ADL4
Not supported
Supported
Supported
Supported
N1ADQ1
Not supported
Supported
Supported
Supported
N1IDL4
Not supported
Supported
Supported
Supported
N1IDL4A
Not supported
Supported
Supported
Supported
N1IDQ1
Not supported
Supported
Supported
Supported
N1IDQ1A
Not supported
Supported
Supported
Supported

1532

Table 26-20 provides the loopback capability of the packet Ethernet boards of the OptiX OSN
equipment.
Table 26-20 Loopback capability of the packet Ethernet boards of the OptiX OSN equipment
Issue 03 (2013-02-20)
Board
Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1PEX1
Not
supported
Supported
Supported
Supported
Not
supported
Not
supported
N2PEX1
Supported
Supported
Not
supported
Not
supported
Not
supported
Not
supported
N1PEX2
Supported
Supported
Not
supported
Not
supported
Not
supported
Not
supported
N1PEG16
Not
supported
Supported
Supported
Supported
Not
supported
Not
supported
N1PEG8
Supported
Supported
Not
supported
Not
supported
Not
supported
Not
supported
N1PETF8
Supported
Supported
Not
supported
Supported
Not
supported
Not
supported
N1PEFF8
Supported
Supported
Not
supported
Supported
Not
supported
Not
supported
R1PEFS8
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
R1PEF4F
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
R1PEGS1
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
Q1PEGS2
Supported
Not
supported
Not
supported
Supported
Not
supported
Not
supported
TNN1EG8
Supported
Supported
Not
supported
Not
supported
Not
supported
Not
supported
TNN1EX2
Supported
Supported
Not
supported
Not
supported
Not
supported
Not
supported
TNN1ETM
C
Supported
Supported
Supported
(only by
GE ports)
Supported
Not
supported
Not
supported
TNN1EFF
8
Supported
Supported
Not
supported
Supported
Not
supported
Not
supported

1533

Table 26-21 provides the loopback capability of the channelized STM-1 CES boards of the
Table 26-21 Loopback capability of the channelized STM-1 CES boards of the OptiX OSN
equipment
Board
Inloop
at a
Port
Outloo
p at a
Port
Inloop
on a
VC-4
Path
Outloo
p on a
VC-4
Path
Inloop on a
VC-12 Path
Outloop on a
VC-12 Path
N1CQ1
Support
ed
Support
ed
Not
support
ed
Not
support
ed
Not supported
Not supported
TNN1CO1
Support
ed
Support
ed
Not
support
ed
Not
support
ed
Supported
Supported
Table 26-22 provides the loopback capability of the packet ATM boards of the OptiX OSN
equipment.
Table 26-22 Loopback capability of the packet ATM boards of the OptiX OSN equipment
Board
Inloop at
a Port
Outloop
at a Port
Inloop on a VC-4
Path
Outloop on a
VC-4 Path
TNN1AFO1
Supported
Supported
Not supported
Not supported
Table 26-23 provides the loopback capability of the dual-domain boards of the OptiX OSN
equipment.
Table 26-23 Loopback capability of the dual-domain boards of the OptiX OSN equipment
Board
Inloop at
a Port
Outloop
at a Port
Inloop
on a VC-4
Path
Outloop
on a
VC-4
Path
Outloop on a
VC-3/VC-12
Path
N1EDQ41
Supported
Supported
Supported
Supported
Not supported
Table 26-24 provides the loopback capability of the SAN/Video boards of the OptiX OSN
equipment.
Issue 03 (2013-02-20)

1534

Table 26-24 Loopback capability of the SAN/Video boards of the OptiX OSN equipment
Board
Inloop at
a Port
Outloop
at a Port
Inloop
on a VC-4
Path
Outloop
on a
VC-4
Path
Outloop on a
VC-3/VC-12
Path
N1MST4
Supported
Supported
Not
supported
Not
supported
Not supported
N1VST4
Supported
Supported
Not
supported
Not
supported
Not supported
26.5 Protection Schemes Supported by Each Board

The SDH boards, PDH boards, data boards, microwave boards, and packet boards of the OptiX
OSN equipment support various protection schemes.
Table 26-25 lists the protection schemes that the SDH boards of the OptiX OSN equipment
support.
Table 26-25 Protection schemes that the SDH boards of the OptiX OSN equipment support
Board
Issue 03 (2013-02-20)
Protection Scheme
TwoFiber
Ring
MSP
FourFiber
Ring
MSP
Linear
MSP
SNCP
SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
rSha
red
Prot
ecti
on
TPS
Prote
ction
N1SL64
N2SL64
N4SL64
N1SF64
A
N1SLD6
4
N4SLD6
4
N1SL16

1535

Board
Issue 03 (2013-02-20)
Protection Scheme
TwoFiber
Ring
MSP
FourFiber
Ring
MSP
Linear
MSP
SNCP
SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
rSha
red
Prot
ecti
on
TPS
Prote
ction
N2SL16
N3SL16
N1SL16
A
N2SL16
A
N3SL16
A
N1SLD1
6
N1SLQ1
6
N4SLQ1
6
N1SLO1
6
N4SLO1
6
N1SF16
N3SLQ4
1
N3SLH4
1
N1SL4
N2SL4
N1SL4A
R1SL4

1536

Board
Protection Scheme
TwoFiber
Ring
MSP
FourFiber
Ring
MSP
Linear
MSP
SNCP
SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
rSha
red
Prot
ecti
on
TPS
Prote
ction
N1SLQ4
N2SLQ4
N1SLQ4
A
N2SLD4
N1SLD4
A
R1SLD4
N1SLT1
N1SLQ1
N2SLQ1
R1SLQ1
N1SL1
N2SL1
N1SL1A
N1SLH1
N1SEP1
N3SLO1
Note: "" means that the board supports the protection scheme and "x" means that the board
does not support the protection scheme.
Table 26-26 lists the protection schemes that the PDH boards of the OptiX OSN equipment
support.
Issue 03 (2013-02-20)

1537

Table 26-26 Protection schemes that the PDH boards of the OptiX OSN equipment support
Board
Protection Scheme
TPS
Protection
for the E1
Services
TPS
Protection
for the E1/
T1 Services
TPS
Protection
for the E3/
T3 Services
TPS
Protection
for the E4/
STM-1
Services
TPS
Protection
for the DDN
Services
R1PL1
R1PD1
N1PQ1
N1PQM
N1PL3
N2PL3
N1PL3A
N2PL3A
N1PD3
N2PD3
N2PQ3
N1DX1
N1DXA
N2SPQ4
N1PFL1
Table 26-27 lists the protection schemes that the data boards of the OptiX OSN equipment
support.
Issue 03 (2013-02-20)

1538

Table 26-27 Protection schemes that the data boards of the OptiX OSN equipment support
Board
Issue 03 (2013-02-20)
Protection Scheme
LCAS
STP/
RSTP
TP
S
Pro
tect
ion
B
PS
Pr
ot
ec
tio
n
PP
S
Pr
ot
ect
io
n
L
A
G
D
L
A
G
LP
T
R
P
R
MSP,
SNCP,
SNCM
P, and
SNCTP
ATM
Protecti
on
R1EFT
4
N1EFT
8
N1EFT
8A
N1EGT
2
N2EGT
2
N1EFS
0
N2EFS
0
N4EFS
0
N5EFS
0
N1EFS
0A
N1EFS
4
N2EFS
4
N3EFS
4
N2EGS
2
N3EGS
2

1539

Board
Protection Scheme
LCAS
STP/
RSTP
TP
S
Pro
tect
ion
B
PS
Pr
ot
ec
tio
n
PP
S
Pr
ot
ect
io
n
L
A
G
D
L
A
G
LP
T
R
P
R
MSP,
SNCP,
SNCM
P, and
SNCTP
ATM
Protecti
on
N1EMS
4
N1EMS
2
N1EGS
4
N3EGS
4
N4EGS
4
N2EGR
2
N2EMR
0
N1EAS
2
N1ADL
4
N1ADQ
1
N1IDL4
N1IDQ
1
N1MST
4
N1VST
4
Table 26-28 lists the protection schemes that the microwave boards of the OptiX OSN equipment
support.
Issue 03 (2013-02-20)

1540

Table 26-28 Protection schemes that the microwave boards of the OptiX OSN equipment
support
Board
Protection schemes
1+1 HSB/FD/SD Protection
N+1 Protection
N1IFSD1
N1RPWR
Table 26-29 lists the protection schemes that the packet boards of the OptiX OSN equipment
support.
Table 26-29 Protection schemes that the packet boards of the OptiX OSN equipment support
Board
Protection Scheme
MPLS
Tunnel
1+1/1:1
Protecti
on
Packetbased
linear
MSP
LPT
LAG
MPLS
PW 1
+1/1:1
MC-LAG
N1PEX1
N2PEX1
N1PEX2
N1PEG16
N1PEG8
TNN1EG8
TNN1EX2
N1PETF8
N1PEFF8
TNN1ETMC
R1PEFS8
R1PEF4F
R1PEGS1
Q1PEGS2
TNN1EFF8
Table 26-30 lists the protection schemes that the dual-domain boards of the OptiX OSN
equipment support.
Issue 03 (2013-02-20)

1541

Table 26-30 Protection schemes that the dual-domain boards of the OptiX OSN equipment
support
Board
Protection Scheme
SDH Protection
N1ED
Q41
Packet
Protection
Twofiber
MSP
ring
Fourfiber
MSP
ring
Linear
MSP
SNCP
SNCM
P
SNCT
P
LAG
MCLAG
26.6 Quick Reference of Power Consumption and Weight of

Each Board
This section lists the power consumption and weight of each board of the OptiX OSN series
equipment.
Table 26-31 lists the power consumption and weight of each board.
Table 26-31 Power consumption and weight of each board
Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
SDH boards
N1SLQ41
12
0.6
N1SLD4
17
0.6
N1SF64A
33(the OptiX
OSN 3500
supports)
1.1
N2SLD4
15
1.0
1.1
R1SLD4
11
0.5
1.1
N1SL4A
17
0.6
26(the OptiX
OSN 7500
supports)
N1SF64
33(the OptiX
OSN 3500
supports)
26(the OptiX
OSN 7500
supports)
N1SL64A
Issue 03 (2013-02-20)
40

1542

Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
N1SL64
30(the OptiX
OSN 3500
supports)
1.1
N1SL4
17
0.6
22(the OptiX
OSN 7500
supports)
N2SL64
32
1.1
N2SL4
15
1.0
T2SL64
40
1.1
R1SL4
10
0.5
N1SF16
26
1.1
R3SL4
11
0.5
N1SLO16
38
1.0
N1SEP1
17
1.0
N1SLQ16
20
0.9
N1SLH1
27
1.0
N2SLQ16
35
1.3
N1SLT1
22
1.3
N1SLD16
23
0.9
N2SLO1
26
1.1
N1SL16A
20
0.6
N3SLO1
20
1.2
N2SL16A
20
1.1
N1SLQ1A
15
1.0
N3SL16A
22
0.9
N1SLQ1
15
1.0
N1SL16
19
1.1
N2SLQ1
15
1.0
N2SL16
19
1.1
R1SLQ1
12
0.4
N3SL16
22
1.1
N1SL1A
17
0.6
N1SLQ4A
17
1.0
N1SL1
17
0.6
N1SLQ4
17
1.0
N2SL1
14
1.0
N2SLQ4
16
1.0
R1SL1
10
0.3
N1SLD4A
17
0.6
R3SL1
11
0.3
T2SL64A
40
1.1
N3SLQ41
16
0.7
N1EU08
11
0.4
N1EU04
0.4
N1OU08
0.4
N2OU08
0.4
N3SLH41
49
1.5
N1SLD64
41
1.2
N4SL64
15(the OptiX
OSN 3500
supports)
1.1
14(the OptiX
OSN 7500
supports)
Issue 03 (2013-02-20)

1543

Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
PDH boards
N1SPQ4
24
0.9
N2PL3
12
0.9
N2SPQ4
24
0.9
N1PQM
22
1.0
N1DXA
10
0.8
N1PQ1
19
1.0
N1DX1
15
1.0
N2PQ1
13
1.0
N1PQ3
13
0.9
R1PD1
15
0.6
N1PD3
19
1.1
R2PD1
15
0.6
N2PD3
12
1.1
R3PD1
0.4
N1PL3A
15
1.0
N1PL1
0.5
N2PL3A
12
0.9
R1PL1
0.5
N1PL3
15
1.0
N2PQ3
13
0.9
N1DM12
0.4
N1TSB8
0.3
N1TSB4
0.3
N1MU04
0.4
N1C34S
0.3
R1L12S
0.3
N1D34S
0.4
N1D12B
0.3
N1D75S
0.4
N1L75S
0.3
N1D12S
0.4
N1PFL1
17
Data boards (TDM mode)
Issue 03 (2013-02-20)
N1MST4
26
0.9
N2EFS4
30
1.0
N1IDQ1
41
1.0
N3EFS4
18
0.6
N1IDL4
41
1.0
N1EFS0A
32
0.7
N1ADQ1
41
1.0
N1EFS0
35
1.0
N1ADL4
41
0.9
N2EFS0
35
1.0
N1EAS2
70
1.2
N4EFS0
35
1.0
N1EMR0
47
1.2
N5EFS0
22
0.6
N2EGR2
40
1.1
N1EGT2
29
0.9
N1EGS4A
53
1.1
N2EGT2
15
0.9
N1EGS4
70
1.1
N1EFT8A
26
1.0
N3EGS4
70
1.1
N1EFT8
26
1.0

1544

Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
N4EGS4
34
0.7
N1EFT4
14
0.5
N1EMS4
65
1.1
N1EFT8
26
1.0
N1EMS2
40
0.8
N1EFT4
14
0.5
N2EGS2
43
1.0
R1EFT4
14
0.5
N3EGS2
25
0.6
N2EMR0
50
1.2
N1EFS4
30
1.0
N1ETF8A
11
0.4
N1ETS8
0.4
N1EFF8A
15
0.4
N1EFF8
0.4
N1ETF8
0.4
N1IDL4A
46
1.5
N1VST4
37
0.8
Packet boards
R1PEFS8
12
0.3
N1PETF8
0.4
Q1PEGS2
0.6
N1PEG16
137
2.3
R1PEGS1
0.4
N1PEX1
107
2.4
N1PEG8
47
1.2
N1PEX2
49
1.4
N2PEX1
48
1.4
N1PEFF8
13
0.5
R1PEF4F
15
0.4
EoD Boards
N1EDQ41
70
1.0
CES boards
N1MD75
12
0.5
N1MD12
12
0.5
N1CQ1
10
0.5
R1ML1A/
B
16
0.4
45
1.4
Microwave boards
N1IFSD1
24
1.1
N1RPWR
WDM boards
Issue 03 (2013-02-20)
N1FIB
0.4
N1MR2B
1.0
N1MR2A
1.0
N1MR2
0.9
N1LWX
30
1.1
N1CMR4
0.9

1545

Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
N1MR4
0.9
N1CMR2
0.8
N1MR2C
1.0
Cross-Connect and system control boards

N1PSXCS
90
2.1
R1PCXLN
60
1.0
N2PSXCS
A
80
1.2
N3PSXCS
A
74
1.5
N1SXCSA
63
2.0
T1PSXCS
A
95
1.4
N4GSCC
19
1.0
Auxiliary boards
N1FANA
19
1.2
R1AMU
0.5
XE1FAN
16
1.5
R1AUX
19
1.0
XE3FAN
10
1.2
R2AUX
19
1.0
R1FAN
20
0.8
Q1AUX
10
0.5
Q1SEI
10
0.9
N1AUX
19
1.0
N1SEI
0.9
T1AUX
0.4
Q1SAP
20
0.7
T1EOW
13
0.5
Q2SAP
25
1.0
R1EOW
10
0.4
Optical amplifier boards and dispersion compensation boards

N1DCU
0.4
62COA
75
8.0
N2DCU
0.4
N1COA
10
3.5
N1RPC02
110
4.2
N1BPA
20
1.0
N1RPC01
70
4.0
N2BPA
11
1.2
61COA
10
3.5
N1BA2
20
1.0
TN11OBU
101
16
1.3
TN11OBU
102
18
1.3
TN12OBU
101
10
1.1
TN12OBU
103
11
1.1
1.2
Power interface boards

R1PIUA
Issue 03 (2013-02-20)
0.5
N1PIU

1546

Issue 03 (2013-02-20)
Board
Power
Consumption
(W)
Weight
(kg)
Board
Power
Consumption
(W)
Weight
(kg)
R1PIUB
0.4
Q2PIU
0.3
R1PIUC
0.5
Q1PIU
1.3
N1PIUA
0.5
R1PIU
0.4
N1PIUB
0.6
T1PIUB
0.5
T1PIU
1.3
UPM
(EPS75-48
15AF)
15
UPM
(EPS30-48
15AF)
10

1547

27
27 Parameter Settings
Parameter Settings
About This Chapter

You can set the parameters for the SDH boards, PDH boards, data boards, packet boards, WDM
boards, optical amplifier boards, and cross-connect and timing unit by using the U2000.
27.1 Packet Processing Boards
The parameters that need to be set for the packet boards include the working mode and maximum
frame length.
27.2 EoD Boards
The parameters that need to be set for the EoD boards include the SDH parameters and Ethernet
parameters.
27.3 Packet Interface Boards
The parameters that you need to set for packet interface boards include J0 byte, J1 byte, J2 byte,
C2 byte, V5 byte, SDH interfaces, PDH interfaces, and recovery value of idle timeslots.
27.4 Data Boards
The parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
27.5 SDH Processing Boards
The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.
27.6 PDH Boards
The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.
27.7 WDM Boards
The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.
27.8 Cross-Connect and Timing Units
The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.
Issue 03 (2013-02-20)

1548

27.9 Optical Amplifier Boards

The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.
Issue 03 (2013-02-20)

1549

27.1 Packet Processing Boards

The parameters that need to be set for the packet boards include the working mode and maximum
frame length.
27.1.1 General Attributes

This topic describes the parameters for configuring the general attributes of an Ethernet port.
The parameters include Port Mode, Enable Port, and Encapsulation Type.
Table 27-1 lists the parameters for configuring the general attributes of an Ethernet port.
Table 27-1 Parameters for configuring the general attributes of an Ethernet port
Field
Value
Description
Port
For example, 21-N1PETF8-1

(Port-1)
Indicates the port name.
Name
For example, Port1
User-defines a port name.
Enable Port
Enabled, Disabled.
The Enable Port parameter

sets whether the Ethernet port
is usable.
Default: Enabled
Click Enable Port(Ethernet

Interface) for more
information.
Layer 2, Layer 3
Port Mode
Selects the working mode of

the Ethernet port.
Layer 2: The port can access
the user-side equipment or
carry Ethernet services that
use the port exclusively.
Layer 3: The port can carry
tunnels.
Encapsulation Type
Null, 802.1Q, QinQ

Default: For details, see
configuration guidelines.
The Encapsulation Type

parameter sets the link layer
encapsulation type of the
port, and specifies the link
layer encapsulation type that
can be identified by this port.
Click Encapsulation Type
(Ethernet Interface) for more
information.
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Field
Value
Description
Working Mode
10M Half-Duplex, 10M FullDuplex, Auto-Negotiation,

100M Half-Duplex, 100M
Full-Duplex, 1000M FullDuplex, 10G Full-Duplex
LAN, 10G Full-Duplex
WAN
Set the Working Mode

parameter to set the working
mode of the Ethernet port on
the board. The Working
Mode parameter indicates
the maximum transmission
rate and communication
mode of a port.
Default: Auto-Negotiation
CAUTION
When configuring a service, set
Working Mode to the same
value if possible for the port and
its interconnected port.
Otherwise, the service may fail.
Click Working Mode

information.
Max Frame Length (byte)
For OptiX OSN 3500/7500:

960 to 9600
For other products: 960 to
9000
Default: 1620
The maximum frame length

is also the maximum
transport unit (MTU).
Click Max Frame Length
(byte) for an Ethernet Port for
more information.
27.1.2 Flow Control

This topic describes the parameters, such as autonegotiation and non-autonegotiation, which are
used for configuring flow control function of an Ethernet port.
Table 27-2 lists the parameters for configuring flow control of an Ethernet port.
Table 27-2 Parameters for configuring flow control of an Ethernet port
Field
Value Range
Description
Port
PORTn
Displays all the available

MAC ports on an Ethernet
board.
Specifies the PORT port. The
letter n indicates the number of
the PORT port.
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Field
Value Range
Description
Non-Autonegotiation
Flow Control Mode
Disabled, Enable Symmetric

Flow Control, Send Only,
Receive Only
Default value: Disable
The Non-Autonegotiation
Flow Control Mode
(Ethernet Port Attribute)
specifies the flow control
mode adopted when an
Ethernet port works in nonauto-negotiation mode.
Click Non-Autonegotiation
Flow Control Mode (Ethernet
Port Attribute) for more
information.
Autonegotiation Flow
Control Mode
The value ranges of the

parameters are different from
each other for different boards
and products. You can click
the hyperlink in the
description to display the
specific information.
The Autonegotiation Flow

Control Mode (Ethernet
Port Attribute) specifies the
flow control mode adopted
when an Ethernet port works in
auto-negotiation mode.
The N1EMS4 and N1EGS4
boards do not support the
autonegotiation traffic control
attribute.
Click Autonegotiation Flow
Control Mode (Ethernet Port
Attribute) for more
information.
27.1.3 Layer 2 Attributes

This topic describes the parameters for configuring the Layer 2 attributes of an Ethernet port.
The parameters include QinQ Type Domain, Tag, Default VLAN ID, and VLAN Priority
Table 27-3 lists the parameters for configuring the Layer 2 attributes of an Ethernet port.
Table 27-3 Parameters for configuring the Layer 2 attributes of an Ethernet port
Issue 03 (2013-02-20)
Field
Value
Description
Port

(Port-1)
Displays the port name.
QinQ Type Domain
0x0600 to 0xFFFE
Sets the QinQ type domain.
NOTE
For the PEG8, PEX2, PEX1,
and EDQ41, this parameter can
be set only to 0x88A8.
This parameter is available

only when you set
Encapsulation Type in
General Attributes to
QinQ.

1552

Field
Value
Description
Tag
Tag Aware, Access, Hybrid
Indicates which type of

packets can be processed.
Tag Aware: The port
transparently transmits the
packet with a VLAN ID
(tagged). If a packet does not
have a VLAN ID (untagged),
the port discards this packet.
In this case, Default VLAN
ID and VLAN Priority are
meaningless.
Access: The port adds the
default VLAN ID to the
packet without any VLAN ID
(untagged). If the packet has
a VLAN ID (tagged), the port
discards this packet.
Hybrid: The port adds the
default VLAN ID to the
packet without any VLAN ID
(untagged). If the packet has
a VLAN ID (tagged), the port
transparently transmits the
packet.
This parameter is unavailable
when you set Encapsulation
Type in General Attributes
to QinQ.
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Field
Value
Description
Default VLAN ID
1 to 4094
Sets the default VLAN ID of

packets that passes through
the port.
When you set Tag to
Access, packets that have a
VLAN ID the same as the
default VLAN ID are
discarded, and packets
without a VLAN are tagged
with the default VLAN ID
and then pass the port.
When you set Tag to
Hybrid, tagged packets are
allowed to pass, and
untagged packets are tagged
with the default VLAN ID
and then pass the port.
NOTE
If an MPLS tunnel needs to
traverse a Layer 2 network, set
the VLAN IDs for the tunnels
connected to the NNI ports at
both ends to the same value
according to the VLAN
planning requirements on the
Layer 2 network.
VLAN Priority
0 to 7
Sets the QoS level. When the

network is busy, packets of a
higher VLAN priority are
processed first and those of a
lower VLAN priority may be
discarded. 0 indicates the
lowest priority and 7 the
highest.
27.1.4 Layer 3 Attributes

This topic describes the parameters for configuring the Layer 3 attributes of an Ethernet port.
The parameters include Enable Tunnel, Specify IP, IP Address, and IP Mask
Table 27-4 lists the parameters for configuring the Layer 3 attributes of an Ethernet port.
Table 27-4 Parameters for configuring the Layer 3 attributes of an Ethernet port
Issue 03 (2013-02-20)
Field
Value
Description
Port

(Port-1)

1554

Field
Value
Description
Enable Tunnel
Enabled, Disabled
The Enable Tunnel

(Ethernet Interface)
parameter sets the MPLS
enabling state of the port.
When Enable Tunnel is set
to Enabled, it indicates that
the port can identify and
process the MPLS label.
Default: Enabled
Click Enable Tunnel

(Ethernet Interface)for more
information.
Manually, Unspecified
Specify IP
Default: Unspecified
The Specify IP parameter,

set by port, indicates the
method of specifying the IP
address parameter of a
specified port.
Click Specify IP(Ethernet
Interface) for more
information.
IP Address
For example, 192.168.0.1
Sets the IP address for the

port.
IP Mask
For example, 255.255.255.0
Sets the subnet mask of the

port.
27.1.5 Advanced Attributes

This topic describes the parameters for configuring the advanced attributes of an Ethernet port.
The parameters include Port Physical parameters, MAC Loopback, and Loopback Check
Table 27-5 lists the parameters for configuring the advanced attributes of an Ethernet port.
Table 27-5 Parameters for configuring the advanced attributes of an Ethernet port
Issue 03 (2013-02-20)
Field
Value
Description
Port

(Port-1)

1555

Field
Value
Description
Port Physical parameters
For example:
Displays physical parameters

of the port.
l Port Enable: Enabled

l Working Mode: AutoNegotiation
l Non-Autonegotiation
Flow Control Mode:
Disabled
l MAC Loopback: NonLoopback
l PHY Loopback: NonLoopback
MAC Loopback
Non-Loopback, Inloop,
Outloop
Sets the loopback state of the

MAC layer.
PHY Loopback
Non-Loopback, Inloop,
Outloop
The PHY Loopback

parameter indicates the
loopback status of the
physical layer of an Ethernet
port. This parameter is an
advanced attribute of the
Ethernet port.
Default: Non-Loopback
Click PHY Loopback

information.
For example,
00-5A-3D-03-4C-1B
MAC Address
Displays the MAC address of

the port.
Default: FF-FF-FF-FF-FFFF
Transmitting Rate(kbit/s)
For example, 1024
Displays the rate at which

packets are transmitted.
Receiving Rate(kbit/s)
For example, 1024
Displays the rate at which

packets are received.
Loopback Check
Enabled, Disabled
Sets loop detection.
Default: Disabled
When this function is

enabled, the equipment
automatically checks
whether a loop is generated
on the link. If a loop is
generated, the related alarm
is reported.
Currently, the OptiX OSN
equipment does not support
this function.
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1556

Field
Value
Description
Loopback Port Block
Enabled, Disabled
Sets the automatic shutdown

of the port.
Default: Disabled
When Loopback Check is

set to Enabled and
Loopback Port Block is set
to Enabled, the equipment
automatically checks
whether a loop is generated
on the link. If a loop is
generated, the port is
automatically shut down to
release the loop.
27.2 EoD Boards

The parameters that need to be set for the EoD boards include the SDH parameters and Ethernet
parameters.
SDH Parameters
l
J0
J1
J2
C2
For the description of the parameter, see 27.5 SDH Processing Boards.
Packet Data Parameters

l
Ethernet interface
For the description of the parameter, see 27.1 Packet Processing Boards.
EoS Parameters
l
Working mode
For more parameters and the description of the parameters, see 27.4.2 Ethernet Parameters.
27.3 Packet Interface Boards

The parameters that you need to set for packet interface boards include J0 byte, J1 byte, J2 byte,
C2 byte, V5 byte, SDH interfaces, PDH interfaces, and recovery value of idle timeslots.
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1557

27.3.1 SDH Parameters

The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.
J1 Byte
J1 is the path trace byte. Successive transmission of the J1 byte at the transmit end helps the
receive end learn that its connection with the specified transmit end is in the continuous
connection state.
When a J1 mismatch is detected at the receive end, the VC-3 path generates an LP_TIM_VC3
alarm and the VC-4 path generates an HP_TIM alarm.
When the J1 byte to be sent is set to the single-byte "" by default, the alarms are not reported.
NOTE
l In the case of the N1EFS4/MST4/EAS2, the J1 byte to be sent is set to " HuaWei SBS " by default.
In the case of the other boards, the J1 byte to be sent is set to the single-byte "" by default.
l In the case of the EMS4/EGS4, it is recommended that you set the J1 byte to be sent to " HuaWei
SBS ".
C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received.
When a C2 mismatch is detected, the VC-3 path generates an LP_SLM_VC3 alarm and the
VC-4 path generates an HP_SLM alarm.
J2 Byte
J2 is the VC-12 path trace byte. This byte is used to transmit repetitively a low order path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter.
When a J2 mismatch is detected, the VC-12 path generates an LP_TIM_VC12 alarm.
When the J2 byte is set to the single-byte "" by default, the alarms are not reported.
V5 Byte
V5 is the path status and signal label byte. This byte is used to detect bit errors and indicate
remote errors or remote failures on lower order paths. The LP_REI and LP_RFI alarms are
generated accordingly.
When a V5 mismatch is detected at the receive end, the VC-12 path generates an LP_SLM_VC12
alarm.
Table 27-6 shows the relationship between the service type and the value of the V5 byte.
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Table 27-6 relationship between the service type and the value of the V5 byte
Service Type
Value of the V5 Byte (Hexadecimal)
Unequipped or supervisory-unequipped
00
Equipped-non-specific payload
01
Asynchronous
02
Bit synchronization
03
Byte synchronization
04
Retained signal flag
05
O.181 test signal
06
VC-AIS
07
Other mapping (For test)
08
ATM mapping
09
HDLC/PPP mapping
0A
HDLC/LAPS mapping
0B
Virtual connection test signal (O.181

special mapping)
0C
GFP mapping
0D
27.3.2 Channelized STM-1 Port

Configuring a channelized STM-1 port includes setting of the parameters such as the
encapsulation type of the port, the maximum data packet size, and the enabling status of the
laser.
Table 27-7 Parameters for the attributes of an SDH port
Issue 03 (2013-02-20)
Field
Value Range
Description
Port
For example, 21-CQ1-1

(PORT-1)
Name
For example, port1
Specifies the name of the port

specified by the user.

1559

Field
Value Range
Description
Port Mode
Layer 1
Displays the working mode

of the CES port Layer 1
indicates the channelized
STM port is currently
available.
The OptiX OSN equipment
currently supports only
Layer 1 in Port Mode. In
this case, the OptiX OSN
equipment can transmit
channelized STM-1 services.
Encapsulation Type
Null
Indicates the link layer

encapsulation type of the
port. It specifies the link layer
encapsulation type that can
be identified and processed
by the port.
When Encapsulation Type
is set to Null, no link layer
encapsulation is available or
the link layer encapsulation is
not performed.
The OptiX OSN equipment
currently supports only
Layer 1 in Port Mode. For
this reason, Encapsulation
Type can only be set to Null
and cannot be changed.
No
Channelize
Displays whether the port is a

channelized port.
Channelize refers to the use
of the low-speed tributary
signals in the STM-N service.
One fiber is used to transmit
multiple channels of data that
are separated from each
other. Each channel of data
exclusively occupies the
bandwidth, in addition to the
starting point, terminating
point, and monitoring policy.
Max Data Packet Size (byte)
Specifies the maximum size

of the packets that can be
received by the port.
This parameter is currently
inapplicable to the OptiX
OSN equipment.
Issue 03 (2013-02-20)

1560

Field
Value Range
Description
Laser Interface Enabling

Status
On, Off
Specifies the enabling status

of the laser on the port.
Default: On
Laser Transmission Distance (m)
Displays the transmission

distance of the laser on the
port.
OSN equipment.
Scrambling Capability
Suppresses multiple 0s and

1s in the data when the
Scrambling Capability is
enabled.
OSN equipment.
CRC Check Length
Specifies the length of the

CRC field in the mapping
protocol.
OSN equipment.
Clock Mode
The Clock Mode parameter

specifies the re-timing mode
of a port.
NOTE
inapplicable to an SDH port.
Loopback Mode
Issue 03 (2013-02-20)
Non-loopback, Inloop,
Outloop
Specifies the loopback status

of the port.
Default: Non-loopback
The loopback mode is used

for locating a fault. Outloop
is used for testing whether the
port module and external
fiber or cable of a board are
proper. Inloop is used for
testing whether the crossconnect unit and service path
of the equipment are proper.

1561

Field
Value Range
Description
CES Encapsulation Clock

Mode
Null, Line Clock Mode,

System Clock Mode
Specifies the encapsulation

mode of the clock signal on a
UNI port on the master side
of the CES service.
Default: Null
l Null: The clock signal is

not encapsulated in the
service packets.
l Line Clock Mode: The
clock frequency signal
extracted on a line port is
used as the time stamp,
which is encapsulated in
the RTP packet header
and transmitted to the
downstream.
l System Clock Mode:
The system frequency
signal is used as the time
stamp, which is
encapsulated in the RTP
packet header and
transmitted to the
downstream.
Poke
Specifies the enabling status

of the CES encapsulation
clock poke.
OSN equipment.
Table 27-8 Parameters for an associated service

Field
Value Range
Description
Service Type
For example, CES service
Displays the type of the

service associated with the
port.
Service ID
For example, 20
Displays the ID of the service

associated with the port.
When you select the value of
the service ID, the active
window changes to the
service management dialog
box of the corresponding
service type.
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1562

Field
Value Range
Description
Service Name
For example, CES
Displays the name of the

port.
Used Resource
For example, 64K

Timeslot1-31
Displays the resource used by

the service associated with
the port.
27.3.3 E1 Port
In addition to the general attributes of an E1 port, you need to set the frame format based on the
advanced attributes to ensure that the frame format specified for the E1 port is the same as the
service encapsulation format.
Table 27-9 Parameters for the general attributes of a PDH port
Field
Value Range
Description
Port
Slot ID-Board name-Port

(Port No.)
Name
For example, Port 1
Enters the port name

specified by the user.
Port Mode
Layer 1, Layer 2, Layer 3
Specifies the working mode

of the PDH port.
NOTE
For the OptiX OSN equipment,
Port Mode can be set to only
Layer 1.
Encapsulation Type
Null
When this parameter is set to

Layer 1, the port can transmit
TDM signals.
Specifies Encapsulation
Type.
When Port Mode is set to
Layer 1, Encapsulation
Type is defaulted to Null and
cannot be changed.
Max Data Packet Size (byte)
Specifies the maximum size

of the packets.
NOTE
This parameter is not applicable
to an E1 port in the CES service.
Issue 03 (2013-02-20)

1563

Table 27-10 Parameters for the advanced attributes of a PDH port

Field
Value Range
Description
Port
Slot ID-Board name-Port

(Port No.)
Frame Format
Unframe, Double Frame,

CRC-4 Multiframe
Specifies the frame format.
Line Encoding Format
HDB3
When the E1 port transmits

CES services in CESoPSN
mode, this parameter can be
set to Double Frame or
CRC-4 Multiframe. It is
recommended that you set
this parameter to CRC-4
Multiframe. When the CES
services are in SAToP mode,
this parameter needs to be set
to Unframe.
Displays the line encoding
format.
The HDB3 codes are
transmitted on the E1 port.
Clock Mode
Master Mode, Slave Mode,

Line Clock Mode
Default: Master Mode
The Clock Mode parameter

specifies the re-timing mode
of a port.
Click Clock Mode for more
information.
Loopback Mode
Non-loopback, Inloop,
Outloop
Specifies the loopback status

of the port.
Impedance
75 ohm, 120 ohm
Displays the impedance of

the port.
NOTE
When the OptiX OSN
3500/7500 uses the N1MD75
board, Impedance is set to 75
ohm and cannot be changed.
When the N1MD12 board is
used, Impedance is set to 120
ohm and cannot be changed.
Frame Mode
Specifies the value of the

frame mode.
The frame modes of the local
port and opposite port need to
be consistent.
NOTE
Issue 03 (2013-02-20)

1564

Field
Value Range
Description

Mode
Null, Line Clock Mode,

System Clock Mode
Queries the encapsulation

mode of the clock signal on a
UNI port on the master side
of the CES service.
Default: Null
l Null: The clock signal is

not encapsulated in the
service packets.
l Line Clock Mode: The
clock frequency signal
extracted on a line port is
used as the time stamp,
which is encapsulated in
the RTP packet header
and transmitted to the
downstream.
l System Clock Mode:
The system frequency
signal is used as the time
stamp, which is
encapsulated in the RTP
packet header and
transmitted to the
downstream.
Poke
Queries the encapsulation

time stamp in the CES
service.
NOTE
Idle Timeslot Recovery

Value
Queries the recovery value of

an idle timeslot in the CES
service.
NOTE
Table 27-11 Parameters for an associated service
Issue 03 (2013-02-20)
Field
Value Range
Description
Service Type
For example, CES service
Displays the type of the

port.

1565

Field
Value Range
Description
Service ID
For example, 20
Displays the ID of the service

associated with the port.
When you select the value of
the service ID, the active
window changes to the
service management dialog
box of the corresponding
service type.
Service Name
For example, CES
Displays the name of the

port.
Used Resource
For example, 64K

Timeslot1-31
Displays the resource used by

the service associated with
the port.
27.4 Data Boards

The parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
27.4.1 SDH Parameters

The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.
J1 Byte
J1 is the path trace byte. Successive transmission of the J1 byte at the transmit end helps the
receive end learn that its connection with the specified transmit end is in the continuous
connection state.
When a J1 mismatch is detected at the receive end, the VC-3 path generates an LP_TIM_VC3
alarm and the VC-4 path generates an HP_TIM alarm.
When the J1 byte to be sent is set to the single-byte "" by default, the alarms are not reported.
NOTE
l In the case of the N1EFS4/MST4/EAS2, the J1 byte to be sent is set to " HuaWei SBS " by default.
In the case of the other boards, the J1 byte to be sent is set to the single-byte "" by default.
l In the case of the EMS4/EGS4, it is recommended that you set the J1 byte to be sent to " HuaWei
SBS ".
C2 Byte
and the payload property. The C2 byte to be sent must match the C2 byte to be received.
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1566

When a C2 mismatch is detected, the VC-3 path generates an LP_SLM_VC3 alarm and the
VC-4 path generates an HP_SLM alarm.
J2 Byte
When a J2 mismatch is detected, the VC-12 path generates an LP_TIM_VC12 alarm.
When the J2 byte is set to the single-byte "" by default, the alarms are not reported.
V5 Byte
generated accordingly.
When a V5 mismatch is detected at the receive end, the VC-12 path generates an LP_SLM_VC12
alarm.
Table 27-12 shows the relationship between the service type and the value of the V5 byte.
Issue 03 (2013-02-20)
Service Type
00
01
Asynchronous
02
Bit synchronization
03
04
05
O.181 test signal
06
VC-AIS
07
08
ATM mapping
09
HDLC/PPP mapping
0A
HDLC/LAPS mapping
0B

special mapping)
0C
GFP mapping
0D

1567

27.4.2 Ethernet Parameters

The Ethernet parameters that need to be set for the data boards include the working mode and
Maximum Frame Length.
27.4.2.1 Basic Attributes

This topic describes the parameters, such as the port attribute, port enabling status, and maximum
frame length, for configuring the basic attributes of an Ethernet port.
Table 27-13 lists the parameters for configuring the basic attributes of an Ethernet port.
Table 27-13 Parameters for configuring the basic attributes of an Ethernet port
Field
Value Range
Description
Port
PORTn
Displays all the available ports

on an Ethernet port. The letter
n indicates the number of the
PORT port.
Name
For example, PORT-1
Specifies the name of a PORT

port. The name can contain up
to 32 characters in English or
16 characters in Chinese.
Enable Port
Disabled, Enabled
"Enabled" indicates that this

port is used and services are
available. "Disabled" indicates
that the services on this port are
not processed. Hence, when
configuring a service, you need
to enable the port to be used.
Default value: Disabled
Click Enable Port (Ethernet

information.
Working Mode
Issue 03 (2013-02-20)
Auto-Negotiation, 10M HalfDuplex, 10M Full-Duplex,

100M Half-Duplex, 100M
Full-Duplex, 1000M HalfDuplex, 1000M Full-Duplex,
10GE Full-Duplex LAN,
10GE Full-Duplex WAN

Specifies the working mode of

the Ethernet port on a board.
This parameter determines the
maximum transmission rate
and communication mode of
the Ethernet port.
When setting this parameter,
you must ensure the working
modes of the interconnected
ports are the same. Otherwise,
the services are not available.
1568

Field
Value Range
Description
Max. Frame Length

The Max. Frame Length

parameter specifies the
maximum frame length that is
supported at an Ethernet port.
Click Max. Frame Length
(Ethernet Port Attribute) for
more information.
MAC Loopback
Non-Loopback, Inloop
The MAC Loopback

parameter specifies the MAC
loopback state at an Ethernet
port. Port loopback setting is
applied to locating faults only.
Click MAC Loopback
more information.
Default value: Non-Loopback
PHY Loopback
Non-Loopback, Inloop
Logic Type
SDH-OPPORT, SDH-EPORT
The PHY Loopback

parameter specifies the PHY
loopback state at an Ethernet
port. Port loopback setting is
applied to locating faults only.
Click PHY Loopback
more information.
Displays the logic type of port.
27.4.2.2 Flow Control

This topic describes the parameters, such as autonegotiation and non-autonegotiation, which are
used for configuring flow control function of an Ethernet port.
Table 27-14 lists the parameters for configuring flow control of an Ethernet port.
Table 27-14 Parameters for configuring flow control of an Ethernet port
Field
Value Range
Description
Port
PORTn

MAC ports on an Ethernet
board.
Specifies the PORT port. The
letter n indicates the number of
the PORT port.
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1569

Field
Value Range
Description
Non-Autonegotiation
Flow Control Mode
Disabled, Enable Symmetric

Flow Control, Send Only,
Receive Only
Default value: Disable
The Non-Autonegotiation
Flow Control Mode
specifies the flow control
mode adopted when an
Ethernet port works in nonauto-negotiation mode.
Click Non-Autonegotiation
Flow Control Mode (Ethernet
information.
Autonegotiation Flow
Control Mode

The Autonegotiation Flow

Control Mode (Ethernet
Port Attribute) specifies the
flow control mode adopted
when an Ethernet port works in
auto-negotiation mode.
The N1EMS4 and N1EGS4
boards do not support the
autonegotiation traffic control
attribute.
Click Autonegotiation Flow
Control Mode (Ethernet Port
Attribute) for more
information.
27.4.2.3 Network Attributes

This topic describes the parameters, such as port attribute and P port encapsulation format, which
are used for configuring network attributes of an Ethernet port.
Table 27-15 lists the parameters for configuring network attributes of an Ethernet port.
Table 27-15 Parameters for configuring network attributes of an Ethernet port
Issue 03 (2013-02-20)
Field
Value Range
Description
Port
PORTn or VCTRUNKn
Specifies the PORT or

VCTRUNK port. The letter n
indicates the number of the
port.

1570

Field
Value Range
Description
Port Attribute

The Port Attribute (Ethernet

Port) parameter specifies the
position of a port in the
network. Different port
attributes support different
packets.
MartinioE, stack VLAN
Encapsulation Format of P
Port (Network Attributes)
indicates that the board
supports receiving of data
packets in the MPLS
encapsulation format and
normal Ethernet data packets.
The port needs to process
different types of packets in
different ways, so you need to
set the port to a PE port or a P
port. The PE port is not
configured with the
encapsulation format, while
the P port is configured with
the encapsulation format. The
P port indicates a port for
connecting the equipment of
the network provider, so the P
port receives data packets in
the MPLS encapsulation
format. You can set the packet
encapsulation format of the P
port by running the
configuration command.
Encapsulation Format of P
Port
Default value: MartinioE
Click Port Attribute (Ethernet

Port) for more information.
This parameter is not

supported by a board that
supports the QinQ function.
Click Encapsulation Format of
P Port (Network Attributes) for
more information.
27.4.2.4 Advanced Attributes

This topic describes the parameters, such as the loop detection, loop port shutdown, and traffic
threshold (Mbit/s), which are used for configuring the advanced attributes of an Ethernet port.
Table 27-16 lists the parameters for configuring the advanced attributes of an Ethernet port.
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Table 27-16 Parameters for configuring the advanced attributes of an Ethernet port
Field
Value Range
Description
Port
PORTn or VCTRUNKn
Indicates the PORT or

VCTRUNK port. The letter
n indicates the number of
the PORT port.
Enabling Broadcast Packet

Suppression
Enabled, Disabled
The Enabling Broadcast

Packet Suppression
(Ethernet Interface
Attributes) parameter
specifies whether to enable
the function for a port to
suppress the broadcast
packets and to control the
traffic of the broadcast data
packets that enter the port.
If the broadcast packet
suppression function is
enabled, and if the
broadcast traffic exceeds
the specified threshold
value, the broadcast
packets that enter the port
are discarded.
Click Enabling Broadcast

Packet Suppression
(Ethernet Interface
Attributes) for more
information.
Broadcast Packet Suppression
Threshold
1-10
Default value: 3
The Broadcast Packet

Suppression Threshold
(Ethernet Interface
Attributes) parameter
allocates the specified
bandwidth to the broadcast
packets. The bandwidth is
allocated on the basis of the
traffic proportion at the
port. If the bandwidth
allocated to the broadcast
packets reaches the
specified threshold, the port
discards the broadcast data
packets that are received.
Click Broadcast Packet
Suppression Threshold
(Ethernet Interface
information.
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Field
Value Range
Description
Traffic Threshold(Mpbs)
0-100 (FE), 0-1000 (GE), in

step length of 1
The Traffic Threshold

(Mpbs) (External
Ethernet Port Attribute)
parameter specifies the data
flow threshold at external
physical ports.
Default value: 100 (FE),

1000 (GE)
Click Traffic Threshold

(Mpbs)(External Ethernet
information.
Port Traffic Threshold Time
Window(Min)
1-30
Default value: 0
The Port Traffic

Threshold Time Window
(Min) parameter specifies
the duration for a
VCTRUNK or an IP port to
monitor the traffic after the
zero traffic monitoring
function of the port is
enabled.
Click Port Traffic
Threshold Time Window
(Min) for more
information.
Loop Detection
Enabled, Disabled
The Loop Detection

function of reporting the
self-loop alarms after one
of the following loopback
cases is detected.
Click Loop Detection
for more information.
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Field
Value Range
Description
Loop Port Shutdown
Enabled, Disabled
The Loop Port Shutdown

parameter is set to disable
the self-loop port after a
self-loop port is detected if
the loop port shutdown
function is enabled. After
the self-loop port is shut
down, the self-loop port
only transmits or receives
the self-loop detection
packets rather than any
other packets. If the port is
not a self-loop port, it starts
to work again.
Default value: Enabled
Click Loop Port Shutdown

Zero-Flow Monitor
Enabled, Disabled
The Zero-Flow Monitor

parameter specifies
whether the traffic on a port
is monitored.
Click Zero-Flow Monitor
(Ethernet Interface
information.
Jumbo Frame Type
0 to 65535
Default value: 34928
The Jumbo Frame Type

value of the jumbo frame
type on an Ethernet port.
The jumbo frame indicates
the oversized Ethernet
frame, whose maximum
length is 65535 bytes. The
Ethernet service board
determines whether the
Ethernet frame is a jumbo
frame according to the
value of the jumbo frame
type.
Click Jumbo Frame Type
DNI Status
Issue 03 (2013-02-20)
Enabled, Disabled

Indicates whether to enable

the DNI status of the
VCTRUNK port on a data
board.
1574

27.4.2.5 TAG Attributes

Tag attributes are important attributes for configuring Ethernet services, including the
parameters such as the default VLAN ID, VLAN priority, ingress detection setting, and tag ID.
Table 27-17 lists the parameters for configuring the tag attributes of an Ethernet port.
Table 27-17 Parameters for configuring the tag attributes of an Ethernet port
Field
Value Range
Description
Port
PORTn or VCTRUNKn
Specifies the PORT or VCTRUNK

port. The letter n indicates the
number of the port.
Tag Identifier
Access, Tag Aware, Hybrid
The Tag Identifier parameter

indicates that the Ethernet port
supports IEEE 802.1Q Ethernet
packets that contain VLAN tags.
You can set three attributes to
differentiate the packets from each
other so that these packets can be
transmitted efficiently.
Default value: Tag Aware
Click Tag Identifier for more

information.
Default VLAN ID
1-4095
Default value: 1
Issue 03 (2013-02-20)
The Default VLAN ID (Ethernet

Port Attribute) parameter
specifies the default VLAN ID of
a port.
Click Default VLAN ID (Ethernet
information.
VLAN Priority
0-7
Default value: 0
The VLAN Priority (Ethernet

specifies the priority of the default
VLAN ID of a port. It indicates the
priority of the service quality.
Click VLAN Priority (Ethernet
information.
Entry Detection
Enabled, Disabled
Default value: Enabled
The Entry Detection (Ethernet

specifies whether to identify the
tag labels in the data packets.
Click Entry Detection (Ethernet
information.

1575

27.4.2.6 Encapsulation/Mapping
The equipment supports the setting of encapsulation and mapping protocols for Ethernet packets,
including the parameters such as mapping protocol, scrambling code, and CRC or not.
Table 27-18 lists the parameters for configuring the encapsulation and mapping of an Ethernet
port.
Table 27-18 Parameters for configuring the encapsulation and mapping of an Ethernet port
Field
Value Range
Description
Port
VCTRUNKn
Indicates the VCTRUNK

port. The letter n indicates the
number of the VCTRUNK
port.
Mapping Protocol

each other for different
boards and products. You can
click the hyperlink in the
The Mapping Protocol

mapping protocol of the
VCTRUNK port.
Click Mapping Protocol for
more information.
Scramble

The Scramble parameter

specifies whether to scramble
the payload area of the
encapsulation protocol and
the scramble mode.
You can set this parameter
only when the mapping
protocol is GFP, HDLC, or
LAPS.
Click Scramble for more
information.
Set Inverse Value for CRC
Yes, No
Default value: Yes
The Set Inverse Value for

CRC parameter specifies
whether to set an inverse
value for the CRC field of the
HDLC or LAPS protocol.
protocol is HDLC or LAPS.
Click Set Inverse Value for
CRC for more information.
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Field
Value Range
Description
Check Field Length

The Check Field Length

parameter specifies the length
of the CRC field of the
mapping protocol.
LAPS.
Click Check Field Length for
more information.
FCS Calculated Bit

Sequence

The FCS Calculated Bit

Sequence parameter
specifies the sequence of
storing the bits in the CRC
field of the mapping protocol.
LAPS.
Click FCS Calculated Bit
Sequence for more
information.
Extension Header Option

The Extension Header

Option parameter specifies
whether Mapping Protocol
of the GFP protocol supports
the extension header.
protocol is GFP.
Click Extension Header
Option for more information.
27.4.2.7 Bound Paths

This topic describes the parameters, such as available resources, available timeslots, and service
direction, which are used for binding a path with an Ethernet port.
NOTE
The configured cross-connections must correspond to the bound bandwidth timeslots. Otherwise, the
services are unavailable.
Table 27-19 lists the parameters that are used for binding a path.
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Table 27-19 Parameters for binding paths

Field
Value Range
Description
Configurable Ports
For example, VCTRUNKn

VCTRUNK ports on the
board.
Available Resources
For example, VC4-1

VC-4s.
Available Timeslots
For example, VC12-1

timeslots.
VCTRUNK Port
VCTRUNKn
Displays the number (n) of

the VCTRUNK port.
Level
For example, VC12-xv
Specifies the level of a path

that is bound with the
VCTRUNK.
Service Direction
Bidirectional, Uplink,
Downlink
Specifies the direction of the

Ethernet service.
Default value: Bidirectional

Bound Path
For example, VC4-1-VC12

(1-3)
Specifies the number of the

path to be bound, for
example, VC4-1-VC12(1-3).
Number of Bound Paths
Displays the number of

VCTRUNKs to be bound.
The Used Channel
For example, VC4-1-VC12

(1)
Displays the actually used

channel.
Activation Status
Active, Deactive
Displays whether the path is

active.
Display in Combination
If you select Display in

Combination, the bound
paths are displayed in a
centralized manner.
Otherwise, the bound paths
are displayed in a distributed
manner.
27.4.3 ATM Parameters

The ATM parameters that need to be set for the ATM boards include the port type and traffic
type.
Port Type
The port types include NNI and UNI. The default port type is UNI.
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Traffic Type
The traffic type must meet the requirements of the port.
Service Type
Five service types are available, namely, CBR, rt-VBR, nrt-VBR, UBR, and UBR+.
Peak Cell Rate

Set the peak cell rate of the ATM services. This parameter must be set for each service type.
Sustainable Cell Rate

Set the sustainable cell rate of the ATM services. In the case of the rt-VBR and nrt-VBR services,
set this parameter.
MBS
Set the MBS of the ATM services. In the case of the rt-VBR and nrt-VBR services, set this
parameter.
CDVT
Set the CDVT of the ATM services. In the case of the CBR, rt-VBR, and UBR services, set this
parameter.
27.5 SDH Processing Boards

The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.
J0 Byte
The J0 byte is used to transmit repetitively a section access point identifier so that a section
receiver can verify its continued connection to the intended transmitter. It is recommended that
you set the J0 byte to the default value, namely, single-byte "Disabled".
J1 Byte
J1 is the higher order path trace byte. This byte is used to transmit repetitively a path access
intended transmitter. When a J1 mismatch is detected at the receive end, the corresponding VC-4
path generates an HP_TIM alarm.
NOTE
Generally, the J1 byte retains the default. However, when Huawei equipment is interconnected with thirdparty equipment, the J1 byte must be set to the same value at both ends.
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J2 Byte
J2 is the lower order path trace byte. This byte is used to transmit repetitively a low order path
access point identifier so that a path receiving terminal can verify its continued connection to
the intended transmitter.
To set and query the J2 byte to be received, enable the lower order monitoring function.
NOTE
In the case of the SDH processing boards, the J2 byte to be sent cannot be set.
C2 Byte
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table 27-20 shows the relationship between the service type and the value of the C2 byte.
Table 27-20 relationship between the service type and the value of the C2 byte
Service Type
Value of the C2 Byte (Hexadecimal)
TUG structure
02
34M/45M into C-3
04
140M into C-4
12
Unequipped
00
27.6 PDH Boards

The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.
J1 Byte
J1 is the path trace byte. This byte is used to transmit repetitively a path access point identifier
so that a path receiving terminal can verify its continued connection to the intended transmitter.
When a J1 mismatch is detected at the receive end, the corresponding VC-4 path generates an
HP_TIM alarm.
The J1 byte is set to the single-byte "" by default.
NOTE
The J1 byte was set to " HuaWei SBS
" by default.
C2 Byte
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
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1580

a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table 27-21 shows the relationship between the service type and the value of the C2 byte.
Table 27-21 relationship between the service type and the value of the C2 byte
Service Type
Value of the C2 Byte (Hexadecimal)
TUG structure
02
34M/45M into C-3
04
140M into C-4
12
Unequipped
00
J2 Byte
V5 Byte
generated accordingly. Table 27-22 shows the relationship between the service type and the
value of the V5 byte.
Issue 03 (2013-02-20)
Service Type
00
01
Asynchronous
02
Bit synchronization
03
04
05
O.181 test signal
06
VC-AIS
07
08
ATM mapping
09
HDLC/PPP mapping
0A

1581

Service Type
HDLC/LAPS mapping
0B

special mapping)
0C
GFP mapping
0D
Equipping Indication
When a service channel only carries the service and does not process the service, select
Unequipped or Supervisory-Unequipped.
When a service channel carries the service and also processes the service, select EquippedUnspecific Payload.
Tributary Loopback
The tributary loopback function is used to locate faults in the service channels.
The tributary loopback is also a diagnosis function. When the tributary loopback is performed,
related services are interrupted.
Path Service Type

This parameter is set to specify service type for the channel.
l
Select E1 or T1 for E1/T1 processing boards according to the actual service type in the
channel.
Select E3 or T3 for E3/T3 processing boards according to the actual service type in the
channel.
Serial Port Protocol Mode

For the DX1, select the protocol mode of the N x 64 kbit/s signals. The protocol mode includes
V.35, V.24, X.21, RS449, RS530 and RS530A.
DDN Clock Source Management

The timing scheme and working clock source can be set for the DX1.
l
Set the timing scheme of the DDN channels 1012 and 1416 to the DCE internal scheme,
DCE slave scheme or DTE external scheme.
Set the timing scheme of the DDN channels 9 and 13 to the DCE internal scheme, DCE
slave scheme, DTE external scheme, DTE internal scheme, DTE slave scheme or DCE
external scheme. By default, the timing scheme is the DCE internal scheme for channels 9
and 13 is the DCE internal scheme.
27.7 WDM Boards

The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
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1582

shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.
Path Use Status

Item
Description
Parameter description
Used to set the path use status
Parameter values
Used and Unused
Parameter value description
Default value: Used
Recommended value
Used
Application scenarios
In configuration, commissioning, and

maintenance stages
Impact on the system
When the Path Use Status of an optical interface

is set to Unused, service alarms at this interface
are suppressed, which disables the automatic laser
turn on function.
Relevant boards
LWX
Configuration requirements
When the channel is not required, its Path Use

Status can be set to Unused. In this case, a
command should be issued to shut down the laser
of this path; otherwise, an alarm indicates that the
laser is forcibly turned on is reported.
Optical Interface Loopback

Item
Description
Used to set the loopback mode of the current

optical interface.
Parameter values
Non-Loopback, Outloop, and Inloop

Non-Loopback: indicates that the equipment is in
normal state. Optical interface loopback is not
required when the equipment normally operates.
Inloop: indicates a mode that signals to be output
from the output interface of the local-end
equipment are looped back to the signal input
interface of this equipment. Inloop is used to test
the signal processing on the board.
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1583

Item
Description
Outloop: indicates a mode that unprocessed
signals accessed to the local-end equipment are
directly looped back to the corresponding output
interface without the signal structure changed.
Outloop is used to test connections between fiber
lines and connectors.
Recommended value
Non-Loopback
In commissioning and maintenance stages
When the loopback mode is set to Inloop or

Outloop, services are interrupted.
Relevant boards
RPC01 and RPC02
None
Item
Description
Used to set the type of services at a client-side

optical interface.
Parameter values
LWX: GE, FE, STM-1, STM-16, OC-3, OC-12,

OC-48, FC-100, FC-200 FICON, FICON
Express, DVB-ASI DVB-SDI, and ESCON
Default value: Any
Recommended value
None

maintenance stages
None
Relevant boards
LWX
The type of actually accessed services must be the

same as the type of configured services.
Otherwise, the services are not available.
Service Type
Client Service Bearer Rate (M)
Issue 03 (2013-02-20)
Item
Description
Used to set the bearer rate of client-side services.
Parameter values(M)
16 to 2500

1584

Item
Description
Parameter value
description
The bearer rate of client-side services can be set only when the
client-side services are of Any type. The set value should equal
to the maximum rate of actually accessed services.
Recommended value
None
In configuration, commissioning, and maintenance stages
A SPEED_OVER alarm is reported when the rate of actually

accessed services exceeds the set value.
Relevant boards
LWX
Configuration
requirements (the set
value of bearer rate
should be the same as the
rate of actually accessed
services)
Actually
accessed
services
Set value
(M)
Actually
accessed
services
Set value (M)
STM-1
155.5
GE
1250
STM-4
622
FE
125
STM-16
2488.3
FC100
1062
OC3
155.5
FC200
2124
OC12
622
FICON
1062
OC48
2488.3
FICON
Express
2124
HDTV
270
ESCON
200
DVB-SDI
270
FDDI
125
DVB-ASI
270
Laser Status
Issue 03 (2013-02-20)
Item
Description
Used to set the laser Open/Close status.
Parameter values
Open and Close

Default value: Open
Open: The laser is turned on to start transmitting

services.
Close: The laser is turned off to stop service
transmitting.
Recommended value
Open

maintenance stages

1585

Item
Description
When the laser is set to Close, services are

interrupted.
Relevant boards
LWX
When an optical interface is unused or is not

connected to a fiber, the laser at this interface
should be set to Open.
Automatic Laser Shutdown

Item
Description
Used to set whether to enable automatic laser

shutdown (ALS) of the downstream laser of the
local board in the case of loss of received signals.
If ALS is enabled, when the received signals are
lost, the laser is automatically shut down and stops
transmitting signals. ALS prolongs the service life
of a laser and avoids personal injury from the laser.
Parameter values
Enabled and Disabled
By default, ALS of optical interfaces on client

sides is set to Enabled and ALS of optical
interfaces on WDM sides is set to Disabled.
Recommended value
ALS of optical interfaces on client sides is set to

Enabled and ALS of optical interfaces on WDM
sides is set to Disabled.
In configuration and maintenance stages
None
Relevant boards
LWX
If the optical interface on a WDM side does not

use the ESC as the network management channel
or no fiber is connected, you can set ALS of the
optical interface to Enabled to prolong the service
life of the laser.
Current Bearer Rate (M)
Issue 03 (2013-02-20)
Item
Description
Used to query the current bearer rate of client-side

services.

1586

Item
Description
Parameter values
Can only be queried
None
Recommended value
None

maintenance stages
None
Relevant boards
LWX
None
Actual Wavelength No./Wavelength (nm)/Frequency (THz)

Item
Description
Used to query the operating wavelength at the

WDM-side optical interface of a board.
Parameter values
Can only be queried
None
Recommended value
None

maintenance stages
None
Relevant boards
LWX
None
Actual Band Type
Issue 03 (2013-02-20)
Item
Description
Used to query the band type.
Parameter values
Can only be queried
None
Recommended value
None
None

1587

Item
Description
Relevant boards
LWX
None
Configure Wavelength No./Wavelength (nm)/Frequency (THz)

Item
Description
Used to configure the operating wavelength at the

WDM-side optical interface of a board.
Parameter values
C-band wavelength spacing: 100G

(192.100-196.00 THz)
CWDM-band wavelength spacing: 20 nm
(1271-1611 nm)
The operating wavelength of a fixed-wavelength

OTU should be set to the actual wavelength of the
OTU. The operating wavelength of a tunablewavelength OTU should be set according to the
network wavelength planning.
Recommended value
None
In configuration stage
l The same wavelength should be used for a

service in the receive and transmit directions.
l If a service travels through multiple
regenerating stations, it is recommended that
these regenerating sections use the same
wavelength.
l It is recommended that the active and standby
channels use the same wavelength when the
inter-board channel protection or client-side
path protection is adopted.
Issue 03 (2013-02-20)
Relevant boards
LWX
The configured logic wavelength must be the same

as the actual physical wavelength. Otherwise, a
CFGDATA_OUTRANGE alarm is reported. In
the case of tunable optical modules, issuing the
captioned command directly changes their
physical wavelengths (but does not change the
band). In the case of non-tunable optical modules,
issuing this command changes their logic
wavelengths only.

1588

Configure Band Type

Item
Description
Used to configure the band type.
Parameter values(dBm)
C and CWDM
None
Recommended value
None

maintenance stages
None
Relevant boards
LWX
The configured logic band must be the same as the

actual physical band. Otherwise, a
CFGDATA_OUTRANGE alarm is reported.
SD Trigger Condition
Item
Description
Used to configure the trigger condition to perform

SD switching on the board.
Parameter values(dBm)
B1_SD, OTUk_DEG, ODUk_PM_DEG, and

None
B1_SD: Regeneration section (B1) signal degrade

OTUk_DEG: OTUk signal degrade
ODUk_PM_DEG: ODUk_PM signal degrade
None: No condition is configured for SD
switching.
Issue 03 (2013-02-20)
Recommended value
Set the value to None.
When the B1_SD, OTUk_DEG, or

ODUk_PM_DEG alarm occurs, the protection
group might be triggered to perform protection
switching.
Relevant boards
LWX
Set the value to B1_SD, OTUk_DEG, or

ODUk_PM_DEG if the protection mechanism
needs such a trigger condition.

1589

27.8 Cross-Connect and Timing Units

The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.
Table 27-23 lists the parameters that need to be set for the cross-connect and timing units.
Table 27-23 Parameters that need to be set for the cross-connect and timing units
Domain
Parameter
Value
Configuration
Clock
Synchroni
zation
Status
NE Name
Displays the name of an NE.
NE Clock
Working Mode
Tracing Mode,
Holdover Mode,
Free-Run Mode
This field shows the current working

mode of the clock function board on
the NE. This field is read-only.
Tracing Mode: It is the normal
working mode and indicates that the
clock is synchronized with the input
reference clock source under the
actual service conditions.
Holdover Mode: Indicates that the
clock works with the stored
frequency information as the timing
reference after all the timing
references are lost.
Free-Run Mode: Indicates that the
clock works through the internal
oscillator.
Issue 03 (2013-02-20)
S1 Byte
Synchronization
Quality
Information
For example: NA
Displays the S1 byte synchronous

quality information in the clock
function on the current NE. For query
only.
S1 Byte Clock
Synchronous
Source
For example: NA
Displays the trace source of the

current NE clock. For query only.
This field displays no information
until the S1 byte (clock protection
function) is activated. Similarly, this
field displays NA until you press the
Query button, and then it displays the
related information.

1590

Domain
Clock
source
priority
Clock
source
switching
condition
Issue 03 (2013-02-20)
Parameter
Value
Configuration
Synchronous
Source
For example:
External Clock
Source 1
Displays the trace source of the

current NE clock. For query only.
Data Output
Method in
Holdover Mode
Normal Data
Output Mode,
Keep the Latest
Data
Default: Normal
Data Output Mode
Displays the data output method.
Clock source
The clock sources currently used by

the NE are listed in sequence. The top
clock source is of the highest priority.
External clock
source mode
2 MHz and 2 Mbit/

s
Select the mode only for the input

external clock source.
Synchronous
status byte
Sa4, Sa5, Sa6,

Sa7, and Sa8
Select the synchronous status byte

only for the input external clock
source that is in 2 Mbit/s mode.
AlS alarm
generated
Selected and not

selected
This parameter specifies the

condition for determining the clock
source switching. When an AIS alarm
occurs on an NE, the NE determines
whether to perform the clock source
switching.
B1 BER
thresholdcrossing
generated
Selected and not

selected

condition for determining the clock
source switching. When the B1 BER
on an NE crosses the threshold, the
NE determines whether to perform
the clock source switching.
RLOS, RLOF and

OOF alarms
generated
Selected
When an R_LOS, R_LOF, or OOF

alarm occurs on an NE, the NE
considers that the corresponding
clock source fails.
Normally, the synchronous source

should be a clock source with the
highest priority among the clock
stratums. If the synchronous source
cannot be traced, try to trace a clock
source with a lower priority level
according to the sequence of the clock
stratums.

1591

Issue 03 (2013-02-20)
Domain
Parameter
Value
Configuration
Phaselocked
source
output by
external
clock
External clock
output mode
when 2M output
synchronous
source is invalid
Synchronization
quality
unavailable,
output AIS, and
shut off
This parameter is used to set the

operation to be performed by the
system when the output of the
synchronous clock (that is, 2M phaselocked source) fails.
Default value:
Shut off
Output mode of
external clock
source 1
2 Mbit/s and 2
MHz
The NE provides two external clock

outputs. This parameter is used to set
the output mode for external clock
source 1.
Output mode of
external clock
source 2
2 Mbit/s and 2
MHz
The NE provides two external clock

outputs. This parameter is used to set
the output mode for external clock
source 2.
Clock source
threshold
No threshold
value, G.813 SDH
equipment timing
source (SETS)
signal, G.812
local clock signal,
G.812 transit
clock signal, G.
811 clock signal,
and unknown
Set a threshold for the 2M

synchronous output sources. The
threshold is set for the clock
protection function of the S1 byte.
The NE clock system uses this
threshold as the basis for ensuring the
quality of the output clock. If a clock
is of a quality higher than the
threshold, the clock system transmits
clock signals.
Clock
source
switching
Lock status
Lockout and
unlock
This parameter is used to set whether

the clock source switching is allowed.
Switching
operation
Forced switching,
manual switching,
and clear
switching

switching operation to be performed
on the clock source.
Clock
source
reversion
parameter
Higher priority
clock source
reversion mode
Auto-revertive
and non-revertive
When the clock source of a higher

priority degrades, the NE
automatically switches to the clock
source of a lower priority. When this
parameter is set to "Auto-revertive",
the NE automatically switches back
to the clock source of a higher priority
when the clock source of the higher
priority is restored. When this
parameter is set to "Non-revertive",
the NE does not automatically switch
back to the clock source of a higher
priority when the clock source of the
higher priority is restored.

1592

Domain
Parameter
Value
Configuration
Clock source
WTR time
0 to 12 minutes

period from the time when the
recovery of the clock is detected to
the time when the clock selector
responds. This setting prevents
repeated switching from occurring in
the case of unstable signals.
Affiliated subnet
Default value: 0

subnet ID.
Protection status
Start extended
SSM protocol,
start standard
SSM protocol, and
stop SSM protocol
This parameter specifies whether to

start up the SSM protocol.
Clock source ID
1 to 15
Huawei equipment uses the first four

bits of the S1 byte to identify the
clock source. Hence, the subnet clock
source ID is the four bits.
SSM
output
control
Line port
All the line ports

of the current NE
This parameter displays the line ports

that can be controlled.
Control status
Enabled and
disabled
This parameter specifies whether the

line port allows the output of the
quality information carried by the S1
byte. Generally, set this parameter to
"Disabled" at edges of a network to
prevent impact on the other
equipment.
Clock
quality
Configuration
quality
Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction
Default value:
Automatic
extraction
This parameter is used to set the clock

quality. Specify the clock quality of
the clock source listed in the priority
table. If an option other than
"Automatic extraction" is selected,
the NE considers the specified clock
quality (other than the actual clock
quality) as the criteria.
Clock
subnet
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1593

Domain
Clock ID
status
Parameter
Value
Configuration
Clock quality
Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction
The clock source quality information

actually received by the NE is
extracted by the NE from the S1 byte
of each clock source. When the
customer queries the actual clock
quality and the NE successfully
returns the result, the quality can be
displayed. Otherwise, it displays "no
information".
Line port
All the line ports

of the current NE
This parameter displays the line ports

that can be configured with the clock
ID.
Enabled status
Enabled and
disabled
Default value:
Enabled
This parameter specifies whether to

enable the setting of the clock ID.
27.9 Optical Amplifier Boards

The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.
Laser Status
Item
Description
Used to set the laser Open/Close status.
Parameter values
Open and Close

Default value of the OBU1: Open
Default value of the RPC01/RPC02: Close
Issue 03 (2013-02-20)
Recommended value
Close

maintenance stages
When the laser is set to Close, services are

interrupted.

1594

Item
Description
Relevant boards
OBU1, RPC01, and RPC02
When services are normal, the laser of the optical

amplifying unit should be set to Open.
Board Work Type

Item
Description
Used to query and set the Board Work Type.
Parameter values
C, C+L, and L
None
Recommended value

maintenance stages
None
Relevant boards
RPC01 and RPC02
None
Configure Band
Issue 03 (2013-02-20)
Item
Description
Used to configure the type of the working band of

a board.
Parameter values
Supports only C band.
Recommended value
None

maintenance stages
None
Relevant boards
None

1595

Configure Working Band Parity

Item
Description
Selects the required parity of the working band.
Parameter values
All, Even, and Odd
All: All 192.10 THz to 196.05 THz odd and even

wavelengths at 50 GHz channel spacing in C band.
There are 80 wavelengths in total. It is applicable
for the OBU1, RPC01, and PRC02 boards.
Even: All 192.10 THz to 196.00 THz even
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.
Odd: All 192.15 THz to 196.05 THz odd
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.
Recommended value
Corresponding wavelengths are used according to

different requirements.
None
Relevant boards
When configuring the parity of wavelengths,

make sure that the parity configured is consistent
with the parity of the actual working wavelengths.
Item
Description
Used to query the actual working band of the

board.
Parameter values
Can only be queried
None
Recommended value
None
None
Relevant boards
OBU1
None
Actual Band
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1596

Actual Working Band Parity

Item
Description
Used to query the parity of the actual working band

of the board.
Parameter values
Can only be queried
None
Recommended value
None
None
Relevant boards
None
Threshold of Input Power Loss (dBm)

Item
Description
Indicates the lower threshold of input optical

power loss (an MUT_LOS alarm is reported).
Parameter values
Can only be queried
The default value varies with the boards and

subjects to the on-site queried result.
Recommended value
None
None
Relevant boards
OBU1
None
Item
Description
Used to query the optical power gain of the current

optical amplifying unit.
Parameter values
Can only be queried
None
Gain (dB)
Issue 03 (2013-02-20)

1597

Item
Description
Recommended value
None

maintenance stages
None
Relevant boards
OBU1
Normally, the queried result should range from the

nominal gain minus 2.5 dB to the nominal gain
plus 2.5 dB.
Nominal Gain Upper Threshold (dB)

Item
Description
Used to query the nominal gain upper threshold.
Parameter values
Can only be queried
None
Recommended value
None
None
Relevant boards
OBU1
None
Nominal Gain Lower Threshold (dB)
Issue 03 (2013-02-20)
Item
Description
Used to query the nominal gain lower threshold.
Parameter values
Can only be queried
None
Recommended value
None
None
Relevant boards
OBU1
None

1598

Rated Optical Power (dBm)

Item
Description
Used to set and query the single-wavelength rated

optical power as the reference value for automatic
optical power adjustment.
Parameter values (dBm)
30.0 to 30.0
Default value at the input optical interface: 19

dBm
Default value at the output optical interface: 4
dBm
Recommended value
OBUC01: input interface: 20 dBm; output

interface: 0 dBm
OBUC03: input interface: 19 dBm; output
interface: 4 dBm

maintenance stages
None
Relevant boards
OBU1
The rated input and output optical power should

be configured by referring to the actual
configurable input and output range of the optical
amplifying unit and should be the same as the
input and output values measured when the
optical amplifying unit operates normally.
Issue 03 (2013-02-20)
Item
Description
Used to set or query the output optical power of

an optical amplifier board.
5 to 30.0 (continuously tunable)
Normally, the fixed pump optical power of the

RPC board should be larger than 23 dBm. The
value is related to the system specifications.
Recommended value
None

maintenance stages

1599

Item
Description
Fixed Pump Optical Power (dBm) must be set

within a range between Min. Fixed Pump
Optical Power (dBm) and Max. Fixed Pump
Optical Power (dBm). If the fixed pump optical
power value is beyond the range, the board might
work abnormally.
Relevant boards
RPC01 and RPC02
None

Item
Description
Used to query the minimum pump optical power

that an optical amplifier board can fix. If the fixed
pump optical power value is smaller than the
minimum value, the board might work
abnormally.
5 to 30.0
None
Recommended value
Default value: 20 dBm

maintenance stages
If the configured value of Fixed Pump Optical

Power (dBm) is smaller than the value of Min.
Fixed Pump Optical Power (dBm), the board
might work abnormally.
Relevant boards
RPC01 and RPC02
None
Issue 03 (2013-02-20)
Item
Description
Used to query the maximum pump optical power

that an optical amplifier board can fix. If the fixed
pump optical power value is larger than the
maximum value, the board might work
abnormally.
5 to 30.0

1600

Issue 03 (2013-02-20)
Item
Description
None
Recommended value
Default value: 26 dBm

maintenance stages
If the configured value of Fixed Pump Optical

Power (dBm) is larger than the value of Max.
Fixed Pump Optical Power (dBm), the board
might work abnormally.
Relevant boards
RPC01 and RPC02
None

1601

28 Task Collection
28
Task Collection
About This Chapter

This topic describes the operation tasks to be performed during board commissioning and board
configuration.
28.1 Querying the Protection Subnet
You can know the network protection schemes by querying the protection subnet to which an
NE belongs. Then, you can configure services for the board according to the protection schemes.
28.2 Troubleshooting Service Unavailability
In certain cases, the services become unavailable after the cross-connections related to the
services are configured. This topic describes the methods of troubleshooting service
unavailability.
28.3 Troubleshooting the Clock Tracing Failure
In many cases, the equipment still fails to trace the clock after you configure the clock source
priority list. To locate the clock tracing problem, you need to check all the stations that the clock
travels along the clock tracing direction and from the source station to the sink station.
28.4 Configuring the F&f Debugging Serial Port and OAM NM Port
The OAM NM port provides the network management function and is used for remote
maintenance. The F&f debugging serial port is used for managing the external equipment such
as the COA, TDA, and DCU. The F&f debugging serial port supports a maximum transmission
distance of 15 m. The AUX board provides the ports for connecting the F&f debugging serial
port and OAM NM port.
28.5 Testing the Frequency Accuracy of the Free-Run Clock
The frequency accuracy indicates the deviation of the actual clock frequency from the nominal
clock frequency, which is a highly stable frequency. Generally, the frequency accuracy is
represented by the relative frequency deviation.
28.6 Testing the Clock Holdover Accuracy
The SDH equipment supports the clock holdover function. That is, the SDH equipment can retain
the clock accuracy of 0.37 ppm or a higher clock accuracy (at a temperature from 20C to 30
C) relative to the clock frequency at the service interruption moment, within 24 hours after the
external clock source is interrupted.
28.7 Checking Board Parameters
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28 Task Collection
To learn about board parameter status, you can check board parameters. Before actual
configuration operations in networking, you need to check board parameters, to make sure that
the board parameter status meets the requirements of actual networking.
28.8 Testing the SAN Service Channel
When a network carries services, you need to check the availability of the service channels.
28.9 Testing the SDI Service Channel
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28 Task Collection
28.1 Querying the Protection Subnet

You can know the network protection schemes by querying the protection subnet to which an
NE belongs. Then, you can configure services for the board according to the protection schemes.
Prerequisites
l
You must be an NM user with "NE operator" authority or higher.
The SDH board must be created.
Procedure
Step 1 Choose Protection Subnet > SDH Protection Subnet Maintenance from the Main Menu to
display the Protection Subnet Attributes dialog box.
Step 2 In Protection Subnet Attributes, the left pane displays the protection subnet to which the NE
belongs, and the right pane displays the attribute information of the protection subnet.
----End
28.2 Troubleshooting Service Unavailability

In certain cases, the services become unavailable after the cross-connections related to the
services are configured. This topic describes the methods of troubleshooting service
unavailability.
Context
After the cross-connections are configured, the services are unavailable.
Impacts on the System

The services are unavailable.
Possible Causes
l
Cause 1: The type of the logical board is different from the type of the physical board.
Cause 2: The services are configured incorrectly.
Cause 3: The other boards on the NE do not operate normally.
Tools, Instruments, and Materials

l
U2000
Procedure
Step 1 Ensure that the type of the logical board configured on the U2000 is the same as the type of the
physical board. If the type of the logical board configured on the U2000 is different from the
type of the physical board, delete the current logical board and then add the correct logical board.
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28 Task Collection
For the operations of deleting a logical board, see Deleting Boards. For the operations of adding
a logical board, see Adding Boards.
Step 2 Ensure that the cross-connect services are configured correctly and that the cross-connect
services are activated. If the cross-connect services are configured correctly, modify the
configuration of the cross-connect services. For details, see Modifying the Service Configuration
Data.
Step 3 Check whether all the boards on the NE operate normally and whether any critical or major
alarms are generated on the boards.
Step 4 Switch the services from the working cross-connect board to the protection cross-connect board.
If the services are restored after the switching, replace the working cross-connect board. If the
services are still unavailable after the switching, perform Step 5.
Step 5 Contact Huawei technical support personnel.
----End
28.3 Troubleshooting the Clock Tracing Failure

In many cases, the equipment still fails to trace the clock after you configure the clock source
priority list. To locate the clock tracing problem, you need to check all the stations that the clock
travels along the clock tracing direction and from the source station to the sink station.
Prerequisites
l
The NE must be connected to the NMS through an NMS port or using a DCC
communication management device.
The U2000 software must be installed on the PC and the PC must be started.
Procedure
Step 1 Ensure that the clock source priority list is configured correctly.
If the problems are detected in Steps 113, correct the configurations according to the operations
in Configuring Clocks.
Step 2 Query the input mode of the external clock and ensure that the input mode of the external clock
source is set correctly. That is, ensure that the input mode of the external clock source is set to
the 2 MHz or 2 Mbit/s.
Step 3 Ensure that the SSM mode is enabled.
Step 4 Ensure that the clock source to be traced is available.
Step 5 If the line source is unavailable, check whether the LOS or LOF alarm occurs on the
corresponding optical port. If the LOS or LOF alarm occurs on the corresponding optical port,
clear the alarm. If the LOS or LOF alarm does not occur on the corresponding optical port, run
the test command to check whether the inter-board communication is normal. If the inter-board
communication is not normal, it indicates that the equipment fails to trace the clock due to the
abnormal inter-board communication.
Step 6 Check whether the external clock is derived from the BITS or other NEs. If the source of the
external clock is incorrect, set the correct external clock source.
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28 Task Collection
Step 7 Check whether the clock source is locked. If the clock source is locked, unlock the clock source.
Step 8 Check whether the switching mode of the clock source is non-revertive on the U2000. If the
switching mode of the clock source is non-revertive, change the switching mode to revertive.
Step 9 Check whether any forced switching or manual switching is performed for other clock sources.
If a forced switching or manual switching is performed for other clock sources, clear the
switching.
Step 10 Check whether the S1 byte that carries the clock source signal is DNU. If the S1 byte that carries
the clock source signal is DNU, go to step 13.
Step 11 Check whether the S1 byte is correct. If the S1 byte is incorrect, set the correct S1 byte.
Step 12 If the S1 byte is correct, check whether the external clock is derived from the BITS or other NEs.
If the source of the external clock is incorrect, set the correct external clock source. Check
whether the clock source is locked. If the clock source is locked, unlock the clock source. Check
whether any forced switching or manual switching is performed for other clock sources. If a
forced switching or manual switching is performed for other clock sources, clear the switching.
Step 13 In the case of the line clock source, check whether the timeslot for receiving the S1 byte is any
of sa4sa8. If the timeslot for receiving the S1 byte is not any of sa4sa8, set the timeslot for
receiving the S1 byte to any of sa4sa8.
----End
28.4 Configuring the F&f Debugging Serial Port and OAM

NM Port
The OAM NM port provides the network management function and is used for remote
maintenance. The F&f debugging serial port is used for managing the external equipment such
as the COA, TDA, and DCU. The F&f debugging serial port supports a maximum transmission
distance of 15 m. The AUX board provides the ports for connecting the F&f debugging serial
port and OAM NM port.
Prerequisites
l
The PC must be connected to the equipment through a network cable. The PC must be
started.
The U2000 must be started.
Procedure
Step 1 Open the NE whose F&f debugging serial port and OAM NM port need to be configured on the
U2000.
Step 2 Choose Communication > Access Control from the Function Tree. See Figure 28-1.
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28 Task Collection
Figure 28-1 Configuring the F&f debugging serial port and OAM NM port
Step 3 Configure the OAM NM port. Select Enable OAM Access. This operation is optional.
Step 4 Configure the F&f debugging serial port. Select Enable Serial Port Access and set the baud
rate to 38400.
Step 5 Click Apply so that the settings can take effect.
----End
28.5 Testing the Frequency Accuracy of the Free-Run Clock

The frequency accuracy indicates the deviation of the actual clock frequency from the nominal
clock frequency, which is a highly stable frequency. Generally, the frequency accuracy is
represented by the relative frequency deviation.
Tools and Instruments

Frequency meter
Test Connection Diagram

Connect the frequency meter to the NE as shown in Figure 28-2.
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28 Task Collection
Figure 28-2 Connection for testing the frequency accuracy of the free-run clock
2 MHz
Standard clock
Equipment
Frequency meter
Procedure
Step 1 Use the frequency meter to measure the frequency of the standard clock.
Step 2 Set the clock to be in free-run mode. Set the output mode of the external clock to the 2 MHz or
2 Mbit/s mode. Connect the output clock signal to the frequency meter for measurement.
Step 3 Use the frequency meter to measure the frequency of the free-run clock. Compare the actual
frequency of the free-run clock with the frequency of the standard clock to calculate the
frequency accuracy of the free-run clock.
Step 4 You can calculate the frequency deviation and determine the frequency accuracy only after you
check the clock frequencies at different time periods within several months and perform
frequency tests under different conditions. In addition, you need to perform the frequency tests
at appropriate time periods based on the actual situations.
----End
28.6 Testing the Clock Holdover Accuracy

The SDH equipment supports the clock holdover function. That is, the SDH equipment can retain
the clock accuracy of 0.37 ppm or a higher clock accuracy (at a temperature from 20C to 30
C) relative to the clock frequency at the service interruption moment, within 24 hours after the
external clock source is interrupted.
Prerequisites
The following operations must be performed:
l
The U2000 LCT must be started.
You must log in to the NE.
Tools and Instruments

Frequency meter, SDH analyzer, and U2000 LCT
Test Connection Diagram

Connect the testing tools to the NE as shown in Figure 28-3.
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28 Task Collection
Figure 28-3 Connection for testing the clock holdover accuracy

Standard clock
Frequency
meter
Equipment
SDH
analyzer
Procedure
Step 1 Turn on Switch K. Configure the standard clock source for the OptiX OSN 3500 on the
U2000 LCT.
Step 2 After performing all the preparations before locking the clock source, record the frequency.
Then, the equipment locks the standard clock source for 24 hours. Turn off Switch K. Then, the
clock of the OptiX OSN 3500 changes to holdover mode. Then, record the clock frequency every
other hour.
Step 3 Check the records in 24 hours. The test requires that the frequency stability of the standard clock
should be higher than 1x1010/day.
----End
28.7 Checking Board Parameters

To learn about board parameter status, you can check board parameters. Before actual
configuration operations in networking, you need to check board parameters, to make sure that
the board parameter status meets the requirements of actual networking.
Procedure
Step 1 Check SDH board parameters. For the SDH board parameters, see Table 28-1.
Table 28-1 SDH board parameters
Boar
d
Type
Paramete
r
MSP
sharing
SDH
Issue 03 (2013-02-20)
Laser
Switch
Navigation Path
Application Scenario
1. In the NE
Explorer,
select a board.
2. Choose
Configuratio
n > SDH
Interface from
the Function
Tree.
When configuring MSP shared services on an

optical interface of a board, enable this
parameter.
When configuring services on an optical
interface of a board, enable this parameter.

1609

Boar
d
Type
Paramete
r
Optical
(Electrical
)Interface
Loopback
28 Task Collection
Navigation Path
3. Click
By
Board/Port
(channel) and
select
Port
from the dropdown list.
l Non-loopback: It is a normal state. When the

equipment runs normally, set this parameter
to non-loopback.
l Inloop: The loop is performed toward the
local NE.
l Outloop: The loop is performed toward the
opposite NE. Inloop and outloop of an optical
interface affect services. They are used to
locate faults.
In the REG working mode, the board processes
only the framer header and regenerator section
overheads. In the case of the non-REG service
configuration, set this parameter to Disabled.
Hardware
REG
Enable
Step 2 Check PDH board parameters. For the PDH board parameters, see Table 28-2.
Table 28-2 PDH board parameters
Boar
d
Type
Paramete
r
Service
Load
Indication
PDH
Tributary
Loopback
Navigation Path
1. In the NE
Explorer,
select a board.
2. Choose
Configuratio
n > PDH
Interface from
the Function
Tree.
3. Click
By
Board/Port
(channel) and
select
Port
l Non-loaded: The service path does not
process the services that are carried, to
suppress alarms in non-loaded service paths.
l Load: The service path processes the services
that are carried. In the case of a tributary board
that has services, set this parameter to Load.
l Non-loopback: It is a normal state. When the
equipment runs normally, set this parameter
to non-loopback.
l Inloop: When input service signals reach the
tributary board of the target NE, the signals
revert to the original trail. This function is
used to locate faults of each service path.
l Outloop: When input service signals reach the
tributary board through the input port of the
local NE, the signals are looped back directly
to the service output end.
Step 3 Check RTN board parameters. For the RTN board parameters, see Table 28-3.
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28 Task Collection
Table 28-3 RTN board parameters

Boar
d
Type
Paramete
r
Navigation Path
Radio
Work
Mode
Specifies the microwave working mode. Its
formats are service capacity, working bandwidth
and modulation mode.
The transmit end and the receive end must have
the same settings of the microwave working
mode.
Radio Link
ID
Radio Link ID: 1 to 4094
IF Port
Loopback
Sets the loopback status of an intermediate

frequency interface on the equipment.
1. In the NE
Explorer,
select a board.
2. Choose
Configuratio
n
>
IF
Interface from
the Function
Tree.
3. Click
By
Board/Port
(channel) and
select
Port
RTN
Non-Loopback refers to the normal status. It is

not required to set loopback during normal
equipment operation.
Outloop means that the input signal passes
through the ingress port and reaches the
intermediate frequency board at the local NE and
then is directly looped back to the service egress
end.
Inloop means that the input signal returns from
the intermediate frequency board of the
destination NE along the original trail.
This function is usually used to locate faults for
various IF interfaces. Performing loopback on an
intermediate frequency interface is a diagnosis
function that may affect services of related ports.
Exercise caution before performing this function.
2M
Wayside
Enable
Status
Enables or disables a 2 Mbit/s bypath service.

This parameter is available only when you set
Radio Work Mode to STM-1,28MHz,
128QAM.
ATPC
Enable
Status
When the ATPC is enabled, according to the

current receive power of the ODU and the set
ATPC thresholds, the ATPC module inserts the
ATPC overhead. According to the ATPC
overhead, the opposite ODU adjusts the transmit
power.
When the ATPC is disabled, the ATPC module
does not insert any ATPC overhead.
Step 4 Check data board parameters. For the data board parameters, see Table 28-4.
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28 Task Collection
Table 28-4 Data board parameters

Board
Type
Paramet
er
Enabled/
Disabled
When configuring Ethernet board port

services, set the port to Enabled.
Working
Mode
Set the working mode of Ethernet ports

according to networking configuration
requirements.
Maximu
m Frame
Length
When a packet exceeds the maximum

frame length that is set, the packet is
discarded. Alternatively, the packet length
is minimized to satisfy the specified frame
length. By default, the value is set to 1522,
unless otherwise specified.
MAC
Loopbac
k
Ethern
et
Navigation Path
1. In the NE Explorer,
select a board.
2. Choose
Configuration
>
Ethernet Interface
Management
>
Ethernet Interface
from the Function
Tree.
3. Click External Port.
4. Click the Basic
Attributes tab.
l Non-loopback: It is a normal state.

When the equipment runs normally, set
this parameter to non-loopback.
l Inloop: Inside the equipment, services
from the cross-connect side are looped
back to the cross-connect side. This
operation affects services configured on
ports and is used to locate faults.
l Non-loopback: It is a normal state.
When the equipment runs normally, set
this parameter to non-loopback.
PHY
Loopbac
k
l Inloop: Inside the equipment, services

from the cross-connect side are looped
back to the cross-connect side. This
operation affects services configured on
ports and is used to locate faults.
TAG
Entry
Detection
Issue 03 (2013-02-20)
select a board.
2. Choose
Configuration
>
Ethernet Interface
Management
>
Ethernet Interface
from the Function
Tree.
4. Click the TAG
Attributes tab.
l Tag Aware: If the client-side equipment

sends tag packets, set the TAG attribute
of external ports to Tag Aware.
l Access: If the client-side equipment
sends untagged packets, set the TAG
attribute of external ports to Access.
l Hybrid: If the client-side equipment
sends tag and untagged packets, set the
TAG attribute of external ports to
Hybrid.
This parameter is used to identify tags in
data packets. During the configuration of
VLAN services, set this parameter to
Enabled.

1612

Board
Type
Paramet
er
Navigation Path
ATM
l UNI: The maximum number of VPI bits
is 8. The UNI is used on edge nodes
between the user network and ATM
network.
Port Type
UPC/
NPC
Enabled/
Disabled
28 Task Collection
select a board.
2. Choose
Configuration
>
ATM
Interface
Management
>
ATM
Interface
Management from
the Function Tree.
l NNI: The maximum number of VPI bits

is 12. The NNI is used between ATM
networks.
l Enabled: When the traffic parameter is
valid and strict control of traffic is
required, set this parameter to
Enabled.
l Disabled: When the traffic parameter is
invalid (excepting the PCR of CBR
services) and service burst and
grooming are permitted, set this
parameter to Disabled.
Loopbac
k
Inloop is used to locate faults. During

normal service configuration, set this
parameter to No Loopback.
Laser
Switch
This parameter is used to set the on/off

status of a laser. During normal service
configuration, set this parameter to Open.
----End
28.8 Testing the SAN Service Channel

Testing the Loopback Function When the FC Flow Control Function Is Disabled
Step 1 Connect the optical fibers to the equipment according to Figure 28-4. Ensure that the mode of
the GBIC optical module of the SmartBits and the mode of the SFP optical module of the MST4
match the mode of the optical fibers.
Issue 03 (2013-02-20)

1613

28 Task Collection
Figure 28-4 Connection for testing the loopback function when the FC flow control function is
disabled
NE1
NE2
SDH
network
SmartBits
Signal flow
Step 2 Disable the FC flow control function on both the local and remote MST4 boards.
Step 3 Loop back the port of the remote MST4 by using an optical fiber or set an inloop on the port of
the remote MST4.
Step 4 Connect the SmartBits to NE1 and set the SmartBits to the private Pt-2-Pt mode.
Step 5 Check whether the services are normal on the SmartBits.
Step 6 If the services are unavailable, configure a loopback to the remote MST4 on the cross-connect
board of NE1 and a loopback to the local MST4 on the cross-connect board of NE2. Then,
perform the test section by section to locate the fault.
----End
Testing the Connection to the FC Switch When the FC Flow Control Function Is
Disabled
Step 1 Connect the optical fibers to the equipment according to Figure 28-5 after ensuring that services
are available on the SmartBits when the FC flow control function is disabled. In addition, do not
modify the configuration of the boards.
Issue 03 (2013-02-20)

1614

28 Task Collection
Figure 28-5 Connection for testing the connection to the FC switch when the FC flow control
function is disabled
Switch A
NE1
NE2
Switch B
SDH
network
SmartBits
SmartBits
Step 2 Set the port of the SmartBits to the public Pt-2-Pt mode. Then, perform the following operations:
link_up, login, public, commit, and packet transmission.
l If an error occurs when you perform the link_up or login operation, check the connection
between the SmartBits and the switch. In addition, check the port rate.
l If an error occurs when you perform the public operation, check whether the mode of the
SFP optical module of the MST4, the mode of the SFP optical module that is installed on the
FC port to which the MST4 is connected, and the mode of the optical fibers match each other.
If the connection is correct, log in to the switch and issue the portcfgshow command to check
the configuration status of the switch port. The configuration of the port must meet the
requirement and the configurations of the ports at both ends must be consistent. Then, issue
the switchshow command to check the status of the FC switch and check whether the port
is in the Online state. In addition, you need to check whether WWW of the switch at the
opposite end, the downstream information, and the upstream information are displayed.
l If the configuration of the switch port is correct and WWW of the switch at the opposite end
is displayed but the downstream information and upstream information are not displayed,
check whether the configuration of the SmartBits is correct. In addition, check whether
WWN Src and WWN Dst are correctly set on the SmartBits.
l If the configuration of the SmartBits is correct, check whether network segments are set on
the FC switches. If network segments are set on the FC switches, ensure that the switch ports
to which the SmartBits is connected are in the same network segment.
----End
28.9 Testing the SDI Service Channel

SDI Service Loopback Test

Step 1 Connect the cables to the equipment according toFigure 28-6.
Issue 03 (2013-02-20)

1615

28 Task Collection
Figure 28-6 Connection for an SDI service loopback test

NE1
SDH
network
Video generator
NE2
Video analyzer
Signal flow
Step 2 Set the service type on a video generator.

Step 3 Set the eye diagram, image, BER, and jitter on a video analyzer.
Step 4 Before the test, set the BER window to 0. Observe the video analyzer to check whether the
service is available.
Step 5 If the service is unavailable, configure a loopback from the local cross-connect board to the
opposite VST4 board and a loopback from the opposite cross-connect board to the local VST4
board. Perform a test section by section to locate the fault.
----End
Issue 03 (2013-02-20)

1616

A Glossary
Glossary
Numerics
2DM
two-way delay measurement
3G
See 3rd Generation.
3R
reshaping, retiming, regenerating
3rd Generation (3G)
The third generation of digital wireless technology, as defined by the International

Telecommunications Union (ITU). Third generation technology is expected to deliver
data transmission speeds between 144 kbit/s and 2 Mbit/s, compared to the 9.6 kbit/s to
19.2 kbit/s offered by second generation technology.
802.1Q in 802.1Q
(QinQ)
A VLAN feature that allows the equipment to add a VLAN tag to a tagged frame. The
implementation of QinQ is to add a public VLAN tag to a frame with a private VLAN
tag to allow the frame with double VLAN tags to be transmitted over the service
provider's backbone network based on the public VLAN tag. This provides a layer 2
VPN tunnel for customers and enables transparent transmission of packets over private
VLANs.
A
AAL
See ATM Adaptation Layer.
ABR
See available bit rate.
AC
alternating current
ACH
associated channel header
ACL
See access control list.
ACR
allowed cell rate
ADM
add/drop multiplexer
ADMC
automatically detected and manually cleared
ADSL
asymmetric digital subscriber line
AF
See assured forwarding.
AGC
automatic gain control
AIS
alarm indication signal
Issue 03 (2013-02-20)

1617

A Glossary
ALC
See automatic level control.
ALS
See automatic laser shutdown.
AM
See adaptive modulation.
AMI
See alternate mark inversion.
AMU
ATM cell multiplex unit
ANSI
See American National Standards Institute.
APD
See avalanche photodiode.
APS
automatic protection switching
ARP
See Address Resolution Protocol.
ASCII
American Standard Code for Information Interchange
ASK
amplitude shift keying
ATM
asynchronous transfer mode
ATM Adaptation
Layer (AAL)
An interface between higher-layer protocols and Asynchronous Transfer Mode (ATM).

The AAL provides a conversion function to and from ATM for various types of
information, including voice, video, and data.
ATPC
See automatic transmit power control.
AU
See administrative unit.
AUG
See administrative unit group.
AWG
arrayed waveguide grating
Address Resolution
Protocol (ARP)
An Internet Protocol used to map IP addresses to MAC addresses. It allows hosts and
routers to determine the link layer addresses through ARP requests and ARP responses.
American National
Standards Institute
(ANSI)
An organization that defines U.S standards for the information processing industry.
ANSI participates in defining network protocol standards.
access control list

(ACL)
A list of entities, together with their access rights, which are authorized to have access
to a resource.
adaptive modulation
(AM)
A technology that is used to automatically adjust the modulation mode according to the
channel quality. When the channel quality is favorable, the equipment uses a highefficiency modulation mode to improve the transmission efficiency and the spectrum
utilization of the system. When the channel quality is degraded, the equipment uses the
low-efficiency modulation mode to improve the anti-interference capability of the link
that carries high-priority services.
administrative unit
(AU)
The information structure which provides adaptation between the higher order path layer
and the multiplex section layer. It consists of an information payload (the higher order
VC) and an AU pointer which indicates the offset of the payload frame start relative to
the multiplex section frame start.
administrative unit
group (AUG)
One or more administrative units occupying fixed, defined positions in an STM payload.
An AUG consists of AU-4s.
alternate mark
inversion (AMI)
A synchronous clock encoding technique which uses bipolar pulses to represent logical
1 values.
Issue 03 (2013-02-20)

1618

A Glossary
assured forwarding
(AF)
One of the four per-hop behaviors (PHB) defined by the Diff-Serv workgroup of IETF.
It is suitable for certain key data services that require assured bandwidth and short delay.
For traffic within the bandwidth limit, AF assures quality in forwarding. For traffic that
exceeds the bandwidth limit, AF degrades the service class and continues to forward the
traffic instead of discarding the packets.
automatic laser
shutdown (ALS)
A technique (procedure) to automatically shutdown the output power of laser transmitters

and optical amplifiers to avoid exposure to hazardous levels.
automatic level control A feature that identifies speech signals and adjusts the sound volume to stay within a
(ALC)
comfortable range, improving user experience.
automatic transmit
A method of adjusting the transmit power based on fading of the transmit signal detected
power control (ATPC) at the receiver
available bit rate (ABR) A kind of service categories defined by the ATM forum. ABR only provides possible
forwarding service and applies to the connections that does not require the real-time
quality. It does not provide any guarantee in terms of cell loss or delay.
avalanche photodiode
(APD)
A semiconductor photodetector with integral detection and amplification stages.

Electrons generated at a p/n junction are accelerated in a region where they free an
avalanche of other electrons. APDs can detect faint signals but require higher voltages
than other semiconductor electronics.
B
B-ISDN
See broadband integrated services digital network.
BA
booster amplifier
BBE
background block error
BC
boundary clock
BCD
binary coded decimal
BDI
See backward defect indication.
BE
See best effort.
BER
bit error rate
BFD
See Bidirectional Forwarding Detection.
BGP
Border Gateway Protocol
BIOS
See basic input/output system.
BIP
See bit interleaved parity.
BIP-8
See bit interleaved parity-8.
BIP-X
bit interleaved parity-X
BITS
See building integrated timing supply.
BMC
best master clock
BNC
See bayonet-neill-concelman.
BPDU
See bridge protocol data unit.
BPS
board protection switching
BRAS
See broadband remote access server.
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1619

A Glossary
BSC
binary synchronous communication
BSS
base station subsystem
BTS
base transceiver station
BWS
backbone wavelength division multiplexing system
Bidirectional
Forwarding Detection
(BFD)
A fast and independent hello protocol that delivers millisecond-level link failure
detection and provides carrier-class availability. After sessions are established between
neighboring systems, the systems can periodically send BFD packets to each other. If
one system fails to receive a BFD packet within the negotiated period, the system regards
that the bidirectional link fails and instructs the upper layer protocol to take actions to
recover the faulty link.
backplane
An electronic circuit board containing circuits and sockets into which additional
electronic devices on other circuit boards or cards can be plugged.
backward defect
indication (BDI)
A function that the sink node of a LSP, when detecting a defect, uses to inform the
upstream end of the LSP of a downstream defect along the return path.
basic input/output
system (BIOS)
A firmware stored in the computer mainboard. It contains basic input/output control

programs, power-on self test (POST) programs, bootstraps, and system setting
information. The BIOS provides hardware setting and control functions for the computer.
bayonet-neillconcelman (BNC)
A connector used for connecting two coaxial cables.
best effort (BE)
A traditional IP packet transport service. In this service, the diagrams are forwarded
following the sequence of the time they reach. All diagrams share the bandwidth of the
network and routers. The amount of resource that a diagram can use depends of the time
it reaches. BE service does not ensure any improvement in delay time, jitter, packet loss
ratio, and high reliability.
bit interleaved parity

(BIP)
A method of error monitoring. With even parity an X-bit code is generated by equipment
at the transmit end over a specified portion of the signal in such a manner that the first
bit of the code provides even parity over the first bit of all X-bit sequences in the covered
portion of the signal, the second bit provides even parity over the second bit of all X-bit
sequences within the specified portion, and so on. Even parity is generated by setting the
BIP-X bits so that there is an even number of 1s in each monitored partition of the signal.
A monitored partition comprises all bits which are in the same bit position within the Xbit sequences in the covered portion of the signal. The covered portion includes the BIPX.
bit interleaved parity-8 Consists of a parity byte calculated bit-wise across a large number of bytes in a
transmission transport frame. Divide a frame is into several blocks with 8 bits (one byte)
(BIP-8)
in a parity unit and then arrange the blocks in matrix. Compute the number of "1" or "0"
over each column. Then fill a 1 in the corresponding bit for the result if the number is
odd, otherwise fill a 0.
bridge protocol data
unit (BPDU)
Issue 03 (2013-02-20)
The data messages that are exchanged across the switches within an extended LAN that
uses a spanning tree protocol (STP) topology. BPDU packets contain information on
ports, addresses, priorities and costs and ensure that the data ends up where it was
intended to go. BPDU messages are exchanged across bridges to detect loops in a
network topology. The loops are then removed by shutting down selected bridges
interfaces and placing redundant switch ports in a backup, or blocked, state.

1620

A Glossary
broadband integrated A standard defined by the ITU-T to handle high-bandwidth applications, such as voice.
services digital network It currently uses the ATM technology to transmit data over SONNET-based circuits at
(B-ISDN)
155 to 622 Mbit/s or higher speed.
broadband remote
access server (BRAS)
A new type of access gateway for broadband networks. As a bridge between backbone
networks and broadband access networks, BRAS provides methods for fundamental
access and manages the broadband access network. It is deployed at the edge of network
to provide broadband access services, convergence, and forwarding of multiple services,
meeting the demands for transmission capacity and bandwidth utilization of different
users. BRAS is a core device for the broadband users' access to a broadband network.
building integrated
timing supply (BITS)
In the situation of multiple synchronous nodes or communication devices, one can use
a device to set up a clock system on the hinge of telecom network to connect the
synchronous network as a whole, and provide satisfactory synchronous base signals to
the building integrated device. This device is called BITS.
built-in WDM
A function which integrates some simple WDM systems into products that belong to the
OSN series. That is, the OSN products can add or drop several wavelengths directly.
C
CAR
committed access rate
CAS
See channel associated signaling.
CAS multiframe
A multiframe set up based on timeslot 16. Each CAS multiframe contains 16 E1 PCM
frames. Among the 8 bits of timeslot 16 in the first frame, the first 4 bits are used for
multiframe synchronization. The multiframe alignment signal (MFAS) for
synchronization is 0000. The last 4 bits are used as the not multiframe alignment signal
(NMFAS). The NMFAS is XYXX. For the other 15 frames, timeslot 16 is used to
transmit exchange and multiplexing (E&M) signaling corresponding to each timeslot.
CAU
See client automatic upgrade.
CBR
See constant bit rate.
CBS
See committed burst size.
CC
See continuity check.
CDVT
cell delay variation tolerance
CE
See customer edge.
CES
See circuit emulation service.
CFM
connectivity fault management
CFR
cell fill rate
CGMP
Cisco Group Management Protocol
CIR
committed information rate
CISPR
International Special Committee on Radio Interference
CIST
See Common and Internal Spanning Tree.
CLEI
common language equipment identification
CLNP
connectionless network protocol
CLP
See cell loss priority.
Issue 03 (2013-02-20)

1621

A Glossary
CMI
coded mark inversion
CRC
See cyclic redundancy check.
CRC-4 multiframe
A multiframe recommended by ITU-T G.704 and set up based on the first bit of timeslot
0. The CRC-4 multiframe is different from the CAS multiframe in principle and
implementation. Each CRC-4 multiframe contains 16 PCM frames. Each CRC-4
multiframe consists of two CRC-4 sub-multiframes. Each CRC-4 sub-multiframe is a
CRC-4 check block that contains 2048 (256 x 8) bits. Bits C1 to C4 of a check block can
check the previous check block.
CSA
Canadian Standards Association
CSES
consecutive severely errored second
CSF
Client Signal Fail
CSMA/CD
See carrier sense multiple access with collision detection.
CSPF
constraint shortest path first
CST
See common spanning tree.
CV
connectivity verification
CW
control word
CWDM
See coarse wavelength division multiplexing.
Common and Internal The single spanning tree jointly calculated by STP and RSTP, the logical connectivity
Spanning Tree (CIST) using MST bridges and regions, and MSTP. The CIST ensures that all LANs in the
bridged local area network are simply and fully connected.
Coordinated Universal The world-wide scientific standard of timekeeping. It is based upon carefully maintained
Time (UTC)
atomic clocks and is kept accurate to within microseconds worldwide.
carrier sense multiple
access with collision
detection (CSMA/CD)
Carrier sense multiple access with collision detection (CSMA/CD) is a computer

networking access method in which:
l
A carrier sensing scheme is used.
A transmitting data station that detects another signal while transmitting a frame,
stops transmitting that frame, transmits a jam signal, and then waits for a random
time interval before trying to send that frame again.
cell loss priority (CLP) A field in the ATM cell header that determines the probability of a cell being dropped
if the network becomes congested. Cells with CLP = 0 are insured traffic, which is
unlikely to be dropped. Cells with CLP = 1 are best-effort traffic, which might be
dropped.
channel associated
signaling (CAS)
A signaling system in which signaling information is transmitted within a dedicated voice

channel. China Signaling System No. 1 is a type of CAS signaling.
circuit emulation
service (CES)
A function with which the E1/T1 data can be transmitted through ATM networks. At the
transmission end, the interface module packs timeslot data into ATM cells. These ATM
cells are sent to the reception end through the ATM network. At the reception end, the
interface module re-assigns the data in these ATM cells to E1/T1 timeslots. The CES
technology guarantees that the data in E1/T1 timeslots can be recovered to the original
sequence at the reception end.
client automatic
upgrade (CAU)
A function that enables a user to automatically detect the update of the client version and
upgrade the client. This keeps the version of the client is the same as that of the server.
Issue 03 (2013-02-20)

1622

A Glossary
coarse wavelength
division multiplexing
(CWDM)
A signal transmission technology that multiplexes widely-spaced optical channels into

the same fiber. CWDM widely spaces wavelengths at a spacing of several nm. CWDM
does not support optical amplifiers and is applied in short-distance chain networking.
collision
A condition in which two packets are being transmitted over a medium at the same time.
Their interference makes both unintelligible.
committed burst size

(CBS)
A parameter used to define the capacity of token bucket C, that is, the maximum burst
IP packet size when the information is transferred at the committed information rate.
This parameter must be larger than 0. It is recommended that this parameter should be
not less than the maximum length of the IP packet that might be forwarded.
common spanning tree A single spanning tree that connects all the MST regions in a network. Every MST region
(CST)
is considered as a switch; therefore, the CST can be considered as their spanning tree
generated with STP/RSTP.
constant bit rate (CBR) A kind of service categories defined by the ATM forum. CBR transfers cells based on
the constant bandwidth. It is applicable to service connections that depend on precise
clocking to ensure undistorted transmission.
continuity check (CC)
Ethernet CFM can detect the connectivity between MEPs. The detection is achieved after
MEPs transmit Continuity Check Messages (CCMs) periodically.
customer edge (CE)
A part of BGP/MPLS IP VPN model. It provides interfaces for direct connection to the
Service Provider (SP) network. A CE can be a router, switch, or host.
cyclic redundancy
check (CRC)
A procedure used in checking for errors in data transmission. CRC error checking uses
a complex calculation to generate a number based on the data transmitted. The sending
device performs the calculation before transmission and includes it in the packet that it
sends to the receiving device. The receiving device repeats the same calculation after
transmission. If both devices obtain the same result, it is assumed that the transmission
was error free. The procedure is known as a redundancy check because each transmission
includes not only data but extra (redundant) error-checking values.
D
DC
direct current
DC-C
See DC-return common (with ground).
DC-I
See DC-return isolate (with ground).
DC-return common
(with ground) (DC-C)
A power system, in which the BGND of the DC return conductor is short-circuited with
the PGND on the output side of the power supply cabinet and also on the line between
the output of the power supply cabinet and the electric equipment.
DC-return isolate (with A power system, in which the BGND of the DC return conductor is short-circuited with
ground) (DC-I)
the PGND on the output side of the power supply cabinet and is isolated from the PGND
on the line between the output of the power supply cabinet and the electric equipment.
DCC
See data communications channel.
DCE
data connection equipment
DCM
See dispersion compensation module.
DCN
See data communication network.
DDF
digital distribution frame
DDN
See digital data network.
Issue 03 (2013-02-20)

1623

DE
discard eligible
DEI
device emulation interrupt
DHCP
See Dynamic Host Configuration Protocol.
DIP switch
dual in-line package switch
DLAG
See distributed link aggregation group.
DM
See delay measurement.
DNI
dual node interconnection
DRDB
dynamic random database
DSCP
See differentiated services code point.
DSL
See digital subscriber line.
DSLAM
See digital subscriber line access multiplexer.
DTE
See data terminal equipment.
DTMF
See dual tone multiple frequency.
DVB-ASI
digital video broadcast-asynchronous serial interface
DVMRP
See Distance Vector Multicast Routing Protocol.
DWDM
See dense wavelength division multiplexing.
DiffServ
See Differentiated Services.
A Glossary
Differentiated Services An IETF standard that defines a mechanism for controlling and forwarding traffic in a
(DiffServ)
differentiated manner based on CoS settings to handle network congestion.
Distance Vector
Multicast Routing
Protocol (DVMRP)
An Internet gateway protocol mainly based on the RIP. The protocol implements a typical
dense mode IP multicast solution. The DVMRP protocol uses IGMP to exchange routing
datagrams with its neighbors.
Dynamic Host
A client-server networking protocol. A DHCP server provides configuration parameters
Configuration Protocol specific to the DHCP client host requesting, generally, information required by the host
(DHCP)
to participate on the Internet network. DHCP also provides a mechanism for allocation
of IP addresses to hosts.
data communication
network (DCN)
A communication network used in a TMN or between TMNs to support the data

communication function.
data communications
channel (DCC)
The data channel that uses the D1D12 bytes in the overhead of an STM-N signal to
transmit information about operation, management, maintenance and provision
(OAM&P) between NEs. The DCC channels that are composed of bytes D1D3 are
referred to as the 192 kbit/s DCC-R channel. The other DCC channels that are composed
of bytes D4D12 are referred to as the 576 kbit/s DCC-M channel.
data terminal
equipment (DTE)
A user device composing the UNI. The DTE accesses the data network through the DCE
equipment (for example, a modem) and usually uses the clock signals produced by DCE.
delay measurement
(DM)
The time elapsed since the start of transmission of the first bit of the frame by a source
node until the reception of the last bit of the loopbacked frame by the same source node,
when the loopback is performed at the frame's destination node.
Issue 03 (2013-02-20)

1624

A Glossary
dense wavelength
division multiplexing
(DWDM)
The technology that utilizes the characteristics of broad bandwidth and low attenuation
of single mode optical fiber, employs multiple wavelengths with specific frequency
spacing as carriers, and allows multiple channels to transmit simultaneously in the same
fiber.
differentiated services
code point (DSCP)
According to the QoS classification standard of the Differentiated Service (Diff-Serv),

the type of services (ToS) field in the IP header consists of six most significant bits and
two currently unused bits, which are used to form codes for priority marking.
Differentiated services code point (DSCP) is the six most important bits in the ToS. It is
the combination of IP precedence and types of service. The DSCP value is used to ensure
that routers supporting only IP precedence can be used because the DSCP value is
compatible with IP precedence. Each DSCP maps a per-hop behavior (PHB). Therefore,
terminal devices can identify traffic using the DSCP value.
digital data network

(DDN)
A high-quality data transport tunnel that combines the digital channel (such as fiber
channel, digital microwave channel, or satellite channel) and the cross multiplex
technology.
digital subscriber line

(DSL)
A technology for providing digital connections over the copper wire or the local
telephone network. DSL performs data communication over the POTS lines without
affecting the POTS service.

access multiplexer
(DSLAM)
A network device, usually situated in the main office of a telephone company that
receives signals from multiple customer Digital Subscriber Line (DSL) connections and
puts the signals on a high-speed backbone line using multiplexing techniques.
dispersion
The maximum error of the local clock compared with the reference clock.
dispersion
compensation module
(DCM)
A module, which contains dispersion compensation fibers to compensate for the

dispersion of transmitting fiber.
distributed link
aggregation group
(DLAG)
A board-level port protection technology used to detect unidirectional fiber cuts and to
negotiate with the opposite end. Once a link down failure occurs on a port or a hardware
failure occurs on a board, the services can automatically be switched to the slave board,
achieving 1+1 protection for the inter-board ports.
dual tone multiple

frequency (DTMF)
In telephone systems, multifrequency signaling in which standard set combinations of

two specific voice band frequencies, one from a group of four low frequencies and the
other from a group of four higher frequencies, are used.
E
E-Aggr
See Ethernet aggregation.
E-LAN
See Ethernet local area network.
E-Line
See Ethernet line.
EBS
See excess burst size.
ECC
See embedded control channel.
EDFA
See erbium-doped fiber amplifier.
EEPROM
See electrically erasable programable read-only memory.
EF
See expedited forwarding.
EFM
Ethernet in the First Mile
Issue 03 (2013-02-20)

1625

A Glossary
EFM OAM
Ethernet in the first mile OAM
EIA
See Electronic Industries Alliance.
EIR
See excess information rate.
EMC
See electromagnetic compatibility.
EPD
early packet discard
EPL
See Ethernet private line.
EPLAN
See Ethernet private LAN service.
EPON
See Ethernet passive optical network.
ERPS
Ethernet ring protection switching
ESC
See electric supervisory channel.
ESCON
See enterprise system connection.
ESD
electrostatic discharge
ESN
See equipment serial number.
ETS
European Telecommunication Standards
ETSI
See European Telecommunications Standards Institute.
EVC
Ethernet virtual connection
EVPL
See Ethernet virtual private line.
EVPLAN
See Ethernet virtual private LAN service.
Electronic Industries
Alliance (EIA)
An association based in Washington, D.C., with members from various electronics

manufacturers. It sets standards for electronic components. RS-232-C, for example, is
the EIA standard for connecting serial components.
EoD
See Ethernet over dual domains.
Ethernet
A LAN technology that uses Carrier Sense Multiple Access/Collision Detection. The
speed of an Ethernet interface can be 10 Mbit/s, 100 Mbit/s, 1000 Mbit/s or 10000 Mbit/
s. An Ethernet network features high reliability and is easy to maintain.
Ethernet aggregation
(E-Aggr)
A type of Ethernet service that is based on a multipoint-to-point EVC (Ethernet virtual

connection).
Ethernet line (E-Line)
A type of Ethernet service that is based on a point-to-point EVC (Ethernet virtual

connection).
Ethernet local area

network (E-LAN)
A type of Ethernet service that is based on a multipoint-to-multipoint EVC (Ethernet

virtual connection).
Ethernet over dual

domains (EoD)
A type of boards. EoD boards bridge the PSN and TDM networks, enabling Ethernet
service transmission across PSN and TDM networks.
Ethernet passive
optical network
(EPON)
A passive optical network based on Ethernet. It is a new generation broadband access

technology that uses a point-to-multipoint structure and passive fiber transmission. It
supports upstream/downstream symmetrical rates of 1.25 Gbit/s and a reach distance of
up to 20 km. In the downstream direction, the bandwidth is shared based on encrypted
broadcast transmission for different users. In the upstream direction, the bandwidth is
shared based on TDM. EPON meets the requirements for high bandwidth.
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A Glossary
Ethernet private LAN

service (EPLAN)
A type of Ethernet service provided by SDH, PDH, ATM, or MPLS networks. This
service is carried over a dedicated bridge and point-to-multipoint connections.
Ethernet private line

(EPL)
A type of Ethernet service that is provided with dedicated bandwidth and point-to-point
connections on an SDH, PDH, ATM, or MPLS server layer network.
Ethernet virtual
private LAN service
(EVPLAN)
service is carried over a shared bridge and point-to-multipoint connections.
Ethernet virtual
private line (EVPL)
service is carried over a shared bridge and point-to-point connections.
European
Telecommunications
Standards Institute
(ETSI)
A standards-setting body in Europe. Also the standards body responsible for GSM.
eSFP
enhanced small form-factor pluggable
electric supervisory
channel (ESC)
A technology that implements communication among all the nodes and transmission of
monitoring data in an optical transmission network. The monitoring data of ESC is
introduced into DCC service overhead and is transmitted with service signals.
electrically erasable
A type of EPROM that can be erased with an electrical signal. It is useful for stable
programable read-only storage for long periods without electricity while still allowing reprograming. EEPROMs
memory (EEPROM)
contain less memory than RAM, take longer to reprogram, and can be reprogramed only
a limited number of times before wearing out.
electromagnetic
compatibility (EMC)
A condition which prevails when telecommunications equipment is performing its

individually designed function in a common electromagnetic environment without
causing or suffering unacceptable degradation due to unintentional electromagnetic
interference to or from other equipment in the same environment.
embedded control
channel (ECC)
A logical channel that uses a data communications channel (DCC) as its physical layer,
to enable transmission of operation, administration, and maintenance (OAM)
information between NEs.
encapsulation
A technology for layered protocols, in which a lower-level protocol accepts a message

from a higher-level protocol and places it in the data portion of the lower-level frame.
Protocol A's packets have complete header information, and are carried by protocol B
as data. Packets that encapsulate protocol A have a B header, an A header, followed by
the information that protocol A is carrying. Note that A could equal to B, as in IP inside
IP.
enterprise system
connection (ESCON)
A path protocol which connects the host with various control units in a storage system.
It is a serial bit stream transmission protocol. The transmission rate is 200 Mbit/s.
equalization
A method of avoiding selective fading of frequencies. Equalization can compensate for

the changes of amplitude frequency caused by frequency selective fading.
equipment serial
number (ESN)
A string of characters that identify a piece of equipment and ensures correct allocation
of a license file to the specified equipment. It is also called "equipment fingerprint".
erbium-doped fiber
amplifier (EDFA)
An optical device that amplifies the optical signals. The device uses a short length of
optical fiber doped with the rare-earth element Erbium and the energy level jump of
Erbium ions activated by pump sources. When the amplifier passes the external light
source pump, it amplifies the optical signals in a specific wavelength range.
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A Glossary
excess burst size (EBS) A parameter related to traffic. In the single rate three color marker (srTCM) mode, the
traffic control is achieved by the token buckets C and E. Excess burst size is a parameter
used to define the capacity of token bucket E, that is, the maximum burst IP packet size
when the information is transferred at the committed information rate. This parameter
must be larger than 0. It is recommended that this parameter should be not less than the
maximum length of the IP packet that might be forwarded.
excess information rate The bandwidth for excessive or burst traffic above the CIR; it equals the result of the
(EIR)
actual transmission rate without the safety rate.
exercise switching
An operation to check whether the protection switching protocol functions properly. The
protection switching is not really performed.
expedited forwarding
(EF)
The highest order QoS in the Diff-Serv network. EF PHB is suitable for services that
demand low packet loss ratio, short delay, and broad bandwidth. In all the cases, EF
traffic can guarantee a transmission rate equal to or faster than the set rate. The DSCP
value of EF PHB is "101110".
F
FC
See fiber channel.
FCC
Federal Communications Commission
FDD
See frequency division duplex.
FDDI
See fiber distributed data interface.
FDI
See forward defect indication.
FDI packet
See forward defect indication packet.
FDV
See frame delay variation.
FEC
See forwarding equivalence class.
FFD
fast failure detection
FIB
See forward information base.
FICON
See Fiber Connect.
FIFO
See first in first out.
FLR
See frame loss ratio.
FPGA
See field programmable gate array.
FPS
See fast protection switching.
FRR
See fast reroute.
FTN
FEC to NHLFE
FTP
File Transfer Protocol
Fiber Connect
(FICON)
A new generation connection protocol which connects the host to various control units.
It carries single byte command protocol through the physical path of fiber channel, and
provides higher rate and better performance than ESCON.
fast protection
switching (FPS)
A type of pseudo wire automatic protection switching (PW APS). When the working
PW is faulty, the source transmits services to the protection PW and the sink receives
the services from the protection PW. FPS generally works with the interworking function
(IWF) to provide end-to-end protection for services.
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A Glossary
fast reroute (FRR)
A technology which provides a temporary protection of link availability when part of a

network fails. The protocol enables the creation of a standby route or path for an active
route or path. When the active route is unavailable, the traffic on the active route can be
switched to the standby route. When the active route is recovered, the traffic can be
switched back to the active route. FRR is categorized into IP FRR, VPN FRR, and TE
FRR.
fiber channel (FC)
A high-speed transport technology used to build storage area networks (SANs). Fiber
channel can be on the networks carrying ATM and IP traffic. It is primarily used for
transporting SCSI traffic from servers to disk arrays. Fiber channel supports single-mode
and multi-mode fiber connections. Fiber channel signaling can run on both twisted pair
copper wires and coaxial cables. Fiber channel provides both connection-oriented and
connectionless services.
fiber distributed data

interface (FDDI)
A standard developed by the American National Standards Institute (ANSI) for highspeed fiber-optic local area networks (LANs). FDDI provides specifications for
transmission rates of 100 megabits (100 million bits) per second on networks based on
the token ring network.
field programmable
gate array (FPGA)
A type of semi-customized circuit used in the application specific integrated circuit

(ASIC) field. It is developed on the basis of the programmable components, such as the
PAL, GAL, and EPLD. It not only remedies the defects of customized circuits but also
overcomes the disadvantage of the original programmable components in terms of the
limited number of gate arrays.
first in first out (FIFO) A stack management mechanism. The first saved data is first read and invoked.
forward defect
indication (FDI)
A packet generated and traced forward to the sink node of the LSP by the node that first
detects defects. It includes fields to indicate the nature of the defect and its location. Its
primary purpose is to suppress alarms being raised at affected higher level client LSPs
and (in turn) their client layers.
forward defect
A packet that responds to the detected failure event. It is used to suppress alarms of the
indication packet (FDI upper layer network where failure has occurred.
packet)
forward information
base (FIB)
A table that provides information for network hardware (bridges and routers) for them
to forward data packets to other networks. The information contained in a routing table
differs according to whether it is used by a bridge or a router. A bridge relies on both the
source (originating) and destination addresses to determine where and how to forward a
packet.
forwarding equivalence A class-based forwarding technology that classifies the packets with the same forwarding
class (FEC)
mode. Packets with the same FEC are processed similarly on an MPLS network. The
division of FECs is flexible, and can be a combination of the source address, destination
address, source port, destination port, protocol type, and VPN.
frame delay variation
(FDV)
A measurement of the variations in the frame delay between a pair of service frames,
where the service frames belong to the same CoS instance on a point to point ETH
connection.
frame loss ratio (FLR) A ratio, is expressed as a percentage, of the number of service frames not delivered
divided by the total number of service frames during time interval T, where the number
of service frames not delivered is the difference between the number of service frames
arriving at the ingress ETH flow point and the number of service frames delivered at the
egress ETH flow point in a point-to-point ETH connection.
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frequency division
duplex (FDD)
A Glossary
An application in which channels are divided by frequency. In an FDD system, the uplink
and downlink use different frequencies. Downlink data is sent through bursts. Both
uplink and downlink transmission use frames with fixed time length.
G
G-ACH
generic associated channel header
GAL
generic associated channel header label
GCC
general communication channel
GCP
GMPLS control plan
GCRA
generic cell rate algorithm
GFC
generic flow control
GFP
See Generic Framing Procedure.
GMPLS
generalized multiprotocol label switching
GNE
See gateway network element.
GPON
gigabit-capable passive optical network
GPS
See Global Positioning System.
GRE
See Generic Routing Encapsulation.
GSM
See Global System for Mobile Communications.
Generic Framing
Procedure (GFP)
A framing and encapsulation method which can be applied to any data type. It has been
standardized by ITU-T SG15.
Generic Routing
Encapsulation (GRE)
A mechanism for encapsulating any network layer protocol over any other network. GRE
is used for encapsulating IP datagrams tunneled through the Internet. GRE serves as a
Layer 3 tunneling protocol and provides a tunnel for transparently transmitting data
packets.
Global Positioning
System (GPS)
A global navigation satellite system. It provides reliable positioning, navigation, and

timing services to worldwide users.
Global System for

Mobile
Communications
(GSM)
The second-generation mobile networking standard defined by European

Telecommunications Standards Institute (ETSI). It is aimed at designing a standard for
global mobile phone networks. The standard allows a subscriber to use a phone globally.
GSM consists of three main parts: mobile switching subsystem (MSS), base station
subsystem (BSS), and mobile station (MS).
gain
The difference between the optical power from the input optical interface of the optical
amplifier and the optical power from the output optical interface of the jumper fiber,
which expressed in dB.
gateway network
element (GNE)
A network element that is used for communication between the NE application layer and
the NM application layer.
H
HCS
higher order connection supervision
HD
high definition
HD-SDI
See high definition-serial digital interface signal.
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A Glossary
HDB3
See high density bipolar of order 3 code.
HDLC
High-Level Data Link Control
HDTV
See high definition television.
HEC
See header error control.
HPA
high order path adaptation
HPT
higher order path termination
HQoS
See hierarchical quality of service.
HSDPA
See High Speed Downlink Packet Access.
HSI
high-speed Internet
HSL
See high-level script language.
High Speed Downlink

Packet Access
(HSDPA)
A modulating-demodulating algorithm put forward in 3GPP R5 to meet the requirement

for asymmetric uplink and downlink transmission of data services. It enables the
maximum downlink data service rate to reach 14.4 Mbit/s without changing the
WCDMA network topology.
header error control

(HEC)
A field within the ATM frame whose purpose is to correct any single bit error in the cell
Header and also to detect any multi-bit errors. It actually performs a CRC check in the
first four header bits and also at the receiving end.
hierarchical quality of
service (HQoS)
A type of QoS that controls the traffic of users and performs the scheduling according
to the priority of user services. HQoS has an advanced traffic statistics function, and the
administrator can monitor the usage of bandwidth of each service. Hence, the bandwidth
can be allocated reasonably through traffic analysis.
high definition
television (HDTV)
A type of TV that is capable of displaying at least 720 progressive or 1080 interlaced

active scan lines. It must be capable of displaying a 16:9 image using at least 540
progressive or 810 interlaced active scan lines.
high definition-serial
digital interface signal
(HD-SDI)
High definition video signal transported by serial digital interface.
high density bipolar of A code used for baseband transmissions between telecommunications devices. The
order 3 code (HDB3)
HDB3 code has the following feature: high capability of clock extraction, no direct
current component, error-checking capability, and a maximum of three consecutive
zeros.
high-level script
language (HSL)
A script language. Based on python, the HSL syntax is simple, clear, and extendable.
hot patch
A patch that is used to repair a deficiency in the software or add a new feature to a program
without restarting the software and interrupting the service. For the equipment using the
built-in system, a hot patch can be loaded, activated, confirmed, deactivated, deleted, or
queried.
I
IAE
incoming alignment error
IANA
See Internet Assigned Numbers Authority.
IC
See integrated circuit.
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A Glossary
ICC
See ITU carrier code.
ICMP
See Internet Control Message Protocol.
ICP
IMA Control Protocol
IEEE
See Institute of Electrical and Electronics Engineers.
IETF
See Internet Engineering Task Force.
IF
See intermediate frequency.
IGMP
See Internet Group Management Protocol.
IGMP snooping
A multicast constraint mechanism running on a layer 2 device. This protocol manages

and controls the multicast group by listening to and analyzing Internet Group
Management Protocol (IGMP) packets between hosts and Layer 3 devices. In this
manner, the spread of the multicast data on layer 2 network can be prevented efficiently.
IGP
See Interior Gateway Protocol.
ILM
incoming label map
IMA
See inverse multiplexing over ATM.
IN
intelligent network
IP
Internet Protocol
IPA
See intelligent power adjustment.
IPTV
See Internet Protocol television.
IPv4
See Internet Protocol version 4.
IPv6
See Internet Protocol version 6.
IS-IS
See Intermediate System to Intermediate System.
ISDN
integrated services digital network
ISO
International Organization for Standardization
ISP
See Internet service provider.
IST
internal spanning tree
ITC
independent transmit clock
ITU
See International Telecommunication Union.
ITU carrier code (ICC) A code assigned to a network operator/service provider, maintained by the ITU-T
Telecommunication Standardization Bureau (TSB).
ITU-T
See International Telecommunication Union-Telecommunication Standardization

Sector.
Institute of Electrical
and Electronics
Engineers (IEEE)
A society of engineering and electronics professionals based in the United States but
boasting membership from numerous other countries. The IEEE focuses on electrical,
electronics, computer engineering, and science-related matters.
Interior Gateway
Protocol (IGP)
A routing protocol that is used within an autonomous system. The IGP runs in smallsized and medium-sized networks. The commonly used IGPs are the routing information
protocol (RIP), the interior gateway routing protocol (IGRP), the enhanced IGRP
(EIGRP), and the open shortest path first (OSPF).
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A Glossary
Intermediate System to A protocol used by network devices (routers) to determine the best way to forward
Intermediate System
datagram or packets through a packet-based network.
(IS-IS)
International
Telecommunication
Union (ITU)
A United Nations agency, one of the most important and influential recommendation
bodies, responsible for recommending standards for telecommunication (ITU-T) and
radio networks (ITU-R).
International
Telecommunication
UnionTelecommunication
Standardization Sector
(ITU-T)
An international body that develops worldwide standards for telecommunications

technologies. These standards are grouped together in series which are prefixed with a
letter indicating the general subject and a number specifying the particular standard. For
example, X.25 comes from the "X" series which deals with data networks and open
system communications and number "25" deals with packet switched networks.
Internet Assigned
Numbers Authority
(IANA)
A department operated by the IAB. IANA delegates authority for IP address-space

allocation and domain-name assignment to the NIC and other organizations. IANA also
maintains a database of assigned protocol identifiers used in the TCP/IP suite, including
autonomous system numbers.
Internet Control
Message Protocol
(ICMP)
A network-layer (ISO/OSI level 3) Internet protocol that provides error correction and
other information relevant to IP packet processing. For example, it can let the IP software
on one machine inform another machine about an unreachable destination. See also
communications protocol, IP, ISO/OSI reference model, packet (definition 1).
Internet Engineering
Task Force (IETF)
A worldwide organization of individuals interested in networking and the Internet.

Managed by the Internet Engineering Steering Group (IESG), the IETF is charged with
studying technical problems facing the Internet and proposing solutions to the Internet
Architecture Board (IAB). The work of the IETF is carried out by various working groups
that concentrate on specific topics such as routing and security. The IETF is the publisher
of the specifications that led to the TCP/IP protocol standard.
Internet Group
Management Protocol
(IGMP)
One of the TCP/IP protocols for managing the membership of Internet Protocol multicast
groups. It is used by IP hosts and adjacent multicast routers to establish and maintain
multicast group memberships.
Internet Protocol
television (IPTV)
A system in which video is transmitted in IP packets. Also called "TV over IP", IPTV
uses streaming video techniques to deliver scheduled TV programs or video-on-demand
(VOD). Unlike transmitting over the air or through cable to a TV set, IPTV uses the
transport protocol of the Internet for delivery and requires either a computer and software
media player or an IPTV set-top box to decode the images in real time.
Internet Protocol
version 4 (IPv4)
The current version of the Internet Protocol (IP). IPv4 utilizes a 32bit address which is
assigned to hosts. An address belongs to one of five classes (A, B, C, D, or E) and is
written as 4 octets separated by periods and may range from 0.0.0.0 through to
255.255.255.255. Each IPv4 address consists of a network number, an optional
subnetwork number, and a host number. The network and subnetwork numbers together
are used for routing, and the host number is used to address an individual host within the
network or subnetwork.
Internet Protocol
version 6 (IPv6)
An update version of IPv4, which is designed by the Internet Engineering Task Force
(IETF) and is also called IP Next Generation (IPng). It is a new version of the Internet
Protocol. The difference between IPv6 and IPv4 is that an IPv4 address has 32 bits while
an IPv6 address has 128 bits.
Internet service
provider (ISP)
An organization that offers users access to the Internet and related services.
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A Glossary
integrated circuit (IC)
A combination of inseparable associated circuit elements that are formed in place and
interconnected on or within a single base material to perform a microcircuit function.
intelligent power
adjustment (IPA)
A mechanism used to reduce the optical power of all the amplifiers in an adjacent
regeneration section in the upstream to a safety level if the system detects the loss of
optical signals on the link. If the fiber is broken, the device performance degrades, or the
connector is not plugged well, the loss of optical signals may occur. With IPA,
maintenance engineers will not be hurt by the laser sent out from the slice of broken
fiber.
intermediate frequency The transitional frequency between the frequencies of a modulated signal and an RF
(IF)
signal.
inverse multiplexing
over ATM (IMA)
A technique that involves inverse multiplexing and de-multiplexing of ATM cells in a

cyclical fashion among links grouped to form a higher bandwidth logical link whose rate
is approximately the sum of the link rates.
L
L2VPN
Layer 2 virtual private network
L3VPN
Layer 3 virtual private network
LACP
See Link Aggregation Control Protocol.
LACPDU
Link Aggregation Control Protocol data unit
LAG
See link aggregation group.
LAN
See local area network.
LAPD
link access procedure on the D channel
LAPS
Link Access Protocol-SDH
LB
local battery
LC
Lucent connector
LCAS
See link capacity adjustment scheme.
LCK
See Locked signal function.
LCN
local communications network
LDP
Label Distribution Protocol
LED
See light emitting diode.
LER
See label edge router.
LIFO
See last in first out.
LLC
See logical link control.
LLID
local loopback ID
LM
See loss measurement.
LMP
link management protocol
LOC
loss of clock
LOM
loss of multiframe
LOP
loss of pointer
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A Glossary
LOS
See loss of signal.
LPA
low order path adaptation
LPT
link-state pass through
LSP
See label switched path.
LSR
See label switching router.
LT
linktrace
LVDS
See low voltage differential signal.
Layer 2 switching
A data forwarding method. In a LAN, a network bridge or 802.3 Ethernet switch

transmits and distributes packet data based on the MAC address. Since the MAC address
is at the second layer of the OSI model, this data forwarding method is called Layer 2
switching.
Link Aggregation
Control Protocol
(LACP)
A dynamic link aggregation protocol that improves the transmission speed and
reliability. The two ends of the link send LACP packets to inform each other of their
parameters and form a logical aggregation link. After the aggregation link is formed,
LACP maintains the link status in real time and dynamically adjusts the ports on the
aggregation link upon detecting the failure of a physical port.
Locked signal function A function administratively locks an MEG end point (MEP) at the server layer, informs
(LCK)
consequential data traffic interruption to the peer MEP at the client layer, and suppresses
the alarm at the client layer.
label edge router (LER) A device that sits at the edge of an MPLS domain, that uses routing information to assign
labels to datagrams and then forwards them into the MPLS domain.
label switched path
(LSP)
A sequence of hops (R0...Rn) in which a packet travels from R0 to Rn through label

switching mechanisms. A label-switched path can be chosen dynamically, based on
common routing mechanisms or through configuration.
label switching router

(LSR)
Basic element of an MPLS network. All LSRs support the MPLS protocol. The LSR is
composed of two parts: control unit and forwarding unit. The former is responsible for
allocating the label, selecting the route, creating the label forwarding table, creating and
removing the label switch path; the latter forwards the labels according to groups
received in the label forwarding table.
last in first out (LIFO) A play mode of the voice mails, the last voice mail is played firstly.
light emitting diode
(LED)
A display and lighting technology used in almost every electrical and electronic product
on the market, to from a tiny on/off light to digital readouts, flashlights, traffic lights and
perimeter lighting. LEDs are also used as the light source in multimode fibers, optical
mice and laser-class printers.
linear MSP
linear multiplex section protection
link aggregation group An aggregation that allows one or more links to be aggregated together to form a link
(LAG)
aggregation group so that a MAC client can treat the link aggregation group as if it were
a single link.
link capacity
adjustment scheme
(LCAS)
Issue 03 (2013-02-20)
LCAS in the virtual concatenation source and sink adaptation functions provides a
control mechanism to hitless increase or decrease the capacity of a link to meet the
bandwidth needs of the application. It also provides a means of removing member links
that have experienced failure. The LCAS assumes that in cases of capacity initiation,
increases or decreases, the construction or destruction of the end-to-end path is the
responsibility of the network and element management systems.

1635

A Glossary
local area network

(LAN)
A network formed by the computers and workstations within the coverage of a few square
kilometers or within a single building. It features high speed and low error rate. Ethernet,
FDDI, and Token Ring are three technologies used to implement a LAN. Current LANs
are generally based on switched Ethernet or Wi-Fi technology and running at 1,000 Mbit/
s (that is, 1 Gbit/s).
logical link control

(LLC)
According to the IEEE 802 family of standards, Logical Link Control (LLC) is the upper
sublayer of the OSI data link layer. The LLC is the same for the various physical media
(such as Ethernet, token ring, WLAN).
loss measurement (LM) A method used to collect counter values applicable for ingress and egress service frames
where the counters maintain a count of transmitted and received data frames between a
pair of MEPs.
loss of signal (LOS)
No transitions occurring in the received signal.
low voltage differential A low noise, low power, low amplitude method for high-speed (gigabits per second) data
signal (LVDS)
transmission over copper wire.
M
MA
maintenance association
MAC
See Media Access Control.
MADM
multiple add/drop multiplexer
MAN
See metropolitan area network.
MBS
maximum burst size
MCF
message communication function
MCR
minimum cell rate
MD
See maintenance domain.
MDF
See main distribution frame.
MDP
message dispatch process
MDU
See multi-dwelling unit.
ME
See maintenance entity.
MEG
See maintenance entity group.
MEL
maintenance entity group level
MEP
maintenance end point
MFAS
See multiframe alignment signal.
MIB
See management information base.
MIP
maintenance intermediate point
MLD
See multicast listener discovery.
MP
maintenance point
MPLS
See Multiprotocol Label Switching.
MPLS TE
multiprotocol label switching traffic engineering
MPLS TP
See Multiprotocol Label Switching traffic policing.
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A Glossary
MPLS VPN
See multiprotocol label switching virtual private network.
MPLS-TP
See multiprotocol label switching transport profile.
MS
multiplex section
MSA
multiplex section adaptation
MSB
most significant bit
MSOH
multiplex section overhead
MSP
See multiplex section protection.
MST
See multiplex section termination.
MSTI
See multiple spanning tree instance.
MSTP
See Multiple Spanning Tree Protocol.
MTBF
See mean time between failures.
MTTR
See mean time to repair.
MTU
See maximum transmission unit.
MUX
See multiplexer.
Media Access Control

(MAC)
A protocol at the media access control sublayer. The protocol is at the lower part of the
data link layer in the OSI model and is mainly responsible for controlling and connecting
the physical media at the physical layer. When transmitting data, the MAC protocol
checks whether to be able to transmit data. If the data can be transmitted, certain control
information is added to the data, and then the data and the control information are
transmitted in a specified format to the physical layer. When receiving data, the MAC
protocol checks whether the information is correct and whether the data is transmitted
correctly. If the information is correct and the data is transmitted correctly, the control
information is removed from the data and then the data is transmitted to the LLC layer.
Multiple Spanning
Tree Protocol (MSTP)
A protocol that can be used in a loop network. Using an algorithm, the MSTP blocks
redundant paths so that the loop network can be trimmed as a tree network. In this case,
the proliferation and endless cycling of packets is avoided in the loop network. The
protocol that introduces the mapping between VLANs and multiple spanning trees. This
solves the problem that data cannot be normally forwarded in a VLAN because in STP/
RSTP, only one spanning tree corresponds to all the VLANs.
Multiprotocol Label
Switching (MPLS)
A technology that uses short tags of fixed length to encapsulate packets in different link
layers, and provides connection-oriented switching for the network layer on the basis of
IP routing and control protocols. It improves the cost performance and expandability of
networks, and is beneficial to routing.
Multiprotocol Label
Switching traffic
policing (MPLS TP)
It is a scheme that supervises the specific traffic entering the communication devices.
By policing the speed of traffic that enters the network, it "punishes" the traffic out of
the threshold, so the traffic going into network is limited to a reasonable range, protecting
the network resources and the interests of the carriers.
main distribution
frame (MDF)
A device at a central office, on which all local loops are terminated.
maintenance domain
(MD)
The network or the part of the network for which connectivity is managed by connectivity
fault management (CFM). The devices in a maintenance domain are managed by a single
Internet service provider (ISP).
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1637

A Glossary
maintenance entity
(ME)
An ME consists of a pair of maintenance entity group end points (MEPs), two ends of a
transport trail, and maintenance association intermediate points (MIPs) on the trail.
maintenance entity
group (MEG)
A MEG consists of MEs that meet the following criteria:

l
Exist within the same management edges.
Have the same MEG hierarchy.
Belong to the same P2P or P2MP connection.
management
A type of database used for managing the devices in a communications network. It
information base (MIB) comprises a collection of objects in a (virtual) database used to manage entities (such as
routers and switches) in a network.
maximum transmission The largest packet of data that can be transmitted on a network. MTU size varies,
unit (MTU)
depending on the network576 bytes on X.25 networks, for example, 1500 bytes on
Ethernet, and 17,914 bytes on 16 Mbit/s token ring. Responsibility for determining the
size of the MTU lies with the link layer of the network. When packets are transmitted
across networks, the path MTU, or PMTU, represents the smallest packet size (the one
that all networks can transmit without breaking up the packet) among the networks
involved.
mean time between
failures (MTBF)
The average time between consecutive failures of a piece of equipment. It is a measure

of the reliability of the system.
mean time to repair

(MTTR)
The average time that a device will take to recover from a failure.
metropolitan area
network (MAN)
A network that interconnects users with computer resources in a geographic area or

region larger than that covered by even a large LAN but smaller than the area covered
by an WAN. The term is applied to the interconnection of networks in a city into a single
larger network (which may then also offer efficient connection to a wide area network).
It is also used to mean the interconnection of several local area networks by bridging
them with backbone lines. The latter usage is also sometimes referred to as a campus
network.
mirror
An action to store a copy of a file to another archive site to release the load of the original
site, or to provide an archive site closer to the users geographically.
mirroring
The duplication of data for backup or to distribute network traffic among several
computers with identical data.
multi-dwelling unit
(MDU)
A network access unit used for multi-dwelling units. It provides Ethernet and IP services
and optionally VoIP or CATV services; has multiple broadband interfaces on the user
side and optionally POTS ports or CATV RF ports. It is mainly applicable to FTTB,
FTTC, or FTTCab networks.
multicast listener
discovery (MLD)
A protocol used by an IPv6 router to discover the multicast listeners on their directly
connected network segments, and to set up and maintain member relationships. On IPv6
networks, after MLD is configured on the receiver hosts and the multicast router to which
the hosts are directly connected, the hosts can dynamically join related groups and the
multicast router can manage members on the local network.
multiframe alignment
signal (MFAS)
A distinctive signal inserted in every multiframe or once in every n multiframes, always

occupying the same relative position within the multiframe, and used to establish and
maintain multiframe alignment.
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A Glossary
multiple spanning tree A type of spanning trees calculated by MSTP within an MST Region, to provide a simply
instance (MSTI)
and fully connected active topology for frames classified as belonging to a VLAN that
is mapped to the MSTI by the MST Configuration. A VLAN cannot be assigned to
multiple MSTIs.
multiplex section
protection (MSP)
A function, which is performed to provide capability for switching a signal between and
including two multiplex section termination (MST) functions, from a "working" to a
"protection" channel.
multiplex section
termination (MST)
A function, which is performed to generate the MSOH during the process of forming an
SDH frame signal and terminates the MSOH in the reverse direction.
multiplexer (MUX)
Equipment which combines a number of tributary channels onto a fewer number of

aggregate bearer channels, the relationship between the tributary and aggregate channels
being fixed.
multiprotocol label
switching transport
profile (MPLS-TP)
A packet transport technology proposed by IETF that combines the packet experience
of MPLS with the operational experience of transport networks.
multiprotocol label
switching virtual
private network
(MPLS VPN)
An Internet Protocol (IP) virtual private network (VPN) based on the multiprotocol label
switching (MPLS) technology. It applies the MPLS technology for network routers and
switches, simplifies the routing mode of core routers, and combines traditional routing
technology and label switching technology. It can be used to construct the broadband
Intranet and Extranet to meet various service requirements.
N
NAS
network access server
NDF
new data flag
NHLFE
next hop label forwarding entry
NMC
network management center
NNI
network-to-network interface
NPC
See network parameter control.
NPE
network provider edge
NRT-VBR
non-real-time variable bit rate
NRZ
non-return to zero
NRZI
non-return to zero inverted
NSAP
See network service access point.
NSF
non-stop forwarding
NTP
Network Time Protocol
network parameter
control (NPC)
During communications, UPC is implemented to monitor the actual traffic on each virtual
circuit that is input to the network. Once the specified parameter is exceeded, measures
will be taken to control. NPC is similar to UPC in function. The difference is that the
incoming traffic monitoring function is divided into UPC and NPC according to their
positions. UPC locates at the user/network interface, while NPC at the network interface.
network service access A network address defined by ISO, at which the OSI Network Service is made available
point (NSAP)
to a Network service user by the Network service provider.
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A Glossary
O
O&M
operation and maintenance
OA
optical amplifier
OADM
See optical add/drop multiplexer.
OAM
See operation, administration and maintenance.
OAMPDU
operation, administration and maintenance protocol data unit
OAU
See optical amplifier unit.
OC
ordinary clock
OCP
optical channel protection
OCS
optical core switching
ODF
optical distribution frame
ODU
See outdoor unit.
OLT
optical line terminal
ONT
See optical network terminal.
ONU
See optical network unit.
OPEX
operating expense
OPU
optical channel payload unit
OSC
See optical supervisory channel.
OSI
See open systems interconnection.
OSN
optical switch node
OSNR
See optical signal-to-noise ratio.
OSPF
See Open Shortest Path First.
OTDR
See optical time domain reflectometer.
OTM
optical terminal multiplexer
OTN
optical transport network
OTU
See optical transponder unit.
OTUk
optical channel transport unit-k
Open Shortest Path

First (OSPF)
A link-state, hierarchical interior gateway protocol (IGP) for network routing. Dijkstra's
algorithm is used to calculate the shortest path tree. It uses cost as its routing metric. A
link state database is constructed with the network topology which is identical on all
routers in the area.
open systems
interconnection (OSI)
A framework of ISO standards for communication between different systems made by

different vendors, in which the communications process is organized into seven different
categories that are placed in a layered sequence based on their relationship to the user.
Each layer uses the layer immediately below it and provides a service to the layer above.
Layers 7 through 4 deal with end-to-end communication between the message source
and destination, and layers 3 through 1 deal with network functions.
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A Glossary
operation,
administration and
maintenance (OAM)
A group of network support functions that monitor and sustain segment operation,
support activities that are concerned with, but not limited to, failure detection,
notification, location, and repairs that are intended to eliminate faults and keep a segment
in an operational state, and support activities required to provide the services of a
subscriber access network to users/subscribers.
optical add/drop
multiplexer (OADM)
A device that can be used to add the optical signals of various wavelengths to one channel
and drop the optical signals of various wavelengths from one channel.
optical amplifier unit

(OAU)
A board that is mainly responsible for amplifying optical signals. The OAU can be used
in both the transmitting direction and the receiving direction.
optical network
terminal (ONT)
A device that terminates the fiber optical network at the customer premises.
optical network unit

(ONU)
A form of Access Node that converts optical signals transmitted via fiber to electrical
signals that can be transmitted via coaxial cable or twisted pair copper wiring to
individual subscribers.
optical signal-to-noise
ratio (OSNR)
The ratio of signal power and noise power in a transmission link. OSNR is the most
important index of measuring the performance of a DWDM system. OSNR = signal
power/noise power.
optical supervisory
channel (OSC)
A technology that uses specific optical wavelengths to realize communication among

nodes in optical transmission network and transmit the monitoring data in a certain
channel.
optical time domain

reflectometer (OTDR)
A device that sends a very short pulse of light down a fiber optic communication system
and measures the time history of the pulse reflection to measure the fiber length, the light
loss and locate the fiber fault.
optical transponder
unit (OTU)
A device or subsystem that converts the accessed client signals into the G.694.1/G.694.2compliant WDM wavelength.
orderwire
A channel that provides voice communication between operation engineers or

maintenance engineers of different stations.
outdoor unit (ODU)
The outdoor unit of the split-structured radio equipment. It implements frequency

conversion and amplification for radio frequency (RF) signals.
P
P2MP
point-to-multipoint
P2P
See point-to-point service.
PADR
PPPoE active discovery request
PBS
See peak burst size.
PCB
See printed circuit board.
PCM
See pulse code modulation.
PCR
See peak cell rate.
PDH
See plesiochronous digital hierarchy.
PDU
See power distribution unit.
PE
See provider edge.
PHB
See per-hop behavior.
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A Glossary
PHP
penultimate hop popping
PIM-DM
Protocol Independent Multicast - Dense Mode
PIM-SM
Protocol Independent Multicast - Sparse Mode
PIR
peak information rate
PLL
See phase-locked loop.
PM
performance monitoring
PMS
Product Management System
POH
path overhead
PON
passive optical network
POS
See packet over SDH/SONET.
PPD
partial packet discard
PPI
PDH physical interface
PPP
Point-to-Point Protocol
PPPoE
Point-to-Point Protocol over Ethernet
PPS
port protection switching
PQ
See priority queuing.
PRBS
See pseudo random binary sequence.
PRC
primary reference clock
PRI
primary rate interface
PSD
See power spectrum density.
PSN
See packet switched network.
PSTN
See public switched telephone network.
PSU
power supply unit
PT
payload type
PTI
payload type indicator
PTN
packet transport network
PTP
See point to point.
PVID
See port default VLAN ID.
PVP
See permanent virtual path.
PW
See pseudo wire.
PWE3
See pseudo wire emulation edge-to-edge.
packet over SDH/

SONET (POS)
A MAN and WAN technology that provides point-to-point data connections. The POS
interface uses SDH/SONET as the physical layer protocol, and supports the transport of
packet data (such as IP packets) in MAN and WAN.
packet switched
network (PSN)
A telecommunications network that works in packet switching mode.
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A Glossary
packet switching
A network technology in which information is transmitted by means of exchanging

packets and the bandwidth of a channel can be shared by multiple connections.
parity check
A method for character level error detection. An extra bit is added to a string of bits,
usually a 7-bit ASCII character, so that the total number of bits 1 is odd or even (odd or
even parity). Both ends of a data transmission must use the same parity. When the
transmitting device frames a character, it counts the numbers of 1s in the frame and
attaches the appropriate parity bit. The recipient counts the 1s and, if there is parity error,
may ask for the data to be retransmitted.
peak burst size (PBS)
A parameter that is used to define the capacity of token bucket P, that is, the maximum
burst IP packet size when the information is transferred at the peak information rate. This
parameter must be larger than 0. It is recommended that PBS should be not less than the
maximum length of the IP packet that might be forwarded. See also CIR, CBS, and PIR.
peak cell rate (PCR)
The maximum rate at which an ATM connection can accept cells.
per-hop behavior
(PHB)
IETF Diff-Serv workgroup defines forwarding behaviors of network nodes as per-hop

behaviors (PHB), such as, traffic scheduling and policing. A device in the network should
select the proper PHB behaviors, based on the value of DSCP. At present, the IETF
defines four types of PHB. They are class selector (CS), expedited forwarding (EF),
assured forwarding (AF), and best-effort (BE).
permanent virtual path Virtual path that consists of PVCs.

(PVP)
phase-locked loop
(PLL)
A circuit that consists essentially of a phase detector which compares the frequency of
a voltage-controlled oscillator with that of an incoming carrier signal or referencefrequency generator; the output of the phase detector, after passing through a loop filter,
is fed back to the voltage-controlled oscillator to keep it exactly in phase with the
incoming or reference frequency.
plesiochronous digital
hierarchy (PDH)
A multiplexing scheme of bit stuffing and byte interleaving. It multiplexes the minimum
rate 64 kit/s into the 2 Mbit/s, 34 Mbit/s, 140 Mbit/s, and 565 Mbit/s rates.
point to point (PTP)
A type of service in which data is sent from a single network termination to another
network termination.
point-to-point service
(P2P)
A service between two terminal users. In P2P services, senders and recipients are
terminal users.
port default VLAN ID

(PVID)
A default VLAN ID of a port. It is allocated to a data frame if the data frame carries no
VLAN tag when reaching the port.
power distribution unit A unit that performs AC or DC power distribution.

(PDU)
power spectrum
density (PSD)
The power layout of random signals in the frequency domain.
printed circuit board

(PCB)
A board used to mechanically support and electrically connect electronic components

using conductive pathways, tracks, or traces, etched from copper sheets laminated onto
a non-conductive substrate.
priority queuing (PQ)
A queue scheduling algorithm based on the absolute priority. According to the PQ

algorithm, services of higher priorities are ensured with greater bandwidth, lower
latency, and less jitter. Packets of lower priorities must wait to be sent till all packets of
higher priorities are sent. In this manner, services of higher priorities are processed earlier
than others.
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provider edge (PE)
A Glossary
A device that is located in the backbone network of the MPLS VPN structure. A PE is
responsible for managing VPN users, establishing LSPs between PEs, and exchanging
routing information between sites of the same VPN. A PE performs the mapping and
forwarding of packets between the private network and the public channel. A PE can be
a UPE, an SPE, or an NPE.
pseudo random binary A sequence that is random in a sense that the value of an element is independent of the
sequence (PRBS)
values of any of the other elements, similar to real random sequences.
pseudo wire (PW)
An emulated connection between two PEs for transmitting frames. The PW is established
and maintained by PEs through signaling protocols. The status information of a PW is
maintained by the two end PEs of a PW.
pseudo wire emulation An end-to-end Layer 2 transmission technology. It emulates the essential attributes of a
edge-to-edge (PWE3) telecommunication service such as ATM, FR or Ethernet in a packet switched network
(PSN). PWE3 also emulates the essential attributes of low speed time division
multiplexing (TDM) circuit and SONET/SDH. The simulation approximates to the real
situation.
public switched
telephone network
(PSTN)
A telecommunications network established to perform telephone services for the public

subscribers. Sometimes it is called POTS.
pulse code modulation A method of encoding information in a signal by changing the amplitude of pulses.
(PCM)
Unlike pulse amplitude modulation (PAM), in which pulse amplitude can change
continuously, pulse code modulation limits pulse amplitudes to several predefined
values. Because the signal is discrete, or digital, rather than analog, pulse code
modulation is more immune to noise than PAM.
Q
QAM
See quadrature amplitude modulation.
QPSK
See quadrature phase shift keying.
QinQ
See 802.1Q in 802.1Q.
QoS
See quality of service.
quadrature amplitude
modulation (QAM)
Both an analog and a digital modulation scheme. It conveys two analog message signals,
or two digital bit streams, by changing (modulating) the amplitudes of two carrier waves,
using the amplitude-shift keying (ASK) digital modulation scheme or amplitude
modulation (AM) analog modulation scheme. These two waves, usually sinusoids, are
out of phase with each other by 90 and are thus called quadrature carriers or quadrature
components hence the name of the scheme.
quadrature phase shift A modulation method of data transmission through the conversion or modulation and
keying (QPSK)
the phase determination of the reference signals (carrier). It is also called the fourth period
or 4-phase PSK or 4-PSK. QPSK uses four dots in the star diagram. The four dots are
evenly distributed on a circle. On these phases, each QPSK character can perform twobit coding and display the codes in Gray code on graph with the minimum BER.
quality of service (QoS) A commonly-used performance indicator of a telecommunication system or channel.
Depending on the specific system and service, it may relate to jitter, delay, packet loss
ratio, bit error ratio, and signal-to-noise ratio. It functions to measure the quality of the
transmission system and the effectiveness of the services, as well as the capability of a
service provider to meet the demands of users.
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A Glossary
R
RADIUS
See Remote Authentication Dial In User Service.
RAN
See radio access network.
RDI
remote defect indication
RED
See random early detection.
REG
See regenerator.
REI
remote error indication
RIP
See Routing Information Protocol.
RMEP
remote maintenance association end point
RMON
remote network monitoring
RNC
See radio network controller.
ROPA
See remote optical pumping amplifier.
RPR
resilient packet ring
RSOH
regenerator section overhead
RST
regenerator section termination
RSTP
See Rapid Spanning Tree Protocol.
RSVP
See Resource Reservation Protocol.
RSVP-TE
See Resource ReserVation Protocol-Traffic Engineering.
RTN
radio transmission node
RTP
real-time performance
RTS
request to send
Rapid Spanning Tree

Protocol (RSTP)
An evolution of the Spanning Tree Protocol, providing for faster spanning tree
convergence after a topology change. The RSTP protocol is backward compatible with
the STP protocol.
Remote Authentication A networking protocol that provides centralized Authentication, Authorization, and
Dial In User Service
Accounting (AAA) management for computers to connect and use a network service.
(RADIUS)
Resource ReserVation
Protocol-Traffic
Engineering (RSVPTE)
An extension to the RSVP protocol for setting up label switched paths (LSPs) in MPLS
networks. The RSVP-TE protocol is used to establish and maintain the LSPs by initiating
label requests and allocating label binding messages. It also supports LSP rerouting and
LSP bandwidth increasing.
Resource Reservation
Protocol (RSVP)
A network control protocol like Internet Control Message Protocol (ICMP) and designed
for Integrated Service and used to reserve resources on every node along a path. RSVP
operates on the transport layer; however, RSVP does not transport application data.
RoHS
restriction of the use of certain hazardous substances
Routing Information
Protocol (RIP)
A simple routing protocol that is part of the TCP/IP protocol suite. It determines a route
based on the smallest hop count between source and destination. RIP is a distance vector
protocol that routinely broadcasts routing information to its neighboring routers and is
known to waste bandwidth.
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A Glossary
radio access network

(RAN)
The network that provides the connection between CPEs and the CN. It isolates the CN
from wireless network.
radio network
controller (RNC)
A piece of equipment in the RNS which is in charge of controlling the use and the integrity
of the radio resources.
random early detection A packet loss algorithm used in congestion avoidance. It discards the packet according
(RED)
to the specified higher limit and lower limit of a queue so that global TCP synchronization
resulting from traditional tail drop can be prevented.
real-time variable bit
rate (rt-VBR)
A parameter intended for real-time applications, such as compressed voice over IP

(VoIP) and video conferencing. The rt-VBR is characterized by a peak cell rate (PCR),
sustained cell rate (SCR), and maximum burst size (MBS). You can expect the source
device to transmit in bursts and at a rate that varies with time.
receiver sensitivity
The minimum acceptable value of average received power at point R to achieve a 1 x

10-12 BER (The FEC is open).
reflectance
The ratio of the reflected optical power to the incident optical power.
regenerator (REG)
A piece of equipment or device that regenerates electrical signals.
remote optical
pumping amplifier
(ROPA)
A remote optical amplifier subsystem designed for applications where power supply and
monitoring systems are unavailable. The ROPA subsystem is a power compensation
solution to the ultra-long distance long hop (LHP) transmission.
rt-VBR
See real-time variable bit rate.
S
SAI
service area identifier
SAN
storage area network
SAToP
Structure-Agnostic Time Division Multiplexing over Packet
SC
square connector
SCR
sustainable cell rate
SD
See signal degrade.
SD-SDI
See standard definition-serial digital interface signal.
SDH
See synchronous digital hierarchy.
SDI
See serial digital interface.
SDP
serious disturbance period
SDRAM
See synchronous dynamic random access memory.
SELV
safety extra-low voltage
SEMF
synchronous equipment management function
SES
severely errored second
SF
See signal fail.
SFP
small form-factor pluggable
SFTP
See Secure File Transfer Protocol.
SHDSL
See single-pair high-speed digital subscriber line.
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A Glossary
SLA
See service level agreement.
SLIP
See Serial Line Interface Protocol.
SMB
Server Message Block
SMSR
side mode suppression ratio
SNCMP
subnetwork connection multipath protection
SNCP
subnetwork connection protection
SNCTP
subnetwork connection tunnel protection
SNMP
See Simple Network Management Protocol.
SOH
section overhead
SONET
See synchronous optical network.
SP
See service provider.
SPC
soft permanent connection
SPE
See superstratum provider edge.
SPI
SDH physical interface
SRG
See shared risk group.
SRLG
shared risk link group
SSH
See Secure Shell.
SSL
See Secure Sockets Layer.
SSM
See Synchronization Status Message.
SSMB
synchronization status message byte
SSU
synchronization supply unit
STP
Spanning Tree Protocol
Secure File Transfer

Protocol (SFTP)
A network protocol designed to provide secure file transfer over SSH.
Secure Shell (SSH)
A set of standards and an associated network protocol that allows establishing a secure
channel between a local and a remote computer. A feature to protect information and
provide powerful authentication function for a network when a user logs in to the network
through an insecure network. It prevents IP addresses from being deceived and plain text
passwords from being captured.
Secure Sockets Layer

(SSL)
A security protocol that works at a socket level. This layer exists between the TCP layer
and the application layer to encrypt/decode data and authenticate concerned entities.
Serial Line Interface

Protocol (SLIP)
A protocol that defines the framing mode over the serial line to implement transmission
of messages over the serial line and provide the remote host interconnection function
with a known IP address.
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Simple Network
Management Protocol
(SNMP)
A Glossary
A network management protocol of TCP/IP. It enables remote users to view and modify
the management information of a network element. This protocol ensures the
transmission of management information between any two points. The polling
mechanism is adopted to provide basic function sets. According to SNMP, agents, which
can be hardware as well as software, can monitor the activities of various devices on the
network and report these activities to the network console workstation. Control
information about each device is maintained by a management information block.
Synchronization Status A message that carries quality levels of timing signals on a synchronous timing link.
Nodes on an SDH network and a synchronization network acquire upstream clock
Message (SSM)
information through this message. Then the nodes can perform proper operations on their
clocks, such as tracing, switching, or converting to holdoff, and forward the
synchronization information to downstream nodes.
serial digital interface
(SDI)
An interface that transmits data in a single channel in sequence.
service level agreement A service agreement between a customer and a service provider. SLA specifies the
(SLA)
service level for a customer. The customer can be a user organization (source domain)
or another differentiated services domain (upstream domain). An SLA may include
traffic conditioning rules which constitute a traffic conditioning agreement as a whole
or partially.
service provider (SP)
An entity that offers service subscriptions to individual subscribers and contracts with
carriers to implement services for a specific DN. A service provider may contract with
more than one carrier.
shared risk group

(SRG)
A group of resources that share a common risk component whose failure can cause the
failure of all the resources in the group.
signal degrade (SD)
A signal indicating that associated data has degraded in the sense that a degraded defect
condition is active.
signal fail (SF)
A signal indicating that associated data has failed in the sense that a near-end defect
condition (non-degrade defect) is active.
single-pair high-speed
(SHDSL)
A symmetric digital subscriber line technology developed from HDSL, SDSL, and
HDSL2, which is defined in ITU-T G.991.2. The SHDSL port is connected to the user
terminal through the plain telephone subscriber line and uses trellis coded pulse
amplitude modulation (TC-PAM) technology to transmit high-speed data and provide
the broadband access service.
span
The physical reach between two pieces of WDM equipment. The number of spans
determines the signal transmission distance supported by a piece of equipment and varies
according to transmission system type.
standard definitionserial digital interface

signal (SD-SDI)
Standard definition video signal transported by serial digital interface.
superstratum provider Core devices that are located within a VPLS full-meshed network. The UPE devices that
edge (SPE)
are connected with the SPE devices are similar to the CE devices. The PWs set up
between the UPE devices and the SPE devices serve as the ACs of the SPE devices. The
SPE devices must learn the MAC addresses of all the sites on UPE side and those of the
UPE interfaces that are connected with the SPE. SPE is sometimes called NPE.
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synchronous digital
hierarchy (SDH)
A Glossary
A transmission scheme that follows ITU-T G.707, G.708, and G.709. It defines the
transmission features of digital signals such as frame structure, multiplexing mode,
transmission rate level, and interface code. SDH is an important part of ISDN and BISDN. It interleaves the bytes of low-speed signals to multiplex the signals to high-speed
counterparts, and the line coding of scrambling is used only for signals. SDH is suitable
for the fiber communication system with high speed and a large capacity since it uses
synchronous multiplexing and flexible mapping structure.
synchronous dynamic A new type of DRAM that can run at much higher clock speeds than conventional
random access memory memory. SDRAM actually synchronizes itself with the CPU's bus and is capable of
running at 100 MHz, about three times faster than conventional FPM RAM, and about
(SDRAM)
twice as fast as EDO DRAM or BEDO DRAM. SDRAM is replacing EDO DRAM in
computers.
synchronous optical
network (SONET)
A high-speed network that provides a standard interface for communications carriers to

connect networks based on fiber optical cable. SONET is designed to handle multiple
data types (voice, video, and so on). It transmits at a base rate of 51.84 Mbit/s, but
multiples of this base rate go as high as 2.488 Gbit/s.
T
TCI
tag control information
TCM
See trellis coded modulation scheme.
TCP/IP
Transmission Control Protocol/Internet Protocol
TDC
tunable dispersion compensator
TDM
See time division multiplexing.
TE
See traffic engineering.
TFTP
See Trivial File Transfer Protocol.
TIM
trail trace identifier mismatch
TLV
See type-length-value.
TM
See terminal multiplexer.
TMN
See telecommunications management network.
TOD
time of day
TPID
tag protocol identifier
TPS
See tributary protection switching.
TST
See Test.
TTI
trail trace identifier
TTSI
See trail termination source identifier.
TUG
tributary unit group
Telnet
A standard terminal emulation protocol in the TCP/IP protocol stack. Telnet allows users
to log in to remote systems and use resources as if they were connected to a local system.
Telnet is defined in RFC 854.
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A Glossary
Test (TST)
A function which is used to perform one-way on-demand in-service or out-of-service

diagnostics tests. This includes verifying bandwidth throughput, frame loss, bit errors,
and so on.
Trivial File Transfer

Protocol (TFTP)
A small and simple alternative to FTP for transferring files. TFTP is intended for
applications that do not need complex interactions between the client and server. TFTP
restricts operations to simple file transfers and does not provide authentication. TFTP is
small enough to be contained in ROM to be used for bootstrapping diskless machines.
tail drop
A congestion management mechanism, in which packets arrive later are discarded when
the queue is full. This policy of discarding packets may result in network-wide
synchronization due to the TCP slow startup mechanism.
telecommunications
management network
(TMN)
A protocol model defined by ITU-T for managing open systems in a communications

network. An architecture for management, including planning, provisioning, installation,
maintenance, operation and administration of telecommunications equipment, networks
and services.
terminal multiplexer
(TM)
A device used at a network terminal to multiplex multiple channels of low rate signals
into one channel of high rate signals, or to demultiplex one channel of high rate signals
into multiple channels of low rate signals.
throughput
The maximum transmission rate of the tested object (system, equipment, connection,
service type) when no packet is discarded. Throughput can be measured with bandwidth.
time division
multiplexing (TDM)
A multiplexing technology. TDM divides the sampling cycle of a channel into time slots
(TSn, n=0, 1, 2, 3), and the sampling value codes of multiple signals engross time slots
in a certain order, forming multiple multiplexing digital signals to be transmitted over
one channel.
traceroute
A program that prints the path to a destination. Traceroute sends a sequence of datagrams
with the time-to-live (TTL) set to 1,2, and so on, and uses ICMP time exceeded messages
that return to determine routers along the path.
traffic engineering (TE) A technology that is used to dynamically monitor the traffic of the network and the load
of the network elements, to adjust in real time the parameters such as traffic management
parameters, route parameters and resource restriction parameters, and to optimize the
utilization of network resources. The purpose is to prevent the congestion caused by
unbalanced loads.
trail termination source A TTSI uniquely identifies an LSP in the network. A TTSI is carried in the connectivity
identifier (TTSI)
verification (CV) packet for checking the connectivity of a trail. If it matches the TTSI
received by the sink point, the trail has no connectivity defect.
trellis coded
modulation scheme
(TCM)
A modulation scheme which allows highly efficient transmission of information over

band-limited channels such as telephone lines.
tributary protection
switching (TPS)
A function that uses a standby tributary processing board to protect N tributary

processing boards.
tunnel
A channel on the packet switching network that transmits service traffic between PEs.
In VPN, a tunnel is an information transmission channel between two entities. The tunnel
ensures secure and transparent transmission of VPN information. In most cases, a tunnel
is an MPLS tunnel.
Issue 03 (2013-02-20)

1650

type-length-value
(TLV)
A Glossary
An encoding type that features high efficiency and expansibility. It is also called CodeLength-Value (CLV). T indicates that different types can be defined through different
values. L indicates the total length of the value field. V indicates the actual data of the
TLV and is most important. TLV encoding features high expansibility. New TLVs can
be added to support new features, which is flexible in describing information loaded in
packets.
U
UART
universal asynchronous receiver/transmitter
UAS
unavailable second
UAT
See unavailable time event.
UBR
unspecified bit rate
UBR+
Unspecified Bit Rate Plus
UDP
See User Datagram Protocol.
UNI
See user-to-network interface.
UPC
See usage parameter control.
UPE
user-end provider edge
UPI
user payload identifier
UPM
uninterruptible power module
UPS
uninterruptible power supply
UTC
See Coordinated Universal Time.
User Datagram
Protocol (UDP)
A TCP/IP standard protocol that allows an application program on one device to send a
datagram to an application program on another. User Datagram Protocol (UDP) uses IP
to deliver datagram. UDP provides application programs with the unreliable
connectionless packet delivery service. There is a possibility that UDP messages will be
lost, duplicated, delayed, or delivered out of order. The destination device does not
confirm whether a data packet is received.
unavailable time event An event that is reported when the monitored object generates 10 consecutive severely
(UAT)
errored seconds (SES) and the SESs begin to be included in the unavailable time. The
event will end when the bit error ratio per second is better than 10-3 within 10 consecutive
seconds.
usage parameter
control (UPC)
During communications, UPC is implemented to monitor the actual traffic on each virtual
circuit that is input to the network. Once the specified parameter is exceeded, measures
will be taken to control. NPC is similar to UPC in function. The difference is that the
incoming traffic monitoring function is divided into UPC and NPC according to their
positions. UPC locates at the user/network interface, while NPC at the network interface.
user-to-network
interface (UNI)
The interface between user equipment and private or public network equipment (for
example, ATM switches).
V
V-NNI
virtual network-network interface
V-UNI
See virtual user-network interface.
Issue 03 (2013-02-20)

1651

A Glossary
VB
virtual bridge
VBR
See variable bit rate.
VCC
See virtual channel connection.
VCCV
virtual circuit connectivity verification
VCG
See virtual concatenation group.
VCI
virtual channel identifier
VDSL
very-high-data-rate digital subscriber line
VDSL2
See very-high-speed digital subscriber line 2.
VLAN
virtual local area network
VOA
variable optical attenuator
VP
See virtual path.
VPI
See virtual path identifier.
VPLS
See virtual private LAN service.
VPN
virtual private network
VPWS
See virtual private wire service.
VRRP
See Virtual Router Redundancy Protocol.
VSI
See virtual switch instance.
Virtual Router
Redundancy Protocol
(VRRP)
A protocol used for multicast or multicast LANs such as an Ethernet. A group of routers
(including an active router and several backup routers) in a LAN is regarded as a virtual
router, which is called a backup group. The virtual router has its own IP address. The
host in the network communicates with other networks through this virtual router. If the
active router in the backup group fails, one of the backup routers in this backup group
becomes active and provides routing service for the host in the network.
VoIP
See voice over IP.
variable bit rate (VBR) One of the traffic classes used by ATM (Asynchronous Transfer Mode). Unlike a
permanent CBR (Constant Bit Rate) channel, a VBR data stream varies in bandwidth
and is better suited to non real time transfers than to real-time streams such as voice calls.
very-high-speed digital An extension of the VDSL technology, which complies with ITU G.993.2, supports
subscriber line 2
multiple spectrum profiles and encapsulation modes, and provides short-distance and
(VDSL2)
high-speed access solutions to the next-generation FTTx access service.
virtual channel
connection (VCC)
A VC logical trail that carries data between two end points in an ATM network. A pointto-multipoint VCC is a set of ATM virtual connections between two or multiple end
points.
virtual concatenation
group (VCG)
A group of co-located member trail termination functions that are connected to the same
virtual concatenation link
virtual path (VP)
A bundle of virtual channels, all of which are switched transparently across an ATM
network based on a common VPI.
virtual path identifier

(VPI)
The field in the Asynchronous Transfer Mode (ATM) cell header that identifies to which
virtual path the cell belongs.
Issue 03 (2013-02-20)

1652

A Glossary
virtual private LAN

service (VPLS)
A type of point-to-multipoint L2VPN service provided over the public network. VPLS
enables geographically isolated user sites to communicate with each other through the
MAN/WAN as if they are on the same LAN.
virtual private wire

service (VPWS)
A technology that bears Layer 2 services. VPWS emulates services such as ATM, FR,
Ethernet, low-speed TDM circuit, and SONET/SDH in a PSN.
virtual switch instance An instance through which the physical access links of VPLS can be mapped to the
(VSI)
virtual links. Each VSI provides independent VPLS service. VSI has Ethernet bridge
function and can terminate PW.
virtual user-network
interface (V-UNI)
A virtual user-network interface, works as an action point to perform service

classification and traffic control in HQoS.
voice over IP (VoIP)
An IP telephony term for a set of facilities used to manage the delivery of voice
information over the Internet. VoIP involves sending voice information in a digital form
in discrete packets rather than by using the traditional circuit-committed protocols of the
public switched telephone network (PSTN).
W
WAN
See wide area network.
WCDMA
See Wideband Code Division Multiple Access.
WDM
wavelength division multiplexing
WEEE
waste electrical and electronic equipment
WFQ
See weighted fair queuing.
WLAN
See wireless local area network.
WRED
See weighted random early detection.
WRR
weighted round robin
WTR
See wait to restore.
Wideband Code
Division Multiple
Access (WCDMA)
A standard defined by the ITU-T for the third-generation wireless technology derived
from the Code Division Multiple Access (CDMA) technology.
wait to restore (WTR)
The number of minutes to wait before services are switched back to the working line.
weighted fair queuing

(WFQ)
A fair queue scheduling algorithm based on bandwidth allocation weights. This

scheduling algorithm allocates the total bandwidth of an interface to queues, according
to their weights and schedules the queues cyclically. In this manner, packets of all priority
queues can be scheduled.
weighted random early A packet loss algorithm used for congestion avoidance. It can prevent the global TCP
detection (WRED)
synchronization caused by traditional tail-drop. WRED is favorable for the high-priority
packet when calculating the packet loss ratio.
wide area network
(WAN)
A network composed of computers which are far away from each other which are
physically connected through specific protocols. WAN covers a broad area, such as a
province, a state or even a country.
wireless local area

network (WLAN)
A hybrid of the computer network and the wireless communication technology. It uses
wireless multiple address channels as transmission media and carriers out data interaction
through electromagnetic wave to implement the functions of the traditional LAN.
Issue 03 (2013-02-20)

1653

A Glossary
Z
Z interface extension
Issue 03 (2013-02-20)
Extending the analogue subscriber to another place by extending the Z interface.

1654

OSN 3500 V200R011C03 Hardware Description 03

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HUAWEI TECHNOLOGIES CO., LTD.

Copyright Huawei Technologies Co., Ltd. 2013. All rights reserved.

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About This Document

About This Document

OptiX OSN 3500

Network design and planning engineers

Hardware installation engineers

DANGER indicates a hazard with a high level or medium

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About This Document

CAUTION indicates a potentially hazardous situation that,

Provides additional information to emphasize or supplement

Buttons, menus, parameters, tabs, window, and dialog titles

Multi-level menus are in boldface and separated by the ">"

Updates in Issue 03 (2013-02-20) Based on Product Version

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OptiX OSN 3500 Intelligent Optical Transmission System

About This Document

Updates in Issue 02 (2012-03-15) Based on Product Version

In topic "EoS Boards", the description of frame length range is optimized.

Updates in Issue 01 (2012-01-30) Based on Product Version

Updates in Issue 02 (2011-10-26) Based on Product Version

Updates in Issue 01 (2011-07-20) Based on Product Version

The description of the N4SL64 boards is added to topic "SDH Boards".

The description of the N1PFL1 boards is added to topic "PDH Boards".

The description of the N1VST4 boards is added to topic "SAN/Video Boards".

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OptiX OSN 3500 Intelligent Optical Transmission System

About This Document

Updates in Issue 02 (2011-04-15) Based on Product Version

Updates in Issue 01 (2011-01-25) Based on Product Version

Updates in Issue 02 (2010-11-01) Based on Product Version

Updates in Issue 01 (2010-07-20) Based on Product Version

The description of the PEX2/PEG8/PEFF8 is added in the topic "Packet Boards".

The description of the EDQ41 is added.

The description of the CQ1/MD12/MD75 is added.

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6.1.9 Configuring and Commissioning the Board............................................................................................59

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6.3.13.2 Performance Events of N6GSCC.................................................................................................91

7 Packet Processing Boards...........................................................................................................92

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7.3.1 Version Description...............................................................................................................................139

8 Packet Interface Boards............................................................................................................178

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8.1.6 Jumpers and DIP Switches....................................................................................................................186

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8.3.13 List of Performance Events.................................................................................................................218

9 EoD Boards................................................................................................................................. 249

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