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Hybrid Modeling and Control of Switching DC-DC Converters Via MLD Systems
Hybrid Modeling and Control of Switching DC-DC Converters Via MLD Systems
SaA1.1
I. INTRODUCTION
Hybrid modeling and control of DC-DC converters has
attracted interest in the fields of power electronics and auto
matic control theory. However, developing a general model
and control technique which considers all possible dynamics
of a converter is still a challenging issue.
Several approaches have been reported in literature for
modeling and control of DC-DC converters [1]-[11]. In
[12] and [13], the principles of operation of these methods
are reviewed and the shortcomings of such methods are
mentioned. The main drawback of all the existing methods is
that their design is based on one operating mode of operation,
i.e. either continuous current mode (CCM) or discontinuous
current mode (DCM). In CCM the current in the inductor
fluctuates during a cycle but never goes down to zero. On
the contrary, in DCM the current in the inductor fluctuates
during the cycle, going down to zero at or before the end
of each cycle. Therefore, the performance and stability of
the closed-loop system is guaranteed only for one operation
mode. Recently in [14], several hybrid control techniques
from different research groups were introduced for DC-DC
This work was done when the first author was a Ph.D student in
Department of Electrical and Electronic Engineering,University of Cagliari,
Italy,Email: mohammad.hejri@diee.unica.it
714
oe(k)
FinHe State
Machine
(FSM)
/0
0-\:0
Switched
Affine
System (SAS)
Mode
xb(k) Selector
:-+I(MS)
.,..
u-..,.
b(k)
oe(k)
=Cx>-
l..----
i(k)
1-------'
=D-
Fig. I.
OF
A BUCK CONVERTER
Rnc
kEN
y =
U =
[ ; ] E
[ ; ] E
[ ;; ]E
RPc
(1)
Rmc
Fig. 2.
Buck Converter
715
_'!:.J..
L
r
-.l
c
Ro+rc (l-Crc LL)
v,
L
v: Ro TC
SRo+TC L
1
-r
_-.l_
_
l
(l+Crcfi)
c Ro+rc
L
(3)
A2
AI,h2
[ ]
(5)
In Mode 3, both the switch and diode are OFF. The required
energy for the load is supplied from stored energy in electric
field of capacitor. The state space equation in this mode is:
(6)
where:
ud(k)=O
(7)
We define Ud(t)E {O, I} as a discrete input which shows
the state of the switch. Ud(t) = 1 when the switch is ON
and Ud(t) = 0 when it is OFF. The basic converter equation
in continuous time is described as:
if
if
if
Ud(t) = 1
Ud(t) = 0/\ idt) > 0
Ud(t) = 0/\ idt) :::; 0
(8)
xc(k+1) =
Fig. 3.
Xd, =
[]
xc(k + 1) =
[ ] (AC3XC(k) + hC3)
AC4XC(k) + hC4
(10)
We define xd(k) = [xd,(k),Xd2(k) V as a discrete state
vector in the hybrid automaton of the buck converter in Fig.
3. This figure has three discrete states, i.e. [1 O]T,[O I V
and [0 O]T that are corresponding to the modes 1,2 and 3,
respectively.
First, the condition idk +N) :::;
a binary variable 51 (k) such that:
0 can be associated
with
(11)
where, iL(k + N) = [1 O](Axc(k) + L:Ol A2hc2) ' The
evolution of the logic state vector Xd(k) can be written as
the following equation:
where:
5j, = 0/\512 = 0
5j, = 0/\512 = 1
--+ 5j, = 0/\512 = 1
--+ 5j, = 1/\512 = 0
1 /\
1 /\ (j f2
0 /\ <h
0 /\
0 --+ (j It
Xd, = 1/\ Xd2 = 0/\51 = 1 --+ 5j, = 0/\512 = 0
Xd1 = 1/\ Xd2 = 0/\ Ud = 1 --+ 5j, = 0/\512 = 1
Xd2
Ud
--+
--+
(13)
In BMLD approach, we define a new discrete state bit Xd3(k)
that denotes the value of Xd,(k) during the previous step, i.e.,
716
Zl (k)
z!2(k)
z!3(k)
(15)
and z3(k) are
xc(k + 1)=
AC3XC(k) + hC3 + Zl (k) + z2(k) + z3(k)
(17)
8!'3(k) as:
min
{u(O),... ,u(Tu-1),
,,(Olt),. ,,,(Tp-llt),
z(Olt),. ,z(Tp-llt)}
Er==lIIQ(y(klt) - r(t))11 2+
(22)
x(Olt)= x(t)
FMLD or BMLD model
x(llt), ,x(Tp)
Xmin
Xmax
where the hat sign indicates the predicted value of the cor
responding parameter. The disturbance is assumed constant
during the prediction horizon, thus:
(19)
Zi,2(k) and
(20)
By substituting of (20) in (19), the overall continuous dy
namic in the FMLD framework is written as:
IV.
y(k + ilk)
xc(k + 1)=
AC3XC(k) + hC3 + Z;ll (k) + Zi,2(k) + Zi,3(k)
(23)
(21)
71 7
TABLE I
CONVERTER PARAMETERS USED FOR SIMULATIONS
c
TC
(a)
3 p.u.
1 p.u.
FMLD.
... .. BMLD.
__
10
nme(p.u.)
(b)
FMLD.
BMLD.
. . . BMLD.
.. . .
___
10
nme(p.u.)
15
10
T =1
p
T =2
p
15
__
(a)
20
30
50
40
Time(p.u.)
(b)
60
70
80
60
70
80
-FMLD
BMLD.I
I........
20
10
T =1
p
T =2
p
T =1
p
20
30
40
50
Time(p.u.)
Fig. 5.
System performance for large output resistance variation, (a)
inductor current,(b) output voltage
(a)
....... BMLDI
I-FMLD
20
Fig. 4.
Converter start by the M PC for FMLD and BMLD models (a)
inductor current,(b) output voltage
10
20
30
40
50
Time(p.u.)
(b)
60
70
80
40
50
Time(p.u.)
60
70
80
....... BMLDI
I-FMLD
:;
Co
:;
o
10
20
30
Fig. 6.
System performance when reference signal variation occurs,(a)
current waveform,(b) voltage waveform
718
CONCLUSION
719
--